diff options
109 files changed, 1789 insertions, 272 deletions
diff --git a/arch/arm/cpu/arm926ejs/spear/Makefile b/arch/arm/cpu/arm926ejs/spear/Makefile index 7b15d4ef7e..3992401590 100644 --- a/arch/arm/cpu/arm926ejs/spear/Makefile +++ b/arch/arm/cpu/arm926ejs/spear/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_DDR_MT47H64M16) += spr600_mt47h64m16_3_333_cl5_psync.o obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_333_cl5_psync.o obj-$(CONFIG_DDR_MT47H32M16) += spr600_mt47h32m16_37e_166_cl4_sync.o obj-$(CONFIG_DDR_MT47H128M8) += spr600_mt47h128m8_3_266_cl5_async.o +else +obj-y += spr_misc.o spr_lowlevel_init.o endif extra-$(CONFIG_SPL_BUILD) := start.o diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index be0d14fbf0..7b9dc65c27 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -84,7 +84,7 @@ int print_cpuinfo(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH) && defined(CONFIG_NAND_FSMC) static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/board/spear/common/spr_lowlevel_init.S b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S index 649488399a..649488399a 100644 --- a/board/spear/common/spr_lowlevel_init.S +++ b/arch/arm/cpu/arm926ejs/spear/spr_lowlevel_init.S diff --git a/board/spear/common/spr_misc.c b/arch/arm/cpu/arm926ejs/spear/spr_misc.c index a02304f49e..a02304f49e 100644 --- a/board/spear/common/spr_misc.c +++ b/arch/arm/cpu/arm926ejs/spear/spr_misc.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index f5f4840f19..c9252751db 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -345,11 +345,38 @@ static void fdt_fixup_msi(void *blob) } #endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +/* Remove JR node used by SEC firmware */ +void fdt_fixup_remove_jr(void *blob) +{ + int jr_node, addr_cells, len; + int crypto_node = fdt_path_offset(blob, "crypto"); + u64 jr_offset, used_jr; + fdt32_t *reg; + + used_jr = sec_firmware_used_jobring_offset(); + fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL); + + jr_node = fdt_node_offset_by_compatible(blob, crypto_node, + "fsl,sec-v4.0-job-ring"); + + while (jr_node != -FDT_ERR_NOTFOUND) { + reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len); + jr_offset = fdt_read_number(reg, addr_cells); + if (jr_offset == used_jr) { + fdt_del_node(blob, jr_node); + break; + } + jr_node = fdt_node_offset_by_compatible(blob, jr_node, + "fsl,sec-v4.0-job-ring"); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { -#ifdef CONFIG_FSL_LSCH2 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - unsigned int svr = in_be32(&gur->svr); + unsigned int svr = gur_in32(&gur->svr); /* delete crypto node if not on an E-processor */ if (!IS_E_PROCESSOR(svr)) @@ -358,11 +385,15 @@ void ft_cpu_setup(void *blob, bd_t *bd) else { ccsr_sec_t __iomem *sec; +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + if (fdt_fixup_kaslr(blob)) + fdt_fixup_remove_jr(blob); +#endif + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif -#endif #ifdef CONFIG_MP ft_fixup_cpu(blob); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index fffce712d3..0e7483437a 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -232,6 +232,59 @@ unsigned int sec_firmware_support_psci_version(void) #endif /* + * Check with sec_firmware if it supports random number generation + * via HW RNG + * + * The return value will be true if it is supported + */ +bool sec_firmware_support_hwrng(void) +{ + uint8_t rand[8]; + if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) { + if (!sec_firmware_get_random(rand, 8)) + return true; + } + + return false; +} + +/* + * sec_firmware_get_random - Get a random number from SEC Firmware + * @rand: random number buffer to be filled + * @bytes: Number of bytes of random number to be supported + * @eret: -1 in case of error, 0 for success + */ +int sec_firmware_get_random(uint8_t *rand, int bytes) +{ + unsigned long long num; + struct pt_regs regs; + int param1; + + if (!bytes || bytes > 8) { + printf("Max Random bytes genration supported is 8\n"); + return -1; + } +#define SIP_RNG_64 0xC200FF11 + regs.regs[0] = SIP_RNG_64; + + if (bytes <= 4) + param1 = 0; + else + param1 = 1; + regs.regs[1] = param1; + + smc_call(®s); + + if (regs.regs[0]) + return -1; + + num = regs.regs[1]; + memcpy(rand, &num, bytes); + + return 0; +} + +/* * sec_firmware_init - Initialize the SEC Firmware * @sec_firmware_img: the SEC Firmware image address * @eret_hold_l: the address to hold exception return address low @@ -278,3 +331,49 @@ int sec_firmware_init(const void *sec_firmware_img, return 0; } + +/* + * fdt_fix_kaslr - Add kalsr-seed node in Device tree + * @fdt: Device tree + * @eret: 0 in case of error, 1 for success + */ +int fdt_fixup_kaslr(void *fdt) +{ + int nodeoffset; + int err, ret = 0; + u8 rand[8]; + +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) + /* Check if random seed generation is supported */ + if (sec_firmware_support_hwrng() == false) + return 0; + + ret = sec_firmware_get_random(rand, 8); + if (ret < 0) { + printf("WARNING: No random number to set kaslr-seed\n"); + return 0; + } + + err = fdt_check_header(fdt); + if (err < 0) { + printf("fdt_chosen: %s\n", fdt_strerror(err)); + return 0; + } + + /* find or create "/chosen" node. */ + nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen"); + if (nodeoffset < 0) + return 0; + + err = fdt_setprop(fdt, nodeoffset, "kaslr-seed", rand, + sizeof(rand)); + if (err < 0) { + printf("WARNING: can't set kaslr-seed %s.\n", + fdt_strerror(err)); + return 0; + } + ret = 1; +#endif + + return ret; +} diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi index b26e21bd7f..14caee7f0d 100644 --- a/arch/arm/dts/am33xx.dtsi +++ b/arch/arm/dts/am33xx.dtsi @@ -315,7 +315,6 @@ &edma 25>; dma-names = "tx", "rx"; interrupts = <64>; - interrupt-parent = <&intc>; reg = <0x48060000 0x1000>; status = "disabled"; }; @@ -328,7 +327,6 @@ &edma 3>; dma-names = "tx", "rx"; interrupts = <28>; - interrupt-parent = <&intc>; reg = <0x481d8000 0x1000>; status = "disabled"; }; @@ -338,7 +336,6 @@ ti,hwmods = "mmc3"; ti,needs-special-reset; interrupts = <29>; - interrupt-parent = <&intc>; reg = <0x47810000 0x1000>; status = "disabled"; }; @@ -724,7 +721,6 @@ 0x4a101200 0x100>; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; /* * c0_rx_thresh_pend * c0_rx_pend @@ -787,7 +783,6 @@ lcdc: lcdc@4830e000 { compatible = "ti,am33xx-tilcdc"; reg = <0x4830e000 0x1000>; - interrupt-parent = <&intc>; interrupts = <36>; ti,hwmods = "lcdc"; status = "disabled"; @@ -796,7 +791,6 @@ tscadc: tscadc@44e0d000 { compatible = "ti,am3359-tscadc"; reg = <0x44e0d000 0x1000>; - interrupt-parent = <&intc>; interrupts = <16>; ti,hwmods = "adc_tsc"; status = "disabled"; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index 8d89b83b53..d8a65145d6 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -632,6 +632,34 @@ status = "disabled"; }; + rstc@f8048000 { + compatible = "atmel,sama5d3-rstc"; + reg = <0xf8048000 0x10>; + clocks = <&clk32k>; + }; + + shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + + pit: timer@f8048030 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xf8048030 0x10>; + clocks = <&h32ck>; + }; + + watchdog@f8048040 { + compatible = "atmel,sama5d4-wdt"; + reg = <0xf8048040 0x10>; + clocks = <&clk32k>; + status = "disabled"; + }; + sckc@f8048050 { compatible = "atmel,at91sam9x5-sckc"; reg = <0xf8048050 0x4>; diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h index bc1d97d7a9..6d42a7111f 100644 --- a/arch/arm/include/asm/armv8/sec_firmware.h +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -8,10 +8,14 @@ #define __SEC_FIRMWARE_H_ #define PSCI_INVALID_VER 0xffffffff +#define SEC_JR3_OFFSET 0x40000 int sec_firmware_init(const void *, u32 *, u32 *); int _sec_firmware_entry(const void *, u32 *, u32 *); bool sec_firmware_is_valid(const void *); +bool sec_firmware_support_hwrng(void); +int sec_firmware_get_random(uint8_t *rand, int bytes); +int fdt_fixup_kaslr(void *fdt); #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI unsigned int sec_firmware_support_psci_version(void); unsigned int _sec_firmware_support_psci_version(void); @@ -22,4 +26,9 @@ static inline unsigned int sec_firmware_support_psci_version(void) } #endif +static inline unsigned int sec_firmware_used_jobring_offset(void) +{ + return SEC_JR3_OFFSET; +} + #endif /* __SEC_FIRMWARE_H_ */ diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile index 624ccd7c2f..dc935fd9e5 100644 --- a/arch/arm/mach-at91/arm926ejs/Makefile +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -22,7 +22,9 @@ obj-y += cache.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o +ifeq ($(CONFIG_ATMEL_PIT_TIMER),) obj-y += timer.o +endif ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 9538bc1fad..1ede4cb10a 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -14,4 +14,6 @@ obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o +ifeq ($(CONFIG_ATMEL_PIT_TIMER),) obj-y += timer.o +endif diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index f70f5ec965..947ce5f1ce 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -18,7 +18,7 @@ config STM32F7 select SPL_OF_CONTROL select SPL_OF_LIBFDT select SPL_OF_TRANSLATE - select SPL_OS_BOOT + imply SPL_OS_BOOT select SPL_PINCTRL select SPL_RAM select SPL_SERIAL_SUPPORT diff --git a/arch/powerpc/cpu/mpc83xx/interrupts.c b/arch/powerpc/cpu/mpc83xx/interrupts.c index 668aa02088..50503b4d2c 100644 --- a/arch/powerpc/cpu/mpc83xx/interrupts.c +++ b/arch/powerpc/cpu/mpc83xx/interrupts.c @@ -20,7 +20,7 @@ struct irq_action { ulong count; }; -int interrupt_init_cpu (unsigned *decrementer_count) +void interrupt_init_cpu (unsigned *decrementer_count) { volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; @@ -29,8 +29,6 @@ int interrupt_init_cpu (unsigned *decrementer_count) /* Enable e300 time base */ immr->sysconf.spcr |= 0x00400000; - - return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index cf730c5c53..b92549000f 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -20,7 +20,7 @@ #include <post.h> #endif -int interrupt_init_cpu(unsigned *decrementer_count) +void interrupt_init_cpu(unsigned *decrementer_count) { ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; @@ -77,8 +77,6 @@ int interrupt_init_cpu(unsigned *decrementer_count) #ifdef CONFIG_POST post_word_store(post_word); #endif - - return (0); } /* Install and free a interrupt handler. Not implemented yet. */ diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c index a6db0baab3..81874790ff 100644 --- a/arch/powerpc/cpu/mpc86xx/interrupts.c +++ b/arch/powerpc/cpu/mpc86xx/interrupts.c @@ -23,7 +23,7 @@ #include <post.h> #endif -int interrupt_init_cpu(unsigned *decrementer_count) +void interrupt_init_cpu(unsigned *decrementer_count) { volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_pic_t *pic = &immr->im_pic; @@ -73,8 +73,6 @@ int interrupt_init_cpu(unsigned *decrementer_count) #ifdef CONFIG_POST post_word_store(post_word); #endif - - return 0; } /* diff --git a/arch/powerpc/cpu/mpc8xx/interrupts.c b/arch/powerpc/cpu/mpc8xx/interrupts.c index e8e287a13f..846148ab98 100644 --- a/arch/powerpc/cpu/mpc8xx/interrupts.c +++ b/arch/powerpc/cpu/mpc8xx/interrupts.c @@ -30,7 +30,7 @@ static void cpm_interrupt(void *regs); /************************************************************************/ -int interrupt_init_cpu(unsigned *decrementer_count) +void interrupt_init_cpu(unsigned *decrementer_count) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; @@ -41,8 +41,6 @@ int interrupt_init_cpu(unsigned *decrementer_count) /* Configure CPM interrupts */ cpm_interrupt_init(); - - return 0; } /************************************************************************/ diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h index 850fe93f97..5e0aa08be9 100644 --- a/arch/powerpc/include/asm/ppc.h +++ b/arch/powerpc/include/asm/ppc.h @@ -122,7 +122,7 @@ static inline void set_msr(unsigned long msr) void print_reginfo(void); #endif -int interrupt_init_cpu(unsigned *); +void interrupt_init_cpu(unsigned *); void timer_interrupt_cpu(struct pt_regs *); unsigned long search_exception_table(unsigned long addr); diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c index 46fa18c63f..e8784aa16e 100644 --- a/arch/powerpc/lib/interrupts.c +++ b/arch/powerpc/lib/interrupts.c @@ -63,13 +63,8 @@ int disable_interrupts (void) int interrupt_init (void) { - int ret; - /* call cpu specific function from $(CPU)/interrupts.c */ - ret = interrupt_init_cpu (&decrementer_count); - - if (ret) - return ret; + interrupt_init_cpu (&decrementer_count); set_dec (decrementer_count); diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS index 720ef2aa69..d75d400eed 100644 --- a/board/isee/igep00x0/MAINTAINERS +++ b/board/isee/igep00x0/MAINTAINERS @@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com> S: Maintained F: board/isee/igep00x0/ F: include/configs/omap3_igep00x0.h -F: configs/igep0020_defconfig -F: configs/igep0030_defconfig +F: configs/igep00x0_defconfig F: configs/igep0032_defconfig diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile index 68b151c3c5..74594da771 100644 --- a/board/isee/igep00x0/Makefile +++ b/board/isee/igep00x0/Makefile @@ -5,4 +5,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := igep00x0.o +ifdef CONFIG_SPL_BUILD +obj-y := spl.o common.o +else +obj-y := igep00x0.o common.o +endif diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c new file mode 100644 index 0000000000..e59516f612 --- /dev/null +++ b/board/isee/igep00x0/common.c @@ -0,0 +1,68 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <twl4030.h> +#include <asm/io.h> +#include <asm/omap_mmc.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_DEFAULT(); +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#if defined(CONFIG_MMC) +int board_mmc_init(bd_t *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} + +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a7a75601dd..5c7f256711 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -17,18 +17,14 @@ #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> -#include <asm/mach-types.h> #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> -#include <linux/mtd/nand.h> #include <linux/mtd/onenand.h> #include <jffs2/load_kernel.h> #include <mtd_node.h> #include <fdt_support.h> #include "igep00x0.h" -DECLARE_GLOBAL_DATA_PTR; - static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, .reg_shift = 2, @@ -42,96 +38,41 @@ U_BOOT_DEVICE(igep_uart) = { }; /* - * Routine: board_init - * Description: Early hardware init. + * Routine: get_board_revision + * Description: GPIO_28 and GPIO_129 are used to read board and revision from + * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from + * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because + * this functionality is shared by USB HOST. + * Once USB reset is applied, U-boot configures these pins as input pullup to + * detect board and revision: + * IGEP0020-RF = 0b00 + * IGEP0020-RC = 0b01 + * IGEP0030-RG = 0b10 + * IGEP0030-RE = 0b11 */ -int board_init(void) +static int get_board_revision(void) { - int loops = 100; - - /* find out flash memory type, assume NAND first */ - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - gpmc_init(); + int revision; - /* Issue a RESET and then READID */ - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) - != NAND_STATUS_READY) { - udelay(1); - if (--loops == 0) { - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - gpmc_init(); /* reinitialize for OneNAND */ - break; - } - } + gpio_request(IGEP0030_USB_TRANSCEIVER_RESET, + "igep0030_usb_transceiver_reset"); + gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0); - /* boot param addr */ - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection"); + gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION); + revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION); + gpio_free(GPIO_IGEP00X0_BOARD_DETECTION); -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE) - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON); -#endif - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -/* - * Routine: get_board_mem_timings - * Description: If we use SPL then there is no x-loader nor config header - * so we have to setup the DDR timings ourself on both banks. - */ -void get_board_mem_timings(struct board_sdrc_timings *timings) -{ - int mfr, id, err = identify_nand_chip(&mfr, &id); - - timings->mr = MICRON_V_MR_165; - if (!err) { - switch (mfr) { - case NAND_MFR_HYNIX: - timings->mcfg = HYNIX_V_MCFG_200(256 << 20); - timings->ctrla = HYNIX_V_ACTIMA_200; - timings->ctrlb = HYNIX_V_ACTIMB_200; - break; - case NAND_MFR_MICRON: - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - break; - default: - /* Should not happen... */ - break; - } - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - gpmc_cs0_flash = MTD_DEV_TYPE_NAND; - } else { - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; - } - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; - } -} + gpio_request(GPIO_IGEP00X0_REVISION_DETECTION, + "igep00x0_revision_detection"); + gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION); + revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION); + gpio_free(GPIO_IGEP00X0_REVISION_DETECTION); -#ifdef CONFIG_SPL_OS_BOOT -int spl_start_uboot(void) -{ - /* break into full u-boot on 'c' */ - if (serial_tstc() && serial_getc() == 'c') - return 1; + gpio_free(IGEP0030_USB_TRANSCEIVER_RESET); - return 0; + return revision; } -#endif -#endif int onenand_board_init(struct mtd_info *mtd) { @@ -199,20 +140,6 @@ int board_eth_init(bd_t *bis) static inline void setup_net_chip(void) {} #endif -#if defined(CONFIG_MMC) -int board_mmc_init(bd_t *bis) -{ - return omap_mmc_init(0, 0, 0, -1, -1); -} -#endif - -#if defined(CONFIG_MMC) -void board_mmc_power_init(void) -{ - twl4030_power_mmc_init(0); -} -#endif - #ifdef CONFIG_OF_BOARD_SETUP static int ft_enable_by_compatible(void *blob, char *compat, int enable) { @@ -247,31 +174,69 @@ int ft_board_setup(void *blob, bd_t *bd) } #endif -void set_fdt(void) +void set_led(void) { - switch (gd->bd->bi_arch_number) { - case MACH_TYPE_IGEP0020: - env_set("fdtfile", "omap3-igep0020.dtb"); + switch (get_board_revision()) { + case 0: + case 1: + gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led"); + gpio_direction_output(IGEP0020_GPIO_LED, 1); + break; + case 2: + case 3: + gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led"); + gpio_direction_output(IGEP0030_GPIO_LED, 0); break; - case MACH_TYPE_IGEP0030: - env_set("fdtfile", "omap3-igep0030.dtb"); + default: + /* Should not happen... */ break; } } +void set_boardname(void) +{ + char rev[5] = { 'F','C','G','E', }; + int i = get_board_revision(); + + rev[i+1] = 0; + env_set("board_rev", rev + i); + env_set("board_name", i < 2 ? "igep0020" : "igep0030"); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { + t2_t *t2_base = (t2_t *)T2_BASE; + u32 pbias_lite; + twl4030_power_init(); + /* set VSIM to 1.8V */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED, + TWL4030_PM_RECEIVER_VSIM_VSEL_18, + TWL4030_PM_RECEIVER_VSIM_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* set up dual-voltage GPIOs to 1.8V */ + pbias_lite = readl(&t2_base->pbias_lite); + pbias_lite &= ~PBIASLITEVMODE1; + pbias_lite |= PBIASLITEPWRDNZ1; + writel(pbias_lite, &t2_base->pbias_lite); + if (get_cpu_family() == CPU_OMAP36XX) + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) | + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ, + OMAP34XX_CTRL_WKUP_CTRL); + setup_net_chip(); omap_die_id_display(); - set_fdt(); + set_led(); + + set_boardname(); return 0; } @@ -292,22 +257,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) *mtdparts = parts; } } - -/* - * Routine: set_muxconf_regs - * Description: Setting up the configuration Mux registers specific to the - * hardware. Many pins need to be moved from protect to primary - * mode. - */ -void set_muxconf_regs(void) -{ - MUX_DEFAULT(); - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - MUX_IGEP0020(); -#endif - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - MUX_IGEP0030(); -#endif -} diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 5698efab5d..1cbe7c94d9 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -103,6 +103,8 @@ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\ @@ -117,13 +119,10 @@ MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\ MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\ MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\ + MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */ #endif - -#define MUX_IGEP0020() \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\ - -#define MUX_IGEP0030() \ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */ diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c new file mode 100644 index 0000000000..eb705cbe88 --- /dev/null +++ b/board/isee/igep00x0/spl.c @@ -0,0 +1,64 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include "igep00x0.h" + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int mfr, id, err = identify_nand_chip(&mfr, &id); + + timings->mr = MICRON_V_MR_165; + if (!err) { + switch (mfr) { + case NAND_MFR_HYNIX: + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + break; + case NAND_MFR_MICRON: + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + break; + default: + /* Should not happen... */ + break; + } + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + } +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif diff --git a/board/spear/common/Makefile b/board/spear/common/Makefile deleted file mode 100644 index b0ba320481..0000000000 --- a/board/spear/common/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -# necessary to create built-in.o -obj- := __dummy__.o -else -obj-y := spr_misc.o -obj-y += spr_lowlevel_init.o -endif diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index 72bff92a9a..6e12275b40 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -1726,7 +1726,7 @@ int mtdparts_init(void) const char *ids, *parts; const char *current_partition; int ids_changed; - char tmp_ep[PARTITION_MAXLEN]; + char tmp_ep[PARTITION_MAXLEN + 1]; char tmp_parts[MTDPARTS_MAXLEN]; debug("\n---mtdparts_init---\n"); @@ -1750,7 +1750,7 @@ int mtdparts_init(void) /* save it for later parsing, cannot rely on current partition pointer * as 'partition' variable may be updated during init */ - tmp_ep[0] = '\0'; + memset(tmp_parts, 0, sizeof(tmp_parts)); if (current_partition) strncpy(tmp_ep, current_partition, PARTITION_MAXLEN); @@ -118,6 +118,11 @@ static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) case SPL_EXPORT_FDT: printf("Argument image is now in RAM: 0x%p\n", (void *)images.ft_addr); + env_set_addr("fdtargsaddr", images.ft_addr); + env_set_hex("fdtargslen", fdt_totalsize(images.ft_addr)); + if (fdt_totalsize(images.ft_addr) > + CONFIG_CMD_SPL_WRITE_SIZE) + puts("WARN: FDT size > CMD_SPL_WRITE_SIZE\n"); break; #endif case SPL_EXPORT_ATAGS: diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 11be1ad27f..ad93602c13 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -14,6 +14,8 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/am57xx_evm_nodt_defconfig b/configs/am57xx_evm_nodt_defconfig index a6ad0d36e0..e6f71e9133 100644 --- a/configs/am57xx_evm_nodt_defconfig +++ b/configs/am57xx_evm_nodt_defconfig @@ -6,6 +6,8 @@ CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index 91baa2b53e..5cd34561a7 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 8661d9f098..c231f5f8ab 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index 4c0595d7a2..e19d564eaf 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index d8c981983e..f183c42e64 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index b87255fa38..dbeae9d26a 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index be221a6cd1..e84c139254 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index 78faadfd8a..148d71fca3 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_LCD=y diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index a4a65c9b80..f9de34ed5b 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index a4a65c9b80..f9de34ed5b 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 13ba9de56f..ef7a79d7b6 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index f08e7ae9a4..462e500afc 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -53,6 +53,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 52811596b4..3aee6f51af 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -53,6 +53,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index bac13a3fbc..08dc34eab8 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -51,6 +51,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index c1d52149e7..9a07b6f6fc 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -51,6 +51,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index 8a7d8777d2..71f8864371 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 170242b24b..a14471c795 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index 8715728845..fb47c04c75 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index e51a827395..57013f8982 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 9c36b6b18a..c8ce33542f 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 1e5d78f46c..99632c6429 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 9f7a3aa062..6cdcb04a40 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 9fa6894eb2..6279d1f63c 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -48,6 +48,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 9eec6e8980..1ccc21c3f8 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -52,4 +52,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index af7643d4c0..b7497bff2f 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -52,4 +52,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index 7a756f6713..4bdd1c0615 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -52,4 +52,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index 2e940398f8..9bd1e54bdd 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 98612dd56a..6b2933549c 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 6a007fd3e9..656af4f705 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 9f09997f0c..8ec0c8f0cb 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -54,6 +54,8 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index c69d27f1c8..d1390fb540 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index cf734a5063..8e2009b524 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 226e54f9f9..a530cf2454 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -49,5 +49,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 4fff0cf734..0357abc6cd 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -14,6 +14,8 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 5572472d01..246de12543 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -20,6 +20,8 @@ CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y CONFIG_OF_BOARD_SETUP=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="androidboot.serialno=${serial#} console=ttyS0,115200 androidboot.console=ttyS0 androidboot.hardware=jacinto6evmboard" CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_VERSION_VARIABLE=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index 1a27fcfcaa..c3e22daa61 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -22,6 +22,8 @@ CONFIG_CMD_PART=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_PHYLIB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig deleted file mode 100644 index abf83c2522..0000000000 --- a/configs/igep0030_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_TARGET_OMAP3_IGEP00X0=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030" -CONFIG_ENV_IS_NOWHERE=y -CONFIG_BOOTDELAY=3 -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_VERSION_VARIABLE=y -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y -# CONFIG_SPL_EXT_SUPPORT is not set -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ONENAND_SUPPORT=y -CONFIG_SPL_OS_BOOT=y -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_SPL=y -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_ONENAND=y -CONFIG_CMD_SPI=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=16 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 -CONFIG_MMC_OMAP_HS=y -CONFIG_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_OMAP3_SPI=y -CONFIG_FAT_WRITE=y -CONFIG_OF_LIBFDT=y -CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/igep0020_defconfig b/configs/igep00x0_defconfig index 600434a4bb..1cdc73d766 100644 --- a/configs/igep0020_defconfig +++ b/configs/igep00x0_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y CONFIG_TARGET_OMAP3_IGEP00X0=y CONFIG_DISTRO_DEFAULTS=y CONFIG_OF_BOARD_SETUP=y -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020" CONFIG_ENV_IS_NOWHERE=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -31,13 +30,6 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_LED_STATUS=y -CONFIG_LED_STATUS_GPIO=y -CONFIG_LED_STATUS0=y -CONFIG_LED_STATUS_BIT=27 -CONFIG_LED_STATUS_STATE=2 -CONFIG_LED_STATUS_BOOT_ENABLE=y -CONFIG_LED_STATUS_BOOT=0 CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index 63d1e4042d..5150eed79c 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 343cb197a1..caceb85b07 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index 6c9f2e32b5..e3dd1b9124 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 6b3cec5ce0..eaf9bb9189 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_DM_KEYBOARD=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_BCM2835=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 2bfd61b08f..d59fd8216c 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -71,6 +71,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 07fb71b769..a997aa74bd 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -69,6 +69,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index 6cc9bb64c6..930700f7c3 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -53,4 +53,6 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 6c24a0d22f..b75e4269bc 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -53,5 +53,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 168bf1961e..e3f67da1c4 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -53,5 +53,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_LCD=y CONFIG_FAT_WRITE=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index e8a9ee9d2d..b7d445ad68 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -66,6 +66,9 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index f3c338c0ac..5539616163 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -63,6 +63,9 @@ CONFIG_DEBUG_UART_CLOCK=132000000 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 32b4c422aa..2843e3b5de 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -72,6 +72,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index c1ddfd03d6..fd4d5311f4 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -67,6 +67,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 823cdcce7d..9434017341 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -68,6 +68,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 09da2e0855..de0ce40a56 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -66,6 +66,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5ac5d08527..cba3c8b640 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -63,6 +63,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 131d0e5b9d..174e2bc5ba 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -65,6 +65,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 395a01760f..ade4d30eaf 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -69,6 +69,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 9eab7f712b..378a03c17a 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -66,6 +66,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index f25ca9cfdb..ff94d7a113 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -65,6 +65,9 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_DM_SPI=y CONFIG_ATMEL_SPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/disk/part_iso.c b/disk/part_iso.c index bb8ed658f2..8aef251f4e 100644 --- a/disk/part_iso.c +++ b/disk/part_iso.c @@ -24,7 +24,7 @@ #undef CHECK_FOR_POWERPC_PLATTFORM #define CD_SECTSIZE 2048 -static unsigned char tmpbuf[CD_SECTSIZE]; +static unsigned char tmpbuf[CD_SECTSIZE] __aligned(ARCH_DMA_MINALIGN); unsigned long iso_dread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, void *buffer) diff --git a/doc/README.falcon b/doc/README.falcon index e9f8a7583c..9a7f0bc235 100644 --- a/doc/README.falcon +++ b/doc/README.falcon @@ -118,7 +118,12 @@ after each run of 'spl export'. Unfortunately the position of temporary storage can not be predicted nor provided at commandline, it depends highly on your system setup and your provided data (ATAGS or FDT). However at the end of an succesful 'spl export' run it will print the -RAM address of temporary storage. +RAM address of temporary storage. The RAM address of FDT will also be +set in the environment variable 'fdtargsaddr', the new length of the +prepared FDT will be set in the environment variable 'fdtargslen'. +These environment variables can be used in scripts for writing updated +FDT to persistent storage. + Now the user have to save the generated BLOB from that printed address to the pre-defined address in persistent storage (CONFIG_CMD_SPL_NAND_OFS in case of NAND). diff --git a/doc/device-tree-bindings/i2c/i2c-stm32.txt b/doc/device-tree-bindings/i2c/i2c-stm32.txt new file mode 100644 index 0000000000..df03743ace --- /dev/null +++ b/doc/device-tree-bindings/i2c/i2c-stm32.txt @@ -0,0 +1,30 @@ +* I2C controller embedded in STMicroelectronis STM32 platforms + +Required properties : +- compatible : Must be "st,stm32f7-i2c" +- reg : Offset and length of the register set for the device +- resets: Must contain the phandle to the reset controller +- clocks: Must contain the input clock of the I2C instance +- A pinctrl state named "default" must be defined to set pins in mode of + operation for I2C transfer +- #address-cells = <1>; +- #size-cells = <0>; + +Optional properties : +- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified, + the default 100 kHz frequency will be used. As only Normal, Fast and Fast+ + modes are implemented, possible values are 100000, 400000 and 1000000. + +Example : + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + resets = <&rcc 181>; + clocks = <&clk_pclk1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/doc/uImage.FIT/signature.txt b/doc/uImage.FIT/signature.txt index 7cdb7bf324..a57cdab339 100644 --- a/doc/uImage.FIT/signature.txt +++ b/doc/uImage.FIT/signature.txt @@ -81,7 +81,7 @@ $ openssl rsa -in keys/dev.key -pubout Device Tree Bindings -------------------- The following properties are required in the FIT's signature node(s) to -allow thes signer to operate. These should be added to the .its file. +allow the signer to operate. These should be added to the .its file. Signature nodes sit at the same level as hash nodes and are called signature@1, signature@2, etc. @@ -150,7 +150,7 @@ all available signing keys until one matches. - required: If present this indicates that the key must be verified for the image / configuration to be considered valid. Only required keys are normally verified by the FIT image booting algorithm. Valid values are -"image" to force verification of all images, and "conf" to force verfication +"image" to force verification of all images, and "conf" to force verification of the selected configuration (which then relies on hashes in the images to verify those). @@ -242,7 +242,7 @@ configuration 3 with kernel 1 and fdt 2: With signed images, nothing protects against this. Whether it gains an advantage for the attacker is debatable, but it is not secure. -To solved this problem, we support signed configurations. In this case it +To solve this problem, we support signed configurations. In this case it is the configurations that are signed, not the image. Each image has its own hash, and we include the hash in the configuration signature. @@ -327,7 +327,7 @@ Enabling FIT Verification In addition to the options to enable FIT itself, the following CONFIGs must be enabled: -CONFIG_FIT_SIGNATURE - enable signing and verfication in FITs +CONFIG_FIT_SIGNATURE - enable signing and verification in FITs CONFIG_RSA - enable RSA algorithm for signing WARNING: When relying on signed FIT images with required signature check @@ -336,7 +336,7 @@ CONFIG_IMAGE_FORMAT_LEGACY Testing ------- -An easy way to test signing and verfication is to use the test script +An easy way to test signing and verification is to use the test script provided in test/vboot/vboot_test.sh. This uses sandbox (a special version of U-Boot which runs under Linux) to show the operation of a 'bootm' command loading and verifying images. diff --git a/doc/uImage.FIT/verified-boot.txt b/doc/uImage.FIT/verified-boot.txt index e639e7ae71..41c9fa9e09 100644 --- a/doc/uImage.FIT/verified-boot.txt +++ b/doc/uImage.FIT/verified-boot.txt @@ -93,7 +93,7 @@ include hashes to verify images, so it is relatively straightforward to add signatures as well. The public key can be stored in U-Boot's CONFIG_OF_CONTROL device tree in -a standard place. Then when a FIT it loaded it can be verified using that +a standard place. Then when a FIT is loaded it can be verified using that public key. Multiple keys and multiple signatures are supported. See signature.txt for more information. diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 720e82d5de..d2d9367bfc 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -174,6 +174,26 @@ config SYS_I2C_S3C24X0 help Support for Samsung I2C controller as Samsung SoCs. +config SYS_I2C_STM32F7 + bool "STMicroelectronics STM32F7 I2C support" + depends on (STM32F7 || STM32H7) && DM_I2C + help + Enable this option to add support for STM32 I2C controller + introduced with STM32F7/H7 SoCs. This I2C controller supports : + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset + config SYS_I2C_UNIPHIER bool "UniPhier I2C driver" depends on ARCH_UNIPHIER && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 4f754191e2..e7ade94d91 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o +obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 48900ed2af..156380c1cc 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -34,3 +34,12 @@ config I2C_MUX_PCA954x paritioning I2C bus and connect multiple devices with the same address to the same I2C controller where driver handles proper routing to target i2c device. PCA9544 and PCA9548 are supported. + +config I2C_MUX_GPIO + tristate "GPIO-based I2C multiplexer" + depends on I2C_MUX && DM_GPIO + help + If you say yes to this option, support will be included for + a GPIO based I2C multiplexer. This driver provides access to + I2C busses connected through a MUX, which is controlled + through GPIO pins. diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index 0811add421..3831f4e4fb 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o +obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c new file mode 100644 index 0000000000..0269b3a18e --- /dev/null +++ b/drivers/i2c/muxes/i2c-mux-gpio.c @@ -0,0 +1,138 @@ +/* + * I2C multiplexer using GPIO API + * + * Copyright 2017 NXP + * + * Peng Fan <peng.fan@nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <asm-generic/gpio.h> +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <fdtdec.h> +#include <i2c.h> +#include <linux/errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * struct i2c_mux_gpio_priv - private data for i2c mux gpio + * + * @values: the reg value of each child node + * @n_values: num of regs + * @gpios: the mux-gpios array + * @n_gpios: num of gpios in mux-gpios + * @idle: the value of idle-state + */ +struct i2c_mux_gpio_priv { + u32 *values; + int n_values; + struct gpio_desc *gpios; + int n_gpios; + u32 idle; +}; + + +static int i2c_mux_gpio_select(struct udevice *dev, struct udevice *bus, + uint channel) +{ + struct i2c_mux_gpio_priv *priv = dev_get_priv(dev); + int i, ret; + + for (i = 0; i < priv->n_gpios; i++) { + ret = dm_gpio_set_value(&priv->gpios[i], (channel >> i) & 1); + if (ret) + return ret; + } + + return 0; +} + +static int i2c_mux_gpio_deselect(struct udevice *dev, struct udevice *bus, + uint channel) +{ + struct i2c_mux_gpio_priv *priv = dev_get_priv(dev); + int i, ret; + + for (i = 0; i < priv->n_gpios; i++) { + ret = dm_gpio_set_value(&priv->gpios[i], (priv->idle >> i) & 1); + if (ret) + return ret; + } + + return 0; +} + +static int i2c_mux_gpio_probe(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + struct i2c_mux_gpio_priv *mux = dev_get_priv(dev); + struct gpio_desc *gpios; + u32 *values; + int i = 0, subnode, ret; + + mux->n_values = fdtdec_get_child_count(fdt, node); + values = devm_kzalloc(dev, sizeof(*mux->values) * mux->n_values, + GFP_KERNEL); + if (!values) { + dev_err(dev, "Cannot alloc values array"); + return -ENOMEM; + } + + fdt_for_each_subnode(subnode, fdt, node) { + *(values + i) = fdtdec_get_uint(fdt, subnode, "reg", -1); + i++; + } + + mux->values = values; + + mux->idle = fdtdec_get_uint(fdt, node, "idle-state", -1); + + mux->n_gpios = gpio_get_list_count(dev, "mux-gpios"); + if (mux->n_gpios < 0) { + dev_err(dev, "Missing mux-gpios property\n"); + return -EINVAL; + } + + gpios = devm_kzalloc(dev, sizeof(struct gpio_desc) * mux->n_gpios, + GFP_KERNEL); + if (!gpios) { + dev_err(dev, "Cannot allocate gpios array\n"); + return -ENOMEM; + } + + ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios, + GPIOD_IS_OUT_ACTIVE); + if (ret <= 0) { + dev_err(dev, "Failed to request mux-gpios\n"); + return ret; + } + + mux->gpios = gpios; + + return 0; +} + +static const struct i2c_mux_ops i2c_mux_gpio_ops = { + .select = i2c_mux_gpio_select, + .deselect = i2c_mux_gpio_deselect, +}; + +static const struct udevice_id i2c_mux_gpio_ids[] = { + { .compatible = "i2c-mux-gpio", }, + {} +}; + +U_BOOT_DRIVER(i2c_mux_gpio) = { + .name = "i2c_mux_gpio", + .id = UCLASS_I2C_MUX, + .of_match = i2c_mux_gpio_ids, + .ops = &i2c_mux_gpio_ops, + .probe = i2c_mux_gpio_probe, + .priv_auto_alloc_size = sizeof(struct i2c_mux_gpio_priv), +}; diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c new file mode 100644 index 0000000000..bf5fefab7b --- /dev/null +++ b/drivers/i2c/stm32f7_i2c.c @@ -0,0 +1,882 @@ +/* + * (C) Copyright 2017 STMicroelectronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <i2c.h> +#include <reset.h> + +#include <dm/device.h> +#include <linux/io.h> + +/* STM32 I2C registers */ +struct stm32_i2c_regs { + u32 cr1; /* I2C control register 1 */ + u32 cr2; /* I2C control register 2 */ + u32 oar1; /* I2C own address 1 register */ + u32 oar2; /* I2C own address 2 register */ + u32 timingr; /* I2C timing register */ + u32 timeoutr; /* I2C timeout register */ + u32 isr; /* I2C interrupt and status register */ + u32 icr; /* I2C interrupt clear register */ + u32 pecr; /* I2C packet error checking register */ + u32 rxdr; /* I2C receive data register */ + u32 txdr; /* I2C transmit data register */ +}; + +#define STM32_I2C_CR1 0x00 +#define STM32_I2C_CR2 0x04 +#define STM32_I2C_TIMINGR 0x10 +#define STM32_I2C_ISR 0x18 +#define STM32_I2C_ICR 0x1C +#define STM32_I2C_RXDR 0x24 +#define STM32_I2C_TXDR 0x28 + +/* STM32 I2C control 1 */ +#define STM32_I2C_CR1_ANFOFF BIT(12) +#define STM32_I2C_CR1_ERRIE BIT(7) +#define STM32_I2C_CR1_TCIE BIT(6) +#define STM32_I2C_CR1_STOPIE BIT(5) +#define STM32_I2C_CR1_NACKIE BIT(4) +#define STM32_I2C_CR1_ADDRIE BIT(3) +#define STM32_I2C_CR1_RXIE BIT(2) +#define STM32_I2C_CR1_TXIE BIT(1) +#define STM32_I2C_CR1_PE BIT(0) + +/* STM32 I2C control 2 */ +#define STM32_I2C_CR2_AUTOEND BIT(25) +#define STM32_I2C_CR2_RELOAD BIT(24) +#define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) +#define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) +#define STM32_I2C_CR2_NACK BIT(15) +#define STM32_I2C_CR2_STOP BIT(14) +#define STM32_I2C_CR2_START BIT(13) +#define STM32_I2C_CR2_HEAD10R BIT(12) +#define STM32_I2C_CR2_ADD10 BIT(11) +#define STM32_I2C_CR2_RD_WRN BIT(10) +#define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) +#define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK)) +#define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) +#define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) +#define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ + | STM32_I2C_CR2_NBYTES_MASK \ + | STM32_I2C_CR2_SADD7_MASK \ + | STM32_I2C_CR2_RELOAD \ + | STM32_I2C_CR2_RD_WRN) + +/* STM32 I2C Interrupt Status */ +#define STM32_I2C_ISR_BUSY BIT(15) +#define STM32_I2C_ISR_ARLO BIT(9) +#define STM32_I2C_ISR_BERR BIT(8) +#define STM32_I2C_ISR_TCR BIT(7) +#define STM32_I2C_ISR_TC BIT(6) +#define STM32_I2C_ISR_STOPF BIT(5) +#define STM32_I2C_ISR_NACKF BIT(4) +#define STM32_I2C_ISR_ADDR BIT(3) +#define STM32_I2C_ISR_RXNE BIT(2) +#define STM32_I2C_ISR_TXIS BIT(1) +#define STM32_I2C_ISR_TXE BIT(0) +#define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \ + | STM32_I2C_ISR_ARLO) + +/* STM32 I2C Interrupt Clear */ +#define STM32_I2C_ICR_ARLOCF BIT(9) +#define STM32_I2C_ICR_BERRCF BIT(8) +#define STM32_I2C_ICR_STOPCF BIT(5) +#define STM32_I2C_ICR_NACKCF BIT(4) + +/* STM32 I2C Timing */ +#define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28) +#define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20) +#define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16) +#define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8) +#define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff) + +#define STM32_I2C_MAX_LEN 0xff + +#define STM32_I2C_DNF_DEFAULT 0 +#define STM32_I2C_DNF_MAX 16 + +#define STM32_I2C_ANALOG_FILTER_ENABLE 1 +#define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ +#define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ + +#define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ +#define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ + +#define STM32_PRESC_MAX BIT(4) +#define STM32_SCLDEL_MAX BIT(4) +#define STM32_SDADEL_MAX BIT(4) +#define STM32_SCLH_MAX BIT(8) +#define STM32_SCLL_MAX BIT(8) + +#define STM32_NSEC_PER_SEC 1000000000L + +#define STANDARD_RATE 100000 +#define FAST_RATE 400000 +#define FAST_PLUS_RATE 1000000 + +enum stm32_i2c_speed { + STM32_I2C_SPEED_STANDARD, /* 100 kHz */ + STM32_I2C_SPEED_FAST, /* 400 kHz */ + STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ + STM32_I2C_SPEED_END, +}; + +/** + * struct stm32_i2c_spec - private i2c specification timing + * @rate: I2C bus speed (Hz) + * @rate_min: 80% of I2C bus speed (Hz) + * @rate_max: 120% of I2C bus speed (Hz) + * @fall_max: Max fall time of both SDA and SCL signals (ns) + * @rise_max: Max rise time of both SDA and SCL signals (ns) + * @hddat_min: Min data hold time (ns) + * @vddat_max: Max data valid time (ns) + * @sudat_min: Min data setup time (ns) + * @l_min: Min low period of the SCL clock (ns) + * @h_min: Min high period of the SCL clock (ns) + */ + +struct stm32_i2c_spec { + u32 rate; + u32 rate_min; + u32 rate_max; + u32 fall_max; + u32 rise_max; + u32 hddat_min; + u32 vddat_max; + u32 sudat_min; + u32 l_min; + u32 h_min; +}; + +/** + * struct stm32_i2c_setup - private I2C timing setup parameters + * @speed: I2C speed mode (standard, Fast Plus) + * @speed_freq: I2C speed frequency (Hz) + * @clock_src: I2C clock source frequency (Hz) + * @rise_time: Rise time (ns) + * @fall_time: Fall time (ns) + * @dnf: Digital filter coefficient (0-16) + * @analog_filter: Analog filter delay (On/Off) + */ +struct stm32_i2c_setup { + enum stm32_i2c_speed speed; + u32 speed_freq; + u32 clock_src; + u32 rise_time; + u32 fall_time; + u8 dnf; + bool analog_filter; +}; + +/** + * struct stm32_i2c_timings - private I2C output parameters + * @prec: Prescaler value + * @scldel: Data setup time + * @sdadel: Data hold time + * @sclh: SCL high period (master mode) + * @sclh: SCL low period (master mode) + */ +struct stm32_i2c_timings { + struct list_head node; + u8 presc; + u8 scldel; + u8 sdadel; + u8 sclh; + u8 scll; +}; + +struct stm32_i2c_priv { + struct stm32_i2c_regs *regs; + struct clk clk; + struct stm32_i2c_setup *setup; + int speed; +}; + +static struct stm32_i2c_spec i2c_specs[] = { + [STM32_I2C_SPEED_STANDARD] = { + .rate = STANDARD_RATE, + .rate_min = 8000, + .rate_max = 120000, + .fall_max = 300, + .rise_max = 1000, + .hddat_min = 0, + .vddat_max = 3450, + .sudat_min = 250, + .l_min = 4700, + .h_min = 4000, + }, + [STM32_I2C_SPEED_FAST] = { + .rate = FAST_RATE, + .rate_min = 320000, + .rate_max = 480000, + .fall_max = 300, + .rise_max = 300, + .hddat_min = 0, + .vddat_max = 900, + .sudat_min = 100, + .l_min = 1300, + .h_min = 600, + }, + [STM32_I2C_SPEED_FAST_PLUS] = { + .rate = FAST_PLUS_RATE, + .rate_min = 800000, + .rate_max = 1200000, + .fall_max = 100, + .rise_max = 120, + .hddat_min = 0, + .vddat_max = 450, + .sudat_min = 50, + .l_min = 500, + .h_min = 260, + }, +}; + +static struct stm32_i2c_setup stm32f7_setup = { + .rise_time = STM32_I2C_RISE_TIME_DEFAULT, + .fall_time = STM32_I2C_FALL_TIME_DEFAULT, + .dnf = STM32_I2C_DNF_DEFAULT, + .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, +}; + +DECLARE_GLOBAL_DATA_PTR; + +static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 status = readl(®s->isr); + + if (status & STM32_I2C_ISR_BUSY) + return -EBUSY; + + return 0; +} + +static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); + + /* Set transfer direction */ + cr2 &= ~STM32_I2C_CR2_RD_WRN; + if (msg->flags & I2C_M_RD) + cr2 |= STM32_I2C_CR2_RD_WRN; + + /* Set slave address */ + cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10); + if (msg->flags & I2C_M_TEN) { + cr2 &= ~STM32_I2C_CR2_SADD10_MASK; + cr2 |= STM32_I2C_CR2_SADD10(msg->addr); + cr2 |= STM32_I2C_CR2_ADD10; + } else { + cr2 &= ~STM32_I2C_CR2_SADD7_MASK; + cr2 |= STM32_I2C_CR2_SADD7(msg->addr); + } + + /* Set nb bytes to transfer and reload or autoend bits */ + cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD | + STM32_I2C_CR2_AUTOEND); + if (msg->len > STM32_I2C_MAX_LEN) { + cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); + cr2 |= STM32_I2C_CR2_RELOAD; + } else { + cr2 |= STM32_I2C_CR2_NBYTES(msg->len); + } + + /* Write configurations register */ + writel(cr2, ®s->cr2); + + /* START/ReSTART generation */ + setbits_le32(®s->cr2, STM32_I2C_CR2_START); +} + +/* + * RELOAD mode must be selected if total number of data bytes to be + * sent is greater than MAX_LEN + */ + +static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 cr2 = readl(®s->cr2); + + cr2 &= ~STM32_I2C_CR2_NBYTES_MASK; + + if (msg->len > STM32_I2C_MAX_LEN) { + cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); + } else { + cr2 &= ~STM32_I2C_CR2_RELOAD; + cr2 |= STM32_I2C_CR2_NBYTES(msg->len); + } + + writel(cr2, ®s->cr2); +} + +static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, + u32 flags, u32 *status) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 time_start = get_timer(0); + + *status = readl(®s->isr); + while (!(*status & flags)) { + if (get_timer(time_start) > CONFIG_SYS_HZ) { + debug("%s: i2c timeout\n", __func__); + return -ETIMEDOUT; + } + + *status = readl(®s->isr); + } + + return 0; +} + +static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF | + STM32_I2C_ISR_STOPF; + u32 status; + int ret; + + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + return ret; + + if (status & STM32_I2C_ISR_BERR) { + debug("%s: Bus error\n", __func__); + + /* Clear BERR flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); + + return -EIO; + } + + if (status & STM32_I2C_ISR_ARLO) { + debug("%s: Arbitration lost\n", __func__); + + /* Clear ARLO flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); + + return -EAGAIN; + } + + if (status & STM32_I2C_ISR_NACKF) { + debug("%s: Receive NACK\n", __func__); + + /* Clear NACK flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); + + /* Wait until STOPF flag is set */ + mask = STM32_I2C_ISR_STOPF; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + return ret; + + ret = -EIO; + } + + if (status & STM32_I2C_ISR_STOPF) { + /* Clear STOP flag */ + setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); + + /* Clear control register 2 */ + setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); + } + + return ret; +} + +static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, + struct i2c_msg *msg, bool stop) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + u32 status; + u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : + STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; + int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? + STM32_I2C_MAX_LEN : msg->len; + int ret = 0; + + /* Add errors */ + mask |= STM32_I2C_ISR_ERRORS; + + stm32_i2c_message_start(i2c_priv, msg, stop); + + while (msg->len) { + /* + * Wait until TXIS/NACKF/BERR/ARLO flags or + * RXNE/BERR/ARLO flags are set + */ + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS)) + break; + + if (status & STM32_I2C_ISR_RXNE) { + *msg->buf++ = readb(®s->rxdr); + msg->len--; + bytes_to_rw--; + } + + if (status & STM32_I2C_ISR_TXIS) { + writeb(*msg->buf++, ®s->txdr); + msg->len--; + bytes_to_rw--; + } + + if (!bytes_to_rw && msg->len) { + /* Wait until TCR flag is set */ + mask = STM32_I2C_ISR_TCR; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? + STM32_I2C_MAX_LEN : msg->len; + mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : + STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; + + stm32_i2c_handle_reload(i2c_priv, msg, stop); + } else if (!bytes_to_rw) { + /* Wait until TC flag is set */ + mask = STM32_I2C_ISR_TC; + ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); + if (ret) + break; + + if (!stop) + /* Message sent, new message has to be sent */ + return 0; + } + } + + /* End of transfer, send stop condition */ + mask = STM32_I2C_CR2_STOP; + setbits_le32(®s->cr2, mask); + + return stm32_i2c_check_end_of_message(i2c_priv); +} + +static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, + int nmsgs) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); + int ret; + + ret = stm32_i2c_check_device_busy(i2c_priv); + if (ret) + return ret; + + for (; nmsgs > 0; nmsgs--, msg++) { + ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1); + if (ret) + return ret; + } + + return 0; +} + +static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, + struct list_head *solutions) +{ + struct stm32_i2c_timings *v; + u32 p_prev = STM32_PRESC_MAX; + u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->clock_src); + u32 af_delay_min, af_delay_max; + u16 p, l, a; + int sdadel_min, sdadel_max, scldel_min; + int ret = 0; + + af_delay_min = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; + af_delay_max = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; + + sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min - + af_delay_min - (setup->dnf + 3) * i2cclk; + + sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - + af_delay_max - (setup->dnf + 4) * i2cclk; + + scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; + + if (sdadel_min < 0) + sdadel_min = 0; + if (sdadel_max < 0) + sdadel_max = 0; + + debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__, + sdadel_min, sdadel_max, scldel_min); + + /* Compute possible values for PRESC, SCLDEL and SDADEL */ + for (p = 0; p < STM32_PRESC_MAX; p++) { + for (l = 0; l < STM32_SCLDEL_MAX; l++) { + u32 scldel = (l + 1) * (p + 1) * i2cclk; + + if (scldel < scldel_min) + continue; + + for (a = 0; a < STM32_SDADEL_MAX; a++) { + u32 sdadel = (a * (p + 1) + 1) * i2cclk; + + if (((sdadel >= sdadel_min) && + (sdadel <= sdadel_max)) && + (p != p_prev)) { + v = kmalloc(sizeof(*v), GFP_KERNEL); + if (!v) + return -ENOMEM; + + v->presc = p; + v->scldel = l; + v->sdadel = a; + p_prev = p; + + list_add_tail(&v->node, solutions); + } + } + } + } + + if (list_empty(solutions)) { + error("%s: no Prescaler solution\n", __func__); + ret = -EPERM; + } + + return ret; +} + +static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, + struct list_head *solutions, + struct stm32_i2c_timings *s) +{ + struct stm32_i2c_timings *v; + u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->speed_freq); + u32 clk_error_prev = i2cbus; + u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, + setup->clock_src); + u32 clk_min, clk_max; + u32 af_delay_min; + u32 dnf_delay; + u32 tsync; + u16 l, h; + int ret = 0; + + af_delay_min = setup->analog_filter ? + STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; + dnf_delay = setup->dnf * i2cclk; + + tsync = af_delay_min + dnf_delay + (2 * i2cclk); + clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; + clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; + + /* + * Among Prescaler possibilities discovered above figures out SCL Low + * and High Period. Provided: + * - SCL Low Period has to be higher than Low Period of the SCL Clock + * defined by I2C Specification. I2C Clock has to be lower than + * (SCL Low Period - Analog/Digital filters) / 4. + * - SCL High Period has to be lower than High Period of the SCL Clock + * defined by I2C Specification + * - I2C Clock has to be lower than SCL High Period + */ + list_for_each_entry(v, solutions, node) { + u32 prescaler = (v->presc + 1) * i2cclk; + + for (l = 0; l < STM32_SCLL_MAX; l++) { + u32 tscl_l = (l + 1) * prescaler + tsync; + if ((tscl_l < i2c_specs[setup->speed].l_min) || + (i2cclk >= + ((tscl_l - af_delay_min - dnf_delay) / 4))) { + continue; + } + + for (h = 0; h < STM32_SCLH_MAX; h++) { + u32 tscl_h = (h + 1) * prescaler + tsync; + u32 tscl = tscl_l + tscl_h + + setup->rise_time + setup->fall_time; + + if ((tscl >= clk_min) && (tscl <= clk_max) && + (tscl_h >= i2c_specs[setup->speed].h_min) && + (i2cclk < tscl_h)) { + int clk_error = tscl - i2cbus; + + if (clk_error < 0) + clk_error = -clk_error; + + if (clk_error < clk_error_prev) { + clk_error_prev = clk_error; + v->scll = l; + v->sclh = h; + s = v; + } + } + } + } + } + + if (!s) { + error("%s: no solution at all\n", __func__); + ret = -EPERM; + } + + return ret; +} + +static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, + struct stm32_i2c_setup *setup, + struct stm32_i2c_timings *output) +{ + struct stm32_i2c_timings *v, *_v, *s; + struct list_head solutions; + int ret; + + if (setup->speed >= STM32_I2C_SPEED_END) { + error("%s: speed out of bound {%d/%d}\n", __func__, + setup->speed, STM32_I2C_SPEED_END - 1); + return -EINVAL; + } + + if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || + (setup->fall_time > i2c_specs[setup->speed].fall_max)) { + error("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", + __func__, + setup->rise_time, i2c_specs[setup->speed].rise_max, + setup->fall_time, i2c_specs[setup->speed].fall_max); + return -EINVAL; + } + + if (setup->dnf > STM32_I2C_DNF_MAX) { + error("%s: DNF out of bound %d/%d\n", __func__, + setup->dnf, STM32_I2C_DNF_MAX); + return -EINVAL; + } + + if (setup->speed_freq > i2c_specs[setup->speed].rate) { + error("%s: Freq {%d/%d}\n", __func__, + setup->speed_freq, i2c_specs[setup->speed].rate); + return -EINVAL; + } + + s = NULL; + INIT_LIST_HEAD(&solutions); + ret = stm32_i2c_compute_solutions(setup, &solutions); + if (ret) + goto exit; + + ret = stm32_i2c_choose_solution(setup, &solutions, s); + if (ret) + goto exit; + + output->presc = s->presc; + output->scldel = s->scldel; + output->sdadel = s->sdadel; + output->scll = s->scll; + output->sclh = s->sclh; + + debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", + __func__, output->presc, + output->scldel, output->sdadel, + output->scll, output->sclh); + +exit: + /* Release list and memory */ + list_for_each_entry_safe(v, _v, &solutions, node) { + list_del(&v->node); + kfree(v); + } + + return ret; +} + +static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, + struct stm32_i2c_timings *timing) +{ + struct stm32_i2c_setup *setup = i2c_priv->setup; + int ret = 0; + + setup->speed = i2c_priv->speed; + setup->speed_freq = i2c_specs[setup->speed].rate; + setup->clock_src = clk_get_rate(&i2c_priv->clk); + + if (!setup->clock_src) { + error("%s: clock rate is 0\n", __func__); + return -EINVAL; + } + + do { + ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); + if (ret) { + debug("%s: failed to compute I2C timings.\n", + __func__); + if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) { + i2c_priv->speed--; + setup->speed = i2c_priv->speed; + setup->speed_freq = + i2c_specs[setup->speed].rate; + debug("%s: downgrade I2C Speed Freq to (%i)\n", + __func__, i2c_specs[setup->speed].rate); + } else { + break; + } + } + } while (ret); + + if (ret) { + error("%s: impossible to compute I2C timings.\n", __func__); + return ret; + } + + debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__, + setup->speed, setup->speed_freq, setup->clock_src); + debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, + setup->rise_time, setup->fall_time); + debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, + setup->analog_filter ? "On" : "Off", setup->dnf); + + return 0; +} + +static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) +{ + struct stm32_i2c_regs *regs = i2c_priv->regs; + struct stm32_i2c_timings t; + int ret; + u32 timing = 0; + + ret = stm32_i2c_setup_timing(i2c_priv, &t); + if (ret) + return ret; + + /* Disable I2C */ + clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); + + /* Timing settings */ + timing |= STM32_I2C_TIMINGR_PRESC(t.presc); + timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); + timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel); + timing |= STM32_I2C_TIMINGR_SCLH(t.sclh); + timing |= STM32_I2C_TIMINGR_SCLL(t.scll); + writel(timing, ®s->timingr); + + /* Enable I2C */ + if (i2c_priv->setup->analog_filter) + clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + else + setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); + setbits_le32(®s->cr1, STM32_I2C_CR1_PE); + + return 0; +} + +static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); + + switch (speed) { + case STANDARD_RATE: + i2c_priv->speed = STM32_I2C_SPEED_STANDARD; + break; + case FAST_RATE: + i2c_priv->speed = STM32_I2C_SPEED_FAST; + break; + case FAST_PLUS_RATE: + i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS; + break; + default: + debug("%s: Speed %d not supported\n", __func__, speed); + return -EINVAL; + } + + return stm32_i2c_hw_config(i2c_priv); +} + +static int stm32_i2c_probe(struct udevice *dev) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); + struct reset_ctl reset_ctl; + fdt_addr_t addr; + int ret; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + i2c_priv->regs = (struct stm32_i2c_regs *)addr; + + ret = clk_get_by_index(dev, 0, &i2c_priv->clk); + if (ret) + return ret; + + ret = clk_enable(&i2c_priv->clk); + if (ret) + goto clk_free; + + ret = reset_get_by_index(dev, 0, &reset_ctl); + if (ret) + goto clk_disable; + + reset_assert(&reset_ctl); + udelay(2); + reset_deassert(&reset_ctl); + + return 0; + +clk_disable: + clk_disable(&i2c_priv->clk); +clk_free: + clk_free(&i2c_priv->clk); + + return ret; +} + +static int stm32_ofdata_to_platdata(struct udevice *dev) +{ + struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); + u32 rise_time, fall_time; + + i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); + if (!i2c_priv->setup) + return -EINVAL; + + rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0); + if (rise_time) + i2c_priv->setup->rise_time = rise_time; + + fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0); + if (fall_time) + i2c_priv->setup->fall_time = fall_time; + + return 0; +} + +static const struct dm_i2c_ops stm32_i2c_ops = { + .xfer = stm32_i2c_xfer, + .set_bus_speed = stm32_i2c_set_bus_speed, +}; + +static const struct udevice_id stm32_i2c_of_match[] = { + { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, + {} +}; + +U_BOOT_DRIVER(stm32f7_i2c) = { + .name = "stm32f7-i2c", + .id = UCLASS_I2C, + .of_match = stm32_i2c_of_match, + .ofdata_to_platdata = stm32_ofdata_to_platdata, + .probe = stm32_i2c_probe, + .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv), + .ops = &stm32_i2c_ops, +}; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 42bc2efd90..f3bb72788a 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr) /*----------------------------------------------------------------------- */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) -flash_info_t *flash_get_info(ulong base) +static flash_info_t *flash_get_info(ulong base) { int i; flash_info_t *info; @@ -355,8 +355,8 @@ static ulong flash_read_long (flash_info_t * info, flash_sect_t sect, /* * Write a proper sized command to the correct address */ -void flash_write_cmd (flash_info_t * info, flash_sect_t sect, - uint offset, u32 cmd) +static void flash_write_cmd(flash_info_t *info, flash_sect_t sect, + uint offset, u32 cmd) { void *addr; @@ -2298,7 +2298,7 @@ static void cfi_flash_set_config_reg(u32 base, u16 val) /*----------------------------------------------------------------------- */ -void flash_protect_default(void) +static void flash_protect_default(void) { #if defined(CONFIG_SYS_FLASH_AUTOPROTECT_LIST) int i; diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 836be25507..47969f3f28 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -18,7 +18,7 @@ config SPL_RAM setting up RAM (e.g. SDRAM / DDR) within SPL. config TPL_RAM - bool "Enable RAM support in SPL" + bool "Enable RAM support in TPL" depends on RAM && TPL_DM help The RAM subsystem adds a small amount of overhead to the image. diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 13f122350b..6305bbf01c 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -44,6 +44,14 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ATMEL_PIT_TIMER + bool "Atmel periodic interval timer support" + depends on TIMER + help + Select this to enable a periodic interval timer for Atmel devices, + it is designed to offer maximum accuracy and efficient management, + even for systems with long response time. + config SANDBOX_TIMER bool "Sandbox timer support" depends on SANDBOX && TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index fa7ce7c835..69e8961a7b 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o +obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c new file mode 100644 index 0000000000..999717b91f --- /dev/null +++ b/drivers/timer/atmel_pit_timer.c @@ -0,0 +1,90 @@ +/* + * Copyright (C) 2017 Microchip Corporation + * Wenyou.Yang <wenyou.yang@microchip.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <timer.h> +#include <asm/io.h> + +#define AT91_PIT_VALUE 0xfffff +#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ + +struct atmel_pit_regs { + u32 mode; + u32 status; + u32 value; + u32 value_image; +}; + +struct atmel_pit_platdata { + struct atmel_pit_regs *regs; +}; + +static int atmel_pit_get_count(struct udevice *dev, u64 *count) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + struct atmel_pit_regs *const regs = plat->regs; + u32 val = readl(®s->value_image); + + *count = timer_conv_64(val); + + return 0; +} + +static int atmel_pit_probe(struct udevice *dev) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + struct atmel_pit_regs *const regs = plat->regs; + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk clk; + ulong clk_rate; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -EINVAL; + + uc_priv->clock_rate = clk_rate / 16; + + writel(AT91_PIT_VALUE | AT91_PIT_PITEN, ®s->mode); + + return 0; +} + +static int atmel_pit_ofdata_to_platdata(struct udevice *dev) +{ + struct atmel_pit_platdata *plat = dev_get_platdata(dev); + + plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev); + + return 0; +} + +static const struct timer_ops atmel_pit_ops = { + .get_count = atmel_pit_get_count, +}; + +static const struct udevice_id atmel_pit_ids[] = { + { .compatible = "atmel,at91sam9260-pit" }, + { } +}; + +U_BOOT_DRIVER(atmel_pit) = { + .name = "atmel_pit", + .id = UCLASS_TIMER, + .of_match = atmel_pit_ids, + .ofdata_to_platdata = atmel_pit_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata), + .probe = atmel_pit_probe, + .ops = &atmel_pit_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index 5a25be4c8a..fed6287eac 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -355,7 +355,7 @@ void recover_transaction(int prev_desc_logical_no) ofs = sizeof(struct journal_header_t); do { - tag = (struct ext3_journal_block_tag *)&p_jdb[ofs]; + tag = (struct ext3_journal_block_tag *)(p_jdb + ofs); ofs += sizeof(struct ext3_journal_block_tag); if (ofs > fs->blksz) @@ -466,7 +466,7 @@ int ext4fs_check_journal_state(int recovery_flag) ofs = sizeof(struct journal_header_t); do { tag = (struct ext3_journal_block_tag *) - &p_jdb[ofs]; + (p_jdb + ofs); ofs += sizeof(struct ext3_journal_block_tag); if (ofs > fs->blksz) break; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index f6f06289f4..4ca024c208 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -762,7 +762,7 @@ static int check_overflow(fsdata *mydata, __u32 clustnum, loff_t size) if (offset != 0) sect_num++; - if (startsect + sect_num > cur_part_info.start + total_sector) + if (startsect + sect_num > total_sector) return -1; return 0; } diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index a029b54804..dc137dbd41 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -13,7 +13,6 @@ #define CONFIG_NR_DRAM_BANKS 2 #include <configs/ti_omap3_common.h> -#include <asm/mach-types.h> /* * We are only ever GP parts and will utilize all of the "downloaded image" @@ -26,15 +25,21 @@ #define CONFIG_REVISION_TAG 1 -/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */ -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \ - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) -#define RED_LED_GPIO 27 -#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#define RED_LED_GPIO 16 -#endif -#endif +/* GPIO banks */ +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */ +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */ + +/* TPS65950 */ +#define PBIASLITEVMODE1 (1 << 8) + +/* LED */ +#define IGEP0020_GPIO_LED 27 +#define IGEP0030_GPIO_LED 16 + +/* Board and revision detection GPIOs */ +#define IGEP0030_USB_TRANSCEIVER_RESET 54 +#define GPIO_IGEP00X0_BOARD_DETECTION 28 +#define GPIO_IGEP00X0_REVISION_DETECTION 129 /* USB */ #define CONFIG_USB_MUSB_UDC 1 @@ -67,9 +72,29 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + #include <config_distro_bootcmd.h> +#define ENV_FINDFDT \ + "findfdt="\ + "if test ${board_name} = igep0020; then " \ + "if test ${board_rev} = F; then " \ + "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ + "else " \ + "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ + "if test ${board_name} = igep0030; then " \ + "if test ${board_rev} = G; then " \ + "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ + "else " \ + "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ + "if test ${fdtfile} = ''; then " \ + "echo WARNING: Could not determine device tree to use; fi; \0" + #define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_FINDFDT \ ENV_DEVICE_SETTINGS \ MEM_LAYOUT_SETTINGS \ BOOTENV diff --git a/include/environment/ti/boot.h b/include/environment/ti/boot.h index 1c3ae40a99..a05f5ba9bd 100644 --- a/include/environment/ti/boot.h +++ b/include/environment/ti/boot.h @@ -28,7 +28,24 @@ "vram=16M\0" \ "partitions=" PARTS_DEFAULT "\0" \ "optargs=\0" \ - "dofastboot=0\0" + "dofastboot=0\0" \ + "emmc_android_boot=" \ + "setenv eval_bootargs setenv bootargs $bootargs; " \ + "run eval_bootargs; " \ + "setenv mmcdev 1; " \ + "setenv fdt_part 3; " \ + "setenv boot_part 9; " \ + "setenv machid fe6; " \ + "mmc dev $mmcdev; " \ + "mmc rescan; " \ + "part start mmc ${mmcdev} ${fdt_part} fdt_start; " \ + "part size mmc ${mmcdev} ${fdt_part} fdt_size; " \ + "part start mmc ${mmcdev} ${boot_part} boot_start; " \ + "part size mmc ${mmcdev} ${boot_part} boot_size; " \ + "mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \ + "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \ + "echo Booting from eMMC ...; " \ + "bootm $loadaddr $loadaddr $fdtaddr;\0" #ifdef CONFIG_OMAP54XX @@ -76,6 +93,7 @@ "setenv bootpart 1:2; " \ "setenv mmcroot /dev/mmcblk0p2 rw; " \ "run mmcboot;" \ + "run emmc_android_boot; " \ "" #endif /* CONFIG_OMAP54XX */ diff --git a/include/flash.h b/include/flash.h index 55c5bdd4b1..f53fe91349 100644 --- a/include/flash.h +++ b/include/flash.h @@ -81,7 +81,6 @@ typedef unsigned long flash_sect_t; /* Prototypes */ extern unsigned long flash_init (void); -extern void flash_protect_default(void); extern void flash_print_info (flash_info_t *); extern int flash_erase (flash_info_t *, int, int); extern int flash_sect_erase (ulong addr_first, ulong addr_last); @@ -114,10 +113,6 @@ extern int jedec_flash_match(flash_info_t *info, ulong base); #define CFI_CMDSET_AMD_LEGACY 0xFFF0 #endif -#if defined(CONFIG_SYS_FLASH_CFI) -extern flash_info_t *flash_get_info(ulong base); -#endif - /*----------------------------------------------------------------------- * return codes from flash_write(): */ diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 52572b9b02..eade2b3614 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -165,8 +165,6 @@ extern int cfi_flash_num_flash_banks; #define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS #endif -void flash_write_cmd(flash_info_t * info, flash_sect_t sect, - uint offset, u32 cmd); phys_addr_t cfi_flash_bank_addr(int i); unsigned long cfi_flash_bank_size(int i); void flash_cmd_reset(flash_info_t *info); diff --git a/scripts/objdiff b/scripts/objdiff index 62e51dae21..4fb5d67968 100755 --- a/scripts/objdiff +++ b/scripts/objdiff @@ -57,13 +57,15 @@ get_output_dir() { do_objdump() { dir=$(get_output_dir $1) base=${1##*/} + stripped=$dir/${base%.o}.stripped dis=$dir/${base%.o}.dis [ ! -d "$dir" ] && mkdir -p $dir # remove addresses for a cleaner diff # http://dummdida.tumblr.com/post/60924060451/binary-diff-between-libc-from-scientificlinux-and - $OBJDUMP -D $1 | sed "s/^[[:space:]]\+[0-9a-f]\+//" > $dis + $STRIP -g $1 -R __bug_table -R .note -R .comment -o $stripped + $OBJDUMP -D $stripped | sed -e "s/^[[:space:]]\+[0-9a-f]\+//" -e "s:^$stripped:$1:" > $dis } dorecord() { @@ -73,6 +75,7 @@ dorecord() { CMT="`git rev-parse --short HEAD`" + STRIP="${CROSS_COMPILE}strip" OBJDUMP="${CROSS_COMPILE}objdump" for d in $FILES; do |