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-rw-r--r--arch/mips/lib/cache.c20
-rw-r--r--arch/mips/lib/cache_init.S46
2 files changed, 20 insertions, 46 deletions
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 1d14fc487e..d56fd1e0f4 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -175,3 +175,23 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
/* ensure cache ops complete before any further memory accesses */
sync();
}
+
+int dcache_status(void)
+{
+ unsigned int cca = read_c0_config() & CONF_CM_CMASK;
+ return cca != CONF_CM_UNCACHED;
+}
+
+void dcache_enable(void)
+{
+ puts("Not supported!\n");
+}
+
+void dcache_disable(void)
+{
+ /* change CCA to uncached */
+ change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+
+ /* ensure the pipeline doesn't contain now-invalid instructions */
+ instruction_hazard_barrier();
+}
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index b209f23f0a..395bfffdb8 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -423,49 +423,3 @@ return:
sync
jr ra
END(mips_cache_reset)
-
-/*
- * dcache_status - get cache status
- *
- * RETURNS: 0 - cache disabled; 1 - cache enabled
- *
- */
-LEAF(dcache_status)
- mfc0 t0, CP0_CONFIG
- li t1, CONF_CM_UNCACHED
- andi t0, t0, CONF_CM_CMASK
- move v0, zero
- beq t0, t1, 2f
- li v0, 1
-2: jr ra
- END(dcache_status)
-
-/*
- * dcache_disable - disable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_disable)
- mfc0 t0, CP0_CONFIG
- li t1, -8
- and t0, t0, t1
- ori t0, t0, CONF_CM_UNCACHED
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_disable)
-
-/*
- * dcache_enable - enable cache
- *
- * RETURNS: N/A
- *
- */
-LEAF(dcache_enable)
- mfc0 t0, CP0_CONFIG
- ori t0, CONF_CM_CMASK
- xori t0, CONF_CM_CMASK
- ori t0, CONFIG_SYS_MIPS_CACHE_MODE
- mtc0 t0, CP0_CONFIG
- jr ra
- END(dcache_enable)