diff options
332 files changed, 3192 insertions, 2968 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 6035623fc4..33fd4652a4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -239,6 +239,7 @@ F: arch/arm/mach-rmobile/ ARM ROCKCHIP M: Simon Glass <sjg@chromium.org> M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> +M: Kever Yang <kever.yang@rock-chips.com> S: Maintained T: git git://git.denx.de/u-boot-rockchip.git F: arch/arm/include/asm/arch-rockchip/ @@ -587,7 +588,7 @@ S: Maintained F: arch/mips/mach-jz47xx/ MMC -M: Jaehoon Chung <jh80.chung@samsung.com> +M: Peng Fan <peng.fan@nxp.com> S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ @@ -1120,9 +1120,6 @@ The following options need to be configured: CONFIG_SH_MMCIF_CLK Define the clock frequency for MMCIF - CONFIG_SUPPORT_EMMC_BOOT - Enable some additional features of the eMMC boot partitions. - - USB Device Firmware Update (DFU) class support: CONFIG_DFU_OVER_USB This enables the USB portion of the DFU USB class diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e84f3d7deb..49f01f1ff1 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1439,6 +1439,7 @@ config ARCH_ROCKCHIP select SYS_THUMB_BUILD if !ARM64 imply ADC imply CMD_DM + imply DEBUG_UART_BOARD_INIT imply DISTRO_DEFAULTS imply FAT_WRITE imply SARADC_ROCKCHIP diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index fe52166e28..ecee9e37a5 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -26,7 +26,11 @@ _start: * order to boot, allow them to set that in their boot0.h file and then * use it here. */ +#ifdef CONFIG_ARCH_ROCKCHIP +#include <asm/arch-rockchip/boot0.h> +#else #include <asm/arch/boot0.h> +#endif #else b reset #endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index dfa5b02958..8e082f2840 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ + rk3399-orangepi.dtb \ rk3288-phycore-rdk.dtb \ rk3288-popmetal.dtb \ rk3288-rock2-square.dtb \ @@ -255,6 +256,7 @@ dtb-$(CONFIG_AM33XX) += \ am335x-evmsk.dtb \ am335x-bonegreen.dtb \ am335x-icev2.dtb \ + am335x-pocketbeagle.dtb \ am335x-pxm50.dtb \ am335x-rut.dtb \ am335x-shc.dtb \ diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi new file mode 100644 index 0000000000..f8ff473f94 --- /dev/null +++ b/arch/arm/dts/am335x-osd335x-common.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author: Robert Nelson <robertcnelson@gmail.com> + */ + +/ { + cpus { + cpu@0 { + cpu0-supply = <&dcdc2_reg>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; +}; + +&cpu0_opp_table { + /* + * Octavo Systems: + * The EFUSE_SMA register is not programmed for any of the AM335x wafers + * we get and we are not programming them during our production test. + * Therefore, from a DEVICE_ID revision point of view, the silicon looks + * like it is Revision 2.1. However, from an EFUSE_SMA point of view for + * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the + * EFUSE_SMA register reads as all zeros). + */ + oppnitro-1000000000 { + opp-supported-hw = <0x06 0x0100>; + }; +}; + +&am33xx_pinmux { + i2c0_pins: pinmux-i2c0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@24 { + reg = <0x24>; + }; +}; + +/include/ "tps65217.dtsi" + +&tps { + interrupts = <7>; /* NMI */ + interrupt-parent = <&intc>; + + ti,pmic-shutdown-controller; + + pwrbutton { + interrupts = <2>; + status = "okay"; + }; + + regulators { + dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; + regulator-always-on; + }; + + dcdc2_reg: regulator@1 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1351500>; + regulator-boot-on; + regulator-always-on; + }; + + dcdc3_reg: regulator@2 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; + regulator-always-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; + regulator-always-on; + }; + + ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; + regulator-always-on; + }; + }; +}; + +&aes { + status = "okay"; +}; + +&sham { + status = "okay"; +}; diff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts new file mode 100644 index 0000000000..62fe5cab9f --- /dev/null +++ b/arch/arm/dts/am335x-pocketbeagle.dts @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * Author: Robert Nelson <robertcnelson@gmail.com> + */ +/dts-v1/; + +#include "am33xx.dtsi" +#include "am335x-osd335x-common.dtsi" + +/ { + model = "TI AM335x PocketBeagle"; + compatible = "ti,am335x-pocketbeagle", "ti,am335x-bone", "ti,am33xx"; + + chosen { + stdout-path = &uart0; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&usr_leds_pins>; + + compatible = "gpio-leds"; + + usr0 { + label = "beaglebone:green:usr0"; + gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + usr1 { + label = "beaglebone:green:usr1"; + gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + usr2 { + label = "beaglebone:green:usr2"; + gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + usr3 { + label = "beaglebone:green:usr3"; + gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vmmcsd_fixed: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&am33xx_pinmux { + i2c2_pins: pinmux-i2c2-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3) /* (D17) uart1_rtsn.I2C2_SCL */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3) /* (D18) uart1_ctsn.I2C2_SDA */ + >; + }; + + ehrpwm0_pins: pinmux-ehrpwm0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (A13) mcasp0_aclkx.ehrpwm0A */ + >; + }; + + ehrpwm1_pins: pinmux-ehrpwm1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U14) gpmc_a2.ehrpwm1A */ + >; + }; + + mmc0_pins: pinmux-mmc0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.gpio0[6] */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* (B12) mcasp0_aclkr.mmc0_sdwp */ + >; + }; + + spi0_pins: pinmux-spi0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + >; + }; + + spi1_pins: pinmux-spi1-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4) /* (C18) eCAP0_in_PWM0_out.spi1_sclk */ + AM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4) /* (E18) uart0_ctsn.spi1_d0 */ + AM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4) /* (E17) uart0_rtsn.spi1_d1 */ + AM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4) /* (A15) xdma_event_intr0.spi1_cs1 */ + >; + }; + + usr_leds_pins: pinmux-usr-leds-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7) /* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */ + AM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7) /* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */ + AM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7) /* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */ + >; + }; + + uart0_pins: pinmux-uart0-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ + >; + }; + + uart4_pins: pinmux-uart4-pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6) /* (T17) gpmc_wait0.uart4_rxd */ + AM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* (U17) gpmc_wpn.uart4_txd */ + >; + }; +}; + +&epwmss0 { + status = "okay"; +}; + +&ehrpwm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm0_pins>; +}; + +&epwmss1 { + status = "okay"; +}; + +&ehrpwm1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ehrpwm1_pins>; +}; + +&i2c0 { + eeprom: eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + status = "okay"; + clock-frequency = <400000>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; +}; + +&rtc { + system-power-controller; +}; + +&tscadc { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + ti,chan-step-avg = <16 16 16 16 16 16 16 16>; + ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>; + ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; diff --git a/arch/arm/dts/at91sam9g20-taurus.dts b/arch/arm/dts/at91sam9g20-taurus.dts index cee228bb8c..c00c5a8b8d 100644 --- a/arch/arm/dts/at91sam9g20-taurus.dts +++ b/arch/arm/dts/at91sam9g20-taurus.dts @@ -15,7 +15,7 @@ / { model = "Siemens taurus"; - compatible = "atmel,at91sam9g20ek", "atmel,at91sam9g20", "atmel,at91sam9"; + compatible = "atmel,at91sam9g20", "atmel,at91sam9"; chosen { u-boot,dm-pre-reloc; @@ -35,88 +35,86 @@ clock-frequency = <18432000>; }; }; +}; - ahb { - apb { - pinctrl@fffff400 { - board { - pinctrl_pck0_as_mck: pck0_as_mck { - atmel,pins = - <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC1 periph B */ - }; - - }; - }; - - dbgu: serial@fffff200 { - u-boot,dm-pre-reloc; - status = "okay"; - }; - - usart0: serial@fffb0000 { - pinctrl-0 = - <&pinctrl_usart0 - &pinctrl_usart0_rts - &pinctrl_usart0_cts - &pinctrl_usart0_dtr_dsr - &pinctrl_usart0_dcd - &pinctrl_usart0_ri>; - status = "okay"; - }; - - usart1: serial@fffb4000 { - status = "okay"; - }; - - macb0: ethernet@fffc4000 { - phy-mode = "rmii"; - status = "okay"; - }; - - usb1: gadget@fffa4000 { - atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; - status = "okay"; - }; - - ssc0: ssc@fffbc000 { - status = "okay"; - pinctrl-0 = <&pinctrl_ssc0_tx>; - }; - - spi0: spi@fffc8000 { - cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; - mtd_dataflash@0 { - compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; - reg = <1>; - }; - }; - - rtc@fffffd20 { - atmel,rtt-rtc-time-reg = <&gpbr 0x0>; - status = "okay"; - }; - - watchdog@fffffd40 { - timeout-sec = <15>; - status = "okay"; - }; - - gpbr: syscon@fffffd50 { - status = "okay"; - }; - }; +&dbgu { + status = "okay"; +}; - nand0: nand@40000000 { - nand-bus-width = <8>; - nand-ecc-mode = "soft"; - nand-on-flash-bbt; - status = "okay"; - }; +&gpbr { + status = "okay"; +}; + +&macb0 { + phy-mode = "rmii"; + status = "okay"; +}; - usb0: ohci@00500000 { - num-ports = <2>; - status = "okay"; +&nand0 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; +}; + +&pinctrl { + u-boot,dm-pre-reloc; + board { + pinctrl_pck0_as_mck: pck0_as_mck { + atmel,pins = + /* PC1 periph B */ + <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; + }; }; + +&rtc { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; +}; + +&spi0 { + cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + +&ssc0 { + status = "okay"; + pinctrl-0 = <&pinctrl_ssc0_tx>; +}; + +&usart0 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; +}; + +&usart1 { + status = "okay"; +}; + +&usb0 { + num-ports = <2>; + status = "okay"; +}; + +&usb1 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&watchdog { + u-boot,dm-pre-reloc; + timeout-sec = <15>; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index c5d23d0203..f5c8253831 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -3,7 +3,7 @@ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ */ -#include <dt-bindings/pinctrl/k3-am65.h> +#include <dt-bindings/pinctrl/k3.h> #include <dt-bindings/dma/k3-udma.h> / { @@ -144,41 +144,41 @@ u-boot,dm-spl; main_uart0_pins_default: main_uart0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01e4, PIN_INPUT | MUX_MODE0) /* (AF11) UART0_RXD */ - AM65X_IOPAD(0x01e8, PIN_OUTPUT | MUX_MODE0) /* (AE11) UART0_TXD */ - AM65X_IOPAD(0x01ec, PIN_INPUT | MUX_MODE0) /* (AG11) UART0_CTSn */ - AM65X_IOPAD(0x01f0, PIN_OUTPUT | MUX_MODE0) /* (AD11) UART0_RTSn */ + AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ + AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ + AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ + AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ >; u-boot,dm-spl; }; main_mmc0_pins_default: main_mmc0_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (B25) MMC0_CLK */ - AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP | MUX_MODE0) /* (B27) MMC0_CMD */ - AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* (A26) MMC0_DAT0 */ - AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP | MUX_MODE0) /* (E25) MMC0_DAT1 */ - AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C26) MMC0_DAT2 */ - AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP | MUX_MODE0) /* (A25) MMC0_DAT3 */ - AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP | MUX_MODE0) /* (E24) MMC0_DAT4 */ - AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP | MUX_MODE0) /* (A24) MMC0_DAT5 */ - AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP | MUX_MODE0) /* (B26) MMC0_DAT6 */ - AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP | MUX_MODE0) /* (D25) MMC0_DAT7 */ - AM65X_IOPAD(0x01b0, PIN_INPUT | MUX_MODE0) /* (C25) MMC0_DS */ + AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ + AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ + AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ + AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ + AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ + AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ + AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ + AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ + AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ + AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ + AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ >; u-boot,dm-spl; }; main_mmc1_pins_default: main_mmc1_pins_default { pinctrl-single,pins = < - AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (C27) MMC1_CLK */ - AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP | MUX_MODE0) /* (C28) MMC1_CMD */ - AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP | MUX_MODE0) /* (D28) MMC1_DAT0 */ - AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP | MUX_MODE0) /* (E27) MMC1_DAT1 */ - AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP | MUX_MODE0) /* (D26) MMC1_DAT2 */ - AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP | MUX_MODE0) /* (D27) MMC1_DAT3 */ - AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP | MUX_MODE0) /* (B24) MMC1_SDCD */ - AM65X_IOPAD(0x02e0, PIN_INPUT | MUX_MODE0) /* (C24) MMC1_SDWP */ + AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ + AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ + AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ + AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ + AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ + AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ + AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ + AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ >; u-boot,dm-spl; }; diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts b/arch/arm/dts/k3-am654-r5-base-board.dts index 081a2eceb2..a07038be70 100644 --- a/arch/arm/dts/k3-am654-r5-base-board.dts +++ b/arch/arm/dts/k3-am654-r5-base-board.dts @@ -99,7 +99,7 @@ }; &dmsc { - mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; + mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; mbox-names = "tx", "rx", "notify"; ti,host-id = <4>; ti,secure-host; @@ -116,17 +116,17 @@ u-boot,dm-spl; wkup_uart0_pins_default: wkup_uart0_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */ - AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */ - AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ - AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */ + AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */ + AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */ >; u-boot,dm-spl; }; wkup_vtt_pins_default: wkup_vtt_pins_default { pinctrl-single,pins = < - AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */ + AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */ >; u-boot,dm-spl; }; diff --git a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi index 4990ed90dc..3524766515 100644 --- a/arch/arm/dts/logicpd-som-lv-baseboard.dtsi +++ b/arch/arm/dts/logicpd-som-lv-baseboard.dtsi @@ -152,8 +152,8 @@ interrupts-extended = <&intc 83 &omap3_pmx_core 0x11a>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; - wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ - cd-gpios = <&gpio4 14 IRQ_TYPE_LEVEL_LOW>; /* gpio_110 */ + wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */ + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; /* gpio_110 */ vmmc-supply = <&vmmc1>; bus-width = <4>; cap-power-off-card; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index ce004d0d18..9162f3dd50 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -155,7 +155,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index f90e7e88db..46f2ffaf8d 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -592,7 +592,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; bus-width = <4>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi new file mode 100644 index 0000000000..d6f1095abb --- /dev/null +++ b/arch/arm/dts/rk3399-opp.dtsi @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <875000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1100000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/arch/arm/dts/rk3399-orangepi-u-boot.dtsi b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi new file mode 100644 index 0000000000..236b61d78d --- /dev/null +++ b/arch/arm/dts/rk3399-orangepi-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +#include "rk3399-u-boot.dtsi" +#include "rk3399-sdram-ddr3-1333.dtsi" diff --git a/arch/arm/dts/rk3399-orangepi.dts b/arch/arm/dts/rk3399-orangepi.dts new file mode 100644 index 0000000000..cf37b96a6b --- /dev/null +++ b/arch/arm/dts/rk3399-orangepi.dts @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Orange Pi RK3399 Board"; + compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = <KEY_BACK>; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = <KEY_MENU>; + press-threshold-microvolt = <1314000>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <KEY_POWER>; + linux,input-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_btn>; + wakeup-source; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_typec0: vcc5v0-typec0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vcc5v0_typec0"; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_s3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + ak09911@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + vdd-supply = <&vcc3v3_s3>; + }; + + mpu6500@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + vddio-supply = <&vcc3v3_s3>; + }; + + lsm6ds3@6a { + compatible = "st,lsm6ds3"; + reg = <0x6a>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gyr_int_l>; + vdd-supply = <&vcc3v3_s3>; + vddio-supply = <&vcc3v3_s3>; + }; + + cm32181@10 { + compatible = "capella,cm32181"; + reg = <0x10>; + interrupt-parent = <&gpio4>; + interrupts = <RK_PD0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + vdd-supply = <&vcc3v3_s3>; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + buttons { + pwr_btn: pwr-btn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <RK_GPIO0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bluetooth { + bt_reg_on_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mpu6500 { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lsm6ds3 { + gyr_int_l: gyr-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm32181 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + clock-frequency = <50000000>; + disable-wp; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc5v0_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index aec13a28f1..319a610022 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -492,7 +492,6 @@ }; &sdmmc { - u-boot,dm-pre-reloc; clock-frequency = <150000000>; max-frequency = <40000000>; supports-sd; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi new file mode 100644 index 0000000000..f533ed95eb --- /dev/null +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> + */ + +&sdmmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts index b620dd8dda..4be4083941 100644 --- a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts +++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts @@ -77,6 +77,7 @@ }; &uart0 { + clock-frequency = <100000000>; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h index a6d66d102b..db83d0e7d3 100644 --- a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h @@ -6,7 +6,7 @@ #ifndef _ASM_ARCH_DDR_RK3188_H #define _ASM_ARCH_DDR_RK3188_H -#include <asm/arch/ddr_rk3288.h> +#include <asm/arch-rockchip/ddr_rk3288.h> /* * RK3188 Memory scheduler register map. diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h b/arch/arm/include/asm/arch-rockchip/hardware.h index cd94bdd1ba..62e8bed8f3 100644 --- a/arch/arm/include/asm/arch-rockchip/hardware.h +++ b/arch/arm/include/asm/arch-rockchip/hardware.h @@ -10,8 +10,6 @@ #define RK_SETBITS(set) RK_CLRSETBITS(0, set) #define RK_CLRBITS(clr) RK_CLRSETBITS(clr, 0) -#define TIMER7_BASE 0xff810020 - #define rk_clrsetreg(addr, clr, set) \ writel(((clr) | (set)) << 16 | (set), addr) #define rk_clrreg(addr, clr) writel((clr) << 16, addr) diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 992a84152c..370031f2ac 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h @@ -1,6 +1,6 @@ #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \ !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \ - !defined(CONFIG_ARCH_BCM63158) + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) #include <asm/arch/gpio.h> #endif #include <asm-generic/gpio.h> diff --git a/arch/arm/lib/vectors.S b/arch/arm/lib/vectors.S index 2ca6e2494a..20f485142e 100644 --- a/arch/arm/lib/vectors.S +++ b/arch/arm/lib/vectors.S @@ -67,8 +67,11 @@ * (1) defines '_start:' as appropriate * (2) inserts the vector table using ARM_VECTORS as appropriate */ +#ifdef CONFIG_ARCH_ROCKCHIP +#include <asm/arch-rockchip/boot0.h> +#else #include <asm/arch/boot0.h> - +#endif #else /* diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index df43b1d7e0..6887fe05dd 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -12,7 +12,6 @@ obj-$(CONFIG_SOC_DM365) += dm365.o obj-$(CONFIG_SOC_DM644X) += dm644x.o obj-$(CONFIG_SOC_DM646X) += dm646x.o obj-$(CONFIG_SOC_DA850) += da850_pinmux.o -obj-$(CONFIG_DRIVER_TI_EMAC) += lxt972.o dp83848.o et1011c.o ksz8873.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_FRAMEWORK) += spl.o diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index aca2f2961d..f97ad3fc74 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -27,25 +27,6 @@ DECLARE_GLOBAL_DATA_PTR; #define PLLC_PLLDIV8 0x170 #define PLLC_PLLDIV9 0x174 -/* SOC-specific pll info */ -#ifdef CONFIG_SOC_DM355 -#define ARM_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DM644X -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DSP_PLLDIV PLLC_PLLDIV1 -#define DDR_PLLDIV PLLC_PLLDIV2 -#endif - -#ifdef CONFIG_SOC_DM646X -#define DSP_PLLDIV PLLC_PLLDIV1 -#define ARM_PLLDIV PLLC_PLLDIV2 -#define DDR_PLLDIV PLLC_PLLDIV1 -#endif - -#ifdef CONFIG_SOC_DA8XX unsigned int sysdiv[9] = { PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5, PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9 @@ -110,103 +91,6 @@ int set_cpu_clk_info(void) return 0; } -#else /* CONFIG_SOC_DA8XX */ - -static unsigned pll_div(volatile void *pllbase, unsigned offset) -{ - u32 div; - - div = REG(pllbase + offset); - return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1; -} - -static inline unsigned pll_prediv(volatile void *pllbase) -{ -#ifdef CONFIG_SOC_DM355 - /* this register read seems to fail on pll0 */ - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return 8; - else - return pll_div(pllbase, PLLC_PREDIV); -#elif defined(CONFIG_SOC_DM365) - return pll_div(pllbase, PLLC_PREDIV); -#endif - return 1; -} - -static inline unsigned pll_postdiv(volatile void *pllbase) -{ -#if defined(CONFIG_SOC_DM355) || defined(CONFIG_SOC_DM365) - return pll_div(pllbase, PLLC_POSTDIV); -#elif defined(CONFIG_SOC_DM6446) - if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE) - return pll_div(pllbase, PLLC_POSTDIV); -#endif - return 1; -} - -static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div) -{ - volatile void *pllbase = (volatile void *) pll_addr; -#ifdef CONFIG_SOC_DM646X - unsigned base = CONFIG_REFCLK_FREQ / 1000; -#else - unsigned base = CONFIG_SYS_HZ_CLOCK / 1000; -#endif - - /* the PLL might be bypassed */ - if (readl(pllbase + PLLC_PLLCTL) & BIT(0)) { - base /= pll_prediv(pllbase); -#if defined(CONFIG_SOC_DM365) - base *= 2 * (readl(pllbase + PLLC_PLLM) & 0x0ff); -#else - base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff); -#endif - base /= pll_postdiv(pllbase); - } - return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); -} - -#ifdef DAVINCI_DM6467EVM -unsigned int davinci_arm_clk_get() -{ - return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV) * 1000000; -} -#endif - -#if defined(CONFIG_SOC_DM365) -unsigned int davinci_clk_get(unsigned int div) -{ - return pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, div) * 1000000; -} -#endif - -int set_cpu_clk_info(void) -{ - unsigned int pllbase = DAVINCI_PLL_CNTRL0_BASE; -#if defined(CONFIG_SOC_DM365) - pllbase = DAVINCI_PLL_CNTRL1_BASE; -#endif - gd->bd->bi_arm_freq = pll_sysclk_mhz(pllbase, ARM_PLLDIV); - -#ifdef DSP_PLLDIV - gd->bd->bi_dsp_freq = - pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV); -#else - gd->bd->bi_dsp_freq = 0; -#endif - - pllbase = DAVINCI_PLL_CNTRL1_BASE; -#if defined(CONFIG_SOC_DM365) - pllbase = DAVINCI_PLL_CNTRL0_BASE; -#endif - gd->bd->bi_ddr_freq = pll_sysclk_mhz(pllbase, DDR_PLLDIV) / 2; - - return 0; -} - -#endif /* !CONFIG_SOC_DA8XX */ - /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c deleted file mode 100644 index bc158d9675..0000000000 --- a/arch/arm/mach-davinci/dm355.c +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm355 and similar chips - * - * Copyright (C) 2009 David Brownell - */ - -#include <common.h> -#include <asm/arch/hardware.h> - - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x00006001; -} - - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX3) |= (1 << 20) | (1 << 19); -} -#endif diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c deleted file mode 100644 index 486b9007f2..0000000000 --- a/arch/arm/mach-davinci/dm365.c +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm365 and similar chips - */ - -#include <common.h> -#include <asm/arch/hardware.h> - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); -} - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); -} -#endif diff --git a/arch/arm/mach-davinci/dm365_lowlevel.c b/arch/arm/mach-davinci/dm365_lowlevel.c deleted file mode 100644 index ad83917402..0000000000 --- a/arch/arm/mach-davinci/dm365_lowlevel.c +++ /dev/null @@ -1,459 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific lowlevel code for tms320dm365 and similar chips - * Actually used for booting from NAND with nand_spl. - * - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#include <common.h> -#include <nand.h> -#include <ns16550.h> -#include <post.h> -#include <asm/ti-common/davinci_nand.h> -#include <asm/arch/dm365_lowlevel.h> -#include <asm/arch/hardware.h> - -void dm365_waitloop(unsigned long loopcnt) -{ - unsigned long i; - - for (i = 0; i < loopcnt; i++) - asm(" NOP"); -} - -int dm365_pll1_init(unsigned long pllmult, unsigned long prediv) -{ - unsigned int clksrc = 0x0; - - /* Power up the PLL */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); - - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll0_regs->pllctl, - clksrc << PLLCTL_CLOCK_MODE_SHIFT); - - /* - * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled - * through MMR - */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); - - /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); - - dm365_waitloop(150); - - /* PLLRST=1(reset assert) */ - setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); - - dm365_waitloop(300); - - /*Bring PLL out of Reset*/ - clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); - - /* Program the Multiper and Pre-Divider for PLL1 */ - writel(pllmult, &dv_pll0_regs->pllm); - writel(prediv, &dv_pll0_regs->prediv); - - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | - PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, - &dv_pll0_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl); - - /* Program the PostDiv for PLL1 */ - writel(PLL_POSTDEN, &dv_pll0_regs->postdiv); - - /* Post divider setting for PLL1 */ - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8); - writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9); - - dm365_waitloop(300); - - /* Set the GOSET bit */ - writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */ - - dm365_waitloop(300); - - /* Wait for PLL to LOCK */ - while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK) - == PLL0_LOCK)) - ; - - /* Enable the PLL Bit of PLLCTL*/ - setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); - - return 0; -} - -int dm365_pll2_init(unsigned long pllm, unsigned long prediv) -{ - unsigned int clksrc = 0x0; - - /* Power up the PLL*/ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN); - - /* - * Select the Clock Mode as Onchip Oscilator or External Clock on - * MXI pin - * VDB has input on MXI pin - */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); - setbits_le32(&dv_pll1_regs->pllctl, - clksrc << PLLCTL_CLOCK_MODE_SHIFT); - - /* - * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled - * through MMR - */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC); - - /* Set PLLEN=0 => PLL BYPASS MODE */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); - - dm365_waitloop(50); - - /* PLLRST=1(reset assert) */ - setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); - - dm365_waitloop(300); - - /* Bring PLL out of Reset */ - clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); - - /* Program the Multiper and Pre-Divider for PLL2 */ - writel(pllm, &dv_pll1_regs->pllm); - writel(prediv, &dv_pll1_regs->prediv); - - writel(PLL_POSTDEN, &dv_pll1_regs->postdiv); - - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE | - PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); - /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE, - &dv_pll1_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */ - writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl); - /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */ - writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl); - - /* Post divider setting for PLL2 */ - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4); - writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5); - - /* GoCmd for PostDivider to take effect */ - writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd); - - dm365_waitloop(150); - - /* Wait for PLL to LOCK */ - while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK) - == PLL1_LOCK)) - ; - - dm365_waitloop(4100); - - /* Enable the PLL2 */ - setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); - - /* do this after PLL's have been set up */ - writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL, - &dv_sys_module_regs->peri_clkctl); - - return 0; -} - -int dm365_ddr_setup(void) -{ - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - clrbits_le32(&dv_sys_module_regs->vtpiocr, - VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN); - - /* Set bit CLRZ (bit 13) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ); - - /* Check VTP READY Status */ - while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY)) - ; - - /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN); - - /* Set bit LOCK(bit7) */ - setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK); - - /* - * Powerdown VTP as it is locked (bit 6) - * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) - */ - setbits_le32(&dv_sys_module_regs->vtpiocr, - VPTIO_IOPWRDN | VPTIO_PWRDN); - - /* Wait for calibration to complete */ - dm365_waitloop(150); - - /* Set the DDR2 to synreset, then enable it again */ - lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - - writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr); - - /* Program SDRAM Bank Config Register */ - writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK), - &dv_ddr2_regs_ctrl->sdbcr); - writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK), - &dv_ddr2_regs_ctrl->sdbcr); - - /* Program SDRAM Timing Control Register1 */ - writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr); - /* Program SDRAM Timing Control Register2 */ - writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2); - - writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr); - - writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr); - - /* Program SDRAM Refresh Control Register */ - writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr); - - lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF); - lpsc_on(DAVINCI_LPSC_DDR_EMIF); - - return 0; -} - -static void dm365_vpss_sync_reset(void) -{ - unsigned int PdNum = 0; - - /* VPSS_CLKMD 1:1 */ - setbits_le32(&dv_sys_module_regs->vpss_clkctl, - VPSS_CLK_CTL_VPSS_CLKMD); - - /* LPSC SyncReset DDR Clock Enable */ - writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) & - ~PSC_MD_STATE_MSK) | PSC_SYNCRESET), - &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]); - - writel((1 << PdNum), &dv_psc_regs->ptcmd); - - while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0)) - ; - while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) & - PSC_MD_STATE_MSK) == PSC_SYNCRESET)) - ; -} - -static void dm365_por_reset(void) -{ - struct davinci_timer *wdog = - (struct davinci_timer *)DAVINCI_WDOG_BASE; - - if (readl(&dv_pll0_regs->rstype) & - (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) { - dm365_vpss_sync_reset(); - - writel(DV_TMPBUF_VAL, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_PORRST); - writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); - writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); - - while (1); - } -} - -static void dm365_wdt_reset(void) -{ - struct davinci_timer *wdog = - (struct davinci_timer *)DAVINCI_WDOG_BASE; - - if (readl(TMPBUF) != DV_TMPBUF_VAL) { - writel(DV_TMPBUF_VAL, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_PORRST); - setbits_le32(TMPSTATUS, FLAG_FLGOFF); - - dm365_waitloop(100); - - dm365_vpss_sync_reset(); - - writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1); - writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2); - - while (1); - } -} - -static void dm365_wdt_flag_on(void) -{ - /* VPSS_CLKMD 1:2 */ - clrbits_le32(&dv_sys_module_regs->vpss_clkctl, - VPSS_CLK_CTL_VPSS_CLKMD); - writel(0, TMPBUF); - setbits_le32(TMPSTATUS, FLAG_FLGON); -} - -void dm365_psc_init(void) -{ - unsigned char i = 0; - unsigned char lpsc_start; - unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax; - unsigned int PdNum = 0; - - lpscmin = 0; - lpscmax = 2; - - for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) { - if (lpscgroup == 0) { - /* Enabling LPSC 3 to 28 SCR first */ - lpsc_start = DAVINCI_LPSC_VPSSMSTR; - lpsc_end = DAVINCI_LPSC_TIMER1; - } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */ - lpsc_start = DAVINCI_LPSC_CFG5; - lpsc_end = DAVINCI_LPSC_VPSSMASTER; - } else { - lpsc_start = DAVINCI_LPSC_MJCP; - lpsc_end = DAVINCI_LPSC_HDVICP; - } - - /* NEXT=0x3, Enable LPSC's */ - for (i = lpsc_start; i <= lpsc_end; i++) - setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE); - - /* - * Program goctl to start transition sequence for LPSCs - * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power - * Domain 0 Modules - */ - writel((1 << PdNum), &dv_psc_regs->ptcmd); - - /* - * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0 - */ - while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) - == 0)) - ; - - /* Wait for MODSTAT = ENABLE from LPSC's */ - for (i = lpsc_start; i <= lpsc_end; i++) - while (!((readl(&dv_psc_regs->mdstat[i]) & - PSC_MD_STATE_MSK) == PSC_ENABLE)) - ; - } -} - -static void dm365_emif_init(void) -{ - writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr); - writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr); - - setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND); - - writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr); - - return; -} - -void dm365_pinmux_ctl(unsigned long offset, unsigned long mask, - unsigned long value) -{ - clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask); - setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value)); -} - -__attribute__((weak)) -void board_gpio_init(void) -{ - return; -} - -#if defined(CONFIG_POST) -int post_log(char *format, ...) -{ - return 0; -} -#endif - -void dm36x_lowlevel_init(ulong bootflag) -{ - struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs = - (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 + - DAVINCI_UART_CTRL_BASE); - - /* Mask all interrupts */ - writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl); - writel(0x0, &dv_aintc_regs->eabase); - writel(0x0, &dv_aintc_regs->eint0); - writel(0x0, &dv_aintc_regs->eint1); - - /* Clear all interrupts */ - writel(0xffffffff, &dv_aintc_regs->fiq0); - writel(0xffffffff, &dv_aintc_regs->fiq1); - writel(0xffffffff, &dv_aintc_regs->irq0); - writel(0xffffffff, &dv_aintc_regs->irq1); - - dm365_por_reset(); - dm365_wdt_reset(); - - /* System PSC setup - enable all */ - dm365_psc_init(); - - /* Setup Pinmux */ - dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0); - dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1); - dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2); - dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3); - dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4); - - /* PLL setup */ - dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM, - CONFIG_SYS_DM36x_PLL1_PREDIV); - dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM, - CONFIG_SYS_DM36x_PLL2_PREDIV); - - /* GPIO setup */ - board_gpio_init(); - - NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1), - CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE); - - /* - * Fix Power and Emulation Management Register - * see sprufh2.pdf page 38 Table 22 - */ - writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST | - DAVINCI_UART_PWREMU_MGMT_UTRST), - &davinci_uart_ctrl_regs->pwremu_mgmt); - - puts("ddr init\n"); - dm365_ddr_setup(); - - puts("emif init\n"); - dm365_emif_init(); - - dm365_wdt_flag_on(); - -#if defined(CONFIG_POST) - /* - * Do memory tests, calls arch_memory_failure_handle() - * if error detected. - */ - memory_post_test(0); -#endif -} diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c deleted file mode 100644 index 2be6a23711..0000000000 --- a/arch/arm/mach-davinci/dm644x.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for tms320dm644x chips - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * Copyright (C) 2008 Lyrtech <www.lyrtech.com> - * Copyright (C) 2004 Texas Instruments. - */ - -#include <common.h> -#include <asm/arch/hardware.h> - - -#define PINMUX0_EMACEN (1 << 31) -#define PINMUX0_AECS5 (1 << 11) -#define PINMUX0_AECS4 (1 << 10) - -#define PINMUX1_I2C (1 << 7) -#define PINMUX1_UART1 (1 << 1) -#define PINMUX1_UART0 (1 << 0) - - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_LPSC_UART0); - - /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0x00006001; - - /* Enable UART0 MUX lines */ - REG(PINMUX1) |= PINMUX1_UART0; -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_LPSC_EMAC); - lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); - lpsc_on(DAVINCI_LPSC_MDIO); - - /* Enable GIO3.3V cells used for EMAC */ - REG(VDD3P3V_PWDN) = 0; - - /* Enable EMAC. */ - REG(PINMUX0) |= PINMUX0_EMACEN; -} -#endif - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_LPSC_I2C); - - /* Enable I2C pin Mux */ - REG(PINMUX1) |= PINMUX1_I2C; -} -#endif - -void davinci_errata_workarounds(void) -{ - /* - * Workaround for TMS320DM6446 errata 1.3.22: - * PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset - * Revision(s) Affected: 1.3 and earlier - */ - REG(PSC_SILVER_BULLET) = 0; - - /* - * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR) - * as suggested in TMS320DM6446 errata 2.1.2: - * - * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions - * low priority modules can occupy the bus and prevent high priority - * modules like the VPSS from getting the required DDR2 throughput. - * A hex value of 0x20 should provide a good ARM (cache enabled) - * performance and still allow good utilization by the VPSS or other - * modules. - */ - REG(VBPR) = 0x20; -} diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c deleted file mode 100644 index 199c40378d..0000000000 --- a/arch/arm/mach-davinci/dm646x.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SoC-specific code for TMS320DM646x chips - */ - -#include <asm/arch/hardware.h> - -void davinci_enable_uart0(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_UART0); -} - -#ifdef CONFIG_DRIVER_TI_EMAC -void davinci_enable_emac(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_EMAC); -} -#endif - -#ifdef CONFIG_SYS_I2C_DAVINCI -void davinci_enable_i2c(void) -{ - lpsc_on(DAVINCI_DM646X_LPSC_I2C); -} -#endif diff --git a/arch/arm/mach-davinci/dp83848.c b/arch/arm/mach-davinci/dp83848.c deleted file mode 100644 index 7115d7bad2..0000000000 --- a/arch/arm/mach-davinci/dp83848.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * National Semiconductor DP83848 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <net.h> -#include <dp83848.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -int dp83848_is_phy_connected(int phy_addr) -{ - u_int16_t id1, id2; - - if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) - return(0); - if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) - return(0); - - if ((id1 == DP83848_PHYID1_OUI) && (id2 == DP83848_PHYID2_OUI)) - return(1); - - return(0); -} - -int dp83848_get_link_speed(int phy_addr) -{ - u_int16_t tmp; - volatile emac_regs* emac = (emac_regs *)EMAC_BASE_ADDR; - - if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) - return(0); - - if (!(tmp & DP83848_LINK_STATUS)) /* link up? */ - return(0); - - if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) - return(0); - - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (tmp & DP83848_DUPLEX) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); -} - - -int dp83848_init_phy(int phy_addr) -{ - int ret = 1; - - if (!dp83848_get_link_speed(phy_addr)) { - /* Try another time */ - udelay(100000); - ret = dp83848_get_link_speed(phy_addr); - } - - /* Disable PHY Interrupts */ - davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); - - return(ret); -} - - -int dp83848_auto_negotiate(int phy_addr) -{ - u_int16_t tmp; - - - if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) - return(0); - - /* Restart Auto_negotiation */ - tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */ - tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */ - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /* Set the Auto_negotiation Advertisement Register - * MII advertising for Next page, 100BaseTxFD and HD, - * 10BaseTFD and HD, IEEE 802.3 - */ - tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX | - DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3; - davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp); - - - /* Read Control Register */ - if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp)) - return(0); - - tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE; - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /* Restart Auto_negotiation */ - tmp |= DP83848_RESTART_AUTONEG; - davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp); - - /*check AutoNegotiate complete */ - udelay(10000); - if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) - return(0); - - if (!(tmp & DP83848_AUTONEG_COMP)) - return(0); - - return (dp83848_get_link_speed(phy_addr)); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/et1011c.c b/arch/arm/mach-davinci/et1011c.c deleted file mode 100644 index bfb7ff2689..0000000000 --- a/arch/arm/mach-davinci/et1011c.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * LSI ET1011C PHY Driver for TI DaVinci(TMS320DM6467) board. - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#include <common.h> -#include <net.h> -#include <miiphy.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -/* LSI PHYSICAL LAYER TRANSCEIVER ET1011C */ - -#define MII_PHY_CONFIG_REG 22 - -/* PHY Config bits */ -#define PHY_SYS_CLK_EN (1 << 4) - -int et1011c_get_link_speed(int phy_addr) -{ - u_int16_t data; - - if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { - davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); - /* Enable 125MHz clock sourced from PHY */ - davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, - data | PHY_SYS_CLK_EN); - return (1); - } - return (0); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/include/mach/da8xx-usb.h b/arch/arm/mach-davinci/include/mach/da8xx-usb.h index 42e1258225..215706e172 100644 --- a/arch/arm/mach-davinci/include/mach/da8xx-usb.h +++ b/arch/arm/mach-davinci/include/mach/da8xx-usb.h @@ -86,7 +86,4 @@ struct da8xx_usb_regs { #define DA8XX_USB_VBUS_GPIO (1 << 15) -int usb_phy_on(void); -void usb_phy_off(void); - #endif /* __DA8XX_MUSB_H__ */ diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 842be589fa..48b11f7a5c 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -40,13 +40,11 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, int n_items); -#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX) +#if defined(CONFIG_DRIVER_TI_EMAC) void davinci_emac_mii_mode_sel(int mode_sel); #endif -#if defined(CONFIG_SOC_DA8XX) void irq_init(void); int da8xx_configure_lpsc_items(const struct lpsc_resource *item, const int n_items); -#endif #endif /* __MISC_H */ diff --git a/arch/arm/mach-davinci/include/mach/emac_defs.h b/arch/arm/mach-davinci/include/mach/emac_defs.h index b08d06dd24..7c6c19ba0f 100644 --- a/arch/arm/mach-davinci/include/mach/emac_defs.h +++ b/arch/arm/mach-davinci/include/mach/emac_defs.h @@ -23,71 +23,15 @@ #include <asm/arch/hardware.h> -#ifdef CONFIG_SOC_DM365 -#define EMAC_BASE_ADDR (0x01d07000) -#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) -#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) -#define EMAC_MDIO_BASE_ADDR (0x01d0b000) -#define DAVINCI_EMAC_VERSION2 -#elif defined(CONFIG_SOC_DA8XX) #define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE #define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE #define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE #define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE #define DAVINCI_EMAC_VERSION2 -#else -#define EMAC_BASE_ADDR (0x01c80000) -#define EMAC_WRAPPER_BASE_ADDR (0x01c81000) -#define EMAC_WRAPPER_RAM_ADDR (0x01c82000) -#define EMAC_MDIO_BASE_ADDR (0x01c84000) -#endif - -#ifdef CONFIG_SOC_DM646X -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif -#ifdef CONFIG_SOC_DM646X -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 76500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ -#elif defined(CONFIG_SOC_DM365) -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 121500000 -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ -#elif defined(CONFIG_SOC_DA8XX) /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID) /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#else -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ -#endif - -#define PHY_KSZ8873 (0x00221450) -int ksz8873_is_phy_connected(int phy_addr); -int ksz8873_get_link_speed(int phy_addr); -int ksz8873_init_phy(int phy_addr); -int ksz8873_auto_negotiate(int phy_addr); - -#define PHY_LXT972 (0x001378e2) -int lxt972_is_phy_connected(int phy_addr); -int lxt972_get_link_speed(int phy_addr); -int lxt972_init_phy(int phy_addr); -int lxt972_auto_negotiate(int phy_addr); - -#define PHY_DP83848 (0x20005c90) -int dp83848_is_phy_connected(int phy_addr); -int dp83848_get_link_speed(int phy_addr); -int dp83848_init_phy(int phy_addr); -int dp83848_auto_negotiate(int phy_addr); - -#define PHY_ET1011C (0x282f013) -int et1011c_get_link_speed(int phy_addr); #endif /* _DM644X_EMAC_H_ */ diff --git a/arch/arm/mach-davinci/include/mach/gpio.h b/arch/arm/mach-davinci/include/mach/gpio.h index 39819788a1..3dca50f776 100644 --- a/arch/arm/mach-davinci/include/mach/gpio.h +++ b/arch/arm/mach-davinci/include/mach/gpio.h @@ -5,21 +5,12 @@ #ifndef _GPIO_DEFS_H_ #define _GPIO_DEFS_H_ -#ifndef CONFIG_SOC_DA8XX -#define DAVINCI_GPIO_BINTEN 0x01C67008 -#define DAVINCI_GPIO_BANK01 0x01C67010 -#define DAVINCI_GPIO_BANK23 0x01C67038 -#define DAVINCI_GPIO_BANK45 0x01C67060 -#define DAVINCI_GPIO_BANK67 0x01C67088 - -#else /* CONFIG_SOC_DA8XX */ #define DAVINCI_GPIO_BINTEN 0x01E26008 #define DAVINCI_GPIO_BANK01 0x01E26010 #define DAVINCI_GPIO_BANK23 0x01E26038 #define DAVINCI_GPIO_BANK45 0x01E26060 #define DAVINCI_GPIO_BANK67 0x01E26088 #define DAVINCI_GPIO_BANK8 0x01E260B0 -#endif /* CONFIG_SOC_DA8XX */ #define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) #define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) @@ -31,10 +22,7 @@ #define gpio_status() gpio_info() #endif #define GPIO_NAME_SIZE 20 -#if defined(CONFIG_SOC_DM644X) -/* GPIO0 to GPIO53, omit the V3.3 volts one */ -#define MAX_NUM_GPIOS 70 -#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850) +#if !defined(CONFIG_SOC_DA850) #define MAX_NUM_GPIOS 128 #else #define MAX_NUM_GPIOS 144 diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h index ca5f85a8bb..4466c6c1d5 100644 --- a/arch/arm/mach-davinci/include/mach/hardware.h +++ b/arch/arm/mach-davinci/include/mach/hardware.h @@ -23,89 +23,6 @@ typedef volatile unsigned int dv_reg; typedef volatile unsigned int * dv_reg_p; #endif -/* - * Base register addresses - * - * NOTE: some of these DM6446-specific addresses DO NOT WORK - * on other DaVinci chips. Double check them before you try - * using the addresses ... or PSC module identifiers, etc. - */ -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_DMA_3PCC_BASE (0x01c00000) -#define DAVINCI_DMA_3PTC0_BASE (0x01c10000) -#define DAVINCI_DMA_3PTC1_BASE (0x01c10400) -#define DAVINCI_UART0_BASE (0x01c20000) -#define DAVINCI_UART1_BASE (0x01c20400) -#define DAVINCI_TIMER3_BASE (0x01c20800) -#define DAVINCI_I2C_BASE (0x01c21000) -#define DAVINCI_TIMER0_BASE (0x01c21400) -#define DAVINCI_TIMER1_BASE (0x01c21800) -#define DAVINCI_WDOG_BASE (0x01c21c00) -#define DAVINCI_PWM0_BASE (0x01c22000) -#define DAVINCI_PWM1_BASE (0x01c22400) -#define DAVINCI_PWM2_BASE (0x01c22800) -#define DAVINCI_TIMER4_BASE (0x01c23800) -#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000) -#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800) -#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00) -#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000) -#define DAVINCI_ARM_INTC_BASE (0x01c48000) -#define DAVINCI_USB_OTG_BASE (0x01c64000) -#define DAVINCI_CFC_ATA_BASE (0x01c66000) -#define DAVINCI_SPI_BASE (0x01c66800) -#define DAVINCI_GPIO_BASE (0x01c67000) -#define DAVINCI_VPSS_REGS_BASE (0x01c70000) -#if !defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) -#endif -#define DAVINCI_DDR_BASE (0x80000000) - -#ifdef CONFIG_SOC_DM644X -#define DAVINCI_UART2_BASE 0x01c20800 -#define DAVINCI_UHPI_BASE 0x01c67800 -#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000 -#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000 -#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000 -#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000 -#define DAVINCI_IMCOP_BASE 0x01cc0000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000 -#define DAVINCI_VLYNQ_BASE 0x01e01000 -#define DAVINCI_ASP_BASE 0x01e02000 -#define DAVINCI_MMC_SD_BASE 0x01e10000 -#define DAVINCI_MS_BASE 0x01e20000 -#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000 - -#elif defined(CONFIG_SOC_DM355) -#define DAVINCI_MMC_SD1_BASE 0x01e00000 -#define DAVINCI_ASP0_BASE 0x01e02000 -#define DAVINCI_ASP1_BASE 0x01e04000 -#define DAVINCI_UART2_BASE 0x01e06000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 -#define DAVINCI_MMC_SD0_BASE 0x01e11000 - -#elif defined(CONFIG_SOC_DM365) -#define DAVINCI_MMC_SD1_BASE 0x01d00000 -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 -#define DAVINCI_MMC_SD0_BASE 0x01d11000 -#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000 -#define DAVINCI_SPI0_BASE 0x01c66000 -#define DAVINCI_SPI1_BASE 0x01c66800 - -#elif defined(CONFIG_SOC_DM646X) -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000 -#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000 -#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 - -#endif - -#else /* CONFIG_SOC_DA8XX */ - #define DAVINCI_UART0_BASE 0x01c42000 #define DAVINCI_UART1_BASE 0x01d0c000 #define DAVINCI_UART2_BASE 0x01d0d000 @@ -162,66 +79,11 @@ typedef volatile unsigned int * dv_reg_p; #define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c) #define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90) #define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94) -#endif /* CONFIG_SOC_DA8XX */ /* Power and Sleep Controller (PSC) Domains */ #define DAVINCI_GPSC_ARMDOMAIN 0 #define DAVINCI_GPSC_DSPDOMAIN 1 -#ifndef CONFIG_SOC_DA8XX - -#define DAVINCI_LPSC_VPSSMSTR 0 -#define DAVINCI_LPSC_VPSSSLV 1 -#define DAVINCI_LPSC_TPCC 2 -#define DAVINCI_LPSC_TPTC0 3 -#define DAVINCI_LPSC_TPTC1 4 -#define DAVINCI_LPSC_EMAC 5 -#define DAVINCI_LPSC_EMAC_WRAPPER 6 -#define DAVINCI_LPSC_MDIO 7 -#define DAVINCI_LPSC_IEEE1394 8 -#define DAVINCI_LPSC_USB 9 -#define DAVINCI_LPSC_ATA 10 -#define DAVINCI_LPSC_VLYNQ 11 -#define DAVINCI_LPSC_UHPI 12 -#define DAVINCI_LPSC_DDR_EMIF 13 -#define DAVINCI_LPSC_AEMIF 14 -#define DAVINCI_LPSC_MMC_SD 15 -#define DAVINCI_LPSC_MEMSTICK 16 -#define DAVINCI_LPSC_McBSP 17 -#define DAVINCI_LPSC_I2C 18 -#define DAVINCI_LPSC_UART0 19 -#define DAVINCI_LPSC_UART1 20 -#define DAVINCI_LPSC_UART2 21 -#define DAVINCI_LPSC_SPI 22 -#define DAVINCI_LPSC_PWM0 23 -#define DAVINCI_LPSC_PWM1 24 -#define DAVINCI_LPSC_PWM2 25 -#define DAVINCI_LPSC_GPIO 26 -#define DAVINCI_LPSC_TIMER0 27 -#define DAVINCI_LPSC_TIMER1 28 -#define DAVINCI_LPSC_TIMER2 29 -#define DAVINCI_LPSC_SYSTEM_SUBSYS 30 -#define DAVINCI_LPSC_ARM 31 -#define DAVINCI_LPSC_SCR2 32 -#define DAVINCI_LPSC_SCR3 33 -#define DAVINCI_LPSC_SCR4 34 -#define DAVINCI_LPSC_CROSSBAR 35 -#define DAVINCI_LPSC_CFG27 36 -#define DAVINCI_LPSC_CFG3 37 -#define DAVINCI_LPSC_CFG5 38 -#define DAVINCI_LPSC_GEM 39 -#define DAVINCI_LPSC_IMCOP 40 -#define DAVINCI_LPSC_VPSSMASTER 47 -#define DAVINCI_LPSC_MJCP 50 -#define DAVINCI_LPSC_HDVICP 51 - -#define DAVINCI_DM646X_LPSC_EMAC 14 -#define DAVINCI_DM646X_LPSC_UART0 26 -#define DAVINCI_DM646X_LPSC_I2C 31 -#define DAVINCI_DM646X_LPSC_TIMER0 34 - -#else /* CONFIG_SOC_DA8XX */ - #define DAVINCI_LPSC_TPCC 0 #define DAVINCI_LPSC_TPTC0 1 #define DAVINCI_LPSC_TPTC1 2 @@ -283,8 +145,6 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29) #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30) -#endif /* CONFIG_SOC_DA8XX */ - #ifndef __ASSEMBLY__ void lpsc_on(unsigned int id); void lpsc_syncreset(unsigned int id); @@ -296,30 +156,6 @@ void davinci_enable_emac(void); void davinci_enable_i2c(void); void davinci_errata_workarounds(void); -#ifndef CONFIG_SOC_DA8XX - -/* Some PSC defines */ -#define PSC_CHP_SHRTSW (0x01c40038) -#define PSC_GBLCTL (0x01c41010) -#define PSC_EPCPR (0x01c41070) -#define PSC_EPCCR (0x01c41078) -#define PSC_PTCMD (0x01c41120) -#define PSC_PTSTAT (0x01c41128) -#define PSC_PDSTAT (0x01c41200) -#define PSC_PDSTAT1 (0x01c41204) -#define PSC_PDCTL (0x01c41300) -#define PSC_PDCTL1 (0x01c41304) - -#define PSC_MDCTL_BASE (0x01c41a00) -#define PSC_MDSTAT_BASE (0x01c41800) - -#define VDD3P3V_PWDN (0x01c40048) -#define UART0_PWREMU_MGMT (0x01c20030) - -#define PSC_SILVER_BULLET (0x01c41a20) - -#else /* CONFIG_SOC_DA8XX */ - #define PSC_ENABLE 0x3 #define PSC_DISABLE 0x2 #define PSC_SYNCRESET 0x1 @@ -354,41 +190,9 @@ struct davinci_psc_regs { #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE) #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE) -#endif /* CONFIG_SOC_DA8XX */ - #define PSC_MDSTAT_STATE 0x3f #define PSC_MDCTL_NEXT 0x07 -#ifndef CONFIG_SOC_DA8XX - -/* Miscellania... */ -#define VBPR (0x20000020) - -/* NOTE: system control modules are *highly* chip-specific, both - * as to register content (e.g. for muxing) and which registers exist. - */ -#define PINMUX0 0x01c40000 -#define PINMUX1 0x01c40004 -#define PINMUX2 0x01c40008 -#define PINMUX3 0x01c4000c -#define PINMUX4 0x01c40010 - -struct davinci_uart_ctrl_regs { - dv_reg revid1; - dv_reg res; - dv_reg pwremu_mgmt; - dv_reg mdr; -}; - -#define DAVINCI_UART_CTRL_BASE 0x28 - -/* UART PWREMU_MGMT definitions */ -#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0) -#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13) -#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14) - -#else /* CONFIG_SOC_DA8XX */ - struct davinci_pllc_regs { dv_reg revid; dv_reg rsvd1[56]; @@ -606,26 +410,6 @@ static inline enum davinci_clk_ids get_async3_src(void) DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2; } -#endif /* CONFIG_SOC_DA8XX */ - -#if defined(CONFIG_SOC_DM365) -#include <asm/arch/aintc_defs.h> -#include <asm/arch/ddr2_defs.h> -#include <asm/arch/gpio.h> -#include <asm/arch/pll_defs.h> -#include <asm/arch/psc_defs.h> -#include <asm/arch/syscfg_defs.h> -#include <asm/arch/timer_defs.h> - -#define TMPBUF 0x00017ff8 -#define TMPSTATUS 0x00017ff0 -#define DV_TMPBUF_VAL 0x591b3ed7 -#define FLAG_PORRST 0x00000001 -#define FLAG_WDTRST 0x00000002 -#define FLAG_FLGON 0x00000004 -#define FLAG_FLGOFF 0x00000010 - -#endif #endif /* !__ASSEMBLY__ */ #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/mach-davinci/include/mach/i2c_defs.h b/arch/arm/mach-davinci/include/mach/i2c_defs.h index 50e31ca3b9..f12460dd5f 100644 --- a/arch/arm/mach-davinci/include/mach/i2c_defs.h +++ b/arch/arm/mach-davinci/include/mach/i2c_defs.h @@ -8,10 +8,6 @@ #ifndef _I2C_DEFS_H_ #define _I2C_DEFS_H_ -#ifndef CONFIG_SOC_DA8XX -#define I2C_BASE 0x01c21000 -#else #define I2C_BASE 0x01c22000 -#endif #endif diff --git a/arch/arm/mach-davinci/include/mach/syscfg_defs.h b/arch/arm/mach-davinci/include/mach/syscfg_defs.h deleted file mode 100644 index 41deeda644..0000000000 --- a/arch/arm/mach-davinci/include/mach/syscfg_defs.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#ifndef _DV_SYSCFG_DEFS_H_ -#define _DV_SYSCFG_DEFS_H_ - -#ifndef CONFIG_SOC_DA8XX -/* System Control Module register structure for DM365 */ -struct dv_sys_module_regs { - unsigned int pinmux[5]; /* 0x00 */ - unsigned int bootcfg; /* 0x14 */ - unsigned int arm_intmux; /* 0x18 */ - unsigned int edma_evtmux; /* 0x1C */ - unsigned int ddr_slew; /* 0x20 */ - unsigned int clkout; /* 0x24 */ - unsigned int device_id; /* 0x28 */ - unsigned int vdac_config; /* 0x2C */ - unsigned int timer64_ctl; /* 0x30 */ - unsigned int usbbphy_ctl; /* 0x34 */ - unsigned int misc; /* 0x38 */ - unsigned int mstpri[2]; /* 0x3C */ - unsigned int vpss_clkctl; /* 0x44 */ - unsigned int peri_clkctl; /* 0x48 */ - unsigned int deepsleep; /* 0x4C */ - unsigned int dft_enable; /* 0x50 */ - unsigned int debounce[8]; /* 0x54 */ - unsigned int vtpiocr; /* 0x74 */ - unsigned int pupdctl0; /* 0x78 */ - unsigned int pupdctl1; /* 0x7C */ - unsigned int hdimcopbt; /* 0x80 */ - unsigned int pll0_config; /* 0x84 */ - unsigned int pll1_config; /* 0x88 */ -}; - -#define VPTIO_RDY (1 << 15) -#define VPTIO_IOPWRDN (1 << 14) -#define VPTIO_CLRZ (1 << 13) -#define VPTIO_LOCK (1 << 7) -#define VPTIO_PWRDN (1 << 6) - -#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7) - -#define dv_sys_module_regs \ - ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE) - -#endif /* !CONFIG_SOC_DA8XX */ -#endif /* _DV_SYSCFG_DEFS_H_ */ diff --git a/arch/arm/mach-davinci/ksz8873.c b/arch/arm/mach-davinci/ksz8873.c deleted file mode 100644 index 85b0c2620c..0000000000 --- a/arch/arm/mach-davinci/ksz8873.c +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Micrel KSZ8873 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2011 Heiko Schocher <hsdenx.de> - * - * based on: - * National Semiconductor DP83848 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <miiphy.h> -#include <net.h> -#include <asm/arch/emac_defs.h> -#include <asm/io.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -int ksz8873_is_phy_connected(int phy_addr) -{ - u_int16_t dummy; - - return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); -} - -int ksz8873_get_link_speed(int phy_addr) -{ - emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; - - /* we always have a link to the switch, 100 FD */ - writel((EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE), - &emac->MACCONTROL); - return 1; -} - - -int ksz8873_init_phy(int phy_addr) -{ - return 1; -} - - -int ksz8873_auto_negotiate(int phy_addr) -{ - return dp83848_get_link_speed(phy_addr); -} diff --git a/arch/arm/mach-davinci/lxt972.c b/arch/arm/mach-davinci/lxt972.c deleted file mode 100644 index b54f67dbfe..0000000000 --- a/arch/arm/mach-davinci/lxt972.c +++ /dev/null @@ -1,112 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Intel LXT971/LXT972 PHY Driver for TI DaVinci - * (TMS320DM644x) based boards. - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - * -------------------------------------------------------- - */ - -#include <common.h> -#include <net.h> -#include <miiphy.h> -#include <lxt971a.h> -#include <asm/arch/emac_defs.h> -#include "../../../drivers/net/ti/davinci_emac.h" - -#ifdef CONFIG_DRIVER_TI_EMAC - -#ifdef CONFIG_CMD_NET - -int lxt972_is_phy_connected(int phy_addr) -{ - u_int16_t id1, id2; - - if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1)) - return(0); - if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2)) - return(0); - - if ((id1 == (0x0013)) && ((id2 & 0xfff0) == 0x78e0)) - return(1); - - return(0); -} - -int lxt972_get_link_speed(int phy_addr) -{ - u_int16_t stat1, tmp; - volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR; - - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) - return(0); - - if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */ - return(0); - - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) - return(0); - - tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE; - - davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); - /* Read back */ - if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) - return(0); - - /* Speed doesn't matter, there is no setting for it in EMAC... */ - if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) { - /* set DM644x EMAC for Full Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE | - EMAC_MACCONTROL_FULLDUPLEX_ENABLE; - } else { - /*set DM644x EMAC for Half Duplex */ - emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE; - } - - return(1); -} - - -int lxt972_init_phy(int phy_addr) -{ - int ret = 1; - - if (!lxt972_get_link_speed(phy_addr)) { - /* Try another time */ - ret = lxt972_get_link_speed(phy_addr); - } - - /* Disable PHY Interrupts */ - davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0); - - return(ret); -} - - -int lxt972_auto_negotiate(int phy_addr) -{ - u_int16_t tmp; - - if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) - return(0); - - /* Restart Auto_negotiation */ - tmp |= BMCR_ANRESTART; - davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); - - /*check AutoNegotiate complete */ - udelay (10000); - if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp)) - return(0); - - if (!(tmp & BMSR_ANEGCOMPLETE)) - return(0); - - return (lxt972_get_link_speed(phy_addr)); -} - -#endif /* CONFIG_CMD_NET */ - -#endif /* CONFIG_DRIVER_ETHER */ diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 919041521b..df500c8f35 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -68,7 +68,6 @@ err: /* * Set the mii mode as MII or RMII */ -#if defined(CONFIG_SOC_DA8XX) void davinci_emac_mii_mode_sel(int mode_sel) { int val; @@ -80,7 +79,7 @@ void davinci_emac_mii_mode_sel(int mode_sel) val |= (1 << 8); writel(val, &davinci_syscfg_regs->cfgchip3); } -#endif + /* * If there is no MAC address in the environment, then it will be initialized * (silently) from the value in the EEPROM. @@ -106,7 +105,6 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) } #endif /* CONFIG_DRIVER_TI_EMAC */ -#if defined(CONFIG_SOC_DA8XX) void irq_init(void) { /* @@ -135,4 +133,3 @@ int da8xx_configure_lpsc_items(const struct lpsc_resource *item, return 0; } -#endif diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c index 9c3ff917bb..dae10aa03b 100644 --- a/arch/arm/mach-davinci/psc.c +++ b/arch/arm/mach-davinci/psc.c @@ -33,19 +33,8 @@ static void lpsc_transition(unsigned int id, unsigned int state) { dv_reg_p mdstat, mdctl, ptstat, ptcmd; -#ifdef CONFIG_SOC_DA8XX struct davinci_psc_regs *psc_regs; -#endif -#ifndef CONFIG_SOC_DA8XX - if (id >= DAVINCI_LPSC_GEM) - return; /* Don't work on DSP Power Domain */ - - mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); - mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); - ptstat = REG_P(PSC_PTSTAT); - ptcmd = REG_P(PSC_PTCMD); -#else if (id < DAVINCI_LPSC_PSC1_BASE) { if (id >= PSC_PSC0_MODULE_ID_CNT) return; @@ -62,7 +51,6 @@ static void lpsc_transition(unsigned int id, unsigned int state) } ptstat = &psc_regs->ptstat; ptcmd = &psc_regs->ptcmd; -#endif while (readl(ptstat) & 0x01) continue; @@ -71,29 +59,6 @@ static void lpsc_transition(unsigned int id, unsigned int state) return; /* Already in that state */ writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); - - switch (id) { -#ifdef CONFIG_SOC_DM644X - /* Special treatment for some modules as for sprue14 p.7.4.2 */ - case DAVINCI_LPSC_VPSSSLV: - case DAVINCI_LPSC_EMAC: - case DAVINCI_LPSC_EMAC_WRAPPER: - case DAVINCI_LPSC_MDIO: - case DAVINCI_LPSC_USB: - case DAVINCI_LPSC_ATA: - case DAVINCI_LPSC_VLYNQ: - case DAVINCI_LPSC_UHPI: - case DAVINCI_LPSC_DDR_EMIF: - case DAVINCI_LPSC_AEMIF: - case DAVINCI_LPSC_MMC_SD: - case DAVINCI_LPSC_MEMSTICK: - case DAVINCI_LPSC_McBSP: - case DAVINCI_LPSC_GPIO: - writel(readl(mdctl) | 0x200, mdctl); - break; -#endif - } - writel(0x01, ptcmd); while (readl(ptstat) & 0x01) @@ -116,44 +81,3 @@ void lpsc_disable(unsigned int id) { lpsc_transition(id, 0x0); } - -/* Not all DaVinci chips have a DSP power domain. */ -#ifdef CONFIG_SOC_DM644X - -/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */ -#if !defined(CONFIG_SYS_USE_DSPLINK) -void dsp_on(void) -{ - int i; - - if (REG(PSC_PDSTAT1) & 0x1f) - return; /* Already on */ - - REG(PSC_GBLCTL) |= 0x01; - REG(PSC_PDCTL1) |= 0x01; - REG(PSC_PDCTL1) &= ~0x100; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; - REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; - REG(PSC_PTCMD) = 0x02; - - for (i = 0; i < 100; i++) { - if (REG(PSC_EPCPR) & 0x02) - break; - } - - REG(PSC_CHP_SHRTSW) = 0x01; - REG(PSC_PDCTL1) |= 0x100; - REG(PSC_EPCCR) = 0x02; - - for (i = 0; i < 100; i++) { - if (!(REG(PSC_PTSTAT) & 0x02)) - break; - } - - REG(PSC_GBLCTL) &= ~0x1f; -} -#endif /* CONFIG_SYS_USE_DSPLINK */ - -#endif /* have a DSP */ diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index c9aaa4841b..103639e347 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -33,12 +33,7 @@ void putc(char c) void spl_board_init(void) { -#ifdef CONFIG_SOC_DM365 - dm36x_lowlevel_init(0); -#endif -#ifdef CONFIG_SOC_DA8XX arch_cpu_init(); -#endif preloader_console_init(); } diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 3807770362..14347e7c7d 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -116,7 +116,6 @@ config TARGET_SNOW config TARGET_SPRING bool "Spring board" select OF_CONTROL - select SPL_DISABLE_OF_CONTROL select SUPPORT_SPL config TARGET_SMDK5420 @@ -150,7 +149,6 @@ config TARGET_ESPRESSO7420 select OF_CONTROL select PINCTRL select PINCTRL_EXYNOS7420 - select SPL_DISABLE_OF_CONTROL select SUPPORT_SPL endchoice diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f99bd3bf65..a832e1dc8c 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -116,6 +116,13 @@ config TARGET_DB_88F6820_AMC config TARGET_TURRIS_OMNIA bool "Support Turris Omnia" select 88F6820 + select BOARD_LATE_INIT + select DM_I2C + select I2C_MUX + select I2C_MUX_PCA954x + select SPL_I2C_MUX + select SYS_I2C_MVTWSI + select ATSHA204A config TARGET_TURRIS_MOX bool "Support Turris Mox" diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b9a026abb5..282d728b82 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -34,7 +34,6 @@ config ROCKCHIP_RK3188 select SPL_RAM select SPL_DRIVERS_MISC_SUPPORT select SPL_ROCKCHIP_EARLYRETURN_TO_BROM - select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -50,7 +49,6 @@ config ROCKCHIP_RK322X select SUPPORT_SPL select SPL select ROCKCHIP_BROM_HELPER - select DEBUG_UART_BOARD_INIT help The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7 including NEON and GPU, Mali-400 graphics, several DDR3 options @@ -102,7 +100,6 @@ config ROCKCHIP_RK3368 imply SPL_SEPARATE_BSS imply SPL_SERIAL_SUPPORT imply TPL_SERIAL_SUPPORT - select DEBUG_UART_BOARD_INIT help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised into a big and little cluster with 4 cores each) Cortex-A53 including @@ -135,7 +132,6 @@ config ROCKCHIP_RK3399 select SPL_SEPARATE_BSS select SPL_SERIAL_SUPPORT select SPL_DRIVERS_MISC_SUPPORT - select DEBUG_UART_BOARD_INIT select BOARD_LATE_INIT select ROCKCHIP_BROM_HELPER help @@ -192,7 +188,7 @@ config ROCKCHIP_BOOT_MODE_REG default 0x10300580 if ROCKCHIP_RV1108 default 0 help - The Soc will enter to different boot mode(defined in asm/arch/boot_mode.h) + The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. config ROCKCHIP_SPL_RESERVE_IRAM diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index f32b3c4ce5..08f80bd91a 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -6,7 +6,7 @@ #include <common.h> #include <adc.h> #include <asm/io.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/boot_mode.h> #if (CONFIG_ROCKCHIP_BOOT_MODE_REG == 0) diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index 2f2f73aedd..9ccb45e6ac 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -4,8 +4,8 @@ */ #include <common.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/io.h> #include <asm/setjmp.h> #include <asm/system.h> diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 5ec69f1311..110d06dba5 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -6,31 +6,13 @@ #include <common.h> #include <debug_uart.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk3036.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> - -#define GRF_BASE 0x20008000 - -#define DEBUG_UART_BASE 0x20068000 +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/sdram_rk3036.h> +#include <asm/arch-rockchip/timer.h> void board_init_f(ulong dummy) { -#ifdef EARLY_DEBUG - struct rk3036_grf * const grf = (void *)GRF_BASE; - /* - * NOTE: sd card and debug uart use same iomux in rk3036, - * so if you enable uart, - * you can not boot from sdcard - */ - rk_clrsetreg(&grf->gpio1c_iomux, - GPIO1C3_MASK << GPIO1C3_SHIFT | - GPIO1C2_MASK << GPIO1C2_SHIFT, - GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | - GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); +#ifdef CONFIG_DEBUG_UART debug_uart_init(); #endif rockchip_timer_init(); diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 872bed9606..2094a4336d 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -9,11 +9,11 @@ #include <ram.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/sdram_rk3036.h> #include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index c63db343e2..5e04d20448 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -9,7 +9,7 @@ config TARGET_KYLIN_RK3036 select BOARD_LATE_INIT config SYS_SOC - default "rockchip" + default "rk3036" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 20d28f7c21..299fc50635 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -10,4 +10,5 @@ ifndef CONFIG_SPL_BUILD obj-y += syscon_rk3036.o endif +obj-y += rk3036.o obj-y += sdram_rk3036.o diff --git a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c index 2145c59fcd..20e2ed6813 100644 --- a/arch/arm/mach-rockchip/rk3036/clk_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/clk_rk3036.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3036.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3036/rk3036.c b/arch/arm/mach-rockchip/rk3036/rk3036.c new file mode 100644 index 0000000000..481af8a934 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3036/rk3036.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0x20008000 + struct rk3036_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_MMC0_D1, + GPIO1C3_UART2_SOUT, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_MMC0_D0, + GPIO1C2_UART2_SIN, + }; + /* + * NOTE: sd card and debug uart use same iomux in rk3036, + * so if you enable uart, + * you can not boot from sdcard + */ + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C3_MASK << GPIO1C3_SHIFT | + GPIO1C2_MASK << GPIO1C2_SHIFT, + GPIO1C3_UART2_SOUT << GPIO1C3_SHIFT | + GPIO1C2_UART2_SIN << GPIO1C2_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c index 2012d9fe04..1d940a0d77 100644 --- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c @@ -5,12 +5,12 @@ #include <common.h> #include <asm/io.h> #include <asm/types.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/grf_rk3036.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk3036.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/cru_rk3036.h> +#include <asm/arch-rockchip/grf_rk3036.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk3036.h> +#include <asm/arch-rockchip/timer.h> +#include <asm/arch-rockchip/uart.h> /* * we can not fit the code to access the device tree in SPL diff --git a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c index d3f4cc77f1..c2fd160799 100644 --- a/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c +++ b/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3036_syscon_ids[] = { { .compatible = "rockchip,rk3036-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c index 7fd667a0b8..b1c66382e3 100644 --- a/arch/arm/mach-rockchip/rk3128-board.c +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -8,11 +8,11 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk3128.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/grf_rk3128.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/timer.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index 40655a22b5..a82b7dc063 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -14,7 +14,7 @@ config TARGET_EVB_RK3128 endchoice config SYS_SOC - default "rockchip" + default "rk3128" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c index b9b0297579..827750bf98 100644 --- a/arch/arm/mach-rockchip/rk3128/clk_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/clk_rk3128.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3128.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3128.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c index 8117895434..1406d5d0d3 100644 --- a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3128_syscon_ids[] = { { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index 5c09b0e4ae..77b9b36d35 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -15,14 +15,14 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3188.h> -#include <asm/arch/sdram.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3188.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -93,38 +93,12 @@ static int setup_arm_clock(void) return ret; } -void board_debug_uart_init(void) -{ - /* Enable early UART on the RK3188 */ -#define GRF_BASE 0x20008000 - struct rk3188_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3, - GPIO1B1_GPIO = 0, - GPIO1B1_UART2_SOUT, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_UART2_SIN, - }; - - /* Enable early UART on the RK3188 */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK << GPIO1B1_SHIFT | - GPIO1B0_MASK << GPIO1B0_SHIFT, - GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | - GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 3802395bc0..e03759f789 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -10,11 +10,11 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/boot_mode.h> #include <dm/pinctrl.h> __weak int rk_board_late_init(void) diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index 2bb35662d1..a6fc691fb6 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -10,7 +10,7 @@ config TARGET_ROCK UART and GPIOs. config SYS_SOC - default "rockchip" + default "rk3188" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile index 7fa010405b..7dc123a3d2 100644 --- a/arch/arm/mach-rockchip/rk3188/Makefile +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -6,5 +6,6 @@ ifndef CONFIG_TPL_BUILD obj-y += clk_rk3188.o +obj-y += rk3188.o obj-y += syscon_rk3188.o endif diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c index e8fcec70cd..9d4fc37eda 100644 --- a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3188/rk3188.c b/arch/arm/mach-rockchip/rk3188/rk3188.c new file mode 100644 index 0000000000..933484e0df --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/rk3188.c @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3, + GPIO1B1_GPIO = 0, + GPIO1B1_UART2_SOUT, + GPIO1B1_JTAG_TDO, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_UART2_SIN, + GPIO1B0_JTAG_TDI, + }; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c index 6572bfa6a2..94f4ec7227 100644 --- a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3188_syscon_ids[] = { { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC }, diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 1e718f2694..888310efbe 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -9,55 +9,14 @@ #include <ram.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/timer.h> u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; } -#define GRF_BASE 0x11000000 -#define SGRF_BASE 0x10140000 - -#define DEBUG_UART_BASE 0x11030000 - -void board_debug_uart_init(void) -{ - static struct rk322x_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART1_SIN, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, - }; - enum { - CON_IOMUX_UART2SEL_SHIFT= 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - }; - - /* Enable early UART2 channel 1 on the RK322x */ - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); -} #define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) @@ -65,6 +24,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -75,7 +35,7 @@ void board_init_f(ulong dummy) */ debug_uart_init(); printascii("SPL Init"); - +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index 5659248178..6170c76f8b 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -8,10 +8,10 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/boot_mode.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> -#include <asm/arch/grf_rk322x.h> +#include <asm/arch-rockchip/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/periph.h> DECLARE_GLOBAL_DATA_PTR; @@ -29,37 +29,10 @@ int board_late_init(void) int board_init(void) { -#include <asm/arch/grf_rk322x.h> +#include <asm/arch-rockchip/grf_rk322x.h> /* Enable early UART2 channel 1 on the RK322x */ #define GRF_BASE 0x11000000 - struct rk322x_grf * const grf = (void *)GRF_BASE; - enum { - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_UART21_SIN, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_UART1_SOUT, - GPIO1B1_UART21_SOUT, - }; - enum { - CON_IOMUX_UART2SEL_SHIFT= 8, - CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, - CON_IOMUX_UART2SEL_2 = 0, - CON_IOMUX_UART2SEL_21, - }; - - rk_clrsetreg(&grf->gpio1b_iomux, - GPIO1B1_MASK | GPIO1B2_MASK, - GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | - GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->con_iomux, - CON_IOMUX_UART2SEL_MASK, - CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); + static struct rk322x_grf * const grf = (void *)GRF_BASE; /* * The integrated macphy is enabled by default, disable it diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index dc8071e4f3..8a1f95f785 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -5,7 +5,7 @@ config TARGET_EVB_RK3229 select BOARD_LATE_INIT config SYS_SOC - default "rockchip" + default "rk322x" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rk322x/Makefile b/arch/arm/mach-rockchip/rk322x/Makefile index ecb3e8dfda..89b0fed692 100644 --- a/arch/arm/mach-rockchip/rk322x/Makefile +++ b/arch/arm/mach-rockchip/rk322x/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # - obj-y += clk_rk322x.o +obj-y += rk322x.o obj-y += syscon_rk322x.o diff --git a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c index accf9443b0..958c7b82b9 100644 --- a/arch/arm/mach-rockchip/rk322x/clk_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/clk_rk322x.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk322x/rk322x.c b/arch/arm/mach-rockchip/rk322x/rk322x.c new file mode 100644 index 0000000000..e5250bc784 --- /dev/null +++ b/arch/arm/mach-rockchip/rk322x/rk322x.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ +#include <asm/io.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/hardware.h> + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0x11000000 + static struct rk322x_grf * const grf = (void *)GRF_BASE; + enum { + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_UART1_SIN, + GPIO1B2_UART21_SIN, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_UART1_SOUT, + GPIO1B1_UART21_SOUT, + }; + enum { + CON_IOMUX_UART2SEL_SHIFT = 8, + CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT, + CON_IOMUX_UART2SEL_2 = 0, + CON_IOMUX_UART2SEL_21, + }; + + /* Enable early UART2 channel 1 on the RK322x */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B2_MASK, + GPIO1B2_UART21_SIN << GPIO1B2_SHIFT | + GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->con_iomux, + CON_IOMUX_UART2SEL_MASK, + CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c index 9aa64f8f1f..0d9dca8173 100644 --- a/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c +++ b/arch/arm/mach-rockchip/rk322x/syscon_rk322x.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk322x_syscon_ids[] = { { .compatible = "rockchip,rk3228-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 93c772184d..d8d215db8a 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -14,15 +14,15 @@ #include <spl.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sys_proto.h> +#include <asm/arch-rockchip/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> #include <dm/test.h> @@ -109,16 +109,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; - /* Example code showing how to enable the debug UART on RK3288 */ -#include <asm/arch/grf_rk3288.h> - /* Enable early UART on the RK3288 */ -#define GRF_BASE 0xff770000 - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -129,6 +120,7 @@ void board_init_f(ulong dummy) */ debug_uart_init(); debug("\nspl:debug uart enabled in %s\n", __func__); +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c index 2aa63f515a..787129bbae 100644 --- a/arch/arm/mach-rockchip/rk3288-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -10,28 +10,17 @@ #include <spl.h> #include <version.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/sys_proto.h> +#include <asm/arch-rockchip/timer.h> -#define GRF_BASE 0xff770000 void board_init_f(ulong dummy) { struct udevice *dev; int ret; - /* Example code showing how to enable the debug UART on RK3288 */ - /* Enable early UART on the RK3288 */ - struct rk3288_grf * const grf = (void *)GRF_BASE; - - rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | - GPIO7C6_MASK << GPIO7C6_SHIFT, - GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | - GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * @@ -41,7 +30,7 @@ void board_init_f(ulong dummy) * printascii("string"); */ debug_uart_init(); - +#endif ret = spl_early_init(); if (ret) { debug("spl_early_init() failed: %d\n", ret); diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 9c4f7f219f..41e9786d46 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -9,12 +9,12 @@ #include <ram.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/periph.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/qos_rk3288.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/qos_rk3288.h> +#include <asm/arch-rockchip/boot_mode.h> #include <asm/gpio.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> @@ -321,7 +321,6 @@ int board_early_init_f(void) { const uintptr_t GRF_SOC_CON0 = 0xff770244; const uintptr_t GRF_SOC_CON2 = 0xff77024c; - struct udevice *pinctrl; struct udevice *dev; int ret; @@ -335,18 +334,7 @@ int board_early_init_f(void) debug("CLK init failed: %d\n", ret); return ret; } - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - return ret; - } - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - return ret; - } rk_setreg(GRF_SOC_CON2, 1 << 0); /* diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index bce8023881..50680ce606 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,7 +148,7 @@ config ROCKCHIP_FAST_SPL and have the required PMIC code. config SYS_SOC - default "rockchip" + default "rk3288" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c index 6ca2271869..e64ee86f08 100644 --- a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c index a725abc5a5..7941ca68a6 100644 --- a/arch/arm/mach-rockchip/rk3288/rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/rk3288.c @@ -3,16 +3,31 @@ * Copyright (c) 2016 Rockchip Electronics Co., Ltd */ #include <asm/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3288.h> -#define GRF_SOC_CON2 0xff77024c +#define GRF_BASE 0xff770000 int arch_cpu_init(void) { /* We do some SoC one time setting here. */ + struct rk3288_grf * const grf = (void *)GRF_BASE; /* Use rkpwm by default */ - rk_setreg(GRF_SOC_CON2, 1 << 0); + rk_setreg(&grf->soc_con2, 1 << 0); return 0; } + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* Enable early UART on the RK3288 */ + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); +} +#endif diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index 3bc80281c7..dff2caa598 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -7,7 +7,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3288_syscon_ids[] = { { .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC }, diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index 43afba2430..6c5c4303a3 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -13,7 +13,7 @@ config TARGET_EVB_RK3328 endchoice config SYS_SOC - default "rockchip" + default "rk3328" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c index e5c2ce5766..f64f0cbbe5 100644 --- a/arch/arm/mach-rockchip/rk3328/clk_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/clk_rk3328.c @@ -5,8 +5,8 @@ #include <common.h> #include <dm.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index a519f5fb84..1cf829dc34 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/armv8/mmu.h> #include <asm/io.h> diff --git a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c index 28dd8cb20a..8a0eceb178 100644 --- a/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/syscon_rk3328.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> #include <dm.h> #include <syscon.h> diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index 230850ad6c..b055ed4aee 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -9,17 +9,9 @@ #include <ram.h> #include <spl.h> #include <asm/io.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> -void board_debug_uart_init(void) -{ -} - void board_init_f(ulong dummy) { struct udevice *pinctrl; diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c index f90a1fdca7..dc65a021c8 100644 --- a/arch/arm/mach-rockchip/rk3368-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -10,12 +10,11 @@ #include <spl.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/hardware.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/timer.h> /* * The SPL (and also the full U-Boot stage on the RK3368) will run in @@ -79,42 +78,12 @@ static void sgrf_init(void) rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); } -void board_debug_uart_init(void) -{ - /* - * N.B.: This is called before the device-model has been - * initialised. For this reason, we can not access - * the GRF address range using the syscon API. - */ - struct rk3368_grf * const grf = - (struct rk3368_grf * const)0xff770000; - - enum { - GPIO2D1_MASK = GENMASK(3, 2), - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT = (1 << 2), - - GPIO2D0_MASK = GENMASK(1, 0), - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN = (1 << 0), - }; - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3368 */ - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D0_MASK, GPIO2D0_UART0_SIN); - rk_clrsetreg(&grf->gpio2d_iomux, - GPIO2D1_MASK, GPIO2D1_UART0_SOUT); -#endif -} - void board_init_f(ulong dummy) { struct udevice *dev; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 7c9b722b00..325572a7e4 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -43,7 +43,7 @@ config TARGET_EVB_PX5 endchoice config SYS_SOC - default "rockchip" + default "rk3368" source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c index 722160dfdc..55e5dd768a 100644 --- a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c index 6d5d4cc760..1ed06c5352 100644 --- a/arch/arm/mach-rockchip/rk3368/rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/rk3368.c @@ -7,9 +7,9 @@ #include <common.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/grf_rk3368.h> #include <syscon.h> DECLARE_GLOBAL_DATA_PTR; @@ -96,3 +96,34 @@ int arch_early_init_r(void) return mcu_init(); } #endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + /* + * N.B.: This is called before the device-model has been + * initialised. For this reason, we can not access + * the GRF address range using the syscon API. + */ +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), + }; + + /* Enable early UART0 on the RK3368 */ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D0_MASK, GPIO2D0_UART0_SIN); + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index c08ce437ea..4ba94f2e80 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -8,7 +8,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3368_syscon_ids[] = { { .compatible = "rockchip,rk3368-grf", diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index ccc136f388..800ca80022 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -12,12 +12,12 @@ #include <spl_gpio.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/bootrom.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/periph.h> -#include <asm/arch/sys_proto.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/sys_proto.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -127,53 +127,6 @@ void secure_timer_init(void) writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); } -void board_debug_uart_init(void) -{ -#define GRF_BASE 0xff770000 -#define GPIO0_BASE 0xff720000 -#define PMUGRF_BASE 0xff320000 - struct rk3399_grf_regs * const grf = (void *)GRF_BASE; -#ifdef CONFIG_TARGET_CHROMEBOOK_BOB - struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; - struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; -#endif - -#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) - /* Enable early UART0 on the RK3399 */ - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C0_SEL_MASK, - GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); - rk_clrsetreg(&grf->gpio2c_iomux, - GRF_GPIO2C1_SEL_MASK, - GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); -#else -# ifdef CONFIG_TARGET_CHROMEBOOK_BOB - rk_setreg(&grf->io_vsel, 1 << 0); - - /* - * Let's enable these power rails here, we are already running the SPI - * Flash based code. - */ - spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); - - spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ - spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); -#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ - - /* Enable early UART2 channel C on the RK3399 */ - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C3_SEL_MASK, - GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); - rk_clrsetreg(&grf->gpio4c_iomux, - GRF_GPIO4C4_SEL_MASK, - GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); - /* Set channel C as UART2 input */ - rk_clrsetreg(&grf->soc_con7, - GRF_UART_DBG_SEL_MASK, - GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); -#endif -} void board_init_f(ulong dummy) { @@ -183,8 +136,7 @@ void board_init_f(ulong dummy) struct rk3399_grf_regs *grf; int ret; -#define EARLY_UART -#ifdef EARLY_UART +#ifdef CONFIG_DEBUG_UART debug_uart_init(); # ifdef CONFIG_TARGET_CHROMEBOOK_BOB diff --git a/arch/arm/mach-rockchip/rk3399-board.c b/arch/arm/mach-rockchip/rk3399-board.c index 137ec714c2..443c87cccc 100644 --- a/arch/arm/mach-rockchip/rk3399-board.c +++ b/arch/arm/mach-rockchip/rk3399-board.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/boot_mode.h> +#include <asm/arch-rockchip/boot_mode.h> int board_late_init(void) { diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 2408adb420..2c5c93c0b8 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -65,7 +65,7 @@ config TARGET_CHROMEBOOK_BOB endchoice config SYS_SOC - default "rockchip" + default "rk3399" config SYS_MALLOC_F_LEN default 0x0800 diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 98f7482f79..f0411c0a21 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> static int rockchip_get_cruclk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index d8467d7333..a7ccd4f3ed 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -4,13 +4,17 @@ */ #include <common.h> +#include <spl_gpio.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/gpio.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; #define GRF_EMMCCORE_CON11 0xff77f02c +#define GRF_BASE 0xff770000 static struct mm_region rk3399_mem_map[] = { { @@ -48,9 +52,60 @@ int dram_init_banksize(void) int arch_cpu_init(void) { /* We do some SoC one time setting here. */ + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; /* Emmc clock generator: disable the clock multipilier */ - rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); + rk_clrreg(&grf->emmccore_con[11], 0x0ff); return 0; } + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ +#define GRF_BASE 0xff770000 +#define GPIO0_BASE 0xff720000 +#define PMUGRF_BASE 0xff320000 + struct rk3399_grf_regs * const grf = (void *)GRF_BASE; +#ifdef CONFIG_TARGET_CHROMEBOOK_BOB + struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; + struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; +#endif + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3399 */ + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C0_SEL_MASK, + GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2c_iomux, + GRF_GPIO2C1_SEL_MASK, + GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); +#else +# ifdef CONFIG_TARGET_CHROMEBOOK_BOB + rk_setreg(&grf->io_vsel, 1 << 0); + + /* + * Let's enable these power rails here, we are already running the SPI + * Flash based code. + */ + spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); + + spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ + spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); +#endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ + + /* Enable early UART2 channel C on the RK3399 */ + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C3_SEL_MASK, + GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); + rk_clrsetreg(&grf->gpio4c_iomux, + GRF_GPIO4C4_SEL_MASK, + GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); + /* Set channel C as UART2 input */ + rk_clrsetreg(&grf->soc_con7, + GRF_UART_DBG_SEL_MASK, + GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); +#endif +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c index 98f4be970f..a8bb5b11e5 100644 --- a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rk3399_syscon_ids[] = { { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c index e751f29d0f..f20e64f48e 100644 --- a/arch/arm/mach-rockchip/rk_timer.c +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -4,7 +4,7 @@ */ #include <common.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/timer.h> #include <asm/io.h> #include <linux/types.h> diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig index 8883aeae7a..e3a63b80e1 100644 --- a/arch/arm/mach-rockchip/rv1108/Kconfig +++ b/arch/arm/mach-rockchip/rv1108/Kconfig @@ -23,7 +23,7 @@ config TARGET_ELGIN_RV1108 RV1108 ELGIN is a board based on the Rockchip RV1108. config SYS_SOC - default "rockchip" + default "rv1108" config SYS_MALLOC_F_LEN default 0x400 diff --git a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c index 5f3705cc39..58a7e889cc 100644 --- a/arch/arm/mach-rockchip/rv1108/clk_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/clk_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rv1108.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1108.h> int rockchip_get_clk(struct udevice **devp) { diff --git a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c index 5a0f0a5611..babdf5720b 100644 --- a/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c +++ b/arch/arm/mach-rockchip/rv1108/syscon_rv1108.c @@ -6,7 +6,7 @@ #include <common.h> #include <dm.h> #include <syscon.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> static const struct udevice_id rv1108_syscon_ids[] = { { .compatible = "rockchip,rv1108-grf", .data = ROCKCHIP_SYSCON_GRF }, diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c index a27138083a..8684dbd4fa 100644 --- a/arch/arm/mach-rockchip/sdram_common.c +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -7,7 +7,7 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/sdram_common.h> #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 86d5d2b62b..c3ca8cdf3b 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -39,6 +39,6 @@ void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif -void do_bridge_reset(int enable); +void do_bridge_reset(int enable, unsigned int mask); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h index dd58922cec..5e490d182e 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h @@ -9,6 +9,7 @@ #include <dt-bindings/reset/altr,rst-mgr.h> void reset_deassert_peripherals_handoff(void); +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h); void socfpga_bridges_reset(int enable); struct socfpga_reset_manager { diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index ec8339e045..e1ea8eb73e 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -126,17 +126,22 @@ int arch_cpu_init(void) #ifndef CONFIG_SPL_BUILD static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - if (argc != 2) + unsigned int mask = ~0; + + if (argc < 2 || argc > 3) return CMD_RET_USAGE; argv++; + if (argc == 3) + mask = simple_strtoul(argv[1], NULL, 16); + switch (*argv[0]) { case 'e': /* Enable */ - do_bridge_reset(1); + do_bridge_reset(1, mask); break; case 'd': /* Disable */ - do_bridge_reset(0); + do_bridge_reset(0, mask); break; default: return CMD_RET_USAGE; @@ -145,10 +150,10 @@ static int do_bridge(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -U_BOOT_CMD(bridge, 2, 1, do_bridge, +U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" "" ); diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c index 63b8c75d31..2e2a40b65d 100644 --- a/arch/arm/mach-socfpga/misc_arria10.c +++ b/arch/arm/mach-socfpga/misc_arria10.c @@ -115,7 +115,7 @@ int print_cpuinfo(void) } #endif -void do_bridge_reset(int enable) +void do_bridge_reset(int enable, unsigned int mask) { if (enable) socfpga_reset_deassert_bridges_handoff(); diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 9865f5b5b1..71547d81ab 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -210,47 +210,26 @@ static struct socfpga_reset_manager *reset_manager_base = static struct socfpga_sdr_ctrl *sdr_ctrl = (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS; -static void socfpga_sdram_apply_static_cfg(void) +void do_bridge_reset(int enable, unsigned int mask) { - const u32 applymask = 0x8; - u32 val = readl(&sdr_ctrl->static_cfg) | applymask; - - /* - * SDRAM staticcfg register specific: - * When applying the register setting, the CPU must not access - * SDRAM. Luckily for us, we can abuse i-cache here to help us - * circumvent the SDRAM access issue. The idea is to make sure - * that the code is in one full i-cache line by branching past - * it and back. Once it is in the i-cache, we execute the core - * of the code and apply the register settings. - * - * The code below uses 7 instructions, while the Cortex-A9 has - * 32-byte cachelines, thus the limit is 8 instructions total. - */ - asm volatile( - ".align 5 \n" - " b 2f \n" - "1: str %0, [%1] \n" - " dsb \n" - " isb \n" - " b 3f \n" - "2: b 1b \n" - "3: nop \n" - : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc"); -} + int i; -void do_bridge_reset(int enable) -{ if (enable) { + socfpga_bridges_set_handoff_regs(!(mask & BIT(0)), + !(mask & BIT(1)), + !(mask & BIT(2))); + for (i = 0; i < 2; i++) { /* Reload SW setting cache */ + iswgrp_handoff[i] = + readl(&sysmgr_regs->iswgrp_handoff[i]); + } + writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); - socfpga_sdram_apply_static_cfg(); writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst); writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); writel(iswgrp_handoff[1], &nic301_regs->remap); } else { writel(0, &sysmgr_regs->fpgaintfgrp_module); writel(0, &sdr_ctrl->fpgaport_rst); - socfpga_sdram_apply_static_cfg(); writel(0, &reset_manager_base->brg_mod_reset); writel(1, &nic301_regs->remap); } diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 113eace650..60c96090ce 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -150,7 +150,7 @@ int arch_early_init_r(void) return 0; } -void do_bridge_reset(int enable) +void do_bridge_reset(int enable, unsigned int mask) { socfpga_bridges_reset(enable); } diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c index 25baef79bc..89a384b59c 100644 --- a/arch/arm/mach-socfpga/reset_manager_gen5.c +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c @@ -73,6 +73,28 @@ void reset_deassert_peripherals_handoff(void) #define L3REGS_REMAP_HPS2FPGA_MASK 0x08 #define L3REGS_REMAP_OCRAM_MASK 0x01 +void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h) +{ + u32 brgmask = 0x0; + u32 l3rmask = L3REGS_REMAP_OCRAM_MASK; + + if (h2f) + brgmask |= BIT(0); + else + l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK; + + if (lwh2f) + brgmask |= BIT(1); + else + l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK; + + if (f2h) + brgmask |= BIT(2); + + writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]); + writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]); +} + void socfpga_bridges_reset(int enable) { const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK | @@ -81,10 +103,10 @@ void socfpga_bridges_reset(int enable) if (enable) { /* brdmodrst */ - writel(0xffffffff, &reset_manager_base->brg_mod_reset); + writel(0x7, &reset_manager_base->brg_mod_reset); + writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS); } else { - writel(0, &sysmgr_regs->iswgrp_handoff[0]); - writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]); + socfpga_bridges_set_handoff_regs(false, false, false); /* Check signal from FPGA. */ if (!fpgamgr_test_fpga_ready()) { diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 9dd0afb4bc..bd2a9fe5ae 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -175,8 +175,9 @@ void board_init_f(ulong dummy) sysmgr_pinmux_init(); sysmgr_config_warmrstcfgio(0); - /* De-assert reset for bridges based on handoff */ - socfpga_bridges_reset(0); + /* De-assert reset for peripherals and bridges based on handoff */ + reset_deassert_peripherals_handoff(); + socfpga_bridges_set_handoff_regs(true, true, true); debug("Unfreezing/Thaw all I/O banks\n"); /* unfreeze / thaw all IO banks */ @@ -205,7 +206,4 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); hang(); } - - if (!socfpga_is_booting_from_fpga()) - socfpga_bridges_reset(1); } diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 8a4872343b..3818e3752a 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -16,10 +16,6 @@ #include <fdt_support.h> #include <environment.h> -#ifdef CONFIG_WDT_ARMADA_37XX -#include <wdt.h> -#endif - #include "mox_sp.h" #define MAX_MOX_MODULES 10 diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 4c08f810a2..ad6e29021e 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -18,40 +18,38 @@ #include <dm/uclass.h> #include <fdt_support.h> #include <time.h> - -#ifdef CONFIG_ATSHA204A # include <atsha204a-i2c.h> -#endif - -#ifdef CONFIG_WDT_ORION -# include <wdt.h> -#endif #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> DECLARE_GLOBAL_DATA_PTR; -#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_EEPROM 0x54 -#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 -#define OMNIA_I2C_EEPROM_ADDRLEN 2 +#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" + +#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a +#define OMNIA_I2C_MCU_CHIP_LEN 1 + +#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54 +#define OMNIA_I2C_EEPROM_CHIP_LEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 -#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0" -#define OMNIA_I2C_MCU_ADDR_STATUS 0x1 -#define OMNIA_I2C_MCU_SATA 0x20 -#define OMNIA_I2C_MCU_CARDDET 0x10 -#define OMNIA_I2C_MCU 0x2a -#define OMNIA_I2C_MCU_WDT_ADDR 0x0b +enum mcu_commands { + CMD_GET_STATUS_WORD = 0x01, + CMD_GET_RESET = 0x09, + CMD_WATCHDOG_STATE = 0x0b, +}; + +enum status_word_bits { + CARD_DET_STSBIT = 0x0010, + MSATA_IND_STSBIT = 0x0020, +}; #define OMNIA_ATSHA204_OTP_VERSION 0 #define OMNIA_ATSHA204_OTP_SERIAL 1 #define OMNIA_ATSHA204_OTP_MAC0 3 #define OMNIA_ATSHA204_OTP_MAC1 4 -#define MVTWSI_ARMADA_DEBUG_REG 0x8c - /* * Those values and defines are taken from the Marvell U-Boot version * "u-boot-2013.01-2014_T3.0" @@ -87,48 +85,97 @@ static struct serdes_map board_serdes_map_sata[] = { {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} }; -static bool omnia_detect_sata(void) +static struct udevice *omnia_get_i2c_chip(const char *name, uint addr, + uint offset_len) { struct udevice *bus, *dev; - int ret, retry = 3; - u16 mode; - - puts("SERDES0 card detect: "); + int ret; - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus!\n"); - return false; + ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus); + if (ret) { + printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n", + OMNIA_I2C_BUS_NAME, ret); + return NULL; } - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); + ret = i2c_get_chip(bus, addr, offset_len, &dev); if (ret) { - puts("Cannot get MCU chip!\n"); - return false; + printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n", + name, ret); + return NULL; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *) &mode, 2); - if (!ret) - break; - } + return dev; +} + +static int omnia_mcu_read(u8 cmd, void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_read(chip, cmd, buf, len); +} - if (!retry) { - puts("I2C read failed! Default PEX\n"); +#ifndef CONFIG_SPL_BUILD +static int omnia_mcu_write(u8 cmd, const void *buf, int len) +{ + struct udevice *chip; + + chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, + OMNIA_I2C_MCU_CHIP_LEN); + if (!chip) + return -ENODEV; + + return dm_i2c_write(chip, cmd, buf, len); +} + +static bool disable_mcu_watchdog(void) +{ + int ret; + + puts("Disabling MCU watchdog... "); + + ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); + if (ret) { + printf("omnia_mcu_write failed: %i\n", ret); return false; } - if (!(mode & OMNIA_I2C_MCU_CARDDET)) { - puts("NONE\n"); + puts("disabled\n"); + + return true; +} +#endif + +static bool omnia_detect_sata(void) +{ + int ret; + u16 stsword; + + puts("MiniPCIe/mSATA card detection... "); + + ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); + if (ret) { + printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", + ret); return false; } - if (mode & OMNIA_I2C_MCU_SATA) { - puts("SATA\n"); - return true; - } else { - puts("PEX\n"); + if (!(stsword & CARD_DET_STSBIT)) { + puts("none\n"); return false; } + + if (stsword & MSATA_IND_STSBIT) + puts("mSATA\n"); + else + puts("MiniPCIe\n"); + + return stsword & MSATA_IND_STSBIT ? true : false; } int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) @@ -153,48 +200,63 @@ struct omnia_eeprom { static bool omnia_read_eeprom(struct omnia_eeprom *oep) { - struct udevice *bus, *dev; - int ret, crc, retry = 3; + struct udevice *chip; + u32 crc; + int ret; + + chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, + OMNIA_I2C_EEPROM_CHIP_LEN); - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_EEPROM_DM_NAME, &bus)) { - puts("Cannot find EEPROM bus\n"); + if (!chip) return false; - } - ret = i2c_get_chip(bus, OMNIA_I2C_EEPROM, OMNIA_I2C_EEPROM_ADDRLEN, &dev); + ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep)); if (ret) { - puts("Cannot get EEPROM chip\n"); + printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret); return false; } - for (; retry > 0; --retry) { - ret = dm_i2c_read(dev, OMNIA_I2C_EEPROM_CONFIG_ADDR, (uchar *) oep, sizeof(struct omnia_eeprom)); - if (ret) - continue; - - if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { - puts("I2C EEPROM missing magic number!\n"); - continue; - } - - crc = crc32(0, (unsigned char *) oep, - sizeof(struct omnia_eeprom) - 4); - if (crc == oep->crc) { - break; - } else { - printf("CRC of EEPROM memory config failed! " - "calc=0x%04x saved=0x%04x\n", crc, oep->crc); - } + if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { + printf("bad EEPROM magic number (%08x, should be %08x)\n", + oep->magic, OMNIA_I2C_EEPROM_MAGIC); + return false; } - if (!retry) { - puts("I2C EEPROM read failed!\n"); + crc = crc32(0, (void *)oep, sizeof(*oep) - 4); + if (crc != oep->crc) { + printf("bad EEPROM CRC (stored %08x, computed %08x)\n", + oep->crc, crc); return false; } return true; } +static int omnia_get_ram_size_gb(void) +{ + static int ram_size; + struct omnia_eeprom oep; + + if (!ram_size) { + /* Get the board config from EEPROM */ + if (omnia_read_eeprom(&oep)) { + debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize); + + if (oep.ramsize == 0x2) + ram_size = 2; + else + ram_size = 1; + } else { + /* Hardcoded fallback */ + puts("Memory config from EEPROM read failed!\n"); + puts("Falling back to default 1 GiB!\n"); + ram_size = 1; + } + } + + return ram_size; +} + /* * Define the DDR layout / topology here in the board file. This will * be used by the DDR3 init code in the SPL U-Boot version to configure @@ -246,37 +308,10 @@ static struct mv_ddr_topology_map board_topology_map_2g = { struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) { - static int mem = 0; - struct omnia_eeprom oep; - - /* Get the board config from EEPROM */ - if (mem == 0) { - if(!omnia_read_eeprom(&oep)) - goto out; - - printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize); - - if (oep.ramsize == 0x2) - mem = 2; - else - mem = 1; - } - -out: - /* Hardcoded fallback */ - if (mem == 0) { - puts("WARNING: Memory config from EEPROM read failed.\n"); - puts("Falling back to default 1GiB map.\n"); - mem = 1; - } - - /* Return the board topology as defined in the board code */ - if (mem == 1) - return &board_topology_map_1g; - if (mem == 2) + if (omnia_get_ram_size_gb() == 2) return &board_topology_map_2g; - - return &board_topology_map_1g; + else + return &board_topology_map_1g; } #ifndef CONFIG_SPL_BUILD @@ -293,12 +328,47 @@ static int set_regdomain(void) printf("Regdomain set to %s\n", rd); return env_set("regdomain", rd); } + +/* + * default factory reset bootcommand on Omnia first sets all the front LEDs + * to green and then tries to load the rescue image from SPI flash memory and + * boot it + */ +#define OMNIA_FACTORY_RESET_BOOTCMD \ + "i2c dev 2; " \ + "i2c mw 0x2a.1 0x3 0x1c 1; " \ + "i2c mw 0x2a.1 0x4 0x1c 1; " \ + "mw.l 0x01000000 0x00ff000c; " \ + "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \ + "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \ + "sf probe; " \ + "sf read 0x1000000 0x100000 0x700000; " \ + "bootm 0x1000000; " \ + "bootz 0x1000000" + +static void handle_reset_button(void) +{ + int ret; + u8 reset_status; + + ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); + if (ret) { + printf("omnia_mcu_read failed: %i, reset status unknown!\n", + ret); + return; + } + + env_set_ulong("omnia_reset", reset_status); + + if (reset_status) { + printf("RESET button was pressed, overwriting bootcmd!\n"); + env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD); + } +} #endif int board_early_init_f(void) { - u32 i2c_debug_reg; - /* Configure MPP */ writel(0x11111111, MVEBU_MPP_BASE + 0x00); writel(0x11111111, MVEBU_MPP_BASE + 0x04); @@ -321,59 +391,16 @@ int board_early_init_f(void) writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); - /* - * Disable I2C debug mode blocking 0x64 I2C address. - * Note: that would be redundant once Turris Omnia migrates to DM_I2C, - * because the mvtwsi driver includes equivalent code. - */ - i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - i2c_debug_reg &= ~(1<<18); - writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG); - return 0; } -#ifndef CONFIG_SPL_BUILD -static bool disable_mcu_watchdog(void) -{ - struct udevice *bus, *dev; - int ret, retry = 3; - uchar buf[1] = {0x0}; - - if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus)) { - puts("Cannot find MCU bus! Can not disable MCU WDT.\n"); - return false; - } - - ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev); - if (ret) { - puts("Cannot get MCU chip! Can not disable MCU WDT.\n"); - return false; - } - - for (; retry > 0; --retry) - if (!dm_i2c_write(dev, OMNIA_I2C_MCU_WDT_ADDR, (uchar *) buf, 1)) - break; - - if (retry <= 0) { - puts("I2C MCU watchdog failed to disable!\n"); - return false; - } - - return true; -} -#endif - int board_init(void) { - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; #ifndef CONFIG_SPL_BUILD - if (disable_mcu_watchdog()) - puts("Disabled MCU startup watchdog.\n"); - - set_regdomain(); + disable_mcu_watchdog(); #endif return 0; @@ -383,17 +410,17 @@ int board_late_init(void) { #ifndef CONFIG_SPL_BUILD set_regdomain(); + handle_reset_button(); #endif return 0; } -#ifdef CONFIG_ATSHA204A static struct udevice *get_atsha204a_dev(void) { - static struct udevice *dev = NULL; + static struct udevice *dev; - if (dev != NULL) + if (dev) return dev; if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) { @@ -403,14 +430,12 @@ static struct udevice *get_atsha204a_dev(void) return dev; } -#endif int checkboard(void) { u32 version_num, serial_num; int err = 1; -#ifdef CONFIG_ATSHA204A struct udevice *dev = get_atsha204a_dev(); if (dev) { @@ -420,13 +445,13 @@ int checkboard(void) err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_VERSION, - (u8 *) &version_num); + (u8 *)&version_num); if (err) goto out; err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false, OMNIA_ATSHA204_OTP_SERIAL, - (u8 *) &serial_num); + (u8 *)&serial_num); if (err) goto out; @@ -434,13 +459,13 @@ int checkboard(void) } out: -#endif - + printf("Turris Omnia:\n"); + printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); if (err) - printf("Board: Turris Omnia (ver N/A). SN: N/A\n"); + printf(" Serial Number: unknown\n"); else - printf("Board: Turris Omnia SNL %08X%08X\n", - be32_to_cpu(version_num), be32_to_cpu(serial_num)); + printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), + be32_to_cpu(serial_num)); return 0; } @@ -458,7 +483,6 @@ static void increment_mac(u8 *mac) int misc_init_r(void) { -#ifdef CONFIG_ATSHA204A int err; struct udevice *dev = get_atsha204a_dev(); u8 mac0[4], mac1[4], mac[6]; @@ -503,8 +527,6 @@ int misc_init_r(void) eth_env_set_enetaddr("eth2addr", mac); out: -#endif - return 0; } diff --git a/board/elgin/elgin_rv1108/elgin_rv1108.c b/board/elgin/elgin_rv1108/elgin_rv1108.c index 3abc514412..0de1f4243e 100644 --- a/board/elgin/elgin_rv1108/elgin_rv1108.c +++ b/board/elgin/elgin_rv1108/elgin_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index d5acc4fe27..8c606463e4 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> void get_ddr_config(struct rk3036_ddr_config *config) { diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c index 63c84fccfe..c64c62f7b0 100644 --- a/board/rockchip/evb_rk3229/evb_rk3229.c +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -6,5 +6,5 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> +#include <asm/arch-rockchip/uart.h> diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index caad30641e..07ee8ce92c 100644 --- a/board/rockchip/evb_rk3399/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS @@ -5,3 +5,10 @@ F: board/rockchip/evb_rk3399 F: include/configs/evb_rk3399.h F: configs/evb-rk3399_defconfig F: configs/firefly-rk3399_defconfig + +ORANGEPI-RK3399 +M: Jagan Teki <jagan@amarulasolutions.com> +S: Maintained +F: configs/orangepi-rk3399_defconfig +F: arch/arm/dts/rk3399-u-boot.dtsi +F: arch/arm/dts/rk3399-orangepi-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 3e9e83f3ad..bf2ad98c47 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index 107929ee8a..457b110cd5 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> #include <fdtdec.h> -#include <asm/arch/grf_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/grf_rv1108.h> +#include <asm/arch-rockchip/hardware.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 3a2f08354f..2faeab9baf 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -6,8 +6,8 @@ #include <common.h> #include <dm.h> #include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_rk3036.h> #include <asm/gpio.h> void get_ddr_config(struct rk3036_ddr_config *config) diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index ea22cb985f..9bb93c7d16 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -4,8 +4,8 @@ */ #include <common.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig index cf71e4ce56..28816bc1a0 100644 --- a/board/siemens/taurus/Kconfig +++ b/board/siemens/taurus/Kconfig @@ -9,4 +9,20 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "taurus" +choice + prompt "Board Type AXM/TAURUS" + default BOARD_AXM + +config BOARD_AXM + bool "AXM board type" + help + Select this, if you want to build for AXM board. + +config BOARD_TAURUS + bool "TAURUS board type" + help + Select this, if you want to build for TAURUS board. + +endchoice + endif diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c index 8396ce502b..6ea97eb4e8 100644 --- a/board/siemens/taurus/taurus.c +++ b/board/siemens/taurus/taurus.c @@ -197,11 +197,11 @@ void mem_init(void) /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/ if (ram_size == 0x800) { - printf("\n\r 64MB"); + printf("\n\r 64MB\n"); sdramc_configure(AT91_SDRAMC_NC_9); } else { /* Size already initialized */ - printf("\n\r 128MB"); + printf("\n\r 128MB\n"); } } #endif @@ -282,24 +282,6 @@ int board_early_init_f(void) return 0; } -/* FIXME gpio code here need to handle through DM_GPIO */ -#ifndef CONFIG_DM_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0); -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1); -} -#endif - #ifdef CONFIG_USB_GADGET_AT91 #include <linux/usb/at91_udc.h> @@ -347,17 +329,6 @@ int dram_init(void) return 0; } -#ifndef CONFIG_DM_ETH -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); -#endif - return rc; -} -#endif - #if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_BOARD_AXM) /* diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index e207535df0..6cd5a5f18e 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -6,9 +6,9 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/timer.h> #include <syscon.h> int mach_cpu_init(void) diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 573e691457..c6b509c109 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -15,11 +15,11 @@ #include <asm/io.h> #include <asm/gpio.h> #include <asm/setup.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <u-boot/sha256.h> diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c index 04f4b8e693..37a599768b 100644 --- a/board/ti/am335x/mux.c +++ b/board/ti/am335x/mux.c @@ -399,7 +399,6 @@ void enable_board_pin_mux(void) configure_module_pin_mux(mii1_pin_mux); } /* Beaglebone LT pinmux */ - configure_module_pin_mux(mii1_pin_mux); configure_module_pin_mux(mmc0_pin_mux); #if defined(CONFIG_NAND) && defined(CONFIG_EMMC_BOOT) configure_module_pin_mux(nand_pin_mux); diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index d3775b2219..0f5ef3a09a 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/pinctrl.h> #include <dm/uclass-internal.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> #include <spl.h> diff --git a/cmd/bootefi.c b/cmd/bootefi.c index efaa548be4..f1d7d8bc66 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -297,18 +297,21 @@ static efi_status_t efi_install_fdt(const char *fdt_opt) static efi_status_t do_bootefi_exec(efi_handle_t handle) { efi_status_t ret; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; /* Transfer environment variable as load options */ ret = set_load_options(handle, "bootargs"); if (ret != EFI_SUCCESS) return ret; - /* we don't support much: */ - env_set("efi_8be4df61-93ca-11d2-aa0d-00e098032b8c_OsIndicationsSupported", - "{ro,boot}(blob)0000000000000000"); - /* Call our payload! */ - ret = EFI_CALL(efi_start_image(handle, NULL, NULL)); + ret = EFI_CALL(efi_start_image(handle, &exit_data_size, &exit_data)); + printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); + if (ret && exit_data) { + printf("## %ls\n", exit_data); + efi_free_pool(exit_data); + } efi_restore_gd(); @@ -361,7 +364,6 @@ static int do_efibootmgr(const char *fdt_opt) } ret = do_bootefi_exec(handle); - printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); if (ret != EFI_SUCCESS) return CMD_RET_FAILURE; @@ -476,7 +478,6 @@ static int do_bootefi_image(const char *image_opt, const char *fdt_opt) goto out; ret = do_bootefi_exec(handle); - printf("## Application terminated, r = %lu\n", ret & ~EFI_ERROR_MASK); out: if (mem_handle) diff --git a/cmd/efidebug.c b/cmd/efidebug.c index a40c4f4be2..c4ac9dd634 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -11,6 +11,7 @@ #include <efi_loader.h> #include <environment.h> #include <exports.h> +#include <hexdump.h> #include <malloc.h> #include <search.h> #include <linux/ctype.h> @@ -545,7 +546,10 @@ static int do_efi_boot_add(cmd_tbl_t *cmdtp, int flag, + sizeof(struct efi_device_path); /* for END */ /* optional data */ - lo.optional_data = (u8 *)(argc == 6 ? "" : argv[6]); + if (argc < 6) + lo.optional_data = NULL; + else + lo.optional_data = (const u8 *)argv[6]; size = efi_serialize_load_option(&lo, (u8 **)&data); if (!size) { @@ -615,12 +619,13 @@ static int do_efi_boot_rm(cmd_tbl_t *cmdtp, int flag, /** * show_efi_boot_opt_data() - dump UEFI load option * - * @id: Load option number - * @data: Value of UEFI load option variable + * @id: load option number + * @data: value of UEFI load option variable + * @size: size of the boot option * * Decode the value of UEFI load option variable and print information. */ -static void show_efi_boot_opt_data(int id, void *data) +static void show_efi_boot_opt_data(int id, void *data, size_t size) { struct efi_load_option lo; char *label, *p; @@ -638,7 +643,7 @@ static void show_efi_boot_opt_data(int id, void *data) utf16_utf8_strncpy(&p, lo.label, label_len16); printf("Boot%04X:\n", id); - printf("\tattributes: %c%c%c (0x%08x)\n", + printf(" attributes: %c%c%c (0x%08x)\n", /* ACTIVE */ lo.attributes & LOAD_OPTION_ACTIVE ? 'A' : '-', /* FORCE RECONNECT */ @@ -646,14 +651,16 @@ static void show_efi_boot_opt_data(int id, void *data) /* HIDDEN */ lo.attributes & LOAD_OPTION_HIDDEN ? 'H' : '-', lo.attributes); - printf("\tlabel: %s\n", label); + printf(" label: %s\n", label); dp_str = efi_dp_str(lo.file_path); - printf("\tfile_path: %ls\n", dp_str); + printf(" file_path: %ls\n", dp_str); efi_free_pool(dp_str); - printf("\tdata: %s\n", lo.optional_data); - + printf(" data:\n"); + print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1, + lo.optional_data, size + (u8 *)data - + (u8 *)lo.optional_data, true); free(label); } @@ -686,13 +693,24 @@ static void show_efi_boot_opt(int id) data)); } if (ret == EFI_SUCCESS) - show_efi_boot_opt_data(id, data); + show_efi_boot_opt_data(id, data, size); else if (ret == EFI_NOT_FOUND) printf("Boot%04X: not found\n", id); free(data); } +static int u16_tohex(u16 c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + + /* not hexadecimal */ + return -1; +} + /** * show_efi_boot_dump() - dump all UEFI load options * @@ -709,38 +727,58 @@ static void show_efi_boot_opt(int id) static int do_efi_boot_dump(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - char regex[256]; - char * const regexlist[] = {regex}; - char *variables = NULL, *boot, *value; - int len; - int id; + u16 *var_name16, *p; + efi_uintn_t buf_size, size; + efi_guid_t guid; + int id, i, digit; + efi_status_t ret; if (argc > 1) return CMD_RET_USAGE; - snprintf(regex, 256, "efi_.*-.*-.*-.*-.*_Boot[0-9A-F]+"); - - /* TODO: use GetNextVariableName? */ - len = hexport_r(&env_htab, '\n', H_MATCH_REGEX | H_MATCH_KEY, - &variables, 0, 1, regexlist); - - if (!len) - return CMD_RET_SUCCESS; - - if (len < 0) + buf_size = 128; + var_name16 = malloc(buf_size); + if (!var_name16) return CMD_RET_FAILURE; - boot = variables; - while (*boot) { - value = strstr(boot, "Boot") + 4; - id = (int)simple_strtoul(value, NULL, 16); - show_efi_boot_opt(id); - boot = strchr(boot, '\n'); - if (!*boot) + var_name16[0] = 0; + for (;;) { + size = buf_size; + ret = EFI_CALL(efi_get_next_variable_name(&size, var_name16, + &guid)); + if (ret == EFI_NOT_FOUND) break; - boot++; + if (ret == EFI_BUFFER_TOO_SMALL) { + buf_size = size; + p = realloc(var_name16, buf_size); + if (!p) { + free(var_name16); + return CMD_RET_FAILURE; + } + var_name16 = p; + ret = EFI_CALL(efi_get_next_variable_name(&size, + var_name16, + &guid)); + } + if (ret != EFI_SUCCESS) { + free(var_name16); + return CMD_RET_FAILURE; + } + + if (memcmp(var_name16, L"Boot", 8)) + continue; + + for (id = 0, i = 0; i < 4; i++) { + digit = u16_tohex(var_name16[4 + i]); + if (digit < 0) + break; + id = (id << 4) + digit; + } + if (i == 4 && !var_name16[8]) + show_efi_boot_opt(id); } - free(variables); + + free(var_name16); return CMD_RET_SUCCESS; } @@ -876,21 +876,21 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt, " Example usage:\n" " gpt write mmc 0 $partitions\n" " gpt verify mmc 0 $partitions\n" - " read <interface> <dev>\n" - " - read GPT into a data structure for manipulation\n" - " guid <interface> <dev>\n" + " gpt guid <interface> <dev>\n" " - print disk GUID\n" - " guid <interface> <dev> <varname>\n" + " gpt guid <interface> <dev> <varname>\n" " - set environment variable to disk GUID\n" " Example usage:\n" " gpt guid mmc 0\n" " gpt guid mmc 0 varname\n" #ifdef CONFIG_CMD_GPT_RENAME "gpt partition renaming commands:\n" - "gpt swap <interface> <dev> <name1> <name2>\n" + " gpt read <interface> <dev>\n" + " - read GPT into a data structure for manipulation\n" + " gpt swap <interface> <dev> <name1> <name2>\n" " - change all partitions named name1 to name2\n" " and vice-versa\n" - "gpt rename <interface> <dev> <part> <name>\n" + " gpt rename <interface> <dev> <part> <name>\n" " - rename the specified partition\n" " Example usage:\n" " gpt swap mmc 0 foo bar\n" diff --git a/cmd/nvedit_efi.c b/cmd/nvedit_efi.c index e65b38dbf3..2805e8182b 100644 --- a/cmd/nvedit_efi.c +++ b/cmd/nvedit_efi.c @@ -291,8 +291,11 @@ static int append_value(char **bufp, size_t *sizep, char *data) if (!tmp_buf) return -1; - if (hex2bin((u8 *)tmp_buf, data, len) < 0) + if (hex2bin((u8 *)tmp_buf, data, len) < 0) { + printf("Error: illegal hexadecimal string\n"); + free(tmp_buf); return -1; + } value = tmp_buf; } else { /* string */ diff --git a/cmd/rockusb.c b/cmd/rockusb.c index e0c1480d6d..9b70c6a6af 100644 --- a/cmd/rockusb.c +++ b/cmd/rockusb.c @@ -8,7 +8,7 @@ #include <console.h> #include <g_dnl.h> #include <usb.h> -#include <asm/arch/f_rockusb.h> +#include <asm/arch-rockchip/f_rockusb.h> static int do_rockusb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 105ff01d14..967ee82bca 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -31,7 +31,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),1 # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="am335x-evm" -CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2" +CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle" CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 5d901d13a3..a3de7a4ec4 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index c27916cbc9..d2548ff660 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -57,6 +57,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 23310c38c7..b52d321a69 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -63,6 +63,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index b69702b677..be9d55e7d4 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -34,6 +34,7 @@ CONFIG_SPL_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_SYS_I2C_TEGRA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK=y CONFIG_E1000=y CONFIG_PCI=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 234416e7f6..3292d644aa 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -58,6 +58,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 3a1a749f3f..9727d28c12 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-arndale" CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_I2C_COMPAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/avnet_ultra96_rev1_defconfig b/configs/avnet_ultra96_rev1_defconfig index fc4429ba20..b504332ff0 100644 --- a/configs/avnet_ultra96_rev1_defconfig +++ b/configs/avnet_ultra96_rev1_defconfig @@ -56,6 +56,7 @@ CONFIG_I2C_MUX_PCA954x=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_SPI_FLASH=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 59ea252f5b..bcc5a0aa4a 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -1,46 +1,74 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y +CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_TARGET_TAURUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068" CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="\0addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}::off\0addtest=setenv bootargs ${bootargs} loglevel=4 test\0baudrate=115200\0boot_file=setenv bootfile /${project_dir}/kernel/uImage\0boot_retries=0\0bootcmd=run flash_self\0bootdelay=3\0ethact=macb0\0flash_nfs=run nand_kernel;run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0flash_self=run nand_kernel;run setbootargs;upgrade_available;bootm ${kernel_ram};reset\0flash_self_test=run nand_kernel;run setbootargs addtest; upgrade_available;bootm ${kernel_ram};reset\0hostname=systemone\0kernel_Off=0x00200000\0kernel_Off_fallback=0x03800000\0kernel_ram=0x21500000\0kernel_size=0x00400000\0kernel_size_fallback=0x00400000\0loads_echo=1\0nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} ${kernel_size}\0net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};run nfsargs;run addip;upgrade_available;bootm ${kernel_ram};reset\0netdev=eth0\0nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs rw nfsroot=${serverip}:${rootpath} at91sam9_wdt.wdt_timeout=16\0partitionset_active=A\0preboot=echo;echo Type 'run flash_self' to use kernel and root filesystem on memory;echo Type 'run flash_nfs' to use kernel from memory and root filesystem over NFS;echo Type 'run net_nfs' to get Kernel over TFTP and mount root filesystem over NFS;echo\0project_dir=systemone\0root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0rootfs=/dev/mtdblock5\0rootfs_fallback=/dev/mtdblock7\0setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops root=${rootfs} rootfstype=jffs2 panic=7 at91sam9_wdt.wdt_timeout=16\0stderr=serial\0stdin=serial\0stdout=serial\0upgrade_available=0\0" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run flash_self" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_SOURCE is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_SPL_DM=y +CONFIG_BLK=y +CONFIG_HAVE_BLOCK_DEVICE=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y +CONFIG_WDT=y +CONFIG_WDT_AT91=y CONFIG_USE_TINY_PRINTF=y +CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index c613962cbd..73c78e23c6 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -50,6 +50,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" # CONFIG_ENV_IS_IN_MMC is not set CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 05b19b31c0..ee3fb149e4 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -45,6 +45,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig index fa9972b47f..dedc8b573a 100644 --- a/configs/cm_t54_defconfig +++ b/configs/cm_t54_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SCSI_AHCI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y CONFIG_CONS_INDEX=4 diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 449f4f9de2..ba17ec0030 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -57,6 +57,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 5e2a204a88..0617b120a0 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -45,6 +45,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 5c0695481b..e2f69eb64e 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -63,6 +63,7 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 8e2667101e..0d9eed3a3e 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -64,6 +64,7 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DFU_MMC=y CONFIG_DFU_SF=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_SPI_FLASH=y diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig index eed0b67a12..980f7b4abb 100644 --- a/configs/dms-ba16-1g_defconfig +++ b/configs/dms-ba16-1g_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig index d9f6d59874..bea75b5d23 100644 --- a/configs/dms-ba16_defconfig +++ b/configs/dms-ba16_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_DWC_AHSATA=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index ec6b5667e5..682e301822 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -65,6 +65,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 3f64669814..7b50d2cbc6 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -68,6 +68,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 47d4ad02b6..6d6bfbc493 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -70,6 +70,7 @@ CONFIG_PCF8575_GPIO=y CONFIG_DM_I2C=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 22fc84a41e..b99906a4d1 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -30,6 +30,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_CPU=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_PCI_COMPAT=y CONFIG_RTC_MC146818=y CONFIG_USB_DWC3_GADGET=y diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig index eba37939f9..3111451162 100644 --- a/configs/ge_bx50v3_defconfig +++ b/configs/ge_bx50v3_defconfig @@ -42,6 +42,7 @@ CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="1:5" CONFIG_SYS_BOOTCOUNT_ADDR=0x7000A000 CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index ff88c3e77c..f9857d13ca 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index b5251abab8..27ef264d82 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_MTD_DEVICE=y CONFIG_PHYLIB=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index e90b3db3ff..25af087820 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -64,6 +64,7 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_DM=y CONFIG_DWC_AHSATA=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 6e668c5a04..09f33755f9 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -32,6 +32,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 989dc445d0..6811a62bd1 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -29,6 +29,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 2fb2fdf7ff..59675e56b9 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -53,6 +53,7 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index 393046edc8..f6a18748a9 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -7,8 +7,11 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_SYS_MALLOC_F_LEN=0x0 -CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0x20068000 +CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -46,6 +49,7 @@ CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_PINCTRL=y CONFIG_DM_REGULATOR_FIXED=y # CONFIG_SPL_DM_SERIAL is not set +CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_DWC2=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 173ceedcc9..a439631e91 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -38,6 +38,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_DM_ETH=y diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 5c411fe1d1..ae8209831b 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -35,6 +35,7 @@ CONFIG_SYSCON=y CONFIG_CLK=y CONFIG_DM_MMC=y # CONFIG_MMC_QUIRKS is not set +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y CONFIG_PHY_FIXED=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index d232fbc76a..d3ed3c4543 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -73,6 +73,7 @@ CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=2 CONFIG_DM_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 88d363a27e..b2ca4f96cc 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 3d74967432..27a838787a 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -44,6 +44,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index 6bbacaa686..d125ccc1af 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 549ca2e964..fcead94f57 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -20,6 +20,7 @@ CONFIG_IMX_RGPIO2P=y # CONFIG_MXC_GPIO is not set CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7ULP=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index 4ec4e5871c..b8ebd56bf9 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -34,6 +34,7 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ADC=y CONFIG_ADC_EXYNOS=y CONFIG_DFU_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_SMC911X=y CONFIG_SMC911X_BASE=0x5000000 diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig index 9a7fccd93e..719ab8dde8 100644 --- a/configs/omap5_uevm_defconfig +++ b/configs/omap5_uevm_defconfig @@ -30,6 +30,7 @@ CONFIG_SCSI_AHCI=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_CMD_TCA642X=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OMAP_HS=y CONFIG_SCSI=y CONFIG_CONS_INDEX=3 diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 6a5e8cc853..409bea88eb 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -68,6 +68,7 @@ CONFIG_SYSCON=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_PWRSEQ=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig new file mode 100644 index 0000000000..cdccf221b5 --- /dev/null +++ b/configs/orangepi-rk3399_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x4000 +CONFIG_DEBUG_UART_BASE=0xFF1A0000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="rk3399-orangepi" +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_ERRNO_STR=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index cf55764ae5..c1904f102b 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -38,6 +38,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index cecb4ee619..da4155b286 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -37,6 +37,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index fdebb55ecb..5481fffa0c 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 33f2a0ad71..17043d5b22 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 0c587161dc..af8267777a 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -47,6 +47,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 41374a33bf..81eda9dc6f 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index d8d2661142..295c822aa9 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -45,6 +45,7 @@ CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 81d19df04c..0aa14878e2 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -53,6 +53,7 @@ CONFIG_FASTBOOT_BUF_SIZE=0x10000000 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=0 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index f9f98c9590..964464ac0f 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -69,6 +69,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index da08bb8918..6b0d7e5853 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -21,6 +21,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index a485ceb42c..1b61232d5c 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index 69b58f5860..1bdcc4797b 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5250-smdk5250" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 989cd6305a..7510f80c2e 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -28,6 +28,7 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-smdk5420" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=1 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index e87f5d5984..f474409516 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index b4a8d5e55c..bfc7495a73 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -43,6 +43,7 @@ CONFIG_I2C_ARB_GPIO_CHALLENGE=y CONFIG_CROS_EC_KEYB=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_DW=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_S5P=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index bd75df8eac..0ea9dff43d 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index f82b770bc8..3c2bb75564 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -45,6 +45,7 @@ CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_PHY=y CONFIG_PHY_STM32_USBPHYC=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 0da77d8c94..02a89592d7 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -1,36 +1,48 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_SYS_THUMB_BUILD=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_AT91=y CONFIG_SPL_LDSCRIPT="arch/$(ARCH)/cpu/u-boot-spl.lds" CONFIG_SYS_TEXT_BASE=0x21000000 CONFIG_TARGET_TAURUS=y +CONFIG_BOARD_TAURUS=y CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x1000 -CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xfffff200 +CONFIG_DEBUG_UART_CLOCK=18432000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067" CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs) root=/dev/mtdblock7 rw rootfstype=jffs2" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="nand read 0x22000000 0x200000 0x300000; bootm" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_TPL_BANNER_PRINT is not set +CONFIG_SPL_CRC32_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_SPI_LOAD=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_SYS_XTRACE="n" # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set CONFIG_CMD_DFU=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_NAND=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -41,19 +53,30 @@ CONFIG_CMD_PING=y CONFIG_CMD_MTDPARTS=y # CONFIG_DOS_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_OF_EMBED=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" +CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y +CONFIG_SPL_DM=y +CONFIG_BLK=y CONFIG_CLK=y CONFIG_CLK_AT91=y CONFIG_DFU_NAND=y # CONFIG_MMC is not set CONFIG_NAND=y CONFIG_NAND_ATMEL=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_ATMEL_USART=y CONFIG_USB=y +CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Siemens AG" @@ -63,3 +86,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WDT=y CONFIG_WDT_AT91=y CONFIG_USE_TINY_PRINTF=y +CONFIG_HEXDUMP=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 999425e460..e04156311f 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SPL_SYS_THUMB_BUILD=y CONFIG_ARCH_MVEBU=y CONFIG_SYS_TEXT_BASE=0x00800000 +CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 @@ -14,7 +15,10 @@ CONFIG_DEBUG_UART_CLOCK=250000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_MISC_INIT_R=y @@ -23,16 +27,22 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0x40000030 CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_LZMADEC=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_AES=y +CONFIG_CMD_HASH=y CONFIG_CMD_BTRFS=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia" @@ -40,8 +50,11 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y -CONFIG_ATSHA204A=y +CONFIG_AHCI_PCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_GPIO=y +# CONFIG_MVEBU_GPIO is not set +CONFIG_DM_PCA953X=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y @@ -53,11 +66,13 @@ CONFIG_MVNETA=y CONFIG_MII=y CONFIG_PCI=y CONFIG_PCI_MVEBU=y +CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y CONFIG_WDT=y CONFIG_WDT_ORION=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 25303e6789..2cc30e0fd2 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -40,6 +40,7 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index 296424ec6e..61007a6770 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -39,6 +39,7 @@ CONFIG_GPIO_UNIPHIER=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_UNIPHIER=y CONFIG_FLASH_CFI_DRIVER=y CONFIG_SYS_FLASH_CFI=y diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index b0c673c98e..83f78776b7 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -34,6 +34,7 @@ CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_UNIPHIER=y CONFIG_MMC_SDHCI=y diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index 5d929437bf..745aa85f3b 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="at91-vinco" CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=50000000 diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 5347ac8fe8..073ff48329 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 300dc3805a..a79f670ea0 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -29,6 +29,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 1b5356c02e..5b351133a8 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -38,6 +38,7 @@ CONFIG_DFU_MMC=y CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y diff --git a/configs/warp_defconfig b/configs/warp_defconfig index df43a79869..a37d769296 100644 --- a/configs/warp_defconfig +++ b/configs/warp_defconfig @@ -29,6 +29,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y # CONFIG_NET is not set CONFIG_DFU_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/xilinx_zynqmp_mini_emmc0_defconfig b/configs/xilinx_zynqmp_mini_emmc0_defconfig index 91d7c6993f..c8d6886493 100644 --- a/configs/xilinx_zynqmp_mini_emmc0_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc0_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_mini_emmc1_defconfig b/configs/xilinx_zynqmp_mini_emmc1_defconfig index 4515b2047d..29e472842a 100644 --- a/configs/xilinx_zynqmp_mini_emmc1_defconfig +++ b/configs/xilinx_zynqmp_mini_emmc1_defconfig @@ -53,6 +53,7 @@ CONFIG_SPL_DM=y # CONFIG_DM_WARN is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y # CONFIG_EFI_LOADER is not set diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index a57c71eeac..7b1f5e9d0a 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -58,6 +58,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y diff --git a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig index f0706f31ef..559a61e8d0 100644 --- a/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm017_dc3_defconfig @@ -50,6 +50,7 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_CADENCE=y CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ZYNQ=y CONFIG_MTD_DEVICE=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index 2cbeeb3900..709a7ef908 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -25,6 +25,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index fb2bf0a64a..e79a038816 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_MII=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 9ba661cebe..ae3a6b32bf 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index ba07f615bb..65a19151a8 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -33,6 +33,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 diff --git a/disk/part_efi.c b/disk/part_efi.c index 239455b816..c0fa753339 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -209,6 +209,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid) guid_bin = gpt_head->disk_guid.b; uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID); + /* Remember to free pte */ + free(gpt_pte); return 0; } @@ -696,6 +698,10 @@ int gpt_verify_headers(struct blk_desc *dev_desc, gpt_header *gpt_head, __func__); return -1; } + + /* Free pte before allocating again */ + free(*gpt_pte); + if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, gpt_pte) != 1) { printf("%s: *** ERROR: Invalid Backup GPT ***\n", diff --git a/doc/README.davinci b/doc/README.davinci index aa7c85011a..6522c24eea 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -1,108 +1,47 @@ Summary ======= -This README is about U-Boot support for TI's ARM 926EJS based family of SoCs. -These SOCs are used for cameras, video security and surveillance, DVR's, etc. -DaVinci SOC's comprise of DM644x, DM646x, DM35x and DM36x series of SOC's -Additionally there are some SOCs meant for the audio market which though have -an OMAP part number are very similar to the DaVinci series of SOC's -Additionally, some family members contain a TI DSP and/or graphics -co processors along with a host of other peripherals. +Note: this document used to be about the entire family of DaVinci SOCs but the +support for the DM* family and DA830 has since been dropped. -Currently the following boards are supported: - -* TI DaVinci DM644x EVM - -* TI DaVinci DM646x EVM - -* TI DaVinci DM355 EVM - -* TI DaVinci DM365 EVM +This README is about U-Boot support for TI's DA850 SoC. This SOC has an OMAP +part number but is very similar to the DaVinci series. -* TI DA830 EVM +Currently the following boards are supported: * TI DA850 EVM -* DM355 based Leopard board - -* DM644x based schmoogie board - -* DM644x based sffsdr board +* TI OMAP-L138 LCDK -* DM644x based sonata board +* Lego EV3 Build ===== -* TI DaVinci DM644x EVM: - -make davinci_dvevm_config -make - -* TI DaVinci DM646x EVM: - -make davinci_dm6467evm_config -make - -* TI DaVinci DM355 EVM: - -make davinci_dm355evm_config -make - -* TI DaVinci DM365 EVM: - -make davinci_dm365evm_config -make - -* TI DA830 EVM: - -make da830evm_config -make - * TI DA850 EVM: make da850evm_config make -* DM355 based Leopard board: - -make davinci_dm355leopard_config -make - -* DM644x based schmoogie board: +* TI OMAP-L138 LCDK -make davinci_schmoogie_config +make omapl138_lcdk_defconfig make -* DM644x based sffsdr board: +* Lego EV3 -make davinci_sffsdr_config -make - -* DM644x based sonata board: - -make davinci_sonata_config +make legoev3_defconfig make Bootloaders =============== -The DaVinci SOC's use 2 bootloaders. The low level initialization -is done by a UBL(user boot loader). The UBL is written to a NAND/NOR/SPI flash -by a programmer. During initial bootup, the ROM Bootloader reads the UBL -from a storage device and loads it into the IRAM. The UBL then loads the U-Boot -into the RAM. -The programmers and UBL are always released as part of any standard TI -software release associated with an SOC. - -Alternative boot method (DA850 EVM only): -For the DA850 EVM an SPL (secondary program loader, see doc/README.SPL) -is provided to load U-Boot directly from SPI flash. In this case, the -SPL does the low level initialization that is otherwise done by the SPL. -To build U-Boot with this SPL, do -make da850evm_config -make u-boot.ais -and program the resulting u-boot.ais file to the SPI flash of the DA850 EVM. +For DA850 an SPL (secondary program loader, see doc/README.SPL) is provided +to load U-Boot directly from SPI flash. The SPL takes care of the low level +initialization. + +The SPL is built as u-boot.ais for all DA850 defconfigs. The resulting +image file can be programmed to the SPI flash of the DA850 EVM/LCDK. Environment Variables ===================== @@ -121,34 +60,14 @@ is used to obtain this information. Links ===== -1) TI DaVinci DM355 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm355.html -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=203&osCsid=c499af6087317f11b3da19b4e8f1af32 - -2) TI DaVinci DM365 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm365.html?247SEM= -http://support.spectrumdigital.com/boards/evmdm365/revc/ - -3) DaVinci DM355 based leopard board -http://designsomething.org/leopardboard/default.aspx -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=192&osCsid=67c20335668ffc57cb35727106eb24b1 - -4) TI DaVinci DM6467 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm6467.html -http://support.spectrumdigital.com/boards/evmdm6467/revf/ - -5) TI DaVinci DM6446 EVM: -http://focus.ti.com/docs/prod/folders/print/tms320dm6446.html -http://www.spectrumdigital.com/product_info.php?cPath=103&products_id=222 - -6) TI DA830 EVM -http://focus.ti.com/apps/docs/gencontent.tsp?appId=1&contentId=52385 -http://www.spectrumdigital.com/product_info.php?cPath=37&products_id=214 - -7) TI DA850 EVM +1) TI DA850 EVM http://focus.ti.com/docs/prod/folders/print/omap-l138.html http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit +2) TI OMAP-L138 LCDK +http://focus.ti.com/docs/prod/folders/print/omap-l138.html +http://www.ti.com/tool/TMDXLCDK138 + Davinci special defines ======================= diff --git a/doc/git-mailrc b/doc/git-mailrc index 13137017fe..a63b76befc 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -22,10 +22,12 @@ alias bmeng Bin Meng <bmeng.cn@gmail.com> alias danielschwierzeck Daniel Schwierzeck <daniel.schwierzeck@gmail.com> alias dinh Dinh Nguyen <dinguyen@kernel.org> alias hs Heiko Schocher <hs@denx.de> +alias freenix Peng Fan <peng.fan@nxp.com> alias iwamatsu Nobuhiro Iwamatsu <iwamatsu@nigauri.org> alias jaehoon Jaehoon Chung <jh80.chung@samsung.com> alias jagan Jagan Teki <jagan@amarulasolutions.com> alias jhersh Joe Hershberger <joe.hershberger@ni.com> +alias kevery Kever Yang <kever.yang@rock-chips.com> alias lukma Lukasz Majewski <lukma@denx.de> alias macpaul Macpaul Lin <macpaul@andestech.com> alias marex Marek Vasut <marex@denx.de> @@ -70,7 +72,7 @@ alias tegra2 tegra alias ti uboot, trini alias uniphier uboot, masahiro alias zynq uboot, monstr -alias rockchip uboot, sjg, Kever Yang <kever.yang@rock-chips.com>, ptomsich +alias rockchip uboot, sjg, kevery, ptomsich alias m68k uboot, alisonwang, angelo_ts alias coldfire m68k @@ -110,7 +112,7 @@ alias kerneldoc uboot, marex alias fdt uboot, sjg alias i2c uboot, hs alias kconfig uboot, masahiro -alias mmc uboot, jaehoon +alias mmc uboot, freenix alias nand uboot alias net uboot, jhersh alias phy uboot, jhersh diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 9c4e8901e8..9bf9cedaf8 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3036.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3036-cru.h> #include <linux/log2.h> diff --git a/drivers/clk/rockchip/clk_rk3128.c b/drivers/clk/rockchip/clk_rk3128.c index 7da785abc6..efda8c830b 100644 --- a/drivers/clk/rockchip/clk_rk3128.c +++ b/drivers/clk/rockchip/clk_rk3128.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3128.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3128.h> +#include <asm/arch-rockchip/hardware.h> #include <bitfield.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3128-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index db7479a237..9bb9959c9d 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -12,10 +12,10 @@ #include <mapmem.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/hardware.h> #include <dt-bindings/clock/rk3188-cru.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 46a569c9ec..48ed14b2af 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -9,9 +9,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3228-cru.h> #include <linux/log2.h> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 930c99f4d9..375d7f8acb 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -13,10 +13,10 @@ #include <mapmem.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> #include <dt-bindings/clock/rk3288-cru.h> #include <dm/device-internal.h> #include <dm/lists.h> diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 106621fe7c..a89e2ecc4a 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -9,10 +9,10 @@ #include <dm.h> #include <errno.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3328.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3328.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3328-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 9492cc2a36..89cbae59c5 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -13,9 +13,9 @@ #include <mapmem.h> #include <syscon.h> #include <bitfield.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/io.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3368-cru.h> diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index cab2bd9943..93a652e5ff 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <bitfield.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3399-cru.h> diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 914e2f4b21..3ebb007fab 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -11,9 +11,9 @@ #include <errno.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rv1108.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1108.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rv1108-cru.h> diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index f78a01aa8f..a5fc7809bc 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -575,14 +575,6 @@ static int udma_get_tchan(struct udma_chan *uc) pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: tchan%d is running!\n", uc->id, - uc->tchan->id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -602,14 +594,6 @@ static int udma_get_rchan(struct udma_chan *uc) pr_debug("chan%d: got rchan%d\n", uc->id, uc->rchan->id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: rchan%d is running!\n", uc->id, - uc->rchan->id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -652,14 +636,6 @@ static int udma_get_chan_pair(struct udma_chan *uc) pr_debug("chan%d: got t/rchan%d pair\n", uc->id, chan_id); - if (udma_is_chan_running(uc)) { - dev_warn(ud->dev, "chan%d: t/rchan%d pair is running!\n", - uc->id, chan_id); - udma_stop(uc); - if (udma_is_chan_running(uc)) - dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); - } - return 0; } @@ -1071,6 +1047,15 @@ static int udma_alloc_chan_resources(struct udma_chan *uc) } } + if (udma_is_chan_running(uc)) { + dev_warn(ud->dev, "chan%d: is running!\n", uc->id); + udma_stop(uc); + if (udma_is_chan_running(uc)) { + dev_err(ud->dev, "chan%d: won't stop!\n", uc->id); + goto err_free_res; + } + } + /* PSI-L pairing */ ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread); if (ret) { @@ -1492,7 +1477,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata) u32 tc_ring_id; int ret; - if (!metadata) + if (metadata) packet_data = *((struct ti_udma_drv_packet_data *)metadata); if (dma->id >= (ud->rchan_cnt + ud->tchan_cnt)) { diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 1196ce0712..303aa6a631 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -158,7 +158,7 @@ static inline int ti_sci_get_response(struct ti_sci_info *info, int ret; /* Receive the response */ - ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms); + ret = mbox_recv(chan, msg, info->desc->max_rx_timeout_ms * 1000); if (ret) { dev_err(info->dev, "%s: Message receive failed. ret = %d\n", __func__, ret); @@ -257,7 +257,8 @@ static int ti_sci_cmd_get_revision(struct ti_sci_handle *handle) info = handle_to_ti_sci_info(handle); - xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION, 0x0, + xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_VERSION, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&hdr, sizeof(struct ti_sci_msg_hdr), sizeof(*rev_info)); if (IS_ERR(xfer)) { @@ -499,8 +500,8 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle, info = handle_to_ti_sci_info(handle); - /* Response is expected, so need of any flags */ - xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, 0, + xfer = ti_sci_setup_one_xfer(info, TI_SCI_MSG_GET_DEVICE_STATE, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&req, sizeof(req), sizeof(*resp)); if (IS_ERR(xfer)) { ret = PTR_ERR(xfer); @@ -2574,8 +2575,8 @@ static int ti_sci_cmd_change_fwl_owner(const struct ti_sci_handle *handle, info = handle_to_ti_sci_info(handle); - xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_GET, - TISCI_MSG_FWL_CHANGE_OWNER, + xfer = ti_sci_setup_one_xfer(info, TISCI_MSG_FWL_CHANGE_OWNER, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, (u32 *)&req, sizeof(req), sizeof(*resp)); if (IS_ERR(xfer)) { ret = PTR_ERR(xfer); diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c index 21df227717..3d96678a45 100644 --- a/drivers/gpio/rk_gpio.c +++ b/drivers/gpio/rk_gpio.c @@ -12,7 +12,8 @@ #include <linux/errno.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/gpio.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 74ac0a4aa7..0a2dafcec6 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -271,6 +271,17 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, do { control = readl(&twsi->control); if (control & MVTWSI_CONTROL_IFLG) { + /* + * On Armada 38x it seems that the controller works as + * if it first set the MVTWSI_CONTROL_IFLAG in the + * control register and only after that it changed the + * status register. + * This sometimes caused weird bugs which only appeared + * on selected I2C speeds and even then only sometimes. + * We therefore add here a simple ndealy(100), which + * seems to fix this weird bug. + */ + ndelay(100); status = readl(&twsi->status); if (status == expected_status) return 0; diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index f9a5796b96..cdd94bb05a 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -12,9 +12,9 @@ #include <errno.h> #include <i2c.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/i2c.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/i2c.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> #include <linux/sizes.h> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c34dd5d187..c23299ea96 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -78,6 +78,12 @@ config SUPPORT_EMMC_RPMB Enable support for reading, writing and programming the key for the Replay Protection Memory Block partition in eMMC. +config SUPPORT_EMMC_BOOT + bool "Support some additional features of the eMMC boot partitions" + help + Enable support for eMMC boot partitions. This also enables + extensions within the mmc command. + config MMC_IO_VOLTAGE bool "Support IO voltage configuration" help @@ -385,6 +391,20 @@ config MMC_SDHCI_SDMA This enables support for the SDMA (Single Operation DMA) defined in the SD Host Controller Standard Specification Version 1.00 . +config MMC_SDHCI_ADMA + bool "Support SDHCI ADMA2" + depends on MMC_SDHCI + help + This enables support for the ADMA (Advanced DMA) defined + in the SD Host Controller Standard Specification Version 3.00 + +config SPL_MMC_SDHCI_ADMA + bool "Support SDHCI ADMA2 in SPL" + depends on MMC_SDHCI + help + This enables support for the ADMA (Advanced DMA) defined + in the SD Host Controller Standard Specification Version 3.00 in SPL. + config MMC_SDHCI_ATMEL bool "Atmel SDHCI controller support" depends on ARCH_AT91 diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 93a836eac3..1992d61182 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -74,15 +74,15 @@ static void dwmci_prepare_data(struct dwmci_host *host, dwmci_set_idma_desc(cur_idmac, flags, cnt, (ulong)bounce_buffer + (i * PAGE_SIZE)); + cur_idmac++; if (blk_cnt <= 8) break; blk_cnt -= 8; - cur_idmac++; i++; } while(1); data_end = (ulong)cur_idmac; - flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN); + flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN)); ctrl = dwmci_readl(host, DWMCI_CTRL); ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN; @@ -114,22 +114,40 @@ static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len) return 0; } +static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size) +{ + unsigned int timeout; + + timeout = size * 8 * 1000; /* counting in bits and msec */ + timeout *= 2; /* wait twice as long */ + timeout /= mmc->clock; + timeout /= mmc->bus_width; + timeout /= mmc->ddr_mode ? 2 : 1; + timeout = (timeout < 1000) ? 1000 : timeout; + + return timeout; +} + static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) { + struct mmc *mmc = host->mmc; int ret = 0; - u32 timeout = 240000; - u32 mask, size, i, len = 0; + u32 timeout, mask, size, i, len = 0; u32 *buf = NULL; ulong start = get_timer(0); u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1) * 2; - size = data->blocksize * data->blocks / 4; + size = data->blocksize * data->blocks; if (data->flags == MMC_DATA_READ) buf = (unsigned int *)data->dest; else buf = (unsigned int *)data->src; + timeout = dwmci_get_timeout(mmc, size); + + size /= 4; + for (;;) { mask = dwmci_readl(host, DWMCI_RINTSTS); /* Error during data transfer. */ @@ -252,14 +270,20 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET); } else { if (data->flags == MMC_DATA_READ) { - bounce_buffer_start(&bbstate, (void*)data->dest, + ret = bounce_buffer_start(&bbstate, + (void*)data->dest, data->blocksize * data->blocks, GEN_BB_WRITE); } else { - bounce_buffer_start(&bbstate, (void*)data->src, + ret = bounce_buffer_start(&bbstate, + (void*)data->src, data->blocksize * data->blocks, GEN_BB_READ); } + + if (ret) + return ret; + dwmci_prepare_data(host, data, cur_idmac, bbstate.bounce_buffer); } diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 9e34557d16..1b7de74a72 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -297,6 +297,13 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); return -ETIMEDOUT; } + } else { +#ifdef CONFIG_DM_GPIO + if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) { + printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); + return -ETIMEDOUT; + } +#endif } esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, @@ -614,18 +621,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) #else int pre_div = 2; #endif - int ddr_pre_div = mmc->ddr_mode ? 2 : 1; int sdhc_clk = priv->sdhc_clk; uint clk; + /* + * For ddr mode, usdhc need to enable DDR mode first, after select + * this DDR mode, usdhc will automatically divide the usdhc clock + */ + if (mmc->ddr_mode) { + writel(readl(®s->mixctrl) | MIX_CTRL_DDREN, ®s->mixctrl); + sdhc_clk >>= 1; + } + if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; - while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) - pre_div *= 2; + if (sdhc_clk / 16 > clock) { + for (; pre_div < 256; pre_div *= 2) + if ((sdhc_clk / pre_div) <= (clock * 16)) + break; + } else + pre_div = 1; - while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16) - div++; + for (div = 1; div <= 16; div++) + if ((sdhc_clk / (div * pre_div)) <= clock) + break; pre_div >>= 1; div -= 1; @@ -1489,14 +1509,15 @@ static int fsl_esdhc_probe(struct udevice *dev) #endif } - priv->wp_enable = 1; - + if (dev_read_prop(dev, "fsl,wp-controller", NULL)) { + priv->wp_enable = 1; + } else { + priv->wp_enable = 0; #ifdef CONFIG_DM_GPIO - ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, + gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN); - if (ret) - priv->wp_enable = 0; #endif + } priv->vs18_enable = 0; diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index bf2d83a52c..b2a1201631 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -13,8 +13,8 @@ #include <pwrseq.h> #include <syscon.h> #include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> #include <linux/err.h> struct rockchip_mmc_plat { diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index cdeba914f9..e2bb90abbd 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -67,17 +67,123 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data) } } -static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, - unsigned int start_addr) +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) +static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len, + bool end) +{ + struct sdhci_adma_desc *desc; + u8 attr; + + desc = &host->adma_desc_table[host->desc_slot]; + + attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA; + if (!end) + host->desc_slot++; + else + attr |= ADMA_DESC_ATTR_END; + + desc->attr = attr; + desc->len = len; + desc->reserved = 0; + desc->addr_lo = (dma_addr_t)buf; +#ifdef CONFIG_DMA_ADDR_T_64BIT + desc->addr_hi = (u64)buf >> 32; +#endif +} + +static void sdhci_prepare_adma_table(struct sdhci_host *host, + struct mmc_data *data) +{ + uint trans_bytes = data->blocksize * data->blocks; + uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN); + int i = desc_count; + char *buf; + + host->desc_slot = 0; + + if (data->flags & MMC_DATA_READ) + buf = data->dest; + else + buf = (char *)data->src; + + while (--i) { + sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false); + buf += ADMA_MAX_LEN; + trans_bytes -= ADMA_MAX_LEN; + } + + sdhci_adma_desc(host, buf, trans_bytes, true); + + flush_cache((dma_addr_t)host->adma_desc_table, + ROUND(desc_count * sizeof(struct sdhci_adma_desc), + ARCH_DMA_MINALIGN)); +} +#elif defined(CONFIG_MMC_SDHCI_SDMA) +static void sdhci_prepare_adma_table(struct sdhci_host *host, + struct mmc_data *data) +{} +#endif +#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)) +static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, + int *is_aligned, int trans_bytes) { - unsigned int stat, rdy, mask, timeout, block = 0; - bool transfer_done = false; -#ifdef CONFIG_MMC_SDHCI_SDMA unsigned char ctrl; + + if (data->flags == MMC_DATA_READ) + host->start_addr = (dma_addr_t)data->dest; + else + host->start_addr = (dma_addr_t)data->src; + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ctrl &= ~SDHCI_CTRL_DMA_MASK; + if (host->flags & USE_ADMA64) + ctrl |= SDHCI_CTRL_ADMA64; + else if (host->flags & USE_ADMA) + ctrl |= SDHCI_CTRL_ADMA32; sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + + if (host->flags & USE_SDMA) { + if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && + (host->start_addr & 0x7) != 0x0) { + *is_aligned = 0; + host->start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); + } + +#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) + /* + * Always use this bounce-buffer when + * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined + */ + *is_aligned = 0; + host->start_addr = (unsigned long)aligned_buffer; + if (data->flags != MMC_DATA_READ) + memcpy(aligned_buffer, data->src, trans_bytes); +#endif + sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS); + + } else if (host->flags & (USE_ADMA | USE_ADMA64)) { + sdhci_prepare_adma_table(host, data); + + sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS); + if (host->flags & USE_ADMA64) + sdhci_writel(host, (u64)host->adma_addr >> 32, + SDHCI_ADMA_ADDRESS_HI); + } + + flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN)); +} +#else +static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data, + int *is_aligned, int trans_bytes) +{} #endif +static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data) +{ + dma_addr_t start_addr = host->start_addr; + unsigned int stat, rdy, mask, timeout, block = 0; + bool transfer_done = false; timeout = 1000000; rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL; @@ -104,14 +210,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, continue; } } -#ifdef CONFIG_MMC_SDHCI_SDMA - if (!transfer_done && (stat & SDHCI_INT_DMA_END)) { + if ((host->flags & USE_DMA) && !transfer_done && + (stat & SDHCI_INT_DMA_END)) { sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS); - start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); - start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; - sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); + if (host->flags & USE_SDMA) { + start_addr &= + ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1); + start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE; + sdhci_writel(host, start_addr, + SDHCI_DMA_ADDRESS); + } } -#endif if (timeout-- > 0) udelay(10); else { @@ -149,10 +258,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, int ret = 0; int trans_bytes = 0, is_aligned = 1; u32 mask, flags, mode; - unsigned int time = 0, start_addr = 0; + unsigned int time = 0; int mmc_dev = mmc_get_blk_desc(mmc)->devnum; ulong start = get_timer(0); + host->start_addr = 0; /* Timeout unit - ms */ static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT; @@ -218,33 +328,11 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, if (data->flags == MMC_DATA_READ) mode |= SDHCI_TRNS_READ; -#ifdef CONFIG_MMC_SDHCI_SDMA - if (data->flags == MMC_DATA_READ) - start_addr = (unsigned long)data->dest; - else - start_addr = (unsigned long)data->src; - if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && - (start_addr & 0x7) != 0x0) { - is_aligned = 0; - start_addr = (unsigned long)aligned_buffer; - if (data->flags != MMC_DATA_READ) - memcpy(aligned_buffer, data->src, trans_bytes); + if (host->flags & USE_DMA) { + mode |= SDHCI_TRNS_DMA; + sdhci_prepare_dma(host, data, &is_aligned, trans_bytes); } -#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER) - /* - * Always use this bounce-buffer when - * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined - */ - is_aligned = 0; - start_addr = (unsigned long)aligned_buffer; - if (data->flags != MMC_DATA_READ) - memcpy(aligned_buffer, data->src, trans_bytes); -#endif - - sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS); - mode |= SDHCI_TRNS_DMA; -#endif sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, data->blocksize), SDHCI_BLOCK_SIZE); @@ -255,12 +343,6 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, } sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); -#ifdef CONFIG_MMC_SDHCI_SDMA - if (data) { - trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); - flush_cache(start_addr, trans_bytes); - } -#endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); start = get_timer(0); do { @@ -286,7 +368,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, ret = -1; if (!ret && data) - ret = sdhci_transfer_data(host, data, start_addr); + ret = sdhci_transfer_data(host, data); if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD) udelay(1000); @@ -570,6 +652,24 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, __func__); return -EINVAL; } + + host->flags |= USE_SDMA; +#endif +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) + if (!(caps & SDHCI_CAN_DO_ADMA2)) { + printf("%s: Your controller doesn't support SDMA!!\n", + __func__); + return -EINVAL; + } + host->adma_desc_table = (struct sdhci_adma_desc *) + memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ); + + host->adma_addr = (dma_addr_t)host->adma_desc_table; +#ifdef CONFIG_DMA_ADDR_T_64BIT + host->flags |= USE_ADMA64; +#else + host->flags |= USE_ADMA; +#endif #endif if (host->quirks & SDHCI_QUIRK_REG32_RW) host->version = diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index e6a84a52b4..cfa9b535c8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -730,43 +730,6 @@ static int nand_davinci_dev_ready(struct mtd_info *mtd) return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1; } -static void nand_flash_init(void) -{ - /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS! - * Instead, have your board_init() set EMIF timings, based on its - * knowledge of the clocks and what devices are hooked up ... and - * don't even do that unless no UBL handled it. - */ -#ifdef CONFIG_SOC_DM644X - u_int32_t acfg1 = 0x3ffffffc; - - /*------------------------------------------------------------------* - * NAND FLASH CHIP TIMEOUT @ 459 MHz * - * * - * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * - * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * - * * - *------------------------------------------------------------------*/ - acfg1 = 0 - | (0 << 31) /* selectStrobe */ - | (0 << 30) /* extWait */ - | (1 << 26) /* writeSetup 10 ns */ - | (3 << 20) /* writeStrobe 40 ns */ - | (1 << 17) /* writeHold 10 ns */ - | (1 << 13) /* readSetup 10 ns */ - | (5 << 7) /* readStrobe 60 ns */ - | (1 << 4) /* readHold 10 ns */ - | (3 << 2) /* turnAround ?? ns */ - | (0 << 0) /* asyncSize 8-bit bus */ - ; - - __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */ - - /* NAND flash on CS2 */ - __raw_writel(0x00000101, &davinci_emif_regs->nandfcr); -#endif -} - void davinci_nand_init(struct nand_chip *nand) { #if defined CONFIG_KEYSTONE_RBL_NAND @@ -820,8 +783,6 @@ void davinci_nand_init(struct nand_chip *nand) nand->write_buf = nand_davinci_write_buf; nand->dev_ready = nand_davinci_dev_ready; - - nand_flash_init(); } int board_nand_init(struct nand_chip *chip) __attribute__((weak)); diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c01ae758c7..26a6121175 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -11,15 +11,15 @@ #include <phy.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/periph.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/grf_rv1108.h> +#include <asm/arch-rockchip/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/grf_rv1108.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index bb879d8d4f..9d53984973 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -816,55 +816,12 @@ int davinci_emac_initialize(void) phy_id |= tmp & 0x0000ffff; - switch (phy_id) { -#ifdef PHY_KSZ8873 - case PHY_KSZ8873: - sprintf(phy[i].name, "KSZ8873 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = ksz8873_init_phy; - phy[i].is_phy_connected = ksz8873_is_phy_connected; - phy[i].get_link_speed = ksz8873_get_link_speed; - phy[i].auto_negotiate = ksz8873_auto_negotiate; - break; -#endif -#ifdef PHY_LXT972 - case PHY_LXT972: - sprintf(phy[i].name, "LXT972 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = lxt972_init_phy; - phy[i].is_phy_connected = lxt972_is_phy_connected; - phy[i].get_link_speed = lxt972_get_link_speed; - phy[i].auto_negotiate = lxt972_auto_negotiate; - break; -#endif -#ifdef PHY_DP83848 - case PHY_DP83848: - sprintf(phy[i].name, "DP83848 @ 0x%02x", - active_phy_addr[i]); - phy[i].init = dp83848_init_phy; - phy[i].is_phy_connected = dp83848_is_phy_connected; - phy[i].get_link_speed = dp83848_get_link_speed; - phy[i].auto_negotiate = dp83848_auto_negotiate; - break; -#endif -#ifdef PHY_ET1011C - case PHY_ET1011C: - sprintf(phy[i].name, "ET1011C @ 0x%02x", - active_phy_addr[i]); - phy[i].init = gen_init_phy; - phy[i].is_phy_connected = gen_is_phy_connected; - phy[i].get_link_speed = et1011c_get_link_speed; - phy[i].auto_negotiate = gen_auto_negotiate; - break; -#endif - default: - sprintf(phy[i].name, "GENERIC @ 0x%02x", - active_phy_addr[i]); - phy[i].init = gen_init_phy; - phy[i].is_phy_connected = gen_is_phy_connected; - phy[i].get_link_speed = gen_get_link_speed; - phy[i].auto_negotiate = gen_auto_negotiate; - } + sprintf(phy[i].name, "GENERIC @ 0x%02x", + active_phy_addr[i]); + phy[i].init = gen_init_phy; + phy[i].is_phy_connected = gen_is_phy_connected; + phy[i].get_link_speed = gen_get_link_speed; + phy[i].auto_negotiate = gen_auto_negotiate; debug("Ethernet PHY: %s\n", phy[i].name); diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index 0e6c559d5e..f01bc77a57 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -116,6 +116,9 @@ static int pinconfig_post_bind(struct udevice *dev) ofnode node; int ret; + if (!dev_of_valid(dev)) + return 0; + dev_for_each_subnode(node, dev) { if (pre_reloc_only && !ofnode_pre_reloc(node)) diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 9994cbafbf..88db294cf1 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -12,7 +12,7 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/pwm.h> +#include <asm/arch-rockchip/pwm.h> #include <power/regulator.h> struct rk_pwm_priv { diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index 8d1b9faacc..92f584fadc 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -12,12 +12,12 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3368.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/ddr_rk3368.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3368.h> +#include <asm/arch-rockchip/grf_rk3368.h> +#include <asm/arch-rockchip/ddr_rk3368.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3128.c b/drivers/ram/rockchip/sdram_rk3128.c index df7b988703..bfabc22a7d 100644 --- a/drivers/ram/rockchip/sdram_rk3128.c +++ b/drivers/ram/rockchip/sdram_rk3128.c @@ -7,9 +7,9 @@ #include <dm.h> #include <ram.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3128.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3128.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index fdd500aa47..00e52ec949 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -15,13 +15,13 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/ddr_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/pmu_rk3188.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3188.h> +#include <asm/arch-rockchip/ddr_rk3188.h> +#include <asm/arch-rockchip/grf_rk3188.h> +#include <asm/arch-rockchip/pmu_rk3188.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> #include <linux/err.h> struct chan_info { diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 53835a9cd0..c596523d4f 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -11,14 +11,14 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk322x.h> -#include <asm/arch/grf_rk322x.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sdram_rk322x.h> -#include <asm/arch/timer.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk322x.h> +#include <asm/arch-rockchip/grf_rk322x.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/sdram_rk322x.h> +#include <asm/arch-rockchip/timer.h> +#include <asm/arch-rockchip/uart.h> +#include <asm/arch-rockchip/sdram_common.h> #include <asm/types.h> #include <linux/err.h> diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index d1e52d84e7..6bb025a851 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -15,13 +15,13 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/ddr_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/ddr_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/pmu_rk3288.h> +#include <asm/arch-rockchip/sdram.h> +#include <asm/arch-rockchip/sdram_common.h> #include <linux/err.h> #include <power/regulator.h> #include <power/rk8xx_pmic.h> diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index e8b234d866..f4e0b18447 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -7,9 +7,9 @@ #include <dm.h> #include <ram.h> #include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/sdram_common.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/sdram_common.h> struct dram_info { struct ram_info info; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 94dd01156a..05ec5fc28d 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -13,12 +13,12 @@ #include <regmap.h> #include <syscon.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/sdram_common.h> -#include <asm/arch/sdram_rk3399.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/sdram_common.h> +#include <asm/arch-rockchip/sdram_rk3399.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/err.h> #include <time.h> diff --git a/drivers/reset/reset-rockchip.c b/drivers/reset/reset-rockchip.c index af07134049..3871fc00d0 100644 --- a/drivers/reset/reset-rockchip.c +++ b/drivers/reset/reset-rockchip.c @@ -7,7 +7,7 @@ #include <dm.h> #include <reset-uclass.h> #include <linux/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <dm/lists.h> /* * Each reg has 16 bits reset signal for devices diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c index 35fefd74c6..b1718f72d1 100644 --- a/drivers/serial/serial_rockchip.c +++ b/drivers/serial/serial_rockchip.c @@ -9,7 +9,7 @@ #include <dt-structs.h> #include <ns16550.h> #include <serial.h> -#include <asm/arch/clock.h> +#include <asm/arch-rockchip/clock.h> #if defined(CONFIG_ROCKCHIP_RK3188) struct rockchip_uart_platdata { diff --git a/drivers/sound/rockchip_sound.c b/drivers/sound/rockchip_sound.c index e7fb9fb164..a092dbc445 100644 --- a/drivers/sound/rockchip_sound.c +++ b/drivers/sound/rockchip_sound.c @@ -13,7 +13,7 @@ #include <i2s.h> #include <misc.h> #include <sound.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> static int rockchip_sound_setup(struct udevice *dev) diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 14437c0a9a..a68553b75b 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -2,6 +2,8 @@ /* * spi driver for rockchip * + * (C) 2019 Theobroma Systems Design und Consulting GmbH + * * (C) Copyright 2015 Google, Inc * * (C) Copyright 2008-2013 Rockchip Electronics @@ -16,14 +18,19 @@ #include <spi.h> #include <linux/errno.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/periph.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/periph.h> #include <dm/pinctrl.h> #include "rk_spi.h" /* Change to 1 to output registers at the start of each transaction */ #define DEBUG_RK_SPI 0 +struct rockchip_spi_params { + /* RXFIFO overruns and TXFIFO underruns stop the master clock */ + bool master_manages_fifo; +}; + struct rockchip_spi_platdata { #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_spi of_plat; @@ -40,11 +47,8 @@ struct rockchip_spi_priv { unsigned int max_freq; unsigned int mode; ulong last_transaction_us; /* Time of last transaction end */ - u8 bits_per_word; /* max 16 bits per word */ - u8 n_bytes; unsigned int speed_hz; unsigned int last_speed_hz; - unsigned int tmode; uint input_rate; }; @@ -130,8 +134,13 @@ static void spi_cs_activate(struct udevice *dev, uint cs) if (plat->deactivate_delay_us && priv->last_transaction_us) { ulong delay_us; /* The delay completed so far */ delay_us = timer_get_us() - priv->last_transaction_us; - if (delay_us < plat->deactivate_delay_us) - udelay(plat->deactivate_delay_us - delay_us); + if (delay_us < plat->deactivate_delay_us) { + ulong additional_delay_us = + plat->deactivate_delay_us - delay_us; + debug("%s: delaying by %ld us\n", + __func__, additional_delay_us); + udelay(additional_delay_us); + } } debug("activate cs%u\n", cs); @@ -263,8 +272,6 @@ static int rockchip_spi_probe(struct udevice *bus) } priv->input_rate = ret; debug("%s: rate = %u\n", __func__, priv->input_rate); - priv->bits_per_word = 8; - priv->tmode = TMOD_TR; /* Tx & Rx */ return 0; } @@ -274,28 +281,10 @@ static int rockchip_spi_claim_bus(struct udevice *dev) struct udevice *bus = dev->parent; struct rockchip_spi_priv *priv = dev_get_priv(bus); struct rockchip_spi *regs = priv->regs; - u8 spi_dfs, spi_tf; uint ctrlr0; /* Disable the SPI hardware */ - rkspi_enable_chip(regs, 0); - - switch (priv->bits_per_word) { - case 8: - priv->n_bytes = 1; - spi_dfs = DFS_8BIT; - spi_tf = HALF_WORD_OFF; - break; - case 16: - priv->n_bytes = 2; - spi_dfs = DFS_16BIT; - spi_tf = HALF_WORD_ON; - break; - default: - debug("%s: unsupported bits: %dbits\n", __func__, - priv->bits_per_word); - return -EPROTONOSUPPORT; - } + rkspi_enable_chip(regs, false); if (priv->speed_hz != priv->last_speed_hz) rkspi_set_clk(priv, priv->speed_hz); @@ -304,7 +293,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 = OMOD_MASTER << OMOD_SHIFT; /* Data Frame Size */ - ctrlr0 |= spi_dfs << DFS_SHIFT; + ctrlr0 |= DFS_8BIT << DFS_SHIFT; /* set SPI mode 0..3 */ if (priv->mode & SPI_CPOL) @@ -325,7 +314,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FBM_MSB << FBM_SHIFT; /* Byte and Halfword Transform */ - ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT; + ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT; /* Rxd Sample Delay */ ctrlr0 |= 0 << RXDSD_SHIFT; @@ -334,7 +323,7 @@ static int rockchip_spi_claim_bus(struct udevice *dev) ctrlr0 |= FRF_SPI << FRF_SHIFT; /* Tx and Rx mode */ - ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; + ctrlr0 |= TMOD_TR << TMOD_SHIFT; writel(ctrlr0, ®s->ctrlr0); @@ -351,6 +340,83 @@ static int rockchip_spi_release_bus(struct udevice *dev) return 0; } +static inline int rockchip_spi_16bit_reader(struct udevice *dev, + u8 **din, int *len) +{ + struct udevice *bus = dev->parent; + const struct rockchip_spi_params * const data = + (void *)dev_get_driver_data(bus); + struct rockchip_spi_priv *priv = dev_get_priv(bus); + struct rockchip_spi *regs = priv->regs; + const u32 saved_ctrlr0 = readl(®s->ctrlr0); +#if defined(DEBUG) + u32 statistics_rxlevels[33] = { }; +#endif + u32 frames = *len / 2; + u8 *in = (u8 *)(*din); + u32 max_chunk_size = SPI_FIFO_DEPTH; + + if (!frames) + return 0; + + /* + * If we know that the hardware will manage RXFIFO overruns + * (i.e. stop the SPI clock until there's space in the FIFO), + * we the allow largest possible chunk size that can be + * represented in CTRLR1. + */ + if (data && data->master_manages_fifo) + max_chunk_size = 0x10000; + + // rockchip_spi_configure(dev, mode, size) + rkspi_enable_chip(regs, false); + clrsetbits_le32(®s->ctrlr0, + TMOD_MASK << TMOD_SHIFT, + TMOD_RO << TMOD_SHIFT); + /* 16bit data frame size */ + clrsetbits_le32(®s->ctrlr0, DFS_MASK, DFS_16BIT); + + /* Update caller's context */ + const u32 bytes_to_process = 2 * frames; + *din += bytes_to_process; + *len -= bytes_to_process; + + /* Process our frames */ + while (frames) { + u32 chunk_size = min(frames, max_chunk_size); + + frames -= chunk_size; + + writew(chunk_size - 1, ®s->ctrlr1); + rkspi_enable_chip(regs, true); + + do { + u32 rx_level = readw(®s->rxflr); +#if defined(DEBUG) + statistics_rxlevels[rx_level]++; +#endif + chunk_size -= rx_level; + while (rx_level--) { + u16 val = readw(regs->rxdr); + *in++ = val & 0xff; + *in++ = val >> 8; + } + } while (chunk_size); + + rkspi_enable_chip(regs, false); + } + +#if defined(DEBUG) + debug("%s: observed rx_level during processing:\n", __func__); + for (int i = 0; i <= 32; ++i) + if (statistics_rxlevels[i]) + debug("\t%2d: %d\n", i, statistics_rxlevels[i]); +#endif + /* Restore the original transfer setup and return error-free. */ + writel(saved_ctrlr0, ®s->ctrlr0); + return 0; +} + static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { @@ -362,7 +428,7 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, const u8 *out = dout; u8 *in = din; int toread, towrite; - int ret; + int ret = 0; debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din, len, flags); @@ -373,8 +439,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev, slave_plat->cs); + /* + * To ensure fast loading of firmware images (e.g. full U-Boot + * stage, ATF, Linux kernel) from SPI flash, we optimise the + * case of read-only transfers by using the full 16bits of each + * FIFO element. + */ + if (!out) + ret = rockchip_spi_16bit_reader(dev, &in, &len); + + /* This is the original 8bit reader/writer code */ while (len > 0) { - int todo = min(len, 0xffff); + int todo = min(len, 0x10000); rkspi_enable_chip(regs, false); writel(todo - 1, ®s->ctrlr1); @@ -397,9 +473,18 @@ static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen, toread--; } } - ret = rkspi_wait_till_not_busy(regs); - if (ret) - break; + + /* + * In case that there's a transmit-component, we need to wait + * until the control goes idle before we can disable the SPI + * control logic (as this will implictly flush the FIFOs). + */ + if (out) { + ret = rkspi_wait_till_not_busy(regs); + if (ret) + break; + } + len -= todo; } @@ -446,10 +531,16 @@ static const struct dm_spi_ops rockchip_spi_ops = { */ }; +const struct rockchip_spi_params rk3399_spi_params = { + .master_manages_fifo = true, +}; + static const struct udevice_id rockchip_spi_ids[] = { { .compatible = "rockchip,rk3288-spi" }, - { .compatible = "rockchip,rk3368-spi" }, - { .compatible = "rockchip,rk3399-spi" }, + { .compatible = "rockchip,rk3368-spi", + .data = (ulong)&rk3399_spi_params }, + { .compatible = "rockchip,rk3399-spi", + .data = (ulong)&rk3399_spi_params }, { } }; diff --git a/drivers/sysreset/sysreset_rockchip.c b/drivers/sysreset/sysreset_rockchip.c index 93d7cfe463..0fc6b683f2 100644 --- a/drivers/sysreset/sysreset_rockchip.c +++ b/drivers/sysreset/sysreset_rockchip.c @@ -8,9 +8,9 @@ #include <errno.h> #include <sysreset.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3328.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3328.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/err.h> int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 69019740b0..54956e557a 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -7,7 +7,7 @@ #include <dm.h> #include <dm/ofnode.h> #include <mapmem.h> -#include <asm/arch/timer.h> +#include <asm/arch-rockchip/timer.h> #include <dt-structs.h> #include <timer.h> #include <asm/io.h> diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index e81eb164b0..f3d24772cd 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -15,7 +15,7 @@ #include <linux/compiler.h> #include <version.h> #include <g_dnl.h> -#include <asm/arch/f_rockusb.h> +#include <asm/arch-rockchip/f_rockusb.h> static inline struct f_rockusb *func_to_rockusb(struct usb_function *f) { diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index 3b6f889f7b..2b0df88f49 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1545,10 +1545,8 @@ static int submit_common_msg(ohci_t *ohci, struct usb_device *dev, return -1; } -#if 0 mdelay(10); /* ohci_dump_status(ohci); */ -#endif timeout = USB_TIMEOUT_MS(pipe); diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c index 2ee0f23b7e..1f2805270a 100644 --- a/drivers/usb/musb/musb_hcd.c +++ b/drivers/usb/musb/musb_hcd.c @@ -327,9 +327,7 @@ static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) csr = readw(&musbr->txcsr); csr |= MUSB_CSR0_TXPKTRDY; -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); if (result < 0) @@ -352,9 +350,7 @@ static int ctrlreq_out_status_phase(struct usb_device *dev) /* Set the StatusPkt bit */ csr = readw(&musbr->txcsr); csr |= (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_H_STATUSPKT); -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); /* Wait until TXPKTRDY bit is cleared */ @@ -372,9 +368,7 @@ static int ctrlreq_in_status_phase(struct usb_device *dev) /* Set the StatusPkt bit and ReqPkt bit */ csr = MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; -#if !defined(CONFIG_SOC_DM365) csr |= MUSB_CSR0_H_DIS_PING; -#endif writew(csr, &musbr->txcsr); result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); diff --git a/drivers/video/rockchip/rk3288_hdmi.c b/drivers/video/rockchip/rk3288_hdmi.c index eb3692c387..315d3adf27 100644 --- a/drivers/video/rockchip/rk3288_hdmi.c +++ b/drivers/video/rockchip/rk3288_hdmi.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <power/regulator.h> #include "rk_hdmi.h" diff --git a/drivers/video/rockchip/rk3288_mipi.c b/drivers/video/rockchip/rk3288_mipi.c index d268b46514..7c4a4cc53b 100644 --- a/drivers/video/rockchip/rk3288_mipi.c +++ b/drivers/video/rockchip/rk3288_mipi.c @@ -14,14 +14,14 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> #define MHz 1000000 diff --git a/drivers/video/rockchip/rk3288_vop.c b/drivers/video/rockchip/rk3288_vop.c index 7e953a628c..0f91dab1f2 100644 --- a/drivers/video/rockchip/rk3288_vop.c +++ b/drivers/video/rockchip/rk3288_vop.c @@ -11,10 +11,10 @@ #include <regmap.h> #include <syscon.h> #include <video.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/grf_rk3288.h> +#include <asm/arch-rockchip/hardware.h> #include "rk_vop.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/rockchip/rk3399_hdmi.c b/drivers/video/rockchip/rk3399_hdmi.c index b75efe6fc3..a62be98327 100644 --- a/drivers/video/rockchip/rk3399_hdmi.c +++ b/drivers/video/rockchip/rk3399_hdmi.c @@ -13,9 +13,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/arch/grf_rk3399.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3399.h> #include <power/regulator.h> #include "rk_hdmi.h" diff --git a/drivers/video/rockchip/rk3399_mipi.c b/drivers/video/rockchip/rk3399_mipi.c index bb9007bf36..a93b73400b 100644 --- a/drivers/video/rockchip/rk3399_mipi.c +++ b/drivers/video/rockchip/rk3399_mipi.c @@ -14,14 +14,14 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> /* Select mipi dsi source, big or little vop */ static int rk_mipi_dsi_source_select(struct udevice *dev) diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 7a02221ae0..81c122d7a9 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -10,7 +10,7 @@ #include <dm.h> #include <regmap.h> #include <video.h> -#include <asm/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <asm/io.h> #include "rk_vop.h" diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c index e074107632..4330725a25 100644 --- a/drivers/video/rockchip/rk_edp.c +++ b/drivers/video/rockchip/rk_edp.c @@ -14,9 +14,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/edp_rk3288.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/edp_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <dt-bindings/clock/rk3288-cru.h> #define MAX_CR_LOOP 5 diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 13d07ee304..51931ceefa 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -14,10 +14,9 @@ #include <regmap.h> #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/hardware.h> #include "rk_hdmi.h" #include "rk_vop.h" /* for rk_vop_probe_regulators */ diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index f0a528c0d6..cf5c0439b1 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -12,9 +12,9 @@ #include <syscon.h> #include <asm/gpio.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/lvds_rk3288.h> -#include <asm/arch/grf_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/lvds_rk3288.h> +#include <asm/arch-rockchip/grf_rk3288.h> #include <dt-bindings/clock/rk3288-cru.h> #include <dt-bindings/video/rk3288.h> diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 4f1a0f3a5f..bcd039b7bc 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -14,14 +14,13 @@ #include "rk_mipi.h" #include <syscon.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> #include <dm/uclass-internal.h> #include <linux/kernel.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/rockchip_mipi_dsi.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/grf_rk3399.h> +#include <asm/arch-rockchip/rockchip_mipi_dsi.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index faf4f24db0..b56c3f336c 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -13,11 +13,10 @@ #include <syscon.h> #include <video.h> #include <asm/gpio.h> -#include <asm/hardware.h> #include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/edp_rk3288.h> -#include <asm/arch/vop_rk3288.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/edp_rk3288.h> +#include <asm/arch-rockchip/vop_rk3288.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> #include <power/regulator.h> diff --git a/drivers/video/rockchip/rk_vop.h b/drivers/video/rockchip/rk_vop.h index 828974d394..8fa2f38939 100644 --- a/drivers/video/rockchip/rk_vop.h +++ b/drivers/video/rockchip/rk_vop.h @@ -6,7 +6,7 @@ #ifndef __RK_VOP_H__ #define __RK_VOP_H__ -#include <asm/arch/vop_rk3288.h> +#include <asm/arch-rockchip/vop_rk3288.h> struct rk_vop_priv { void *grf; diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 8eca3f3ca9..f909d40f45 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -55,7 +55,7 @@ config WDT help Enable driver model for watchdog timer. At the moment the API is very simple and only supports four operations: - start, restart, stop and reset (expire immediately). + start, stop, reset and expire_now (expire immediately). What exactly happens when the timer expires is up to a particular device/driver. diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c index 6f35854823..cb7e182742 100644 --- a/fs/btrfs/btrfs.c +++ b/fs/btrfs/btrfs.c @@ -119,17 +119,17 @@ int btrfs_ls(const char *path) if (inr == -1ULL) { printf("Cannot lookup path %s\n", path); - return 1; + return -1; } if (type != BTRFS_FT_DIR) { printf("Not a directory: %s\n", path); - return 1; + return -1; } if (btrfs_readdir(&root, inr, readdir_callback)) { printf("An error occured while listing directory %s\n", path); - return 1; + return -1; } return 0; @@ -158,12 +158,12 @@ int btrfs_size(const char *file, loff_t *size) if (inr == -1ULL) { printf("Cannot lookup file %s\n", file); - return 1; + return -1; } if (type != BTRFS_FT_REG_FILE) { printf("Not a regular file: %s\n", file); - return 1; + return -1; } *size = inode.size; @@ -183,12 +183,12 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, if (inr == -1ULL) { printf("Cannot lookup file %s\n", file); - return 1; + return -1; } if (type != BTRFS_FT_REG_FILE) { printf("Not a regular file: %s\n", file); - return 1; + return -1; } if (!len) @@ -200,7 +200,7 @@ int btrfs_read(const char *file, void *buf, loff_t offset, loff_t len, rd = btrfs_file_read(&root, inr, offset, len, buf); if (rd == -1ULL) { printf("An error occured while reading file %s\n", file); - return 1; + return -1; } *actread = rd; diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index 7aaf8f9b0d..2dc4a6fcd7 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -198,17 +198,16 @@ int btrfs_read_superblock(void) break; if (btrfs_check_super_csum(raw_sb)) { - printf("%s: invalid checksum at superblock mirror %i\n", - __func__, i); + debug("%s: invalid checksum at superblock mirror %i\n", + __func__, i); continue; } btrfs_super_block_to_cpu(sb); if (sb->magic != BTRFS_MAGIC) { - printf("%s: invalid BTRFS magic 0x%016llX at " - "superblock mirror %i\n", __func__, sb->magic, - i); + debug("%s: invalid BTRFS magic 0x%016llX at " + "superblock mirror %i\n", __func__, sb->magic, i); } else if (sb->bytenr != superblock_offsets[i]) { printf("%s: invalid bytenr 0x%016llX (expected " "0x%016llX) at superblock mirror %i\n", @@ -224,7 +223,7 @@ int btrfs_read_superblock(void) } if (!btrfs_info.sb.generation) { - printf("%s: No valid BTRFS superblock found!\n", __func__); + debug("%s: No valid BTRFS superblock found!\n", __func__); return -1; } diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 57edeee941..22d1e41bc8 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -21,8 +21,6 @@ #define CONFIG_LOADCMD "fatload" #define CONFIG_RFSPART "2" -#define CONFIG_SUPPORT_EMMC_BOOT - #include "mx6_common.h" #include <linux/sizes.h> diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index c14b010550..2c651aab17 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -63,8 +63,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h index 1d296ba51a..9c8c8979f0 100644 --- a/include/configs/apalis-tk1.h +++ b/include/configs/apalis-tk1.h @@ -18,9 +18,6 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -/* SD/MMC support */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* Environment in eMMC, before config block at the end of 1st "boot sector" */ #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ CONFIG_TDX_CFG_BLOCK_OFFSET) diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 91054d8c05..9d9e16e5d9 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -46,8 +46,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* * SATA Configs */ diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 06b02ce90a..dd321c4748 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -14,9 +14,6 @@ #include "exynos5250-common.h" #include <configs/exynos5-common.h> -/* SD/MMC configuration */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h index 84c801d10a..51af93a32f 100644 --- a/include/configs/brppt1.h +++ b/include/configs/brppt1.h @@ -31,11 +31,6 @@ /*#define CONFIG_MACH_TYPE 3589*/ #define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ -/* MMC/SD IP block */ -#if defined(CONFIG_EMMC_BOOT) - #define CONFIG_SUPPORT_EMMC_BOOT -#endif /* CONFIG_EMMC_BOOT */ - /* * When we have NAND flash we expect to be making use of mtdparts, * both for ease of use in U-Boot and for passing information on to diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 26d1a97891..4c93fc6cbe 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -153,7 +153,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #endif /* USB Configs */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h index a00329db29..4198ff0511 100644 --- a/include/configs/clearfog.h +++ b/include/configs/clearfog.h @@ -26,10 +26,6 @@ */ #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE -#ifdef CONFIG_CMD_MMC -#define CONFIG_SUPPORT_EMMC_BOOT -#endif - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h index cda1b5528f..2387f864e3 100644 --- a/include/configs/cm_t54.h +++ b/include/configs/cm_t54.h @@ -41,7 +41,6 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT -#define CONFIG_SUPPORT_EMMC_BOOT /* SATA Boot related defines */ #define CONFIG_SPL_SATA_BOOT_DEVICE 0 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index 129a42466d..b540b3e074 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -44,8 +44,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - /* Network */ #define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 5a4b9801cb..7dfc92c085 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -35,8 +35,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 1 #elif CONFIG_TARGET_COLIBRI_IMX7_EMMC #define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SUPPORT_EMMC_BOOT #endif #undef CONFIG_BOOTM_PLAN9 diff --git a/include/configs/display5.h b/include/configs/display5.h index 8ab47abfa8..8829cbad91 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -83,7 +83,6 @@ #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index f6be6595fe..aec70ee718 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -96,8 +96,6 @@ /* SPI SPL */ #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB xHCI HOST */ #define CONFIG_USB_XHCI_OMAP diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h index cf021083ae..7155ebac5c 100644 --- a/include/configs/dragonboard410c.h +++ b/include/configs/dragonboard410c.h @@ -31,13 +31,6 @@ * it has to be done after each HCD reset */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -/* Support all possible USB ethernet dongles */ - -/* Extra Commands */ -/* Enable that for switching of boot partitions */ -/* Disabled by default as some sub-commands can brick eMMC */ -/*#define CONFIG_SUPPORT_EMMC_BOOT */ - /* BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE diff --git a/include/configs/edison.h b/include/configs/edison.h index a6155ba5a8..218b50a1d9 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -34,7 +34,6 @@ #define CONFIG_ENV_SIZE (64 * 1024) #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) #define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) -#define CONFIG_SUPPORT_EMMC_BOOT /* RTC */ #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 858bed012c..8bc7a3ad2e 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -76,7 +76,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ #define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ #define CONFIG_FDTFILE "imx6q-marsboard.dtb" diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index db1fc934bb..397bbf6d9d 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -44,7 +44,6 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 -#define CONFIG_SUPPORT_EMMC_BOOT /* specific .lds file */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 196f114c60..0481ed06a9 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -19,9 +19,6 @@ #define CONFIG_MXC_UART_BASE UART3_BASE #define CONSOLE_DEV "ttymxc2" -#define CONFIG_SUPPORT_EMMC_BOOT - - #include "mx6_common.h" #include <linux/sizes.h> diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 93608e5aec..02ceb4c8fc 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -81,9 +81,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -/* eMMC Configs */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* * SATA Configs */ diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h index 030dbedce8..7605e145c2 100644 --- a/include/configs/imx6dl-mamoj.h +++ b/include/configs/imx6dl-mamoj.h @@ -51,7 +51,6 @@ /* MMC */ #define CONFIG_SYS_MMC_ENV_DEV 2 -#define CONFIG_SUPPORT_EMMC_BOOT /* Ethernet */ #define CONFIG_FEC_MXC_PHYADDR 1 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index aaecf6f053..7759bbf264 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -224,7 +224,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_MXC_GPIO diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 18ea5a8fb6..40163c8d50 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -53,7 +53,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a97ccb50b2..975f32474c 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -24,7 +24,6 @@ /* MMC Configs */ #ifdef CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT #endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index e449364ad4..5f67893f31 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -42,7 +42,6 @@ /* MMC */ #define MMC_SUPPORTS_TUNING -#define CONFIG_SUPPORT_EMMC_BOOT /* DRAM */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 555942a2c2..ec1537541a 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -16,8 +16,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "mx6sabre_common.h" /* Falcon Mode */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 39d29de744..77856a8f3a 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -38,7 +38,6 @@ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index b8dcaa1036..5bd6392973 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -28,7 +28,6 @@ #define IOMUXC_BASE_ADDR IOMUXC1_RBASE #define CONFIG_FSL_USDHC -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_FSL_USDHC_NUM 1 diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 66bd288040..0d8f945349 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -39,7 +39,6 @@ /* Enhance our eMMC support / experience. */ #define CONFIG_HSMMC2_8BIT -#define CONFIG_SUPPORT_EMMC_BOOT /* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h index 70cf4665df..e0c76ff43d 100644 --- a/include/configs/opos6uldev.h +++ b/include/configs/opos6uldev.h @@ -33,9 +33,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* MMC */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* USB */ #ifdef CONFIG_USB_EHCI_MX6 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 050f69801b..cd051bf263 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -41,7 +41,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 04d316f113..365a5984e4 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -58,7 +58,6 @@ "bootmenu_1=Boot using PICO-Pi baseboard=" \ "setenv fdtfile imx7d-pico-pi.dtb\0" \ -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 6c02446a65..f5d09d18e5 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RK3036_COMMON_H #define __CONFIG_RK3036_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index 4f6f4af957..1d41702846 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -8,7 +8,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index 22eb064fad..3a96748f6b 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RK322X_COMMON_H #define __CONFIG_RK322X_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 3a1cbf28af..7c79ed6138 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -6,7 +6,7 @@ #ifndef __CONFIG_RK3288_COMMON_H #define __CONFIG_RK3288_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index cf51f25bf3..bb2e96ba05 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include <linux/sizes.h> #define CONFIG_SYS_SDRAM_BASE 0 diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h index 952ea9fdca..6f61f01538 100644 --- a/include/configs/rv1108_common.h +++ b/include/configs/rv1108_common.h @@ -5,7 +5,7 @@ #ifndef __CONFIG_RV1108_COMMON_H #define __CONFIG_RV1108_COMMON_H -#include <asm/arch/hardware.h> +#include <asm/arch-rockchip/hardware.h> #include "rockchip-common.h" #define CONFIG_SYS_MALLOC_LEN (32 << 20) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 3069373236..fd6c97a0c6 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -77,7 +77,6 @@ /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 -#define CONFIG_SUPPORT_EMMC_BOOT /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/taurus.h b/include/configs/taurus.h index c3353d74a9..45a4a800c5 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -41,6 +41,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG + #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* general purpose I/O */ @@ -48,12 +49,9 @@ #define CONFIG_AT91_GPIO #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ -/* serial console */ -#define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU #define CONFIG_USART_ID ATMEL_ID_SYS - /* * SDRAM: 1 bank, min 32, max 128 MB * Initialized before u-boot gets started. @@ -106,7 +104,6 @@ /* SPI EEPROM */ #define TAURUS_SPI_MASK (1 << 4) -#define TAURUS_SPI_CS_PIN AT91_PIN_PA3 #if defined(CONFIG_SPL_BUILD) /* SPL related */ @@ -120,8 +117,57 @@ #define CONFIG_ENV_OFFSET 0x100000 #define CONFIG_ENV_OFFSET_REDUND 0x180000 #define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_BOARD_AXM) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ + "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ + "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \ + "boot_retries=0\0" \ + "ethact=macb0\0" \ + "flash_nfs=run nand_kernel;run nfsargs;run addip;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "flash_self_test=run nand_kernel;run setbootargs addtest;" \ + "upgrade_available;bootm ${kernel_ram};reset\0" \ + "hostname=systemone\0" \ + "kernel_Off=0x00200000\0" \ + "kernel_Off_fallback=0x03800000\0" \ + "kernel_ram=0x21500000\0" \ + "kernel_size=0x00400000\0" \ + "kernel_size_fallback=0x00400000\0" \ + "loads_echo=1\0" \ + "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \ + "${kernel_size}\0" \ + "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \ + "run nfsargs;run addip;upgrade_available;" \ + "bootm ${kernel_ram};reset\0" \ + "netdev=eth0\0" \ + "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \ + "rw nfsroot=${serverip}:${rootpath} " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "partitionset_active=A\0" \ + "preboot=echo;echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory;echo Type 'run flash_nfs' to use " \ + "kernel from memory and root filesystem over NFS;echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS;echo\0" \ + "project_dir=systemone\0" \ + "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \ + "rootfs=/dev/mtdblock5\0" \ + "rootfs_fallback=/dev/mtdblock7\0" \ + "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \ + "root=${rootfs} rootfstype=jffs2 panic=7 " \ + "at91sam9_wdt.wdt_timeout=16\0" \ + "stderr=serial\0" \ + "stdin=serial\0" \ + "stdout=serial\0" \ + "upgrade_available=0\0" +#endif +#endif /* #ifndef CONFIG_SPL_BUILD */ /* * Size of malloc() pool */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 5a148873c7..018f54428b 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -18,31 +18,6 @@ */ #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -/* - * Commands configuration - */ - -/* I2C support */ -#define CONFIG_DM_I2C -#define CONFIG_I2C_MUX -#define CONFIG_I2C_MUX_PCA954x -#define CONFIG_SPL_I2C_MUX -#define CONFIG_SYS_I2C_MVTWSI - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI @@ -114,9 +89,16 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 31a9c59ed5..bec7b68794 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -94,9 +94,6 @@ #define CONFIG_SYS_NAND_DATA_BASE 0x68000000 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* SD/MMC */ -#define CONFIG_SUPPORT_EMMC_BOOT - /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) diff --git a/include/configs/vinco.h b/include/configs/vinco.h index ec22a30cda..eebb3f7ca7 100644 --- a/include/configs/vinco.h +++ b/include/configs/vinco.h @@ -43,7 +43,6 @@ /* MMC */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_GENERIC_ATMEL_MCI #define ATMEL_BASE_MMCI 0xfc000000 #define CONFIG_SYS_MMC_CLK_OD 500000 diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index d3cbdc6f2e..fd98c1417e 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -95,7 +95,6 @@ #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE #ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ /* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ #define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ diff --git a/include/configs/warp.h b/include/configs/warp.h index 9aa8a48d3d..5345f5314d 100644 --- a/include/configs/warp.h +++ b/include/configs/warp.h @@ -23,7 +23,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE -#define CONFIG_SUPPORT_EMMC_BOOT /* Watchdog */ #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 37649cf2c5..0ef8e35948 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -29,7 +29,6 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 37a9ae90e5..684faaee2e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -47,10 +47,6 @@ #define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_BOOTP_MAY_FAIL -#if defined(CONFIG_MMC_SDHCI_ZYNQ) -# define CONFIG_SUPPORT_EMMC_BOOT -#endif - #ifdef CONFIG_NAND_ARASAN # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_ONFI_DETECTION diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 08e0ca0c8f..4cbf8aa526 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -21,7 +21,6 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ /* I2C configs */ #define CONFIG_SYS_I2C diff --git a/include/configs/zc5202.h b/include/configs/zc5202.h index 40d33f7830..77ff04754b 100644 --- a/include/configs/zc5202.h +++ b/include/configs/zc5202.h @@ -12,8 +12,6 @@ #define CONSOLE_DEV "ttymxc1" #define CONFIG_MMCROOT "/dev/mmcblk0p2" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "el6x_common.h" /* Ethernet */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h index b9673e2c06..e4fe7a462d 100644 --- a/include/configs/zc5601.h +++ b/include/configs/zc5601.h @@ -13,8 +13,6 @@ #define CONSOLE_DEV "ttymxc1" #define CONFIG_MMCROOT "/dev/mmcblk0p1" -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - #include "el6x_common.h" /* Ethernet */ diff --git a/include/dt-bindings/pinctrl/k3-am65.h b/include/dt-bindings/pinctrl/k3.h index c86c9fd4ce..a67521cdc4 100644 --- a/include/dt-bindings/pinctrl/k3-am65.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -7,17 +7,6 @@ #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H -/* K3 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE15 15 - #define PULL_DISABLE (1 << 16) #define PULL_UP (1 << 17) #define INPUT_EN (1 << 18) @@ -43,7 +32,7 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN) -#define AM65X_IOPAD(pa, val) (((pa) & 0x1fff)) (val) -#define AM65X_WKUP_IOPAD(pa, val) (((pa) & 0x1fff)) (val) +#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #endif diff --git a/include/efi_loader.h b/include/efi_loader.h index 39ed8a6fa5..7af3f16ef8 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -207,12 +207,17 @@ struct efi_object { * struct efi_loaded_image_obj - handle of a loaded image * * @header: EFI object header + * @exit_status: exit status passed to Exit() + * @exit_data_size: exit data size passed to Exit() + * @exit_data: exit data passed to Exit() * @exit_jmp: long jump buffer for returning form started image * @entry: entry address of the relocated image */ struct efi_loaded_image_obj { struct efi_object header; efi_status_t exit_status; + efi_uintn_t *exit_data_size; + u16 **exit_data; struct jmp_buf_data exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); @@ -560,7 +565,7 @@ struct efi_load_option { u16 file_path_length; u16 *label; struct efi_device_path *file_path; - u8 *optional_data; + const u8 *optional_data; }; void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data); diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 49d3d6d0b4..dd42e49023 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -16,7 +16,7 @@ #define EFI_ST_SUCCESS 0 #define EFI_ST_FAILURE 1 - +#define EFI_ST_SUCCESS_STR L"SUCCESS" /* * Prints a message. */ diff --git a/include/fs.h b/include/fs.h index 6854597700..7601b0343b 100644 --- a/include/fs.h +++ b/include/fs.h @@ -71,30 +71,33 @@ int fs_exists(const char *filename); */ int fs_size(const char *filename, loff_t *size); -/* - * fs_read - Read file from the partition previously set by fs_set_blk_dev() - * Note that not all filesystem types support either/both offset!=0 or len!=0. +/** + * fs_read() - read file from the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support either or both of offset != 0 + * and len != 0. * - * @filename: Name of file to read from - * @addr: The address to read into - * @offset: The offset in file to read from - * @len: The number of bytes to read. Maybe 0 to read entire file - * @actread: Returns the actual number of bytes read - * @return 0 if ok with valid *actread, -1 on error conditions + * @filename: full path of the file to read from + * @addr: address of the buffer to write to + * @offset: offset in the file from where to start reading + * @len: the number of bytes to read. Use 0 to read entire file. + * @actread: returns the actual number of bytes read + * Return: 0 if OK with valid *actread, -1 on error conditions */ int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len, loff_t *actread); -/* - * fs_write - Write file to the partition previously set by fs_set_blk_dev() - * Note that not all filesystem types support offset!=0. +/** + * fs_write() - write file to the partition previously set by fs_set_blk_dev() + * + * Note that not all filesystem drivers support offset != 0. * - * @filename: Name of file to read from - * @addr: The address to read into - * @offset: The offset in file to read from. Maybe 0 to write to start of file - * @len: The number of bytes to write - * @actwrite: Returns the actual number of bytes written - * @return 0 if ok with valid *actwrite, -1 on error conditions + * @filename: full path of the file to write to + * @addr: address of the buffer to read from + * @offset: offset in the file from where to start writing + * @len: the number of bytes to write + * @actwrite: returns the actual number of bytes written + * Return: 0 if OK with valid *actwrite, -1 on error conditions */ int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len, loff_t *actwrite); diff --git a/include/sdhci.h b/include/sdhci.h index bef37df982..eee493ab5f 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -186,6 +186,7 @@ /* 55-57 reserved */ #define SDHCI_ADMA_ADDRESS 0x58 +#define SDHCI_ADMA_ADDRESS_HI 0x5c /* 60-FB reserved */ @@ -252,6 +253,38 @@ struct sdhci_ops { void (*set_delay)(struct sdhci_host *host); }; +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) +#define ADMA_MAX_LEN 65532 +#ifdef CONFIG_DMA_ADDR_T_64BIT +#define ADMA_DESC_LEN 16 +#else +#define ADMA_DESC_LEN 8 +#endif +#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \ + MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN + +#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN) + +/* Decriptor table defines */ +#define ADMA_DESC_ATTR_VALID BIT(0) +#define ADMA_DESC_ATTR_END BIT(1) +#define ADMA_DESC_ATTR_INT BIT(2) +#define ADMA_DESC_ATTR_ACT1 BIT(4) +#define ADMA_DESC_ATTR_ACT2 BIT(5) + +#define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 +#define ADMA_DESC_LINK_DESC (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2) + +struct sdhci_adma_desc { + u8 attr; + u8 reserved; + u16 len; + u32 addr_lo; +#ifdef CONFIG_DMA_ADDR_T_64BIT + u32 addr_hi; +#endif +} __packed; +#endif struct sdhci_host { const char *name; void *ioaddr; @@ -272,6 +305,17 @@ struct sdhci_host { uint voltages; struct mmc_config cfg; + dma_addr_t start_addr; + int flags; +#define USE_SDMA (0x1 << 0) +#define USE_ADMA (0x1 << 1) +#define USE_ADMA64 (0x1 << 2) +#define USE_DMA (USE_SDMA | USE_ADMA | USE_ADMA64) + dma_addr_t adma_addr; +#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) + struct sdhci_adma_desc *adma_desc_table; + uint desc_slot; +#endif }; #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS diff --git a/lib/Kconfig b/lib/Kconfig index 05f82d4a50..38012506d2 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -359,7 +359,7 @@ config LZO This enables support for LZO compression algorithm.r config GZIP - bool "Enable gzip decompression support for SPL build" + bool "Enable gzip decompression support" select ZLIB default y help diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c index 4ccba22875..7bf51874c1 100644 --- a/lib/efi_loader/efi_bootmgr.c +++ b/lib/efi_loader/efi_bootmgr.c @@ -53,19 +53,20 @@ void efi_deserialize_load_option(struct efi_load_option *lo, u8 *data) */ unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data) { - unsigned long label_len, option_len; + unsigned long label_len; unsigned long size; u8 *p; label_len = (u16_strlen(lo->label) + 1) * sizeof(u16); - option_len = strlen((char *)lo->optional_data); /* total size */ size = sizeof(lo->attributes); size += sizeof(lo->file_path_length); size += label_len; size += lo->file_path_length; - size += option_len + 1; + if (lo->optional_data) + size += (utf8_utf16_strlen((const char *)lo->optional_data) + + 1) * sizeof(u16); p = malloc(size); if (!p) return 0; @@ -84,10 +85,10 @@ unsigned long efi_serialize_load_option(struct efi_load_option *lo, u8 **data) memcpy(p, lo->file_path, lo->file_path_length); p += lo->file_path_length; - memcpy(p, lo->optional_data, option_len); - p += option_len; - *(char *)p = '\0'; - + if (lo->optional_data) { + utf8_utf16_strcpy((u16 **)&p, (const char *)lo->optional_data); + p += sizeof(u16); /* size of trailing \0 */ + } return size; } diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 601b0a2cb8..e5c46e9f08 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -423,10 +423,12 @@ static efi_status_t EFIAPI efi_free_pool_ext(void *buffer) } /** - * efi_add_handle() - add a new object to the object list - * @obj: object to be added + * efi_add_handle() - add a new handle to the object list * - * The protocols list is initialized. The object handle is set. + * @handle: handle to be added + * + * The protocols list is initialized. The handle is added to the list of known + * UEFI objects. */ void efi_add_handle(efi_handle_t handle) { @@ -618,7 +620,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, } if ((type & (EVT_NOTIFY_WAIT | EVT_NOTIFY_SIGNAL)) && - (is_valid_tpl(notify_tpl) != EFI_SUCCESS)) + (!notify_function || is_valid_tpl(notify_tpl) != EFI_SUCCESS)) return EFI_INVALID_PARAMETER; evt = calloc(1, sizeof(struct efi_event)); @@ -2626,6 +2628,9 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_is_direct_boot = false; + image_obj->exit_data_size = exit_data_size; + image_obj->exit_data = exit_data; + /* call the image! */ if (setjmp(&image_obj->exit_jmp)) { /* @@ -2670,6 +2675,41 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, } /** + * efi_update_exit_data() - fill exit data parameters of StartImage() + * + * @image_obj image handle + * @exit_data_size size of the exit data buffer + * @exit_data buffer with data returned by UEFI payload + * Return: status code + */ +static efi_status_t efi_update_exit_data(struct efi_loaded_image_obj *image_obj, + efi_uintn_t exit_data_size, + u16 *exit_data) +{ + efi_status_t ret; + + /* + * If exit_data is not provided to StartImage(), exit_data_size must be + * ignored. + */ + if (!image_obj->exit_data) + return EFI_SUCCESS; + if (image_obj->exit_data_size) + *image_obj->exit_data_size = exit_data_size; + if (exit_data_size && exit_data) { + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + exit_data_size, + (void **)image_obj->exit_data); + if (ret != EFI_SUCCESS) + return ret; + memcpy(*image_obj->exit_data, exit_data, exit_data_size); + } else { + image_obj->exit_data = NULL; + } + return EFI_SUCCESS; +} + +/** * efi_exit() - leave an EFI application or driver * @image_handle: handle of the application or driver that is exiting * @exit_status: status code @@ -2709,6 +2749,15 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, if (ret != EFI_SUCCESS) goto out; + /* Exit data is only foreseen in case of failure. */ + if (exit_status != EFI_SUCCESS) { + ret = efi_update_exit_data(image_obj, exit_data_size, + exit_data); + /* Exiting has priority. Don't return error to caller. */ + if (ret != EFI_SUCCESS) + EFI_PRINT("%s: out of memory\n", __func__); + } + /* Make sure entry/exit counts for EFI world cross-overs match */ EFI_EXIT(exit_status); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 987cc6dc5f..776077cc35 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -452,7 +452,7 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) uint64_t r = 0; /* Sanity check */ - if (!memory || (memory & EFI_PAGE_MASK)) { + if (!memory || (memory & EFI_PAGE_MASK) || !pages) { printf("%s: illegal free 0x%llx, 0x%zx\n", __func__, memory, pages); return EFI_INVALID_PARAMETER; diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index b32a7b3f93..87db51cbb7 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -79,6 +79,7 @@ out: */ efi_status_t efi_init_obj_list(void) { + u64 os_indications_supported = 0; /* None */ efi_status_t ret = EFI_SUCCESS; /* Initialize once only */ @@ -90,6 +91,16 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + /* Indicate supported features */ + ret = EFI_CALL(efi_set_variable(L"OsIndicationsSupported", + &efi_global_variable_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + sizeof(os_indications_supported), + &os_indications_supported)); + if (ret != EFI_SUCCESS) + goto out; + /* Initialize system table */ ret = efi_initialize_system_table(); if (ret != EFI_SUCCESS) diff --git a/lib/efi_selftest/efi_selftest_miniapp_exit.c b/lib/efi_selftest/efi_selftest_miniapp_exit.c index b3ca109d81..6b5cfb01cf 100644 --- a/lib/efi_selftest/efi_selftest_miniapp_exit.c +++ b/lib/efi_selftest/efi_selftest_miniapp_exit.c @@ -9,7 +9,7 @@ */ #include <common.h> -#include <efi_api.h> +#include <efi_selftest.h> static efi_guid_t loaded_image_protocol_guid = EFI_LOADED_IMAGE_PROTOCOL_GUID; @@ -66,15 +66,22 @@ efi_status_t EFIAPI efi_main(efi_handle_t handle, struct efi_system_table *systable) { struct efi_simple_text_output_protocol *con_out = systable->con_out; - efi_status_t ret = EFI_UNSUPPORTED; + efi_status_t ret; + u16 text[] = EFI_ST_SUCCESS_STR; con_out->output_string(con_out, L"EFI application calling Exit\n"); - if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) + if (check_loaded_image_protocol(handle, systable) != EFI_SUCCESS) { + con_out->output_string(con_out, + L"Loaded image protocol missing\n"); ret = EFI_NOT_FOUND; + goto out; + } - /* The return value is checked by the calling test */ - systable->boottime->exit(handle, ret, 0, NULL); + /* This return value is expected by the calling test */ + ret = EFI_UNSUPPORTED; +out: + systable->boottime->exit(handle, ret, sizeof(text), text); /* * This statement should not be reached. diff --git a/lib/efi_selftest/efi_selftest_startimage_exit.c b/lib/efi_selftest/efi_selftest_startimage_exit.c index fa4b7d4a9b..96049dea86 100644 --- a/lib/efi_selftest/efi_selftest_startimage_exit.c +++ b/lib/efi_selftest/efi_selftest_startimage_exit.c @@ -123,6 +123,9 @@ static int execute(void) { efi_status_t ret; efi_handle_t handle; + efi_uintn_t exit_data_size = 0; + u16 *exit_data = NULL; + u16 expected_text[] = EFI_ST_SUCCESS_STR; ret = boottime->load_image(false, image_handle, NULL, image, img.length, &handle); @@ -130,11 +133,21 @@ static int execute(void) efi_st_error("Failed to load image\n"); return EFI_ST_FAILURE; } - ret = boottime->start_image(handle, NULL, NULL); + ret = boottime->start_image(handle, &exit_data_size, &exit_data); if (ret != EFI_UNSUPPORTED) { efi_st_error("Wrong return value from application\n"); return EFI_ST_FAILURE; } + if (!exit_data || exit_data_size != sizeof(expected_text) || + efi_st_memcmp(exit_data, expected_text, sizeof(expected_text))) { + efi_st_error("Incorrect exit data\n"); + return EFI_ST_FAILURE; + } + ret = boottime->free_pool(exit_data); + if (ret != EFI_SUCCESS) { + efi_st_error("Failed to free exit data\n"); + return EFI_ST_FAILURE; + } return EFI_ST_SUCCESS; } diff --git a/lib/uuid.c b/lib/uuid.c index fa20ee39fc..2d4d6ef7e4 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -238,6 +238,8 @@ void gen_rand_uuid(unsigned char *uuid_bin) unsigned int *ptr = (unsigned int *)&uuid; int i; + srand(get_ticks() + rand()); + /* Set all fields randomly */ for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++) *(ptr + i) = cpu_to_be32(rand()); diff --git a/lib/vsprintf.c b/lib/vsprintf.c index 2403825dc9..3502b8088f 100644 --- a/lib/vsprintf.c +++ b/lib/vsprintf.c @@ -16,7 +16,6 @@ #include <efi_loader.h> #include <div64.h> #include <hexdump.h> -#include <uuid.h> #include <stdarg.h> #include <linux/ctype.h> #include <linux/err.h> diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c450e1157a..bc86b848a2 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -118,7 +118,6 @@ CONFIG_BMP_32BPP CONFIG_BOARDDIR CONFIG_BOARDNAME CONFIG_BOARDNAME_LOCAL -CONFIG_BOARD_AXM CONFIG_BOARD_COMMON CONFIG_BOARD_ECC_SUPPORT CONFIG_BOARD_IS_OPENRD_BASE @@ -128,7 +127,6 @@ CONFIG_BOARD_NAME CONFIG_BOARD_POSTCLK_INIT CONFIG_BOARD_REVISION_TAG CONFIG_BOARD_SIZE_LIMIT -CONFIG_BOARD_TAURUS CONFIG_BOOGER CONFIG_BOOTBLOCK CONFIG_BOOTFILE @@ -1939,7 +1937,6 @@ CONFIG_ST_SMI CONFIG_SUNXI_GPIO CONFIG_SUNXI_MAX_FB_SIZE CONFIG_SUPERH_ON_CHIP_R8A66597 -CONFIG_SUPPORT_EMMC_BOOT CONFIG_SUVD3 CONFIG_SXNI855T CONFIG_SYSFLAGS_ADDR diff --git a/tools/Makefile b/tools/Makefile index 12a3027e23..eadeba417d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -272,6 +272,7 @@ subdir- += env ifneq ($(CROSS_BUILD_TOOLS),) override HOSTCC = $(CC) +override HOSTCFLAGS = $(CFLAGS) quiet_cmd_crosstools_strip = STRIP $^ cmd_crosstools_strip = $(STRIP) $^; touch $@ diff --git a/tools/kwbimage.c b/tools/kwbimage.c index dffaf9043a..b8f8d38212 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -701,7 +701,7 @@ int kwb_verify(RSA *key, void *data, int datasz, struct sig_v1 *sig, goto err_ctx; } - if (!EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key)) { + if (EVP_VerifyFinal(ctx, sig->sig, sizeof(sig->sig), evp_key) != 1) { ret = openssl_err("Could not verify signature"); goto err_ctx; } |