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Diffstat (limited to 'README')
-rw-r--r-- | README | 51 |
1 files changed, 0 insertions, 51 deletions
@@ -363,68 +363,17 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base. - CONFIG_SYS_FSL_DDRC_GEN1 - Freescale DDR1 controller. - - CONFIG_SYS_FSL_DDRC_GEN2 - Freescale DDR2 controller. - - CONFIG_SYS_FSL_DDRC_GEN3 - Freescale DDR3 controller. - - CONFIG_SYS_FSL_DDRC_GEN4 - Freescale DDR4 controller. - - CONFIG_SYS_FSL_DDRC_ARM_GEN3 - Freescale DDR3 controller for ARM-based SoCs. - - CONFIG_SYS_FSL_DDR1 - Board config to use DDR1. It can be enabled for SoCs with - Freescale DDR1 or DDR2 controllers, depending on the board - implemetation. - - CONFIG_SYS_FSL_DDR2 - Board config to use DDR2. It can be enabled for SoCs with - Freescale DDR2 or DDR3 controllers, depending on the board - implementation. - - CONFIG_SYS_FSL_DDR3 - Board config to use DDR3. It can be enabled for SoCs with - Freescale DDR3 or DDR3L controllers. - - CONFIG_SYS_FSL_DDR3L - Board config to use DDR3L. It can be enabled for SoCs with - DDR3L controllers. - CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller). - CONFIG_SYS_FSL_DDR_BE - Defines the DDR controller register space as Big Endian - - CONFIG_SYS_FSL_DDR_LE - Defines the DDR controller register space as Little Endian - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. - CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS - Number of controllers used as main memory. - - CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS - Number of controllers used for other than main memory. - - CONFIG_SYS_FSL_SEC_BE - Defines the SEC controller register space as Big Endian - - CONFIG_SYS_FSL_SEC_LE - Defines the SEC controller register space as Little Endian - - MIPS CPU options: CONFIG_XWAY_SWAP_BYTES |