diff options
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d856..4d46587214 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -560,14 +593,14 @@ config SYS_FSL_EC1 bool help Ethernet controller 1, this is connected to - MAC17 for LX2160A or to MAC3 for other SoCs + MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs Provides DPAA2 capabilities config SYS_FSL_EC2 bool help Ethernet controller 2, this is connected to - MAC18 for LX2160A or to MAC4 for other SoCs + MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs Provides DPAA2 capabilities config SYS_FSL_ERRATUM_A008336 |