diff options
Diffstat (limited to 'arch/arm/dts/k3-am642-sk-u-boot.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-am642-sk-u-boot.dtsi | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi index dda2c5d18a..69dbe943bd 100644 --- a/arch/arm/dts/k3-am642-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi @@ -14,32 +14,32 @@ }; memory@80000000 { - u-boot,dm-spl; + bootph-pre-ram; }; }; &cbass_main{ - u-boot,dm-spl; + bootph-pre-ram; timer1: timer@2400000 { compatible = "ti,omap5430-timer"; reg = <0x0 0x2400000 0x0 0x80>; ti,timer-alwon; clock-frequency = <200000000>; - u-boot,dm-spl; + bootph-pre-ram; }; }; &main_conf { - u-boot,dm-spl; + bootph-pre-ram; chipid@14 { - u-boot,dm-spl; + bootph-pre-ram; }; }; &main_pmx0 { - u-boot,dm-spl; + bootph-pre-ram; main_i2c0_pins_default: main-i2c0-pins-default { - u-boot,dm-spl; + bootph-pre-ram; pinctrl-single,pins = < AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */ @@ -48,7 +48,7 @@ }; &main_i2c0 { - u-boot,dm-spl; + bootph-pre-ram; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; @@ -116,48 +116,48 @@ }; &main_uart0 { - u-boot,dm-spl; + bootph-pre-ram; }; &dmss { - u-boot,dm-spl; + bootph-pre-ram; }; &secure_proxy_main { - u-boot,dm-spl; + bootph-pre-ram; }; &dmsc { - u-boot,dm-spl; + bootph-pre-ram; k3_sysreset: sysreset-controller { compatible = "ti,sci-sysreset"; - u-boot,dm-spl; + bootph-pre-ram; }; }; &k3_pds { - u-boot,dm-spl; + bootph-pre-ram; }; &k3_clks { - u-boot,dm-spl; + bootph-pre-ram; }; &k3_reset { - u-boot,dm-spl; + bootph-pre-ram; }; &sdhci0 { status = "disabled"; - u-boot,dm-spl; + bootph-pre-ram; }; &sdhci1 { - u-boot,dm-spl; + bootph-pre-ram; }; &main_mmc1_pins_default { - u-boot,dm-spl; + bootph-pre-ram; }; &cpsw3g { @@ -165,49 +165,49 @@ <0x0 0x43000200 0x0 0x8>; reg-names = "cpsw_nuss", "mac_efuse"; /delete-property/ ranges; - u-boot,dm-spl; + bootph-pre-ram; cpsw-phy-sel@04044 { compatible = "ti,am64-phy-gmii-sel"; reg = <0x0 0x43004044 0x0 0x8>; - u-boot,dm-spl; + bootph-pre-ram; }; ethernet-ports { - u-boot,dm-spl; + bootph-pre-ram; }; }; &cpsw_port2 { - u-boot,dm-spl; + bootph-pre-ram; }; &main_bcdma { - u-boot,dm-spl; + bootph-pre-ram; }; &main_pktdma { - u-boot,dm-spl; + bootph-pre-ram; }; &rgmii1_pins_default { - u-boot,dm-spl; + bootph-pre-ram; }; &rgmii2_pins_default { - u-boot,dm-spl; + bootph-pre-ram; }; &mdio1_pins_default { - u-boot,dm-spl; + bootph-pre-ram; }; &cpsw3g_phy1 { - u-boot,dm-spl; + bootph-pre-ram; }; &main_usb0_pins_default { - u-boot,dm-spl; + bootph-pre-ram; }; &serdes_ln_ctrl { @@ -215,26 +215,26 @@ }; &usbss0 { - u-boot,dm-spl; + bootph-pre-ram; }; &usb0 { dr_mode = "host"; - u-boot,dm-spl; + bootph-pre-ram; }; &serdes_wiz0 { - u-boot,dm-spl; + bootph-pre-ram; }; &serdes0_usb_link { - u-boot,dm-spl; + bootph-pre-ram; }; &serdes0 { - u-boot,dm-spl; + bootph-pre-ram; }; &serdes_refclk { - u-boot,dm-spl; + bootph-pre-ram; }; |