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Diffstat (limited to 'arch/arm/dts/socfpga_agilex-u-boot.dtsi')
-rw-r--r--arch/arm/dts/socfpga_agilex-u-boot.dtsi20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
index 08f7cf7f7a..4d7680455b 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi
@@ -11,22 +11,22 @@
memory {
#address-cells = <2>;
#size-cells = <2>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
soc {
- u-boot,dm-pre-reloc;
+ bootph-all;
ccu: cache-controller@f7000000 {
compatible = "arteris,ncore-ccu";
reg = <0xf7000000 0x100900>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
};
};
&clkmgr {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&gmac1 {
@@ -66,13 +66,13 @@
};
&qspi {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&rst {
compatible = "altr,rst-mgr";
altr,modrst-offset = <0x20>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sdr {
@@ -81,18 +81,18 @@
<0xf8010000 0x190>,
<0xf8011000 0x500>;
resets = <&rst DDRSCH_RESET>;
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&sysmgr {
compatible = "altr,sys-mgr", "syscon";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&uart0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};
&watchdog0 {
- u-boot,dm-pre-reloc;
+ bootph-all;
};