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Diffstat (limited to 'arch/arm/dts/zynq-cse-nand.dts')
-rw-r--r--arch/arm/dts/zynq-cse-nand.dts10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/dts/zynq-cse-nand.dts b/arch/arm/dts/zynq-cse-nand.dts
index 27adfb9216..18f627f3d7 100644
--- a/arch/arm/dts/zynq-cse-nand.dts
+++ b/arch/arm/dts/zynq-cse-nand.dts
@@ -28,11 +28,11 @@
dcc: dcc {
compatible = "arm,dcc";
status = "disabled";
- u-boot,dm-pre-reloc;
+ bootph-all;
};
amba: amba {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -54,14 +54,14 @@
};
slcr: slcr@f8000000 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
- u-boot,dm-pre-reloc;
+ bootph-all;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
clock-output-names = "armpll", "ddrpll",
@@ -88,7 +88,7 @@
};
scutimer: timer@f8f00600 {
- u-boot,dm-pre-reloc;
+ bootph-all;
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
clock-frequency = <333333333>;