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Diffstat (limited to 'arch/arm/include/asm/arch-mx7ulp/imx-regs.h')
-rw-r--r--arch/arm/include/asm/arch-mx7ulp/imx-regs.h20
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index 63b02de087..3c82e9921e 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -10,6 +10,8 @@
#define ARCH_MXC
+#define ROM_SW_INFO_ADDR 0x000001E8
+
#define CAAM_SEC_SRAM_BASE (0x26000000)
#define CAAM_SEC_SRAM_SIZE (SZ_32K)
#define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1)
@@ -56,6 +58,7 @@
#define USDHC1_AIPS2_SLOT (56)
#define RGPIO2P0_AIPS0_SLOT (15)
#define RGPIO2P1_AIPS2_SLOT (15)
+#define SNVS_AIPS2_SLOT (35)
#define IOMUXC0_AIPS0_SLOT (61)
#define OCOTP_CTRL_AIPS1_SLOT (38)
#define OCOTP_CTRL_PCC1_SLOT (38)
@@ -175,6 +178,9 @@
#define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT)))
#define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT)))
+#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT)))
+#define SNVS_LP_LPCR (SNVS_BASE + 0x38)
+
#define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT)))
#define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT)))
@@ -937,6 +943,9 @@
#define MMDC_MPWRDQBY3DL_WR_DQ25_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ25_DEL))
#define MMDC_MPWRDQBY3DL_WR_DQ24_DEL_MASK ((0x3f << MMDC_MPWRDQBY3DL_WR_DQ24_DEL))
+#define SNVS_LPCR_DPEN (0x20)
+#define SNVS_LPCR_SRTC_ENV (0x1)
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
@@ -1112,6 +1121,17 @@ struct usbphy_regs {
u32 usb1_pfda_ctrl1_tog; /* 0x14c */
};
+struct bootrom_sw_info {
+ u8 reserved_1;
+ u8 boot_dev_instance;
+ u8 boot_dev_type;
+ u8 reserved_2;
+ u32 core_freq;
+ u32 axi_freq;
+ u32 ddr_freq;
+ u32 rom_tick_freq;
+ u32 reserved_3[3];
+};
#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
#define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140)