diff options
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/soc.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/soc.c | 180 |
1 files changed, 15 insertions, 165 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 29f7d5be02..c5e20408c6 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -11,6 +11,7 @@ #include <asm/mach-imx/boot_mode.h> #include <efi_loader.h> #include <spl.h> +#include <asm/arch/rdc.h> #include <asm/arch/s400_api.h> #include <asm/arch/mu_hal.h> #include <cpu_func.h> @@ -344,180 +345,29 @@ static void set_core0_reset_vector(u32 entry) setbits_le32(SIM1_BASE_ADDR + 0x8, (0x1 << 26)); } -enum rdc_type { - RDC_TRDC, - RDC_XRDC, -}; - -static int release_rdc(enum rdc_type type) -{ - ulong s_mu_base = 0x27020000UL; - struct imx8ulp_s400_msg msg; - int ret; - u32 rdc_id = (type == RDC_XRDC) ? 0x78 : 0x74; - - msg.version = AHAB_VERSION; - msg.tag = AHAB_CMD_TAG; - msg.size = 2; - msg.command = AHAB_RELEASE_RDC_REQ_CID; - msg.data[0] = (rdc_id << 8) | 0x2; /* A35 XRDC */ - - mu_hal_init(s_mu_base); - mu_hal_sendmsg(s_mu_base, 0, *((u32 *)&msg)); - mu_hal_sendmsg(s_mu_base, 1, msg.data[0]); - - ret = mu_hal_receivemsg(s_mu_base, 0, (u32 *)&msg); - if (!ret) { - ret = mu_hal_receivemsg(s_mu_base, 1, &msg.data[0]); - if (!ret) { - if ((msg.data[0] & 0xff) == 0xd6) - return 0; - } - - return -EIO; - } - - return ret; -} - -struct mbc_mem_dom { - u32 mem_glbcfg[4]; - u32 nse_blk_index; - u32 nse_blk_set; - u32 nse_blk_clr; - u32 nsr_blk_clr_all; - u32 memn_glbac[8]; - /* The upper only existed in the beginning of each MBC */ - u32 mem0_blk_cfg_w[64]; - u32 mem0_blk_nse_w[16]; - u32 mem1_blk_cfg_w[8]; - u32 mem1_blk_nse_w[2]; - u32 mem2_blk_cfg_w[8]; - u32 mem2_blk_nse_w[2]; - u32 mem3_blk_cfg_w[8]; - u32 mem3_blk_nse_w[2];/*0x1F0, 0x1F4 */ - u32 reserved[2]; -}; - -struct trdc { - u8 res0[0x1000]; - struct mbc_mem_dom mem_dom[4][8]; -}; - -/* MBC[m]_[d]_MEM[s]_BLK_CFG_W[w] */ -int trdc_mbc_set_access(u32 mbc_x, u32 dom_x, u32 mem_x, u32 blk_x, u32 perm) -{ - struct trdc *trdc_base = (struct trdc *)0x28031000U; - struct mbc_mem_dom *mbc_dom; - u32 *cfg_w, *nse_w; - u32 index, offset, val; - - mbc_dom = &trdc_base->mem_dom[mbc_x][dom_x]; - - switch (mem_x) { - case 0: - cfg_w = &mbc_dom->mem0_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem0_blk_nse_w[blk_x / 32]; - break; - case 1: - cfg_w = &mbc_dom->mem1_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem1_blk_nse_w[blk_x / 32]; - break; - case 2: - cfg_w = &mbc_dom->mem2_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem2_blk_nse_w[blk_x / 32]; - break; - case 3: - cfg_w = &mbc_dom->mem3_blk_cfg_w[blk_x / 8]; - nse_w = &mbc_dom->mem3_blk_nse_w[blk_x / 32]; - break; - default: - return -EINVAL; - }; - - index = blk_x % 8; - offset = index * 4; - - val = readl((void __iomem *)cfg_w); - - val &= ~(0xFU << offset); - - if (perm == 0x7700) { - val |= (0x0 << offset); - writel(perm, (void __iomem *)cfg_w); - } else if (perm == 0x0077) { - val |= (0x8 << offset); /* nse bit set */ - writel(val, (void __iomem *)cfg_w); - } else { - return -EINVAL; - } - - return 0; -} - -int trdc_set_access(void) +static int trdc_set_access(void) { /* - * CGC0: PBridge0 slot 47 - * trdc_mbc_set_access(2, 7, 0, 47, 0x7700); - * For secure access, default single boot already support, - * For non-secure access, need add in future per usecase. + * TRDC mgr + 4 MBC + 2 MRC. + * S400 should already configure when release RDC + * A35 only map non-secure region for pbridge0 and 1, set sec_access to false */ - trdc_mbc_set_access(2, 7, 0, 49, 0x7700); - trdc_mbc_set_access(2, 7, 0, 50, 0x7700); - trdc_mbc_set_access(2, 7, 0, 51, 0x7700); - trdc_mbc_set_access(2, 7, 0, 52, 0x7700); + trdc_mbc_set_access(2, 7, 0, 49, false); + trdc_mbc_set_access(2, 7, 0, 50, false); + trdc_mbc_set_access(2, 7, 0, 51, false); + trdc_mbc_set_access(2, 7, 0, 52, false); + trdc_mbc_set_access(2, 7, 0, 53, false); + trdc_mbc_set_access(2, 7, 0, 54, false); - trdc_mbc_set_access(2, 7, 0, 47, 0x0077); + /* CGC0: PBridge0 slot 47 */ + trdc_mbc_set_access(2, 7, 0, 47, false); - /* iomuxc 0 */ - trdc_mbc_set_access(2, 7, 1, 33, 0x7700); + /* Iomuxc0: : PBridge1 slot 33 */ + trdc_mbc_set_access(2, 7, 1, 33, false); return 0; } -static void xrdc_mrc_region_set_access(int mrc_index, u32 addr, u32 access) -{ - ulong xrdc_base = 0x292f0000, off; - u32 mrgd[5]; - u8 mrcfg, j, region_num; - u8 dsel; - - mrcfg = readb(xrdc_base + 0x140 + mrc_index); - region_num = mrcfg & 0x1f; - - for (j = 0; j < region_num; j++) { - off = 0x2000 + mrc_index * 0x200 + j * 0x20; - - mrgd[0] = readl(xrdc_base + off); - mrgd[1] = readl(xrdc_base + off + 4); - mrgd[2] = readl(xrdc_base + off + 8); - mrgd[3] = readl(xrdc_base + off + 0xc); - mrgd[4] = readl(xrdc_base + off + 0x10); - - debug("MRC [%u][%u]\n", mrc_index, j); - debug("0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", - mrgd[0], mrgd[1], mrgd[2], mrgd[3], mrgd[4]); - - /* hit */ - if (addr >= mrgd[0] && addr <= mrgd[1]) { - /* find domain 7 DSEL */ - dsel = (mrgd[2] >> 21) & 0x7; - if (dsel == 1) { - mrgd[4] &= ~0xFFF; - mrgd[4] |= (access & 0xFFF); - } else if (dsel == 2) { - mrgd[4] &= ~0xFFF0000; - mrgd[4] |= ((access & 0xFFF) << 16); - } - - /* not handle other cases, since S400 only set ACCESS1 and 2 */ - writel(mrgd[4], xrdc_base + off + 0x10); - return; - } - } -} - int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { |