diff options
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/boot_mode.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/px30/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/mach-rockchip/rk3568/rk3568.c | 27 |
4 files changed, 35 insertions, 4 deletions
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index da6871eb18..d840c59d45 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -261,6 +261,8 @@ config ROCKCHIP_RK3399 config ROCKCHIP_RK3568 bool "Support Rockchip RK3568" select ARM64 + select SUPPORT_SPL + select SPL select CLK select PINCTRL select RAM diff --git a/arch/arm/mach-rockchip/boot_mode.c b/arch/arm/mach-rockchip/boot_mode.c index 2158934159..1a1a887fc2 100644 --- a/arch/arm/mach-rockchip/boot_mode.c +++ b/arch/arm/mach-rockchip/boot_mode.c @@ -95,7 +95,7 @@ int setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: debug("%s: enter fastboot!\n", __func__); - env_set("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb 0"); break; case BOOT_UMS: debug("%s: enter UMS!\n", __func__); diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index aa5cc471ee..145bf3591f 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -27,6 +27,14 @@ config TARGET_PX30_CORE * PX30.Core needs to mount on top of CTOUCH2.0 for creating complete PX30.Core C.TOUCH Carrier board. + PX30.Core CTOUCH2-OF10: + * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. + * CTOUCH2.0 is a general purpose Carrier board with capacitive + touch interface support. + * 10.1" OF is a capacitive touch 10.1" Open Frame panel solutions. + * PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged + 10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame. + config ROCKCHIP_BOOT_MODE_REG default 0xff010200 diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c index 973b4f9dcb..22eeb77d41 100644 --- a/arch/arm/mach-rockchip/rk3568/rk3568.c +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c @@ -11,9 +11,18 @@ #include <asm/arch-rockchip/hardware.h> #include <dt-bindings/clock/rk3568-cru.h> -#define PMUGRF_BASE 0xfdc20000 -#define GRF_BASE 0xfdc60000 - +#define PMUGRF_BASE 0xfdc20000 +#define GRF_BASE 0xfdc60000 +#define GRF_GPIO1B_DS_2 0x218 +#define GRF_GPIO1B_DS_3 0x21c +#define GRF_GPIO1C_DS_0 0x220 +#define GRF_GPIO1C_DS_1 0x224 +#define GRF_GPIO1C_DS_2 0x228 +#define GRF_GPIO1C_DS_3 0x22c +#define SGRF_BASE 0xFDD18000 +#define SGRF_SOC_CON4 0x10 +#define EMMC_HPROT_SECURE_CTRL 0x03 +#define SDMMC0_HPROT_SECURE_CTRL 0x01 /* PMU_GRF_GPIO0D_IOMUX_L */ enum { GPIO0D1_SHIFT = 4, @@ -81,5 +90,17 @@ void board_debug_uart_init(void) int arch_cpu_init(void) { +#ifdef CONFIG_SPL_BUILD + /* Set the emmc sdmmc0 to secure */ + rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11 + | SDMMC0_HPROT_SECURE_CTRL << 4)); + /* set the emmc driver strength to level 2 */ + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2); + writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3); +#endif return 0; } |