diff options
Diffstat (limited to 'arch/arm')
102 files changed, 656 insertions, 363 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b5bd3284cd..f0fd57f8d6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -9,9 +9,9 @@ config ARM64 select PHYS_64BIT select SYS_CACHE_SHIFT_6 -if ARM64 config POSITION_INDEPENDENT bool "Generate position-independent pre-relocation code" + depends on ARM64 || CPU_V7A help U-Boot expects to be linked to a specific hard-coded address, and to be loaded to and run from that address. This option lifts that @@ -22,6 +22,7 @@ config POSITION_INDEPENDENT config INIT_SP_RELATIVE bool "Specify the early stack pointer relative to the .bss section" + depends on ARM64 default n if ARCH_QEMU default y if POSITION_INDEPENDENT help @@ -37,6 +38,7 @@ config INIT_SP_RELATIVE config SYS_INIT_SP_BSS_OFFSET int "Early stack offset from the .bss base address" + depends on ARM64 depends on INIT_SP_RELATIVE default 524288 help @@ -46,6 +48,7 @@ config SYS_INIT_SP_BSS_OFFSET do not overlap any appended DTB. config LINUX_KERNEL_IMAGE_HEADER + depends on ARM64 bool help Place a Linux kernel image header at the start of the U-Boot binary. @@ -54,14 +57,18 @@ config LINUX_KERNEL_IMAGE_HEADER image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but which isn't part of the binary. -if LINUX_KERNEL_IMAGE_HEADER config LNX_KRNL_IMG_TEXT_OFFSET_BASE + depends on LINUX_KERNEL_IMAGE_HEADER hex help The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the TEXT_OFFSET value written to the Linux kernel image header. -endif -endif + +config GICV2 + bool + +config GICV3 + bool config GIC_V3_ITS bool "ARM GICV3 ITS" @@ -104,7 +111,6 @@ config THUMB2_KERNEL config SYS_ICACHE_OFF bool "Do not enable icache" - default n help Do not enable instruction cache in U-Boot. @@ -117,7 +123,6 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" - default n help Do not enable data cache in U-Boot. @@ -332,21 +337,6 @@ config SYS_ARM_ARCH default 4 if CPU_SA1100 default 8 if ARM64 -config SYS_CACHE_SHIFT_5 - bool - -config SYS_CACHE_SHIFT_6 - bool - -config SYS_CACHE_SHIFT_7 - bool - -config SYS_CACHELINE_SIZE - int - default 128 if SYS_CACHE_SHIFT_7 - default 64 if SYS_CACHE_SHIFT_6 - default 32 if SYS_CACHE_SHIFT_5 - choice prompt "Select the ARM data write cache policy" default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \ @@ -452,7 +442,6 @@ config ENABLE_ARM_SOC_BOOT0_HOOK config ARM_CORTEX_CPU_IS_UP bool - default n config USE_ARCH_MEMCPY bool "Use an assembly optimized implementation of memcpy" @@ -723,6 +712,7 @@ config ARCH_KEYSTONE bool "TI Keystone" select CMD_POWEROFF select CPU_V7A + select DDR_SPD select GPIO_EXTRA_HEADER select SUPPORT_SPL select SYS_ARCH_TIMER @@ -787,6 +777,7 @@ config ARCH_IMX8 select ARM64 select DM select GPIO_EXTRA_HEADER + select MACH_IMX select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK @@ -794,9 +785,11 @@ config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE + select SYS_I2C_MXC select DM select SUPPORT_SPL imply CMD_DM @@ -805,6 +798,7 @@ config ARCH_IMX8ULP bool "NXP i.MX8ULP platform" select ARM64 select DM + select MACH_IMX select OF_CONTROL select SUPPORT_SPL select GPIO_EXTRA_HEADER @@ -816,6 +810,7 @@ config ARCH_IMXRT select DM select DM_SERIAL select GPIO_EXTRA_HEADER + select MACH_IMX select SUPPORT_SPL imply CMD_DM @@ -823,6 +818,7 @@ config ARCH_MX23 bool "NXP i.MX23 family" select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select MACH_IMX select PL011_SERIAL select SUPPORT_SPL @@ -830,6 +826,7 @@ config ARCH_MX25 bool "NXP MX25" select CPU_ARM926EJS select GPIO_EXTRA_HEADER + select MACH_IMX imply MXC_GPIO config ARCH_MX28 @@ -837,17 +834,20 @@ config ARCH_MX28 select CPU_ARM926EJS select GPIO_EXTRA_HEADER select PL011_SERIAL + select MACH_IMX select SUPPORT_SPL config ARCH_MX31 bool "NXP i.MX31 family" select CPU_ARM1136 select GPIO_EXTRA_HEADER + select MACH_IMX config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -860,6 +860,7 @@ config ARCH_MX7 select ARCH_MISC_INIT select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC if IMX_HAB select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -871,6 +872,7 @@ config ARCH_MX6 bool "Freescale MX6" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE @@ -887,6 +889,7 @@ config ARCH_MX5 select BOARD_EARLY_INIT_F select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX imply MXC_GPIO config ARCH_NEXELL @@ -952,6 +955,7 @@ config ARCH_SOCFPGA select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL + select GICV2 select GPIO_EXTRA_HEADER select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select OF_CONTROL @@ -962,7 +966,7 @@ config ARCH_SOCFPGA select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG select SUPPORT_SPL @@ -982,11 +986,11 @@ config ARCH_SOCFPGA imply SPL_DM_SPI imply SPL_DM_SPI_FLASH imply SPL_LIBDISK_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE imply SPL_SPI_FLASH_SUPPORT - imply SPL_SPI_SUPPORT + imply SPL_SPI imply L2X0_CACHE config ARCH_SUNXI @@ -1032,9 +1036,9 @@ config ARCH_SUNXI imply SPL_GPIO imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT if MMC + imply SPL_MMC if MMC imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply USB_GADGET config ARCH_U8500 @@ -1044,14 +1048,22 @@ config ARCH_U8500 select DM_GPIO select DM_MMC if MMC select DM_SERIAL + select DM_USB_GADGET if DM_USB select OF_CONTROL select SYSRESET select TIMER + imply AB8500_USB_PHY imply ARM_PL180_MMCI + imply CLK + imply DM_PMIC imply DM_RTC + imply NOMADIK_GPIO imply NOMADIK_MTU_TIMER + imply PHY imply PL01X_SERIAL + imply PMIC_AB8500 imply RTC_PL031 + imply SYS_THUMB_BUILD imply SYSRESET_SYSCON config ARCH_VERSAL @@ -1062,6 +1074,7 @@ config ARCH_VERSAL select DM_ETH if NET select DM_MMC if MMC select DM_SERIAL + select GICV3 select GPIO_EXTRA_HEADER select OF_CONTROL select SOC_DEVICE @@ -1072,6 +1085,7 @@ config ARCH_VF610 bool "Freescale Vybrid" select CPU_V7A select GPIO_EXTRA_HEADER + select MACH_IMX select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS imply MTD_RAW_NAND @@ -1131,6 +1145,7 @@ config ARCH_ZYNQMP select DM_SPI if SPI select DM_SPI_FLASH if DM_SPI select FIRMWARE + select GICV2 select GPIO_EXTRA_HEADER select OF_CONTROL select SPL_BOARD_INIT if SPL @@ -1880,6 +1895,7 @@ config TARGET_DURIAN config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 + select GICV2 config TARGET_XENGUEST_ARM64 bool "Xen guest ARM64" @@ -1891,13 +1907,56 @@ config TARGET_XENGUEST_ARM64 select SSCANF endchoice +config SUPPORT_PASSING_ATAGS + bool "Support pre-devicetree ATAG-based booting" + depends on !ARM64 + imply SETUP_MEMORY_TAGS + help + Support for booting older Linux kernels, using ATAGs rather than + passing a devicetree. This is option is rarely used, and the + semantics are defined at + https://www.kernel.org/doc/Documentation/arm/Booting at section 4a. + +config SETUP_MEMORY_TAGS + bool "Pass memory size information via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config CMDLINE_TAG + bool "Pass Linux kernel cmdline via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config INITRD_TAG + bool "Pass initrd starting point and size via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config REVISION_TAG + bool "Pass system revision via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config SERIAL_TAG + bool "Pass system serial number via ATAG" + depends on SUPPORT_PASSING_ATAGS + +config STATIC_MACH_TYPE + bool "Statically define the Machine ID number" + help + When booting via ATAGs, enable this option if we know the correct + machine ID number to use at compile time. Some systems will be + passed the number dynamically by whatever loads U-Boot. + +config MACH_TYPE + int "Machine ID number" + depends on STATIC_MACH_TYPE + help + When booting via ATAGs, the machine type must be passed as a number. + For the full list see https://www.arm.linux.org.uk/developer/machines + config ARCH_SUPPORT_TFABOOT bool config TFABOOT bool "Support for booting from TF-A" depends on ARCH_SUPPORT_TFABOOT - default n help Some platforms support the setup of secure registers (for instance for CPU errata handling) or provide secure services like PSCI. diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 16c63e1266..b107b1af27 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -25,6 +25,7 @@ endif PLATFORM_RELFLAGS += -fno-common -ffixed-r9 PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \ + $(call cc-option,-mgeneral-regs-only) \ $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) # LLVM support @@ -158,7 +159,8 @@ ifdef CONFIG_EFI_LOADER OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel endif -ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_MACH_IMX +ifneq ($(CONFIG_IMX_CONFIG),"") ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD INPUTS-y += SPL @@ -174,6 +176,7 @@ ifneq ($(CONFIG_VF610),) INPUTS-y += u-boot.vyb endif endif +endif EFI_LDS := elf_arm_efi.lds EFI_CRT0 := crt0_arm_efi.o diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index da7278e59f..4bc27f6373 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -39,7 +39,7 @@ reset: msr cpsr,r0 /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -62,7 +62,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -81,7 +81,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Jump to board specific initialization... The Mask ROM will have already initialized * basic memory. Go here to bump up clock rate and handle wake up conditions. @@ -91,4 +91,4 @@ cpu_init_crit: mov lr, ip /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index ecb4e44fd8..9ad1f03142 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -37,8 +37,8 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif @@ -62,8 +62,8 @@ c_runtime_cpu_setup: ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) cpu_init_crit: mov ip, lr @@ -76,4 +76,4 @@ cpu_init_crit: mov lr, ip mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e2b5f2bff4..02cbda9d22 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -53,7 +53,7 @@ copyex: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -78,7 +78,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -97,7 +97,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will @@ -109,4 +109,4 @@ cpu_init_crit: mov lr, ip #endif mov pc, lr -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 0a8985b90a..763d79e803 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; static gd_t gdata __section(".data"); -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL static struct bd_info bdata __section(".data"); #endif @@ -108,7 +108,7 @@ static void mxs_spl_fixup_vectors(void) static void mxs_spl_console_init(void) { -#ifdef CONFIG_SPL_SERIAL_SUPPORT +#ifdef CONFIG_SPL_SERIAL gd->bd = &bdata; gd->baudrate = CONFIG_BAUDRATE; serial_init(); diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index ff592ba810..0afcc47aad 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -46,7 +46,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -69,7 +69,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush D cache before disabling it @@ -100,7 +100,7 @@ flush_dcache: #endif mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ @@ -109,4 +109,4 @@ flush_dcache: mov lr, r4 /* restore link */ #endif mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 0ec340b1a6..2d5186774a 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -45,7 +45,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -70,7 +70,7 @@ c_runtime_cpu_setup: */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) cpu_init_crit: /* * flush v4 I/D caches @@ -89,7 +89,7 @@ cpu_init_crit: orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ mcr p15, 0, r0, c1, c0, 0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * Go setup Memory and board specific bits prior to relocation. */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0e83e394d5..bfbd85ae64 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o endif -ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) +ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 747059b56a..f919d02db4 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -20,6 +20,7 @@ config ARCH_LS1021A select SYS_FSL_SEC_LE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES + select SYS_I2C_MXC imply CMD_PCI imply SCSI imply SCSI_AHCI diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 940995ef5a..984ae8b87b 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -42,8 +42,8 @@ void get_sys_info(struct sys_info *sys_info) unsigned long sysclk = CONFIG_SYS_CLK_FREQ; sys_info->freq_systembus = sysclk; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c index 308536c336..a194968623 100644 --- a/arch/arm/cpu/armv7/ls102xa/spl.c +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -8,7 +8,7 @@ u32 spl_boot_device(void) { -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif return BOOT_DEVICE_NAND; diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index dcb4195d7b..698e15b8e1 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -39,6 +39,42 @@ reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_POSITION_INDEPENDENT + /* + * Fix .rela.dyn relocations. This allows U-Boot to loaded to and + * executed at a different address than it was linked at. + */ +pie_fixup: + adr r0, reset /* r0 <- Runtime value of reset label */ + ldr r1, =reset /* r1 <- Linked value of reset label */ + subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */ + beq pie_fixup_done + + adr r0, pie_fixup + ldr r1, _rel_dyn_start_ofs + add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */ + +pie_fix_loop: + ldr r0, [r2] /* r0 <- Link location */ + ldr r1, [r2, #4] /* r1 <- fixup */ + cmp r1, #23 /* relative fixup? */ + bne pie_skip_reloc + + /* relative fix: increase location by offset */ + add r0, r4 + ldr r1, [r0] + add r1, r4 + str r1, [r0] + str r0, [r2] + add r2, #8 +pie_skip_reloc: + cmp r2, r3 + blo pie_fix_loop +pie_fixup_done: +#endif + #ifdef CONFIG_ARMV7_LPAE /* * check for Hypervisor support @@ -80,11 +116,11 @@ switch_to_hypervisor_ret: #endif /* the mask ROM code should have PLL and others stable */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #ifdef CONFIG_CPU_V7A bl cpu_init_cp15 #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) bl cpu_init_crit #endif #endif @@ -320,8 +356,8 @@ skip_errata_801819: mov pc, r5 @ back to my caller ENDPROC(cpu_init_cp15) -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /************************************************************************* * * CPU_init_critical registers @@ -340,3 +376,10 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif + +#if CONFIG_POSITION_INDEPENDENT +_rel_dyn_start_ofs: + .word __rel_dyn_start - pie_fixup +_rel_dyn_end_ofs: + .word __rel_dyn_end - pie_fixup +#endif diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index b7a10a8e34..0a3fdfa471 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -3,7 +3,6 @@ if ARM64 config ARMV8_SPL_EXCEPTION_VECTORS bool "Install crash dump exception vectors" depends on SPL - default n help The default exception vector table is only used for the crash dump, but still takes quite a lot of space in the image size. @@ -128,7 +127,6 @@ config PSCI_RESET config ARMV8_PSCI bool "Enable PSCI support" if EXPERT - default n help PSCI is Power State Coordination Interface defined by ARM. The PSCI in U-boot provides a general framework and each platform @@ -156,7 +154,6 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER config ARMV8_EA_EL3_FIRST bool "External aborts and SError interrupt exception are taken in EL3" - default n help Exception handling at all exception levels for External Abort and SError interrupt exception are taken in EL3. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9cef363fba..1e166c73e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -4,6 +4,8 @@ config ARCH_LS1012A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR_BE @@ -25,6 +27,7 @@ config ARCH_LS1028A select ARMV8_SET_SMPEN select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 select SYS_FSL_SRDS_1 @@ -58,7 +61,9 @@ config ARCH_LS1043A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -84,13 +89,16 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C imply CMD_PCI + imply ID_EEPROM config ARCH_LS1046A bool select ARMV8_SET_SMPEN select FSL_LAYERSCAPE select FSL_LSCH2 + select GICV2 select HAS_FSL_XHCI_USB if USB_HOST + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -117,8 +125,10 @@ config ARCH_LS1046A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + imply ID_EEPROM imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config ARCH_LS1088A bool @@ -126,6 +136,8 @@ config ARCH_LS1088A select ARM_ERRATA_855873 if !TFABOOT select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -158,7 +170,9 @@ config ARCH_LS1088A select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS + imply ID_EEPROM imply SCSI + imply SPL_SYS_I2C_LEGACY imply PANIC_HANG config ARCH_LS2080A @@ -170,6 +184,8 @@ config ARCH_LS2080A select ARM_ERRATA_833471 select FSL_LAYERSCAPE select FSL_LSCH3 + select GICV3 + select SKIP_LOWLEVEL_INIT select SYS_FSL_SRDS_1 select SYS_HAS_SERDES select SYS_FSL_DDR @@ -210,12 +226,15 @@ config ARCH_LS2080A select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS + imply ID_EEPROM imply PANIC_HANG + imply SPL_SYS_I2C_LEGACY config ARCH_LX2162A bool select ARMV8_SET_SMPEN select FSL_LSCH3 + select GICV3 select NXP_LSCH3_2 select SYS_HAS_SERDES select SYS_FSL_SRDS_1 @@ -242,11 +261,13 @@ config ARCH_LX2162A imply PANIC_HANG imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config ARCH_LX2160A bool select ARMV8_SET_SMPEN select FSL_LSCH3 + select GICV3 select HAS_FSL_XHCI_USB if USB_HOST select NXP_LSCH3_2 select SYS_HAS_SERDES @@ -272,12 +293,15 @@ config ARCH_LX2160A select SYS_I2C_MXC select RESV_RAM if GIC_V3_ITS imply DISTRO_DEFAULTS + imply ID_EEPROM imply PANIC_HANG imply SCSI imply SCSI_AHCI + imply SPL_SYS_I2C_LEGACY config FSL_LSCH2 bool + select SKIP_LOWLEVEL_INIT select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 @@ -429,7 +453,6 @@ config QSPI_AHB_INIT config FSPI_AHB_EN_4BYTE bool "Enable 4-byte Fast Read command for AHB mode" - default n help The default setting for FlexSPI AHB bus just supports 3-byte addressing. But some FlexSPI flash sizes are up to 64MBytes. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 63d34e1ec0..3f97c8aee4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -61,8 +61,8 @@ void get_sys_info(struct sys_info *sys_info) #endif cluster_clk = CONFIG_CLUSTER_CLK_FREQ; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #else sys_info->freq_ddrbus = sysclk; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 25a1c36d2a..6f50cbad2b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -78,10 +78,10 @@ void get_sys_info(struct sys_info *sys_info) void *offset; sys_info->freq_systembus = sysclk; -#ifdef CONFIG_DDR_CLK_FREQ - sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; +#if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ) + sys_info->freq_ddrbus = get_board_ddr_clk(); #ifdef CONFIG_SYS_FSL_HAS_DP_DDR - sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ; + sys_info->freq_ddrbus2 = get_board_ddr_clk(); #endif #else sys_info->freq_ddrbus = sysclk; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 42a0968546..41f3e95019 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -329,7 +329,7 @@ static void erratum_rcw_src(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) u8 __iomem *ptr; #ifdef I2C1_BASE_ADDR ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S index 363ded03e6..d6bd188459 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S @@ -93,7 +93,7 @@ __secondary_boot_func: 4: #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 switch_el x7, _dead_loop, 0f, _dead_loop -0: armv8_switch_to_el1_m x4, x6, x7 +0: armv8_switch_to_el1_m x4, x6, x7, x9 #else switch_el x7, 0f, _dead_loop, _dead_loop 0: armv8_switch_to_el2_m x4, x6, x7 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 1d5e344452..68111b6eff 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC return BOOT_DEVICE_MMC1; #endif #ifdef CONFIG_SPL_NAND_SUPPORT @@ -88,7 +88,7 @@ void board_init_f(ulong dummy) preloader_console_init(); spl_set_bd(); -#ifdef CONFIG_SYS_I2C_LEGACY +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) #ifdef CONFIG_SPL_I2C i2c_init_all(); #endif diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index a31af4ffc8..9dbdff3a4f 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -40,7 +40,7 @@ ENTRY(armv8_switch_to_el1) * now, jump to the address saved in x4. */ br x4 -1: armv8_switch_to_el1_m x4, x5, x6 +1: armv8_switch_to_el1_m x4, x5, x6, x7 ENDPROC(armv8_switch_to_el1) .popsection diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 575abac09c..896e05f1fd 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -45,7 +45,7 @@ reset: orr r0,r0,#0xd3 msr cpsr,r0 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -92,7 +92,7 @@ c_runtime_cpu_setup: * ************************************************************************* */ -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X) cpu_init_crit: /* * flush v4 I/D caches @@ -111,7 +111,7 @@ cpu_init_crit: mcr p15, 0, r0, c1, c0, 0 mov pc, lr /* back to my caller */ -#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */ +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */ /* * Enable MMU to use DCache as DRAM. diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 8eb005309e..2f84f20575 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -39,7 +39,7 @@ reset: * we do sys-critical inits only at reboot, * not when booting from ram! */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) bl cpu_init_crit #endif @@ -95,7 +95,7 @@ cpu_init_crit: ldr r1, cpuspeed str r1, [r0, #PPCR] -#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /* * before relocating, we have to setup RAM timing * because memory timing is board-dependend, you will diff --git a/arch/arm/dts/ste-ab8500.dtsi b/arch/arm/dts/ste-ab8500.dtsi index 14d4d8617d..dcc4a60c0c 100644 --- a/arch/arm/dts/ste-ab8500.dtsi +++ b/arch/arm/dts/ste-ab8500.dtsi @@ -42,15 +42,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH>, + <39 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "HW_CONV_END", "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_tvout_reg>; #address-cells = <1>; @@ -122,9 +122,11 @@ ab8500_temp { compatible = "stericsson,abx500-temp"; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ABX500_TEMP_WARM"; io-channels = <&gpadc 0x06>, <&gpadc 0x07>; - io-channel-name = "aux1", "aux2"; + io-channel-names = "aux1", "aux2"; }; ab8500_battery: ab8500_battery { @@ -134,29 +136,77 @@ ab8500_fg { compatible = "stericsson,ab8500-fg"; - battery = <&ab8500_battery>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; + battery = <&ab8500_battery>; io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; + io-channel-names = "main_bat_v"; }; ab8500_btemp { compatible = "stericsson,ab8500-btemp"; - battery = <&ab8500_battery>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; + battery = <&ab8500_battery>; io-channels = <&gpadc 0x02>, <&gpadc 0x01>; - io-channel-name = "btemp_ball", + io-channel-names = "btemp_ball", "bat_ctrl"; }; ab8500_charger { - compatible = "stericsson,ab8500-charger"; + compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; battery = <&ab8500_battery>; vddadc-supply = <&ab8500_ldo_tvout_reg>; io-channels = <&gpadc 0x03>, <&gpadc 0x0a>, <&gpadc 0x09>, <&gpadc 0x0b>; - io-channel-name = "main_charger_v", + io-channel-names = "main_charger_v", "main_charger_c", "vbus_v", "usb_charger_c"; @@ -167,15 +217,15 @@ battery = <&ab8500_battery>; }; - ab8500_usb { + ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -188,12 +238,13 @@ musb_1v8-supply = <&db8500_vsmps2_reg>; clocks = <&prcmu_clk PRCMU_SYSCLK>; clock-names = "sysclk"; + #phy-cells = <0>; }; ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; @@ -201,7 +252,19 @@ compatible = "stericsson,ab8500-sysctrl"; }; - ab8500-pwm { + ab8500-pwm-1 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-2 { + compatible = "stericsson,ab8500-pwm"; + clocks = <&ab8500_clock AB8500_SYSCLK_INT>; + clock-names = "intclk"; + }; + + ab8500-pwm-3 { compatible = "stericsson,ab8500-pwm"; clocks = <&ab8500_clock AB8500_SYSCLK_INT>; clock-names = "intclk"; @@ -255,8 +318,8 @@ // supplies to the display/camera ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; /* BUG: If turned off MMC will be affected. */ regulator-always-on; @@ -324,5 +387,10 @@ vana-supply = <&ab8500_ldo_ana_reg>; }; }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; }; }; diff --git a/arch/arm/dts/ste-ab8505.dtsi b/arch/arm/dts/ste-ab8505.dtsi index c72aa250bf..a1197fd37e 100644 --- a/arch/arm/dts/ste-ab8505.dtsi +++ b/arch/arm/dts/ste-ab8505.dtsi @@ -13,7 +13,8 @@ <&gpadc 0x08>, /* Main battery voltage */ <&gpadc 0x09>, /* VBUS */ <&gpadc 0x0b>, /* Charger current */ - <&gpadc 0x0c>; /* Backup battery voltage */ + <&gpadc 0x0c>, /* Backup battery voltage */ + <&gpadc 0x0d>; /* Die temperature */ }; soc { @@ -38,16 +39,15 @@ ab8500-rtc { compatible = "stericsson,ab8500-rtc"; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH - 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "60S", "ALARM"; }; gpadc: ab8500-gpadc { compatible = "stericsson,ab8500-gpadc"; - interrupts = <32 IRQ_TYPE_LEVEL_HIGH - 39 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "HW_CONV_END", "SW_CONV_END"; + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "SW_CONV_END"; vddadc-supply = <&ab8500_ldo_adc_reg>; #address-cells = <1>; #size-cells = <0>; @@ -84,42 +84,93 @@ bk_bat_v: channel@0c { reg = <0x0c>; }; + die_temp: channel@0d { + reg = <0x0d>; + }; usb_id: channel@0e { reg = <0x0e>; }; }; ab8500_battery: ab8500_battery { - status = "disabled"; + stericsson,battery-type = "LIPO"; thermistor-on-batctrl; }; ab8500_fg { status = "disabled"; compatible = "stericsson,ab8500-fg"; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>, + <8 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <27 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "NCONV_ACCU", + "BATT_OVV", + "LOW_BAT_F", + "CC_INT_CALIB", + "CCEOC"; battery = <&ab8500_battery>; io-channels = <&gpadc 0x08>; - io-channel-name = "main_bat_v"; + io-channel-names = "main_bat_v"; }; ab8500_btemp { status = "disabled"; compatible = "stericsson,ab8500-btemp"; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>, + <80 IRQ_TYPE_LEVEL_HIGH>, + <83 IRQ_TYPE_LEVEL_HIGH>, + <81 IRQ_TYPE_LEVEL_HIGH>, + <82 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "BAT_CTRL_INDB", + "BTEMP_LOW", + "BTEMP_HIGH", + "BTEMP_LOW_MEDIUM", + "BTEMP_MEDIUM_HIGH"; battery = <&ab8500_battery>; io-channels = <&gpadc 0x02>, <&gpadc 0x01>; - io-channel-name = "btemp_ball", + io-channel-names = "btemp_ball", "bat_ctrl"; }; ab8500_charger { status = "disabled"; compatible = "stericsson,ab8500-charger"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <11 IRQ_TYPE_LEVEL_HIGH>, + <0 IRQ_TYPE_LEVEL_HIGH>, + <107 IRQ_TYPE_LEVEL_HIGH>, + <106 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <105 IRQ_TYPE_LEVEL_HIGH>, + <104 IRQ_TYPE_LEVEL_HIGH>, + <89 IRQ_TYPE_LEVEL_HIGH>, + <22 IRQ_TYPE_LEVEL_HIGH>, + <21 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "MAIN_CH_UNPLUG_DET", + "MAIN_CHARGE_PLUG_DET", + "MAIN_EXT_CH_NOT_OK", + "MAIN_CH_TH_PROT_R", + "MAIN_CH_TH_PROT_F", + "VBUS_DET_F", + "VBUS_DET_R", + "USB_LINK_STATUS", + "USB_CH_TH_PROT_R", + "USB_CH_TH_PROT_F", + "USB_CHARGER_NOT_OKR", + "VBUS_OVV", + "CH_WD_EXP", + "VBUS_CH_DROP_END"; battery = <&ab8500_battery>; vddadc-supply = <&ab8500_ldo_adc_reg>; io-channels = <&gpadc 0x09>, <&gpadc 0x0b>; - io-channel-name = "vbus_v", + io-channel-names = "vbus_v", "usb_charger_c"; }; @@ -131,13 +182,13 @@ ab8500_usb: ab8500_usb { compatible = "stericsson,ab8500-usb"; - interrupts = < 90 IRQ_TYPE_LEVEL_HIGH - 96 IRQ_TYPE_LEVEL_HIGH - 14 IRQ_TYPE_LEVEL_HIGH - 15 IRQ_TYPE_LEVEL_HIGH - 79 IRQ_TYPE_LEVEL_HIGH - 74 IRQ_TYPE_LEVEL_HIGH - 75 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <90 IRQ_TYPE_LEVEL_HIGH>, + <96 IRQ_TYPE_LEVEL_HIGH>, + <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>, + <79 IRQ_TYPE_LEVEL_HIGH>, + <74 IRQ_TYPE_LEVEL_HIGH>, + <75 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ID_WAKEUP_R", "ID_WAKEUP_F", "VBUS_DET_F", @@ -150,12 +201,13 @@ musb_1v8-supply = <&db8500_vsmps2_reg>; clocks = <&prcmu_clk PRCMU_SYSCLK>; clock-names = "sysclk"; + #phy-cells = <0>; }; ab8500-ponkey { compatible = "stericsson,ab8500-poweron-key"; - interrupts = <6 IRQ_TYPE_LEVEL_HIGH - 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>, + <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "ONKEY_DBF", "ONKEY_DBR"; }; @@ -271,5 +323,10 @@ vana-supply = <&ab8500_ldo_ana_reg>; }; }; + + usb_per5@a03e0000 { + phys = <&ab8500_usb>; + phy-names = "usb"; + }; }; }; diff --git a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi index 4a99ee5a92..e350175305 100644 --- a/arch/arm/dts/ste-dbx5x0-u-boot.dtsi +++ b/arch/arm/dts/ste-dbx5x0-u-boot.dtsi @@ -4,8 +4,14 @@ #include "ste-dbx5x0.dtsi" / { + /* FIXME: Remove this when clk driver is implemented */ + sdmmcclk: sdmmcclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + soc { - /* FIXME: Remove this when clk driver is implemented */ mtu@a03c6000 { clock-frequency = <133000000>; }; @@ -18,6 +24,9 @@ uart@80007000 { clock = <38400000>; }; + mmc@80005000 { + clocks = <&sdmmcclk>; + }; }; reboot { diff --git a/arch/arm/dts/ste-dbx5x0.dtsi b/arch/arm/dts/ste-dbx5x0.dtsi index 6671f74c9f..68607e4ad8 100644 --- a/arch/arm/dts/ste-dbx5x0.dtsi +++ b/arch/arm/dts/ste-dbx5x0.dtsi @@ -260,7 +260,7 @@ reg = <0x80150000 0x2000>; }; - L2: l2-cache { + L2: cache-controller { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; @@ -883,7 +883,7 @@ status = "disabled"; }; - sdi0_per1@80126000 { + mmc@80126000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80126000 0x1000>; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; @@ -899,7 +899,7 @@ status = "disabled"; }; - sdi1_per2@80118000 { + mmc@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; @@ -915,7 +915,7 @@ status = "disabled"; }; - sdi2_per3@80005000 { + mmc@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; @@ -931,7 +931,7 @@ status = "disabled"; }; - sdi3_per2@80119000 { + mmc@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; @@ -947,7 +947,7 @@ status = "disabled"; }; - sdi4_per2@80114000 { + mmc@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; @@ -963,7 +963,7 @@ status = "disabled"; }; - sdi5_per3@80008000 { + mmc@80008000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/ste-ux500-samsung-stemmy.dts b/arch/arm/dts/ste-ux500-samsung-stemmy.dts index 7e7f4c823a..14be86086b 100644 --- a/arch/arm/dts/ste-ux500-samsung-stemmy.dts +++ b/arch/arm/dts/ste-ux500-samsung-stemmy.dts @@ -12,9 +12,25 @@ }; soc { + /* eMMC */ + mmc@80005000 { + status = "okay"; + + arm,primecell-periphid = <0x10480180>; + max-frequency = <100000000>; + bus-width = <8>; + + non-removable; + cap-mmc-highspeed; + }; + /* Debugging console UART */ uart@80007000 { status = "okay"; }; + + mcde@a0350000 { + status = "okay"; + }; }; }; diff --git a/arch/arm/include/asm/arch-am33xx/chilisom.h b/arch/arm/include/asm/arch-am33xx/chilisom.h index 493be64311..e423c9d071 100644 --- a/arch/arm/include/asm/arch-am33xx/chilisom.h +++ b/arch/arm/include/asm/arch-am33xx/chilisom.h @@ -6,7 +6,7 @@ #ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__ #define __ARCH_ARM_MACH_CHILISOM_SOM_H__ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) void chilisom_enable_pin_mux(void); void chilisom_spl_board_init(void); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 3675ce763d..733373ecf0 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -123,7 +123,6 @@ #elif defined(CONFIG_ARCH_LS1088A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 #define CONFIG_SYS_PAGE_SIZE 0x10000 #define SRDS_MAX_LANES 4 @@ -183,10 +182,6 @@ #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) #define TZPC_BASE 0x02200000 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) -#if !CONFIG_IS_ENABLED(DM_I2C) -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_EARLY_INIT -#endif #define SRDS_MAX_LANES 8 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -239,7 +234,6 @@ #elif defined(CONFIG_ARCH_LS1028A) #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 #define CONFIG_FSL_TZASC_400 diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index a2131ca07c..27f183b93d 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -41,9 +41,12 @@ extern void udc_disconnect(void); struct tag_serialnr; #ifdef CONFIG_SERIAL_TAG #define BOOTM_ENABLE_SERIAL_TAG 1 -void get_board_serial(struct tag_serialnr *serialnr); #else #define BOOTM_ENABLE_SERIAL_TAG 0 +#endif +#if defined(CONFIG_SERIAL_TAG) || defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG) +void get_board_serial(struct tag_serialnr *serialnr); +#else static inline void get_board_serial(struct tag_serialnr *serialnr) { } diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index 485310d660..e1eefc283f 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -256,7 +256,7 @@ lr .req x30 * For loading 64-bit OS, x0 is physical address to the FDT blob. * They will be passed to the guest. */ -.macro armv8_switch_to_el1_m, ep, flag, tmp +.macro armv8_switch_to_el1_m, ep, flag, tmp, tmp2 /* Initialize Generic Timers */ mrs \tmp, cnthctl_el2 /* Enable EL1 access to timers */ @@ -306,7 +306,14 @@ lr .req x30 b.eq 1f /* Initialize HCR_EL2 */ - ldr \tmp, =(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) + /* Only disable PAuth traps if PAuth is supported */ + mrs \tmp, id_aa64isar1_el1 + ldr \tmp2, =(ID_AA64ISAR1_EL1_GPI | ID_AA64ISAR1_EL1_GPA | \ + ID_AA64ISAR1_EL1_API | ID_AA64ISAR1_EL1_APA) + tst \tmp, \tmp2 + mov \tmp2, #(HCR_EL2_RW_AARCH64 | HCR_EL2_HCD_DIS) + orr \tmp, \tmp2, #(HCR_EL2_APK | HCR_EL2_API) + csel \tmp, \tmp2, \tmp, eq msr hcr_el2, \tmp /* Return to the EL1_SP1 mode from EL2 */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 8b3a54e64c..f75eea16b3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -75,11 +75,26 @@ /* * HCR_EL2 bits definitions */ +#define HCR_EL2_API (1 << 41) /* Trap pointer authentication + instructions */ +#define HCR_EL2_APK (1 << 40) /* Trap pointer authentication + key access */ #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ /* + * ID_AA64ISAR1_EL1 bits definitions + */ +#define ID_AA64ISAR1_EL1_GPI (0xF << 28) /* Implementation-defined generic + code auth algorithm */ +#define ID_AA64ISAR1_EL1_GPA (0xF << 24) /* QARMA generic code auth + algorithm */ +#define ID_AA64ISAR1_EL1_API (0xF << 8) /* Implementation-defined address + auth algorithm */ +#define ID_AA64ISAR1_EL1_APA (0xF << 4) /* QARMA address auth algorithm */ + +/* * ID_AA64PFR0_EL1 bits definitions */ #define ID_AA64PFR0_EL1_EL3 (0xF << 12) /* EL3 implemented */ @@ -551,7 +566,6 @@ s32 psci_affinity_info(u32 function_id, u32 target_affinity, u32 psci_migrate_info_type(void); void psci_system_off(void); void psci_system_reset(void); -s32 psci_features(u32 function_id, u32 psci_fid); #endif #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 46b6be21a8..956d258c9d 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -130,6 +130,14 @@ ENTRY(_main) ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ adr lr, here +#if defined(CONFIG_POSITION_INDEPENDENT) + adr r0, _main + ldr r1, _start_ofs + add r0, r1 + ldr r1, =CONFIG_SYS_TEXT_BASE + sub r1, r0 + add lr, r1 +#endif ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 #if defined(CONFIG_CPU_V7M) @@ -180,3 +188,6 @@ here: #endif ENDPROC(_main) + +_start_ofs: + .word _start - _main diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index e5f7267be1..14b7f61c1a 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -78,22 +78,28 @@ ENDPROC(relocate_vectors) */ ENTRY(relocate_code) - ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ - subs r4, r0, r1 /* r4 <- relocation offset */ - beq relocate_done /* skip relocation */ - ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ - + adr r3, relocate_code + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + subs r4, r0, r1 /* r4 <- Run to copy offset */ + beq relocate_done /* skip relocation */ + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + ldr r2, _image_copy_end_ofs + add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: - ldmia r1!, {r10-r11} /* copy from source address [r1] */ - stmia r0!, {r10-r11} /* copy to target address [r0] */ - cmp r1, r2 /* until source end address [r2] */ + ldmia r1!, {r10-r11} /* copy from source address [r1] */ + stmia r0!, {r10-r11} /* copy to target address [r0] */ + cmp r1, r2 /* until source end address [r2] */ blo copy_loop /* * fix .rel.dyn relocations */ - ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */ - ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */ + ldr r1, _rel_dyn_start_ofs + add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */ fixloop: ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ and r1, r1, #0xff @@ -129,3 +135,12 @@ relocate_done: #endif ENDPROC(relocate_code) + +_image_copy_start_ofs: + .word __image_copy_start - relocate_code +_image_copy_end_ofs: + .word __image_copy_end - relocate_code +_rel_dyn_start_ofs: + .word __rel_dyn_start - relocate_code +_rel_dyn_end_ofs: + .word __rel_dyn_end - relocate_code diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c90505e5ed..4448ca1592 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -298,7 +298,6 @@ endchoice config ATMEL_SFR bool - default n config SYS_SOC default "at91" diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index de99c616ac..5e3cce03b7 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -10,7 +10,7 @@ #include <config.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #include <asm/arch/hardware.h> #include <asm/arch/at91_mc.h> @@ -148,4 +148,4 @@ SMRDATA1: .word CONFIG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c index d0c7325392..ea19ec322e 100644 --- a/arch/arm/mach-at91/spl_at91.c +++ b/arch/arm/mach-at91/spl_at91.c @@ -136,7 +136,7 @@ void board_init_f(ulong dummy) at91_periph_clk_enable(ATMEL_ID_PIOC); #endif -#if defined(CONFIG_SPL_SERIAL_SUPPORT) +#if defined(CONFIG_SPL_SERIAL) /* init console */ at91_seriald_hw_init(); preloader_console_init(); diff --git a/arch/arm/mach-davinci/include/mach/davinci_misc.h b/arch/arm/mach-davinci/include/mach/davinci_misc.h index 48b11f7a5c..a40de0cc9c 100644 --- a/arch/arm/mach-davinci/include/mach/davinci_misc.h +++ b/arch/arm/mach-davinci/include/mach/davinci_misc.h @@ -35,7 +35,6 @@ struct lpsc_resource { const int lpsc_no; }; -int dvevm_read_mac_address(uint8_t *buf); void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr); int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins); int davinci_configure_pin_mux_items(const struct pinmux_resource *item, diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 90b38b7e02..73fdd1f243 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -42,33 +42,6 @@ int dram_init_banksize(void) #ifdef CONFIG_DRIVER_TI_EMAC /* - * Read ethernet MAC address from EEPROM for DVEVM compatible boards. - * Returns 1 if found, 0 otherwise. - */ -int dvevm_read_mac_address(uint8_t *buf) -{ -#ifdef CONFIG_SYS_I2C_EEPROM_ADDR - /* Read MAC address. */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &buf[0], 6)) - goto i2cerr; - - /* Check that MAC address is valid. */ - if (!is_valid_ethaddr(buf)) - goto err; - - return 1; /* Found */ - -i2cerr: - printf("Read from EEPROM @ 0x%02x failed\n", - CONFIG_SYS_I2C_EEPROM_ADDR); -err: -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */ - - return 0; -} - -/* * Set the mii mode as MII or RMII */ void davinci_emac_mii_mode_sel(int mode_sel) diff --git a/arch/arm/mach-davinci/spl.c b/arch/arm/mach-davinci/spl.c index d0d7a81471..54aff78894 100644 --- a/arch/arm/mach-davinci/spl.c +++ b/arch/arm/mach-davinci/spl.c @@ -51,7 +51,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_NAND; #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case DAVINCI_SD_OR_MMC_BOOT: case DAVINCI_MMC_ONLY_BOOT: return BOOT_DEVICE_MMC1; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 0b4276c036..7df0e17617 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -141,7 +141,7 @@ if ARCH_EXYNOS7 choice prompt "EXYNOS7 board select" -config TARGET_ESPRESSO7420 +config TARGET_ESPRESSO7420 bool "ESPRESSO7420 board" select ARM64 select ARMV8_MULTIENTRY diff --git a/arch/arm/mach-exynos/lowlevel_init.c b/arch/arm/mach-exynos/lowlevel_init.c index 97d6ca8fc2..2645a8ff49 100644 --- a/arch/arm/mach-exynos/lowlevel_init.c +++ b/arch/arm/mach-exynos/lowlevel_init.c @@ -218,7 +218,7 @@ int do_lowlevel_init(void) if (actions & DO_CLOCKS) { system_clock_init(); #ifdef CONFIG_DEBUG_UART -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL)) || \ !defined(CONFIG_SPL_BUILD) exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE); debug_uart_init(); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 653463ab46..dd4f027f36 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -1,8 +1,13 @@ +config MACH_IMX + bool + config HAS_CAAM bool config IMX_CONFIG - string + string "DCD script to use" + depends on MACH_IMX + default "arch/arm/mach-imx/spl_sd.cfg" config ROM_UNIFIED_SECTIONS bool diff --git a/arch/arm/mach-imx/image-container.c b/arch/arm/mach-imx/image-container.c index 68b30bcfc5..0e76786482 100644 --- a/arch/arm/mach-imx/image-container.c +++ b/arch/arm/mach-imx/image-container.c @@ -73,7 +73,7 @@ static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, return -ENOMEM; } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC if (dev_type == MMC_DEV) { unsigned long count = 0; struct mmc *mmc = (struct mmc *)dev; @@ -213,7 +213,7 @@ unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash) } #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long raw_sect) { diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 02db322f51..ee5cc47903 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -172,7 +172,7 @@ enum boot_device get_boot_device(void) return boot_dev; } -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define FUSE_UNIQUE_ID_WORD0 16 #define FUSE_UNIQUE_ID_WORD1 17 void get_board_serial(struct tag_serialnr *serialnr) @@ -201,7 +201,7 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->low = val1; serialnr->high = val2; } -#endif /*CONFIG_SERIAL_TAG*/ +#endif /*CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG*/ #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 1c33acc7dd..bba6323f96 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -405,7 +405,7 @@ int dram_init(void) return 0; } -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG void get_board_serial(struct tag_serialnr *serialnr) { u32 uid[4]; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 515c3020fa..ee73006ae8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -102,7 +102,6 @@ config MX6_OCRAM_256KB config MX6_DDRCAL bool "Include dynamic DDR calibration routines" depends on SPL - default n help Say "Y" if your board uses dynamic (per-boot) DDR calibration. If unsure, say N. @@ -305,12 +304,12 @@ config TARGET_MX6DL_MAMOJ select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBDISK_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL - select SPL_MMC_SUPPORT if SPL + select SPL_MMC if SPL select SPL_OF_CONTROL if SPL select SPL_OF_LIBFDT if SPL select SPL_PINCTRL if SPL select SPL_SEPARATE_BSS if SPL - select SPL_SERIAL_SUPPORT if SPL + select SPL_SERIAL if SPL select SPL_USB_GADGET if SPL select SPL_USB_HOST if SPL select SPL_USB_SDP_SUPPORT if SPL diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index adedc01164..059e65879c 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -91,6 +91,7 @@ config TARGET_COLIBRI_IMX7 select DM select DM_SERIAL select DM_THERMAL + select MX7D imply CMD_DM endchoice diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index fda25ba66a..9c7d5f18da 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -15,6 +15,7 @@ #include <asm/arch/imx-rdc.h> #include <asm/mach-imx/boot_mode.h> #include <asm/arch/crm_regs.h> +#include <asm/bootm.h> #include <dm.h> #include <env.h> #include <imx_thermal.h> @@ -224,7 +225,7 @@ const struct rproc_att hostmap[] = { }; #endif -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) /* enable all periherial can be accessed in nosec mode */ static void init_csu(void) { @@ -337,10 +338,19 @@ int arch_cpu_init(void) int arch_misc_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + struct tag_serialnr serialnr; + char serial_string[0x20]; + if (is_mx7d()) env_set("soc", "imx7d"); else env_set("soc", "imx7s"); + + /* Set serial# standard environment variable based on OTP settings */ + get_board_serial(&serialnr); + snprintf(serial_string, sizeof(serial_string), "0x%08x%08x", + serialnr.low, serialnr.high); + env_set("serial#", serial_string); #endif #ifdef CONFIG_FSL_CAAM @@ -351,7 +361,7 @@ int arch_misc_init(void) } #endif -#ifdef CONFIG_SERIAL_TAG +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* * OCOTP_TESTER * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 36033d611c..c2845241d9 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -199,7 +199,7 @@ int g_dnl_get_board_bcd_device_number(int gcnum) } #endif -#if defined(CONFIG_SPL_MMC_SUPPORT) +#if defined(CONFIG_SPL_MMC) /* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */ u32 spl_mmc_boot_mode(const u32 boot_device) { diff --git a/arch/arm/mach-imx/syscounter.c b/arch/arm/mach-imx/syscounter.c index 6dfed365d2..7c02e199a3 100644 --- a/arch/arm/mach-imx/syscounter.c +++ b/arch/arm/mach-imx/syscounter.c @@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec) return usec; } -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) int timer_init(void) { struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR; diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c index d213e06afb..9ce576186c 100644 --- a/arch/arm/mach-k3/sysfw-loader.c +++ b/arch/arm/mach-k3/sysfw-loader.c @@ -370,7 +370,7 @@ void k3_sysfw_loader(bool rom_loaded_sysfw, /* Load combined System Controller firmware and config data image */ switch (bootdev.boot_device) { -#if CONFIG_IS_ENABLED(MMC_SUPPORT) +#if CONFIG_IS_ENABLED(MMC) case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index a4b5630c46..9002e26d75 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -91,18 +91,6 @@ #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE #endif /* CONFIG_IDE */ -/* - * I2C related stuff - */ -#if defined(CONFIG_CMD_I2C) && !CONFIG_IS_ENABLED(DM_I2C) -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_LEGACY -#define CONFIG_SYS_I2C_MVTWSI -#endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - /* Use common timer */ #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index e067604d9b..134b6b17c2 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -8,7 +8,6 @@ config SYS_VENDOR config MT8512 bool "MediaTek MT8512 SoC" - default n choice prompt "MediaTek board select" diff --git a/arch/arm/mach-mediatek/spl.c b/arch/arm/mach-mediatek/spl.c index 927175c5a3..d3cda94617 100644 --- a/arch/arm/mach-mediatek/spl.c +++ b/arch/arm/mach-mediatek/spl.c @@ -31,9 +31,9 @@ void board_init_f(ulong dummy) u32 spl_boot_device(void) { -#if defined(CONFIG_SPL_SPI_SUPPORT) +#if defined(CONFIG_SPL_SPI) return BOOT_DEVICE_SPI; -#elif defined(CONFIG_SPL_MMC_SUPPORT) +#elif defined(CONFIG_SPL_MMC) return BOOT_DEVICE_MMC1; #elif defined(CONFIG_SPL_NAND_SUPPORT) return BOOT_DEVICE_NAND; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 89737a37ad..087643725e 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -2,7 +2,6 @@ if ARCH_MVEBU config HAVE_MVEBU_EFUSE bool - default n config ARMADA_32BIT bool @@ -184,6 +183,33 @@ config TARGET_CRS3XX_98DX3236 endchoice +choice + prompt "DDR bus width" + default DDR_64BIT + depends on ARMADA_XP + +config DDR_64BIT + bool "64bit bus width" + +config DDR_32BIT + bool "32bit bus width" + +endchoice + +config DDR_LOG_LEVEL + int "DDR training code log level" + depends on ARMADA_XP + default 0 + range 0 3 + help + Amount of information provided on error while running the DDR + training code. At level 0, provides an error code in a case of + failure, RL, WL errors and other algorithm failure. At level 1, + provides the D-Unit setup (SPD/Static configuration). At level 2, + provides the windows margin as a results of DQS centeralization. + At level 3, rovides the windows margin of each DQ as a results of + DQS centeralization. + config SYS_BOARD default "clearfog" if TARGET_CLEARFOG default "helios4" if TARGET_HELIOS4 @@ -256,7 +282,7 @@ config MVEBU_SPL_BOOT_DEVICE_SPI imply SPL_DM_SPI imply SPL_SPI_FLASH_SUPPORT imply SPL_SPI_LOAD - imply SPL_SPI_SUPPORT + imply SPL_SPI select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_MMC @@ -267,12 +293,12 @@ config MVEBU_SPL_BOOT_DEVICE_MMC imply SPL_DM_MMC imply SPL_GPIO imply SPL_LIBDISK_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC select SPL_BOOTROM_SUPPORT config MVEBU_SPL_BOOT_DEVICE_SATA bool "SATA" - imply SPL_SATA_SUPPORT + imply SPL_SATA imply SPL_LIBDISK_SUPPORT select SPL_BOOTROM_SUPPORT @@ -284,14 +310,12 @@ endchoice config MVEBU_EFUSE bool "Enable eFuse support" - default n depends on HAVE_MVEBU_EFUSE help Enable support for reading and writing eFuses on mvebu SoCs. config MVEBU_EFUSE_FAKE bool "Fake eFuse access (dry run)" - default n depends on MVEBU_EFUSE help This enables a "dry run" mode where eFuses are not really programmed. diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 02a5b88015..6ecd394a53 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -27,10 +27,6 @@ #define CONFIG_SYS_L2_PL310 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#endif - /* * By default the generated mvebu kwbimage.cfg is used * If for some board, different configuration file need to be used, @@ -63,8 +59,6 @@ #ifndef CONFIG_SYS_I2C_SOFT #define CONFIG_I2C_MVTWSI #endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 #endif /* Use common timer */ diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 8d6d4902f6..b798c797cc 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -17,7 +17,8 @@ #include <asm/arch/cpu.h> #include <asm/arch/soc.h> -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC_SUPPORT) || defined(CONFIG_SPL_SATA_SUPPORT) +#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) || defined(CONFIG_SPL_MMC) || \ + defined(CONFIG_SPL_SATA) /* * When loading U-Boot via SPL from SPI NOR, CONFIG_SYS_SPI_U_BOOT_OFFS must @@ -39,7 +40,7 @@ * and CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET need to point to the * kwbimage main header. */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION #error CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is unsupported #endif @@ -56,7 +57,7 @@ * stored at sector 1. Therefore CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be * set to 1. Otherwise U-Boot SPL would not be able to load U-Boot proper. */ -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA #if !defined(CONFIG_SPL_SATA_RAW_U_BOOT_USE_SECTOR) || !defined(CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR) || CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR != 1 #error CONFIG_SPL_SATA_RAW_U_BOOT_SECTOR must be set to 1 #endif @@ -92,7 +93,7 @@ struct kwbimage_main_hdr_v1 { uint8_t checksum; /* 0x1F */ } __packed; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { return MMCSD_MODE_RAW; @@ -121,10 +122,10 @@ int spl_parse_board_header(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT mhdr->blockid != IBR_HDR_SPI_ID && #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA mhdr->blockid != IBR_HDR_SATA_ID && #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC mhdr->blockid != IBR_HDR_SDIO_ID && #endif 1 @@ -135,7 +136,7 @@ int spl_parse_board_header(struct spl_image_info *spl_image, spl_image->offset = mhdr->srcaddr; -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA /* * For SATA srcaddr is specified in number of sectors. * The main header is must be stored at sector number 1. @@ -152,7 +153,7 @@ int spl_parse_board_header(struct spl_image_info *spl_image, } #endif -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC /* * For SDIO (eMMC) srcaddr is specified in number of sectors. * This expects that sector size is 512 bytes and recalculates @@ -193,11 +194,11 @@ u32 spl_boot_device(void) * If SPL is compiled with chosen boot_device support * then use SPL driver for loading U-Boot proper. */ -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case BOOT_DEVICE_MMC1: return BOOT_DEVICE_MMC1; #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA case BOOT_FROM_SATA: return BOOT_FROM_SATA; #endif diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 08639653b7..263142683b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -20,11 +20,11 @@ config OMAP34XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_OMAP3_ID_NAND imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply TWL4030_POWER @@ -42,11 +42,11 @@ config OMAP44XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SIMPLE imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD @@ -66,12 +66,12 @@ config OMAP54XX imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_AM33XX_BCH imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SYS_I2C_OMAP24XX config TI814X @@ -120,6 +120,7 @@ config AM33XX select SPECIFY_CONSOLE_INDEX imply NAND_OMAP_ELM imply NAND_OMAP_GPMC + imply SKIP_LOWLEVEL_INIT imply SPL_NAND_AM33XX_BCH imply SPL_NAND_SUPPORT imply SYS_I2C_OMAP24XX diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 4268419b16..1402376915 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -46,12 +46,12 @@ config TARGET_AM335X_EVM imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_OF_LIBFDT imply SPL_POWER imply SPL_SEPARATE_BSS - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_SYS_MALLOC_SIMPLE imply SPL_WATCHDOG imply SPL_YMODEM_SUPPORT @@ -230,10 +230,10 @@ config TARGET_AM43XX_EVM imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBDISK_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_MMC_SUPPORT + imply SPL_MMC imply SPL_NAND_SUPPORT imply SPL_POWER - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_WATCHDOG imply SPL_YMODEM_SUPPORT help diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index 61c76d045f..4e4f98ea90 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -13,7 +13,7 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif obj-$(CONFIG_TI816X) += ti816x_emif4.o diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index d390f2e1f3..c44667668e 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) sdram_init(); #endif @@ -351,7 +351,7 @@ int arch_misc_init(void) #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)) @@ -599,7 +599,7 @@ void board_init_f(ulong dummy) int arch_cpu_init_dm(void) { hw_data_init(); -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) early_system_init(); #endif return 0; diff --git a/arch/arm/mach-omap2/am33xx/chilisom.c b/arch/arm/mach-omap2/am33xx/chilisom.c index 15b6b35ae7..459bac13e0 100644 --- a/arch/arm/mach-omap2/am33xx/chilisom.c +++ b/arch/arm/mach-omap2/am33xx/chilisom.c @@ -22,7 +22,7 @@ #include <power/tps65217.h> #include <spl.h> -#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -182,4 +182,4 @@ void sdram_init(void) &ddr3_chilisom_emif_reg_data, 0); } -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ +#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 7cdf7f1589..fdb8b479ea 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -203,7 +203,7 @@ void spl_board_init(void) gpmc_init(); #endif #if defined(CONFIG_SPL_I2C) && !CONFIG_IS_ENABLED(DM_I2C) - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW) arch_misc_init(); diff --git a/arch/arm/mach-omap2/clocks-common.c b/arch/arm/mach-omap2/clocks-common.c index 14b638a651..73ab5fbfae 100644 --- a/arch/arm/mach-omap2/clocks-common.c +++ b/arch/arm/mach-omap2/clocks-common.c @@ -918,8 +918,8 @@ void gpi2c_init(void) static int gpi2c = 1; if (gpi2c) { - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); + i2c_init(CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE); gpi2c = 0; } } diff --git a/arch/arm/mach-omap2/omap3/board.c b/arch/arm/mach-omap2/omap3/board.c index 363af52845..8b70251457 100644 --- a/arch/arm/mach-omap2/omap3/board.c +++ b/arch/arm/mach-omap2/omap3/board.c @@ -76,8 +76,8 @@ void early_system_init(void) hw_data_init(); } -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) /****************************************************************************** * Routine: secure_unlock diff --git a/arch/arm/mach-omap2/omap3/lowlevel_init.S b/arch/arm/mach-omap2/omap3/lowlevel_init.S index 4fa89418a1..ab7cdcf3d4 100644 --- a/arch/arm/mach-omap2/omap3/lowlevel_init.S +++ b/arch/arm/mach-omap2/omap3/lowlevel_init.S @@ -170,8 +170,8 @@ pll_div_val5: go_to_speed_end: #endif -#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \ - !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY) +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \ + !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) ENTRY(lowlevel_init) ldr sp, SRAM_STACK str ip, [sp] /* stash ip register */ diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile index 606153e407..a8b87f6d71 100644 --- a/arch/arm/mach-orion5x/Makefile +++ b/arch/arm/mach-orion5x/Makefile @@ -11,7 +11,7 @@ obj-y = cpu.o obj-y += dram.o obj-y += timer.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT +ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o endif diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 69e40cf382..0e9c0fa996 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -29,7 +29,7 @@ config RCAR_GEN3 imply SPL_GZIP imply SPL_LIBCOMMON_SUPPORT imply SPL_LIBGENERIC_SUPPORT - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_SYS_MALLOC_SIMPLE imply SPL_TINY_MEMSET imply SPL_YMODEM_SUPPORT diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index d5e437f0d2..ea98bb00f3 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -133,7 +133,6 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT - default n choice prompt "Qos setting primary" diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index a6dcce180b..98549742e7 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -4,61 +4,73 @@ menu "Select Target SoC" config R8A774A1 bool "Renesas SoC R8A774A1" + select GICV2 imply CLK_R8A774A1 imply PINCTRL_PFC_R8A774A1 config R8A774B1 bool "Renesas SoC R8A774B1" + select GICV2 imply CLK_R8A774B1 imply PINCTRL_PFC_R8A774B1 config R8A774C0 bool "Renesas SoC R8A774C0" + select GICV2 imply CLK_R8A774C0 imply PINCTRL_PFC_R8A774C0 config R8A774E1 bool "Renesas SoC R8A774E1" + select GICV2 imply CLK_R8A774E1 imply PINCTRL_PFC_R8A774E1 config R8A7795 bool "Renesas SoC R8A7795" + select GICV2 imply CLK_R8A7795 imply PINCTRL_PFC_R8A7795 config R8A7796 bool "Renesas SoC R8A7796" + select GICV2 imply CLK_R8A7796 imply PINCTRL_PFC_R8A7796 config R8A77965 bool "Renesas SoC R8A77965" + select GICV2 imply CLK_R8A77965 imply PINCTRL_PFC_R8A77965 config R8A77970 bool "Renesas SoC R8A77970" + select GICV2 imply CLK_R8A77970 imply PINCTRL_PFC_R8A77970 config R8A77980 bool "Renesas SoC R8A77980" + select GICV2 imply CLK_R8A77980 imply PINCTRL_PFC_R8A77980 config R8A77990 bool "Renesas SoC R8A77990" + select GICV2 imply CLK_R8A77990 imply PINCTRL_PFC_R8A77990 config R8A77995 bool "Renesas SoC R8A77995" + select GICV2 imply CLK_R8A77995 imply PINCTRL_PFC_R8A77995 config R8A779A0 bool "Renesas SoC R8A779A0" + select GICV3 imply CLK_R8A779A0 imply PINCTRL_PFC_R8A779A0 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h index f3fbf77b0a..ef74d59fed 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h @@ -10,10 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00640801 #define MSTP1_BITS 0xDB6E9BDF diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h index fec9f7bf5d..681d1ea524 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h @@ -13,9 +13,6 @@ * R-Car (R8A7791) I/O Addresses */ -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* SDHI */ #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h index 8acd7ba750..06db64af6c 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h @@ -10,10 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE6520000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00400801 #define MSTP1_BITS 0x9B6F987F diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h index 278c7768d9..31433c3693 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h @@ -14,9 +14,6 @@ * R8A7793 I/O Addresses */ -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* SDHI */ #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h index 73259c7ec1..3baa4237c2 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h @@ -10,9 +10,6 @@ #include "rcar-base.h" -/* SH-I2C */ -#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 - /* Module stop control/status register bits */ #define MSTP0_BITS 0x00440801 #define MSTP1_BITS 0x936899DA diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h index a20740679f..4c98dffa07 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h @@ -70,14 +70,6 @@ #define SMSTPCR10 0xE6150998 #define SMSTPCR11 0xE615099C -/* - * SH-I2C - * Ch2 and ch3 are different address. These are defined - * in the header of each SoCs. - */ -#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000 - /* RCAR-I2C */ #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000 #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000 diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index 5cd8a8c787..ca1274272d 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -74,9 +74,6 @@ #define PUEN_USB1_OVC (1 << 2) #define PUEN_USB1_PWEN (1 << 1) -/* IICDVFS (I2C) */ -#define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 - #ifndef __ASSEMBLY__ #include <asm/types.h> #include <linux/bitops.h> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index b164afb529..da6871eb18 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,8 +11,8 @@ config ROCKCHIP_PX30 select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL select TPL_NEEDS_SEPARATE_STACK if TPL imply SPL_SEPARATE_BSS - select SPL_SERIAL_SUPPORT - select TPL_SERIAL_SUPPORT + select SPL_SERIAL + select TPL_SERIAL select DEBUG_UART_BOARD_INIT imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD @@ -84,9 +84,9 @@ config ROCKCHIP_RK322X select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_DRIVERS_MISC imply ROCKCHIP_COMMON_BOARD - imply SPL_SERIAL_SUPPORT + imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD select TPL_LIBCOMMON_SUPPORT select TPL_LIBGENERIC_SUPPORT @@ -100,6 +100,7 @@ config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7A select OF_BOARD_SETUP + select SKIP_LOWLEVEL_INIT_ONLY select SUPPORT_SPL select SPL select SUPPORT_TPL @@ -118,7 +119,7 @@ config ROCKCHIP_RK3288 imply TPL_RAM imply TPL_REGMAP imply TPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_SYSCON imply USB_FUNCTION_ROCKUSB imply CMD_ROCKUSB @@ -145,8 +146,8 @@ config ROCKCHIP_RK3308 imply SPL_REGMAP imply SPL_SYSCON imply SPL_RAM - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply SPL_SEPARATE_BSS help The Rockchip RK3308 is a ARM-based Soc which embedded with quad @@ -164,8 +165,8 @@ config ROCKCHIP_RK3328 imply ROCKCHIP_COMMON_BOARD imply ROCKCHIP_SDRAM_COMMON imply SPL_ROCKCHIP_COMMON_BOARD - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply SPL_SEPARATE_BSS select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT @@ -187,8 +188,8 @@ config ROCKCHIP_RK3368 imply ROCKCHIP_COMMON_BOARD imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS - imply SPL_SERIAL_SUPPORT - imply TPL_SERIAL_SUPPORT + imply SPL_SERIAL + imply TPL_SERIAL imply TPL_ROCKCHIP_COMMON_BOARD help The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised @@ -218,7 +219,7 @@ config ROCKCHIP_RK3399 select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL select TPL_NEEDS_SEPARATE_STACK if TPL select SPL_SEPARATE_BSS - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_DRIVERS_MISC select CLK select FIT @@ -234,7 +235,7 @@ config ROCKCHIP_RK3399 imply ROCKCHIP_SDRAM_COMMON imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF imply SPL_ROCKCHIP_COMMON_BOARD - imply TPL_SERIAL_SUPPORT + imply TPL_SERIAL imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE @@ -381,7 +382,7 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM This enables support code in the BOOT0 hook for the TPL stage to allow multiple entries. -config SPL_MMC_SUPPORT +config SPL_MMC default y if !SPL_ROCKCHIP_BACK_TO_BROM config ROCKCHIP_SPI_IMAGE diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 16090f5b08..aa5cc471ee 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -36,7 +36,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LDSCRIPT diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index 51cd43b396..b746795d81 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -22,7 +22,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y source "board/rockchip/evb_rk3036/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index e24e68ea51..9a76490998 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -24,7 +24,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LIBCOMMON_SUPPORT diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 2fc6f6ea3e..6458cd5581 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -20,7 +20,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_MAX_SIZE diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index a5db59ae59..f37b1bdfd5 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -163,7 +163,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TPL_LDSCRIPT diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index b9fdfe2e95..8fa536e15d 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -14,7 +14,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config ROCKCHIP_BOOT_MODE_REG diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c index cc908e1b0e..cca638bbef 100644 --- a/arch/arm/mach-rockchip/tpl.c +++ b/arch/arm/mach-rockchip/tpl.c @@ -48,7 +48,7 @@ void board_init_f(ulong dummy) struct udevice *dev; int ret; -#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL_SUPPORT) +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL) /* * Debug UART can be used from here if required: * diff --git a/arch/arm/mach-snapdragon/misc.c b/arch/arm/mach-snapdragon/misc.c index 985625a548..7d452f4529 100644 --- a/arch/arm/mach-snapdragon/misc.c +++ b/arch/arm/mach-snapdragon/misc.c @@ -9,6 +9,7 @@ #include <common.h> #include <mmc.h> #include <asm/arch/misc.h> +#include <asm/unaligned.h> /* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ #define UNSTUFF_BITS(resp, start, size) \ @@ -33,21 +34,22 @@ u32 msm_board_serial(void) if (!mmc_dev) return 0; + if (mmc_init(mmc_dev)) + return 0; + return UNSTUFF_BITS(mmc_dev->cid, 16, 32); } void msm_generate_mac_addr(u8 *mac) { - int i; - char sn[9]; - - snprintf(sn, 9, "%08x", msm_board_serial()); - - /* fill in the mac with serialno, use locally adminstrated pool */ + /* use locally adminstrated pool */ mac[0] = 0x02; - mac[1] = 00; - for (i = 3; i >= 0; i--) { - mac[i + 2] = hextoul(&sn[2 * i], NULL); - sn[2 * i] = 0; - } + mac[1] = 0x00; + + /* + * Put the 32-bit serial number in the last 32-bit of the MAC address. + * Use big endian order so it is consistent with the serial number + * written as a hexadecimal string, e.g. 0x1234abcd -> 02:00:12:34:ab:cd + */ + put_unaligned_be32(msm_board_serial(), &mac[2]); } diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c index b5f43f09d1..ecb656e4de 100644 --- a/arch/arm/mach-socfpga/spl_a10.c +++ b/arch/arm/mach-socfpga/spl_a10.c @@ -93,7 +93,7 @@ u32 spl_boot_device(void) } } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 7c71611768..441d893333 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -52,7 +52,7 @@ u32 spl_boot_device(void) } } -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC u32 spl_mmc_boot_mode(const u32 boot_device) { #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) diff --git a/arch/arm/mach-socfpga/spl_soc64.c b/arch/arm/mach-socfpga/spl_soc64.c index cb98ab39e4..ba6efc1d86 100644 --- a/arch/arm/mach-socfpga/spl_soc64.c +++ b/arch/arm/mach-socfpga/spl_soc64.c @@ -14,7 +14,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; } -#if IS_ENABLED(CONFIG_SPL_MMC_SUPPORT) +#if IS_ENABLED(CONFIG_SPL_MMC) u32 spl_boot_mode(const u32 boot_device) { if (IS_ENABLED(CONFIG_SPL_FS_FAT) || IS_ENABLED(CONFIG_SPL_FS_EXT4)) diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 2f1e7d3a15..a439dbd10f 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -41,7 +41,7 @@ config STM32F7 select SPL_OF_TRANSLATE select SPL_PINCTRL select SPL_RAM - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYS_MALLOC_SIMPLE select SPL_TIMER select SPL_XIP_SUPPORT diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 5d7eca649a..69d56c23e1 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -15,14 +15,14 @@ config SPL select SPL_PINCTRL select SPL_REGMAP select SPL_DM_RESET - select SPL_SERIAL_SUPPORT + select SPL_SERIAL select SPL_SYSCON select SPL_WATCHDOG if WATCHDOG imply BOOTSTAGE_STASH if SPL_BOOTSTAGE imply SPL_BOOTSTAGE if BOOTSTAGE imply SPL_DISPLAY_PRINT imply SPL_LIBDISK_SUPPORT - imply SPL_SPI_LOAD if SPL_SPI_SUPPORT + imply SPL_SPI_LOAD if SPL_SPI config SYS_SOC default "stm32mp" @@ -190,7 +190,6 @@ config STM32_ECDSA_VERIFY config CMD_STM32KEY bool "command stm32key to fuse public key hash" - default n help fuse public key hash in corresponding fuse used to authenticate binary. diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 49f94f095c..1d4a4fdd0c 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -209,6 +209,8 @@ config MACH_SUN4I select DRAM_SUN4I select SUNXI_GEN_SUN4I select SUPPORT_SPL + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN5I bool "sun5i (Allwinner A13)" @@ -219,6 +221,8 @@ config MACH_SUN5I select SUNXI_GEN_SUN4I select SUPPORT_SPL imply CONS_INDEX_2 if !DM_SERIAL + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN6I bool "sun6i (Allwinner A31)" @@ -245,6 +249,8 @@ config MACH_SUN7I select SUNXI_GEN_SUN4I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT + imply SPL_SYS_I2C_LEGACY + imply SYS_I2C_LEGACY config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" @@ -303,6 +309,7 @@ config MACH_SUN8I_R40 select SUNXI_DRAM_DW select SUNXI_DRAM_DW_32BIT select PHY_SUN4I_USB + imply SPL_SYS_I2C_LEGACY config MACH_SUN8I_V3S bool "sun8i (Allwinner V3/V3s/S3/S3L)" @@ -622,7 +629,6 @@ config SYS_SOC config UART0_PORT_F bool "UART0 on MicroSD breakout board" - default n ---help--- Repurpose the SD card slot for getting access to the UART0 serial console. Primarily useful only for low level u-boot debugging on @@ -633,7 +639,6 @@ config UART0_PORT_F config OLD_SUNXI_KERNEL_COMPAT bool "Enable workarounds for booting old kernels" - default n ---help--- Set this to enable various workarounds for old kernels, this results in sub-optimal settings for newer kernels, only enable if needed. @@ -764,14 +769,12 @@ config I2C0_ENABLE config I2C1_ENABLE bool "Enable I2C/TWI controller 1" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. config I2C2_ENABLE bool "Enable I2C/TWI controller 2" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -779,7 +782,6 @@ config I2C2_ENABLE if MACH_SUN6I || MACH_SUN7I config I2C3_ENABLE bool "Enable I2C/TWI controller 3" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -798,7 +800,6 @@ endif if MACH_SUN7I config I2C4_ENABLE bool "Enable I2C/TWI controller 4" - default n select CMD_I2C ---help--- See I2C0_ENABLE help text. @@ -806,7 +807,6 @@ endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" - default n ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. @@ -838,14 +838,12 @@ config VIDEO_HDMI config VIDEO_VGA bool "VGA output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) - default n ---help--- Say Y here to add support for outputting video over VGA. config VIDEO_VGA_VIA_LCD bool "VGA via LCD controller support" depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) - default n ---help--- Say Y here to add support for external DACs connected to the parallel LCD interface driving a VGA connector, such as found on the @@ -854,7 +852,6 @@ config VIDEO_VGA_VIA_LCD config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH bool "Force sync active high for VGA via LCD controller support" depends on VIDEO_VGA_VIA_LCD - default n ---help--- Say Y here if you've a board which uses opendrain drivers for the vga hsync and vsync signals. Opendrain drivers cannot generate steep enough @@ -872,7 +869,6 @@ config VIDEO_VGA_EXTERNAL_DAC_EN config VIDEO_COMPOSITE bool "Composite video output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) - default n ---help--- Say Y here to add support for outputting composite video. @@ -936,7 +932,6 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI - default n select CMD_I2C ---help--- Say y here if the LCD panel needs to be configured via i2c. This @@ -969,7 +964,6 @@ config VIDEO_LCD_IF_LVDS config SUNXI_DE2 bool - default n config VIDEO_DE2 bool "Display Engine 2 video driver" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 478c7a9e38..957e3ce64a 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -9,7 +9,7 @@ config SPL_LIBCOMMON_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config TEGRA_CLKRST @@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON select CPU_V7A select SPL select SPL_BOARD_INIT if SPL + select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL select SUPPORT_SPL select TEGRA_CLKRST select TEGRA_COMMON @@ -124,6 +125,7 @@ config TEGRA124 config TEGRA210 bool "Tegra210 family" + select GICV2 select TEGRA_ARMV8_COMMON select TEGRA_CLKRST select TEGRA_GPIO @@ -137,6 +139,7 @@ config TEGRA210 config TEGRA186 bool "Tegra186 family" select DM_MAILBOX + select GICV2 select TEGRA186_BPMP select TEGRA186_CLOCK select TEGRA186_GPIO diff --git a/arch/arm/mach-u8500/Kconfig b/arch/arm/mach-u8500/Kconfig index db7a29a54c..b067a719e7 100644 --- a/arch/arm/mach-u8500/Kconfig +++ b/arch/arm/mach-u8500/Kconfig @@ -13,14 +13,15 @@ config TARGET_STEMMY The Samsung "stemmy" board supports Samsung smartphones released with the ST-Ericsson NovaThor U8500 SoC, e.g. - - Samsung Galaxy S III mini (GT-I8190) "golden" + - Samsung Galaxy Ace 2 (GT-I8160) "codina" + - Samsung Galaxy Amp (SGH-I407) "kyle" + - Samsung Galaxy Beam (GT-I8530) "gavini" + - Samsung Galaxy Exhibit (SGH-T599) "codina" (TMO) - Samsung Galaxy S Advance (GT-I9070) "janice" + - Samsung Galaxy S III mini (GT-I8190) "golden" - Samsung Galaxy Xcover 2 (GT-S7710) "skomer" - - Samsung Galaxy Ace 2 (GT-I8160) "codina" - - and likely others as well (untested). - See board/ste/stemmy/README for details. + See doc/board/ste/stemmy.rst for details. endchoice diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index d333b7091d..5172efac0c 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,7 +6,7 @@ obj-y += boards.o obj-y += spl_board_init.o obj-y += memconf.o obj-y += bcu/ -obj-$(CONFIG_SPL_MMC_SUPPORT) += mmc-boot-mode.o +obj-$(CONFIG_SPL_MMC) += mmc-boot-mode.o else diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index ebd2da3887..0c6ad345ff 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -21,9 +21,6 @@ config SYS_CONFIG_NAME Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header will be used for board configuration. -config GICV3 - def_bool y - config SYS_MALLOC_LEN default 0x2000000 diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index e54310383b..cf2e727916 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -15,16 +15,16 @@ config SPL_LIBDISK_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_MMC_SUPPORT +config SPL_MMC default y if MMC_SDHCI_ZYNQ -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config SPL_SPI_FLASH_SUPPORT default y if ZYNQ_QSPI -config SPL_SPI_SUPPORT +config SPL_SPI default y if ZYNQ_QSPI config ZYNQ_DDRC_INIT diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index d09141c3bc..b1a5184b68 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -45,7 +45,7 @@ u32 spl_boot_device(void) u32 mode; switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI case ZYNQ_BM_QSPI: mode = BOOT_DEVICE_SPI; break; @@ -56,7 +56,7 @@ u32 spl_boot_device(void) case ZYNQ_BM_NOR: mode = BOOT_DEVICE_NOR; break; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case ZYNQ_BM_SD: mode = BOOT_DEVICE_MMC1; break; diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index 39144d654e..f7b08db355 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -12,16 +12,16 @@ config SPL_LIBDISK_SUPPORT config SPL_LIBGENERIC_SUPPORT default y -config SPL_MMC_SUPPORT +config SPL_MMC default y if MMC_SDHCI_ZYNQ -config SPL_SERIAL_SUPPORT +config SPL_SERIAL default y config SPL_SPI_FLASH_SUPPORT default y if ZYNQ_QSPI -config SPL_SPI_SUPPORT +config SPL_SPI default y if ZYNQ_QSPI config SYS_BOARD diff --git a/arch/arm/mach-zynqmp/spl.c b/arch/arm/mach-zynqmp/spl.c index 8fcae2c6a6..6b836cbff2 100644 --- a/arch/arm/mach-zynqmp/spl.c +++ b/arch/arm/mach-zynqmp/spl.c @@ -88,7 +88,7 @@ u32 spl_boot_device(void) switch (bootmode) { case JTAG_MODE: return BOOT_DEVICE_RAM; -#ifdef CONFIG_SPL_MMC_SUPPORT +#ifdef CONFIG_SPL_MMC case SD_MODE1: case SD1_LSHFT_MODE: /* not working on silicon v1 */ return BOOT_DEVICE_MMC2; @@ -100,11 +100,11 @@ u32 spl_boot_device(void) case USB_MODE: return BOOT_DEVICE_DFU; #endif -#ifdef CONFIG_SPL_SATA_SUPPORT +#ifdef CONFIG_SPL_SATA case SW_SATA_MODE: return BOOT_DEVICE_SATA; #endif -#ifdef CONFIG_SPL_SPI_SUPPORT +#ifdef CONFIG_SPL_SPI case QSPI_MODE_24BIT: case QSPI_MODE_32BIT: return BOOT_DEVICE_SPI; |