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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/fsl-imx8-ca35.dtsi4
-rw-r--r--arch/arm/dts/imx6ull-somlabs-visionsom.dts276
-rw-r--r--arch/arm/dts/imx7ulp-evk.dts2
-rw-r--r--arch/arm/include/asm/arch-mx7ulp/imx-regs.h4
-rw-r--r--arch/arm/mach-imx/imx8m/clock_imx8mm.c10
-rw-r--r--arch/arm/mach-imx/mx6/Kconfig13
-rw-r--r--arch/arm/mach-imx/mx7ulp/soc.c2
8 files changed, 306 insertions, 6 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e469d191fb..44f742017e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -677,6 +677,7 @@ dtb-$(CONFIG_MX6ULL) += \
imx6ull-colibri.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
+ imx6ull-somlabs-visionsom.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MX6) += \
diff --git a/arch/arm/dts/fsl-imx8-ca35.dtsi b/arch/arm/dts/fsl-imx8-ca35.dtsi
index 28bc32c8b7..9af8b1511c 100644
--- a/arch/arm/dts/fsl-imx8-ca35.dtsi
+++ b/arch/arm/dts/fsl-imx8-ca35.dtsi
@@ -18,6 +18,7 @@
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_1: cpu@1 {
@@ -26,6 +27,7 @@
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_2: cpu@2 {
@@ -34,6 +36,7 @@
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_3: cpu@3 {
@@ -42,6 +45,7 @@
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&A35_L2>;
+ #cooling-cells = <2>;
};
A35_L2: l2-cache0 {
diff --git a/arch/arm/dts/imx6ull-somlabs-visionsom.dts b/arch/arm/dts/imx6ull-somlabs-visionsom.dts
new file mode 100644
index 0000000000..868f3f8440
--- /dev/null
+++ b/arch/arm/dts/imx6ull-somlabs-visionsom.dts
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2019 SoMLabs
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx6ull.dtsi"
+
+/ {
+ model = "SoMLabs VisionSOM-6ULL";
+ compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ usr0 {
+ label = "usr0";
+ gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ usr1 {
+ label = "usr1";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ };
+
+ usr2 {
+ label = "usr2";
+ gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc1";
+ };
+
+ usr3 {
+ label = "usr3";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usb_otg1_vbus: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg2>;
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ };
+};
+
+&cpu0 {
+ arm-supply = <&reg_arm>;
+ soc-supply = <&reg_soc>;
+};
+
+&clks {
+ assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
+ assigned-clock-rates = <786432000>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy0>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x1>;
+ fsl,cpu_pupscr_sw = <0x0>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+
+};
+
+&i2c2 {
+ clock_frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1>;
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ /* 32kHz low power reference clock for WiFi */
+ MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
+ /* LED 0..3 */
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
+
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
+ >;
+ };
+
+ pinctrl_usb_otg2: usbotg2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
+ >;
+ };
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xfff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <&reg_usb_otg1_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ tx-d-cal = <0x5>;
+};
+
+&usbphy2 {
+ tx-d-cal = <0x5>;
+};
+
+&usdhc2 {
+ non-removable;
+ disable-wp;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,wdog_b;
+};
diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts
index 08a682f314..8f6a935e24 100644
--- a/arch/arm/dts/imx7ulp-evk.dts
+++ b/arch/arm/dts/imx7ulp-evk.dts
@@ -156,7 +156,7 @@
pinctrl_backlight: backlight_grp {
fsl,pins = <
- IMX7ULP_PAD_PTF2__PTF2 0x20100
+ IMX7ULP_PAD_PTF2__PTF2 0x20000
>;
};
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index 3c82e9921e..9a420dc30b 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -946,6 +946,10 @@
#define SNVS_LPCR_DPEN (0x20)
#define SNVS_LPCR_SRTC_ENV (0x1)
+#define SRC_BASE_ADDR CMC1_RBASE
+#define IRAM_BASE_ADDR OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
+
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index ca4b4c05ab..c423ac0058 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -47,7 +47,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
};
-int fracpll_configure(enum pll_clocks pll, u32 freq)
+static int fracpll_configure(enum pll_clocks pll, u32 freq)
{
int i;
u32 tmp, div_val;
@@ -268,7 +268,7 @@ u32 imx_get_uartclk(void)
return 24000000U;
}
-u32 decode_intpll(enum clk_root_src intpll)
+static u32 decode_intpll(enum clk_root_src intpll)
{
u32 pll_gnrl_ctl, pll_div_ctl, pll_clke_mask;
u32 main_div, pre_div, post_div, div;
@@ -415,7 +415,7 @@ u32 decode_intpll(enum clk_root_src intpll)
return lldiv(freq, pre_div * (1 << post_div) * div);
}
-u32 decode_fracpll(enum clk_root_src frac_pll)
+static u32 decode_fracpll(enum clk_root_src frac_pll)
{
u32 pll_gnrl_ctl, pll_fdiv_ctl0, pll_fdiv_ctl1;
u32 main_div, pre_div, post_div, k;
@@ -480,7 +480,7 @@ u32 decode_fracpll(enum clk_root_src frac_pll)
65536 * pre_div * (1 << post_div));
}
-u32 get_root_src_clk(enum clk_root_src root_src)
+static u32 get_root_src_clk(enum clk_root_src root_src)
{
switch (root_src) {
case OSC_24M_CLK:
@@ -524,7 +524,7 @@ u32 get_root_src_clk(enum clk_root_src root_src)
return 0;
}
-u32 get_root_clk(enum clk_root_index clock_id)
+static u32 get_root_clk(enum clk_root_index clock_id)
{
enum clk_root_src root_src;
u32 post_podf, pre_podf, root_src_clk;
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index f1a1021f10..9d91f9ab44 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -540,6 +540,18 @@ config TARGET_SKSIMX6
bool "sks-imx6"
select SUPPORT_SPL
+config TARGET_SOMLABS_VISIONSOM_6ULL
+ bool "visionsom-6ull"
+ select MX6ULL
+ select BOARD_LATE_INIT
+ select DM
+ select DM_ETH
+ select DM_GPIO
+ select DM_MMC
+ select DM_SERIAL
+ select DM_THERMAL
+ imply CMD_DM
+
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
@@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig"
source "board/seco/Kconfig"
source "board/sks-kinkel/sksimx6/Kconfig"
source "board/solidrun/mx6cuboxi/Kconfig"
+source "board/somlabs/visionsom-6ull/Kconfig"
source "board/technexion/pico-imx6/Kconfig"
source "board/technexion/pico-imx6ul/Kconfig"
source "board/tbs/tbs2910/Kconfig"
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 7f8fdc7005..46484813d2 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -118,6 +118,7 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
+#if !defined(CONFIG_SPL) || (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
@@ -175,6 +176,7 @@ void s_init(void)
#endif
return;
}
+#endif
#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-20 09:30:25 +0300