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Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/t4240_serdes.c')
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c202
1 files changed, 0 insertions, 202 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index a8c0c47f4a..61402e84ef 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -262,208 +262,6 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_ARCH_T4160)
-static const struct serdes_config serdes1_cfg_tbl[] = {
- /* SerDes 1 */
- {1, {NONE, NONE, NONE, NONE,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10,
- XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {NONE, NONE, NONE, NONE,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
- HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {NONE, NONE, NONE, NONE,
- SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
- SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, NONE, NONE,
- NONE, NONE, QSGMII_FM1_A, NONE} },
- {}
-};
-static const struct serdes_config serdes2_cfg_tbl[] = {
- /* SerDes 2 */
- {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
- SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, QSGMII_FM2_A, NONE} },
- {55, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {56, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
- {57, {NONE, XFI_FM1_MAC10,
- XFI_FM2_MAC10, NONE,
- SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
- NONE, NONE} },
- {}
-};
-static const struct serdes_config serdes3_cfg_tbl[] = {
- /* SerDes 3 */
- {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
- {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
- {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {NONE, NONE, NONE, NONE,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {NONE, NONE, NONE, NONE,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- SRIO1, SRIO1, SRIO1, SRIO1} },
- {}
-};
-static const struct serdes_config serdes4_cfg_tbl[] = {
- /* SerDes 4 */
- {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
- {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
- {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
- {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
- {}
-}
-;
#else
#error "Need to define SerDes protocol"
#endif
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-10 07:53:11 +0300