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diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
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index 0000000000..82bb5a2a53
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+++ b/arch/riscv/cpu/andesv5/Kconfig
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+config RISCV_NDS
+ bool
+ select ARCH_EARLY_INIT_R
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply V5L2_CACHE
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
+ help
+ Run U-Boot on AndeStar V5 platforms and use some specific features
+ which are provided by Andes Technology AndeStar V5 families.