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-rw-r--r--arch/riscv/cpu/ax25/Kconfig24
-rw-r--r--arch/riscv/cpu/ax25/Makefile8
-rw-r--r--arch/riscv/cpu/ax25/cache.c172
-rw-r--r--arch/riscv/cpu/ax25/cpu.c75
-rw-r--r--arch/riscv/cpu/ax25/spl.c27
5 files changed, 0 insertions, 306 deletions
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
deleted file mode 100644
index 4a7295d30c..0000000000
--- a/arch/riscv/cpu/ax25/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-config RISCV_NDS
- bool
- select ARCH_EARLY_INIT_R
- imply CPU
- imply CPU_RISCV
- imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply SPL_CPU
- imply SPL_OPENSBI
- imply SPL_LOAD_FIT
- help
- Run U-Boot on AndeStar V5 platforms and use some specific features
- which are provided by Andes Technology AndeStar V5 families.
-
-if RISCV_NDS
-
-config RISCV_NDS_CACHE
- bool "AndeStar V5 families specific cache support"
- depends on RISCV_MMODE || SPL_RISCV_MMODE
- help
- Provide Andes Technology AndeStar V5 families specific cache support.
-
-endif
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile
deleted file mode 100644
index 35a1a2fb83..0000000000
--- a/arch/riscv/cpu/ax25/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2017 Andes Technology Corporation
-# Rick Chen, Andes Technology Corporation <rick@andestech.com>
-
-obj-y := cpu.o
-obj-y += cache.o
-obj-y += spl.o
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
deleted file mode 100644
index 35f23c748d..0000000000
--- a/arch/riscv/cpu/ax25/cache.c
+++ /dev/null
@@ -1,172 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <dm.h>
-#include <asm/cache.h>
-#include <dm/uclass-internal.h>
-#include <cache.h>
-#include <asm/csr.h>
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
-/* mcctlcommand */
-#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
-
-/* D-cache operation */
-#define CCTL_L1D_WBINVAL_ALL 6
-#endif
-#endif
-
-#ifdef CONFIG_V5L2_CACHE
-static void _cache_enable(void)
-{
- struct udevice *dev = NULL;
-
- uclass_find_first_device(UCLASS_CACHE, &dev);
-
- if (dev)
- cache_enable(dev);
-}
-
-static void _cache_disable(void)
-{
- struct udevice *dev = NULL;
-
- uclass_find_first_device(UCLASS_CACHE, &dev);
-
- if (dev)
- cache_disable(dev);
-}
-#endif
-
-void flush_dcache_all(void)
-{
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
-#endif
-#endif
-#endif
-}
-
-void flush_dcache_range(unsigned long start, unsigned long end)
-{
- flush_dcache_all();
-}
-
-void invalidate_dcache_range(unsigned long start, unsigned long end)
-{
- flush_dcache_all();
-}
-
-void icache_enable(void)
-{
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- asm volatile (
- "csrr t1, mcache_ctl\n\t"
- "ori t0, t1, 0x1\n\t"
- "csrw mcache_ctl, t0\n\t"
- );
-#endif
-#endif
-#endif
-}
-
-void icache_disable(void)
-{
-#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- asm volatile (
- "fence.i\n\t"
- "csrr t1, mcache_ctl\n\t"
- "andi t0, t1, ~0x1\n\t"
- "csrw mcache_ctl, t0\n\t"
- );
-#endif
-#endif
-#endif
-}
-
-void dcache_enable(void)
-{
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- asm volatile (
- "csrr t1, mcache_ctl\n\t"
- "ori t0, t1, 0x2\n\t"
- "csrw mcache_ctl, t0\n\t"
- );
-#endif
-#ifdef CONFIG_V5L2_CACHE
- _cache_enable();
-#endif
-#endif
-#endif
-}
-
-void dcache_disable(void)
-{
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
- asm volatile (
- "csrr t1, mcache_ctl\n\t"
- "andi t0, t1, ~0x2\n\t"
- "csrw mcache_ctl, t0\n\t"
- );
-#endif
-#ifdef CONFIG_V5L2_CACHE
- _cache_disable();
-#endif
-#endif
-#endif
-}
-
-int icache_status(void)
-{
- int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- asm volatile (
- "csrr t1, mcache_ctl\n\t"
- "andi %0, t1, 0x01\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
-#endif
-#endif
-
- return ret;
-}
-
-int dcache_status(void)
-{
- int ret = 0;
-
-#ifdef CONFIG_RISCV_NDS_CACHE
-#if CONFIG_IS_ENABLED(RISCV_MMODE)
- asm volatile (
- "csrr t1, mcache_ctl\n\t"
- "andi %0, t1, 0x02\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
-#endif
-#endif
-
- return ret;
-}
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
deleted file mode 100644
index a46674f7c2..0000000000
--- a/arch/riscv/cpu/ax25/cpu.c
+++ /dev/null
@@ -1,75 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2017 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-
-/* CPU specific code */
-#include <common.h>
-#include <cpu_func.h>
-#include <irq_func.h>
-#include <asm/cache.h>
-#include <asm/csr.h>
-
-#define CSR_MCACHE_CTL 0x7ca
-#define CSR_MMISC_CTL 0x7d0
-#define CSR_MARCHID 0xf12
-
-#define V5_MCACHE_CTL_IC_EN_OFFSET 0
-#define V5_MCACHE_CTL_DC_EN_OFFSET 1
-#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8
-#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
-#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
-
-#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
-#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
-#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
-#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
-
-
-/*
- * cleanup_before_linux() is called just before we call linux
- * it prepares the processor for linux
- *
- * we disable interrupt and caches.
- */
-int cleanup_before_linux(void)
-{
- disable_interrupts();
-
- /* turn off I/D-cache */
- cache_flush();
- icache_disable();
- dcache_disable();
-
- return 0;
-}
-
-void harts_early_init(void)
-{
- if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
- unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
-
- if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
- mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
- if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
- mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
- csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
-
- /*
- * Check DC_COHEN_EN, if cannot write to mcache_ctl,
- * we assume this bitmap not support L2 CM
- */
- mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
- /* Wait for DC_COHSTA bit be set */
- while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
- mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- }
- }
-}
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c
deleted file mode 100644
index 413849043b..0000000000
--- a/arch/riscv/cpu/ax25/spl.c
+++ /dev/null
@@ -1,27 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2023 Andes Technology Corporation
- * Rick Chen, Andes Technology Corporation <rick@andestech.com>
- */
-#include <common.h>
-#include <cpu_func.h>
-#include <hang.h>
-#include <init.h>
-#include <log.h>
-#include <spl.h>
-#include <asm/global_data.h>
-#include <asm/system.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_IS_ENABLED(RAM_SUPPORT)
-struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size)
-{
- return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset);
-}
-
-void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
-{
- return spl_get_load_buffer(0, sectors * bl_len);
-}
-#endif
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-26 00:25:14 +0300