diff options
Diffstat (limited to 'arch/riscv/dts/fu740-c000-u-boot.dtsi')
| -rw-r--r-- | arch/riscv/dts/fu740-c000-u-boot.dtsi | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi index 917e9bf163..706224b384 100644 --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi @@ -9,47 +9,47 @@ cpus { assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>; assigned-clock-rates = <1200000000>; - u-boot,dm-spl; + bootph-pre-ram; cpu0: cpu@0 { clocks = <&prci FU740_PRCI_CLK_COREPLL>; - u-boot,dm-spl; + bootph-pre-ram; status = "okay"; cpu0_intc: interrupt-controller { - u-boot,dm-spl; + bootph-pre-ram; }; }; cpu1: cpu@1 { clocks = <&prci FU740_PRCI_CLK_COREPLL>; - u-boot,dm-spl; + bootph-pre-ram; cpu1_intc: interrupt-controller { - u-boot,dm-spl; + bootph-pre-ram; }; }; cpu2: cpu@2 { clocks = <&prci FU740_PRCI_CLK_COREPLL>; - u-boot,dm-spl; + bootph-pre-ram; cpu2_intc: interrupt-controller { - u-boot,dm-spl; + bootph-pre-ram; }; }; cpu3: cpu@3 { clocks = <&prci FU740_PRCI_CLK_COREPLL>; - u-boot,dm-spl; + bootph-pre-ram; cpu3_intc: interrupt-controller { - u-boot,dm-spl; + bootph-pre-ram; }; }; cpu4: cpu@4 { clocks = <&prci FU740_PRCI_CLK_COREPLL>; - u-boot,dm-spl; + bootph-pre-ram; cpu4_intc: interrupt-controller { - u-boot,dm-spl; + bootph-pre-ram; }; }; }; soc { - u-boot,dm-spl; + bootph-pre-ram; clint: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 @@ -58,7 +58,7 @@ &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; reg = <0x0 0x2000000 0x0 0x10000>; - u-boot,dm-spl; + bootph-pre-ram; }; prci: clock-controller@10000000 { #reset-cells = <1>; @@ -78,25 +78,25 @@ 0x0 0x100b8000 0x0 0x1000>; clocks = <&prci FU740_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; - u-boot,dm-spl; + bootph-pre-ram; }; }; }; &prci { - u-boot,dm-spl; + bootph-pre-ram; }; &uart0 { - u-boot,dm-spl; + bootph-pre-ram; }; &spi0 { - u-boot,dm-spl; + bootph-pre-ram; }; &i2c0 { - u-boot,dm-spl; + bootph-pre-ram; }; ð0 { |