diff options
Diffstat (limited to 'arch/riscv/dts/jh7110.dtsi')
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 485b9053d0..9e5b0576f9 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -1186,17 +1186,18 @@ }; pcie0: pcie@2B000000 { - compatible = "plda,pci-xpressrich3-axi"; + compatible = "starfive,jh7110-pcie"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - reg = <0x0 0x2B000000 0x0 0x1000000 - 0x9 0x40000000 0x0 0x10000000>; + reg = <0x0 0x2B000000 0x0 0x1000000>, + <0x9 0x40000000 0x0 0x10000000>; reg-names = "reg", "config"; device_type = "pci"; starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; msi-parent = <&plic>; interrupts = <56>; interrupt-controller; @@ -1215,25 +1216,27 @@ <&rstgen RSTN_U0_PLDA_PCIE_APB>; reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; - clocks = <&clkgen JH7110_PCIE0_CLK_TL>, + clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, + <&clkgen JH7110_PCIE0_CLK_TL>, <&clkgen JH7110_PCIE0_CLK_AXI_MST0>, <&clkgen JH7110_PCIE0_CLK_APB>; - clock-names = "tl", "axi_mst0", "apb"; + clock-names = "noc", "tl", "axi_mst0", "apb"; status = "disabled"; }; pcie1: pcie@2C000000 { - compatible = "plda,pci-xpressrich3-axi"; + compatible = "starfive,jh7110-pcie"; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - reg = <0x0 0x2C000000 0x0 0x1000000 - 0x9 0xc0000000 0x0 0x10000000>; + reg = <0x0 0x2C000000 0x0 0x1000000>, + <0x9 0xc0000000 0x0 0x10000000>; reg-names = "reg", "config"; device_type = "pci"; starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>; bus-range = <0x0 0xff>; - ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x06000000>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; msi-parent = <&plic>; interrupts = <57>; interrupt-controller; @@ -1252,10 +1255,11 @@ <&rstgen RSTN_U1_PLDA_PCIE_APB>; reset-names = "rst_mst0", "rst_slv0", "rst_slv", "rst_brg", "rst_core", "rst_apb"; - clocks = <&clkgen JH7110_PCIE1_CLK_TL>, + clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, + <&clkgen JH7110_PCIE1_CLK_TL>, <&clkgen JH7110_PCIE1_CLK_AXI_MST0>, <&clkgen JH7110_PCIE1_CLK_APB>; - clock-names = "tl", "axi_mst0", "apb"; + clock-names = "noc", "tl", "axi_mst0", "apb"; status = "disabled"; }; |