diff options
Diffstat (limited to 'arch/riscv/dts/jh7110.dtsi')
| -rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 250 |
1 files changed, 157 insertions, 93 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index 9ab211748b..485b9053d0 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -659,7 +659,20 @@ status = "disabled"; }; - i2c5: i2c5@12050000 { + i2c2: i2c@10050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10050000 0x0 0x10000>; + clocks = <&clkgen JH7110_I2C2_CLK_CORE>, + <&clkgen JH7110_I2C2_CLK_APB>; + clock-names = "ref", "pclk"; + resets = <&rstgen RSTN_U2_DW_I2C_APB>; + interrupts = <37>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@12050000 { compatible = "snps,designware-i2c"; reg = <0x0 0x12050000 0x0 0x10000>; clocks = <&clkgen JH7110_I2C5_CLK_CORE>, @@ -1270,126 +1283,177 @@ reg = <0 0x295B0000 0 0x90>; }; - hdmi_output: hdmi-output { - compatible = "verisilicon,hdmi-encoder"; - verisilicon,dss-syscon = <&dssctrl>; - verisilicon,mux-mask = <0x70 0x380>; - verisilicon,mux-val = <0x40 0x280>; - status = "disabled"; - }; - dc8200: dc8200@29400000 { - compatible = "verisilicon,dc8200"; + compatible = "starfive,sf-dc8200"; reg = <0x0 0x29400000 0x0 0x100>, - <0x0 0x29400800 0x0 0x2000>, - <0x0 0x17030000 0x0 0x1000>; - interrupts = <95>; - status = "disabled"; - clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>, - <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>, - <&clkgen JH7110_VOUT_SRC>, - <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, - <&clkgen JH7110_AHB1>, - <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>, - <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>, - <&clkgen JH7110_I2STX_4CH0_BCLK_MST>, - <&clkvout JH7110_U0_DC8200_CLK_PIX0>, - <&clkvout JH7110_U0_DC8200_CLK_PIX1>, - <&clkvout JH7110_U0_DC8200_CLK_AXI>, - <&clkvout JH7110_U0_DC8200_CLK_CORE>, - <&clkvout JH7110_U0_DC8200_CLK_AHB>; - clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc", - "noc_disp","noc_isp","noc_stg","vout_src", - "top_vout_axi","ahb1","top_vout_ahb", - "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1", - "axi_clk","core_clk","vout_ahb"; + <0x0 0x29400800 0x0 0x2000>; + reg-names = "hi", "low"; + status = "okay"; + clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>, + <&clkgen JH7110_VOUT_SRC>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>, + <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>, + <&clkvout JH7110_U0_DC8200_CLK_PIX0>, + <&clkvout JH7110_U0_DC8200_CLK_PIX1>, + <&clkvout JH7110_U0_DC8200_CLK_AXI>, + <&clkvout JH7110_U0_DC8200_CLK_CORE>, + <&clkvout JH7110_U0_DC8200_CLK_AHB>, + <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>, + <&hdmitx0_pixelclk>, + <&clkvout JH7110_DC8200_PIX0>, + <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>, + <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>; + clock-names = "disp_axi","vout_src", + "top_vout_axi","top_vout_ahb", + "dc_pix0","dc_pix1", + "dc_axi","dc_core","dc_ahb", + "top_vout_lcd","hdmitx0_pixelclk","dc8200_pix0", + "dc8200_pix0_out","dc8200_pix1_out"; resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>, <&rstgen RSTN_U0_DC8200_AXI>, <&rstgen RSTN_U0_DC8200_AHB>, <&rstgen RSTN_U0_DC8200_CORE>, - <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>, - <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>, - <&rstgen RSTN_U0_JTAG2APB_PRESETN>, - <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>, - <&rstgen RSTN_U0_NOC_BUS_DDRC_N>; + <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>; reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core", - "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb", - "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb", - "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc"; + "rst_noc_disp"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + vopb_out_mipi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_in_vopb>; + }; + + vopb_out_hdmi: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmi_in_vopb>; + }; + + vopb_out_lvds: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds_in_vopb>; + }; + + vopb_out_edp: endpoint@3 { + reg = <3>; + remote-endpoint = <&edp_in_vopb>; + }; + }; }; - mipi_dphy: mipi-dphy@295e0000{ - compatible = "starfive,jh7100-mipi-dphy-tx"; - reg = <0x0 0x295e0000 0x0 0x10000>; - clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>; - clock-names = "dphy_txesc"; - resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>, - <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>; - reset-names = "dphy_sys", "dphy_txbytehs"; - #phy-cells = <0>; - status = "disabled"; + edp: edp@29600000 { + compatible = "rockchip,rk3288-edp"; + reg = <0x0 0x29600000 0x0 0x4000>; + status = "okay"; + ports { + edp_in: port { + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + }; + }; + }; + + hdmi: hdmi@29590000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0x0 0x29590000 0x0 0x4000>; + status = "okay"; + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + }; + }; }; - mipi_dsi: mipi@295d0000 { - compatible = "cdns,dsi"; - reg = <0x0 0x295d0000 0x0 0x10000>; - reg-names = "dsi"; + lvds: lvds@ff96c000 { + compatible = "rockchip,rk3288-lvds"; + reg = <0x0 0xff96c000 0x0 0x4000>; + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + lvds_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + lvds_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + }; + }; + }; + + mipi_dsi0: mipi@295d0000 { + compatible = "starfive,sf_mipi_dsi"; + reg = <0x0 0x295d0000 0x0 0x10000>, + <0x0 0x295e0000 0x0 0x10000>, + <0x0 0x17010000 0x0 0x1000>; + reg-names = "dsi", "phy", "syscon"; clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>, <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>, - <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>; - clock-names = "sys", "apb", "txesc", "dpi"; + <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>, + <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>; + clock-names = "sys", "apb", "txesc", "dpi","dphy_txesc"; resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>, <&rstgen RSTN_U0_CDNS_DSITX_APB>, <&rstgen RSTN_U0_CDNS_DSITX_RXESC>, <&rstgen RSTN_U0_CDNS_DSITX_SYS>, <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>, - <&rstgen RSTN_U0_CDNS_DSITX_TXESC>; + <&rstgen RSTN_U0_CDNS_DSITX_TXESC>, + <&rstgen RSTN_U0_MIPITX_DPHY_SYS>, + <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>; reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc", - "dsi_sys", "dsi_txbytehs", "dsi_txesc"; - phys = <&mipi_dphy>; - phy-names = "dphy"; - status = "disabled"; + "dsi_sys", "dsi_txbytehs", "dsi_txesc", + "dphy_sys", "dphy_txbytehs"; - port { - dsi_out_port: endpoint { - /*remote-endpoint = <&panel_dsi_port>;*/ + status = "disabled"; + ports { + mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + mipi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi>; + }; }; }; + }; - mipi_panel: panel@0 { - /*compatible = "";*/ - status = "disabled"; - }; + dsi_host: dsi-host { + compatible = "starfive,mipi-dsi"; + status = "okay"; }; - hdmi: hdmi@29590000 { - compatible = "rockchip,rk3036-inno-hdmi"; - reg = <0x0 0x29590000 0x0 0x4000>; - /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/ - /*clocks = <&cru PCLK_HDMI>;*/ - /*clock-names = "pclk";*/ - /*pinctrl-names = "default";*/ - /*pinctrl-0 = <&hdmi_ctl>;*/ + hdmi_output: hdmi-output { + compatible = "verisilicon,hdmi-encoder"; + verisilicon,dss-syscon = <&dssctrl>; + verisilicon,mux-mask = <0x70 0x380>; + verisilicon,mux-val = <0x40 0x280>; + status = "disabled"; + }; + + mipi_dphy: mipi-dphy@295e0000{ + compatible = "starfive,jh7100-mipi-dphy-tx"; + reg = <0x0 0x295e0000 0x0 0x10000>; + clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>; + clock-names = "dphy_txesc"; + resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>, + <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>; + reset-names = "dphy_sys", "dphy_txbytehs"; + #phy-cells = <0>; status = "disabled"; - clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>, - <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>, - <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>; - clock-names = "sysclk", "mclk", "bclk"; - resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>; - reset-names = "hdmi_tx"; }; sound: snd-card { |