1 files changed, 89 insertions, 0 deletions
diff --git a/arch/riscv/dts/starfive_visionfive.dts b/arch/riscv/dts/starfive_visionfive.dts
new file mode 100644
index 0000000000..e5bb25042c
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "StarFive VisionFive V2";
+	compatible = "starfive,jh7110";
+
+	chosen {
+			stdout-path = "/soc/serial@10000000:115200";
+	};
+
+	aliases {
+		spi0="/soc/qspi@13010000";
+		gpio0="/soc/gpio@13040000";
+		ethernet0="/soc/gmac0@16030000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x1 0x0>;
+	};
+
+	soc {
+	};
+};
+
+&cpu0 {
+	status = "okay";
+};
+
+&clkgen {
+	clocks = <&osc>, <&gmac1_rmii_refin>,
+		<&stg_apb>, <&gmac0_rmii_refin>;
+	clock-names = "osc", "gmac1_rmii_refin",
+		"stg_apb", "gmac0_rmii_refin";
+};
+
+&sdio0 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+	bus-width = <8>;
+	status = "okay";
+};
+
+&sdio1 {
+	clock-frequency = <4000000>;
+	max-frequency = <1000000>;
+	bus-width = <4>;
+	status = "okay";
+};
+
+&gmac0 {
+	phy-reset-gpios = <&gpio 63 0>;
+	status = "okay";
+};
+
+&gpio {
+	compatible = "starfive,jh7110-gpio";
+	gpio-controller;
+};
+
+&uart0 {
+	reg-offset = <0>;
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&gpioa {
+	status = "disabled";
+};
+
+
+
+
+
+
+
+
+
+
+
+