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-rw-r--r--arch/riscv/dts/jh7110.dtsi6
-rw-r--r--arch/riscv/dts/jh7110_clk.dtsi19
2 files changed, 22 insertions, 3 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index a7952031ce..1b570148ef 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -785,12 +785,14 @@
"tx",
"ptp_ref",
"stmmaceth",
- "pclk";
+ "pclk",
+ "gtxc";
clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
<&clkgen JH7110_U0_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC0_PTP>,
<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
- <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
+ <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
+ <&clkgen JH7110_GMAC0_GTXC>;
resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
reset-names = "ahb", "stmmaceth";
diff --git a/arch/riscv/dts/jh7110_clk.dtsi b/arch/riscv/dts/jh7110_clk.dtsi
index d67134fa8a..fce9df8419 100644
--- a/arch/riscv/dts/jh7110_clk.dtsi
+++ b/arch/riscv/dts/jh7110_clk.dtsi
@@ -112,6 +112,23 @@
#clock-cells = <0>;
clock-frequency = <297000000>;
};
-
/* external clocks end */
+
+ pll0_out: pll0_out {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1000000000>;
+ };
+
+ pll1_out: pll1_out {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1066000000>;
+ };
+
+ pll2_out: pll2_out {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1228800000>;
+ };
};