diff options
Diffstat (limited to 'arch/riscv')
-rw-r--r-- | arch/riscv/dts/jh7110.dtsi | 12 | ||||
-rw-r--r-- | arch/riscv/dts/starfive_evb.dts | 15 |
2 files changed, 23 insertions, 4 deletions
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi index e353aeb25b..1022a08db5 100644 --- a/arch/riscv/dts/jh7110.dtsi +++ b/arch/riscv/dts/jh7110.dtsi @@ -354,21 +354,25 @@ usbdrd30: usbdrd{ compatible = "starfive,jh7110-cdns3"; + dma-coherent; #address-cells = <2>; #size-cells = <2>; - clocks = <&clkgen JH7110_USB0_CLK_APP_125>, + reg = <0x0 0x10210000 0x0 0x1000>, + <0x0 0x10200000 0x0 0x1000>; + clocks = <&clkgen JH7110_USB_125M>, + <&clkgen JH7110_USB0_CLK_APP_125>, <&clkgen JH7110_USB0_CLK_LPM>, <&clkgen JH7110_USB0_CLK_STB>, <&clkgen JH7110_USB0_CLK_USB_APB>, <&clkgen JH7110_USB0_CLK_AXI>, <&clkgen JH7110_USB0_CLK_UTMI_APB>; - clock-names = "app","lpm","stb","apb","axi","utmi"; + clock-names = "125m","app","lpm","stb","apb","axi","utmi"; resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>, <&rstgen RSTN_U0_CDN_USB_APB>, <&rstgen RSTN_U0_CDN_USB_AXI>, <&rstgen RSTN_U0_CDN_USB_UTMI_APB>; reset-names = "pwrup","apb","axi","utmi"; - starfive,stg-syscon = <&stg_syscon 0x4>; + starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>; starfive,sys-syscon = <&sys_syscon 0x18>; status = "disabled"; @@ -378,7 +382,7 @@ <0x0 0x10110000 0x0 0x10000>, <0x0 0x10120000 0x0 0x10000>; reg-names = "otg", "xhci", "dev"; - interrupts = <108>, <109>, <110>; + interrupts = <100>, <108>, <110>; interrupt-names = "host", "peripheral", "otg"; phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy"; maximum-speed = "super-speed"; diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts index 19b8e5f1e0..0ce86ad8bd 100644 --- a/arch/riscv/dts/starfive_evb.dts +++ b/arch/riscv/dts/starfive_evb.dts @@ -297,6 +297,21 @@ }; &usbdrd30 { + clocks = <&clkgen JH7110_USB_125M>, + <&clkgen JH7110_USB0_CLK_APP_125>, + <&clkgen JH7110_USB0_CLK_LPM>, + <&clkgen JH7110_USB0_CLK_STB>, + <&clkgen JH7110_USB0_CLK_USB_APB>, + <&clkgen JH7110_USB0_CLK_AXI>, + <&clkgen JH7110_USB0_CLK_UTMI_APB>, + <&clkgen JH7110_PCIE0_CLK_APB>; + clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy"; + resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>, + <&rstgen RSTN_U0_CDN_USB_APB>, + <&rstgen RSTN_U0_CDN_USB_AXI>, + <&rstgen RSTN_U0_CDN_USB_UTMI_APB>, + <&rstgen RSTN_U0_PLDA_PCIE_APB>; + reset-names = "pwrup","apb","axi","utmi", "phy"; status = "okay"; }; |