diff options
Diffstat (limited to 'arch/xtensa')
-rw-r--r-- | arch/xtensa/include/asm/arch-dc232b/core.h | 2 | ||||
-rw-r--r-- | arch/xtensa/include/asm/arch-dc232b/tie-asm.h | 4 | ||||
-rw-r--r-- | arch/xtensa/include/asm/arch-dc233c/core.h | 3 | ||||
-rw-r--r-- | arch/xtensa/include/asm/arch-dc233c/tie-asm.h | 4 | ||||
-rw-r--r-- | arch/xtensa/include/asm/arch-de212/core.h | 3 | ||||
-rw-r--r-- | arch/xtensa/include/asm/cacheasm.h | 2 |
6 files changed, 0 insertions, 18 deletions
diff --git a/arch/xtensa/include/asm/arch-dc232b/core.h b/arch/xtensa/include/asm/arch-dc232b/core.h index 92ea0dfe35..c1453f719e 100644 --- a/arch/xtensa/include/asm/arch-dc232b/core.h +++ b/arch/xtensa/include/asm/arch-dc232b/core.h @@ -127,8 +127,6 @@ #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ diff --git a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h index 7003cad40d..35a26dca7c 100644 --- a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h @@ -26,7 +26,6 @@ #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ - /* Macro to save all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). * Save area ptr (clobbered): ptr (1 byte aligned) @@ -109,11 +108,8 @@ .endif .endm // xchal_ncp_load - - #define XCHAL_NCP_NUM_ATMPS 2 - #define XCHAL_SA_NUM_ATMPS 2 #endif /*_XTENSA_CORE_TIE_ASM_H*/ diff --git a/arch/xtensa/include/asm/arch-dc233c/core.h b/arch/xtensa/include/asm/arch-dc233c/core.h index ca07d8ee21..4646cdbfb4 100644 --- a/arch/xtensa/include/asm/arch-dc233c/core.h +++ b/arch/xtensa/include/asm/arch-dc233c/core.h @@ -149,13 +149,10 @@ #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- diff --git a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h index 317d4e1312..7b3d1f3c57 100644 --- a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h +++ b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h @@ -31,8 +31,6 @@ | ((ccuse) & XTHAL_SAS_ANYCC) \ | ((abi) & XTHAL_SAS_ANYABI) ) - - /* * Macro to save all non-coprocessor (extra) custom TIE and optional state * (not including zero-overhead loop registers). @@ -164,8 +162,6 @@ #define XCHAL_NCP_NUM_ATMPS 1 - - #define XCHAL_SA_NUM_ATMPS 1 #endif /*_XTENSA_CORE_TIE_ASM_H*/ diff --git a/arch/xtensa/include/asm/arch-de212/core.h b/arch/xtensa/include/asm/arch-de212/core.h index 7268692d0e..443fd459ca 100644 --- a/arch/xtensa/include/asm/arch-de212/core.h +++ b/arch/xtensa/include/asm/arch-de212/core.h @@ -206,13 +206,10 @@ #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ - - /**************************************************************************** Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code ****************************************************************************/ - #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY /*---------------------------------------------------------------------- diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h index 6d321f8866..69448cfff7 100644 --- a/arch/xtensa/include/asm/cacheasm.h +++ b/arch/xtensa/include/asm/cacheasm.h @@ -134,7 +134,6 @@ .endm - .macro ___flush_invalidate_dcache_range ar as at #if XCHAL_DCACHE_SIZE @@ -171,7 +170,6 @@ .endm - .macro ___flush_invalidate_dcache_page ar as #if XCHAL_DCACHE_SIZE |