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-rw-r--r--arch/riscv/Kconfig10
-rw-r--r--arch/riscv/dts/Makefile3
-rw-r--r--arch/riscv/dts/jh7110-u-boot.dtsi8
-rw-r--r--arch/riscv/dts/jh7110.dtsi64
-rw-r--r--arch/riscv/dts/starfive_devkits-u-boot.dtsi (renamed from arch/riscv/dts/starfive_visionfive-u-boot.dtsi)9
-rw-r--r--arch/riscv/dts/starfive_devkits.dts371
-rw-r--r--arch/riscv/dts/starfive_evb.dts2
-rw-r--r--arch/riscv/dts/starfive_visionfive.dts104
-rw-r--r--arch/riscv/dts/starfive_visionfive2-u-boot.dtsi45
-rw-r--r--arch/riscv/dts/starfive_visionfive2.dts477
-rw-r--r--arch/riscv/include/asm/arch-jh7110/eeprom.h14
11 files changed, 972 insertions, 135 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 2cff0d9536..b8adf6ba36 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -23,8 +23,11 @@ config TARGET_SIFIVE_UNLEASHED
config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board"
-config TARGET_STARFIVE_VISIONFIVE
- bool "Support StarFive VisionFive Board"
+config TARGET_STARFIVE_DEVKITS
+ bool "Support StarFive DevKits Board"
+
+config TARGET_STARFIVE_VISIONFIVE2
+ bool "Support StarFive VisionFive2 Board"
config TARGET_STARFIVE_EVB
bool "Support StarFive Evb Board"
@@ -71,7 +74,8 @@ source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
-source "board/starfive/visionfive/Kconfig"
+source "board/starfive/devkits/Kconfig"
+source "board/starfive/visionfive2/Kconfig"
source "board/starfive/evb/Kconfig"
# platform-specific options below
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index d433afa6f4..79679c91ad 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -7,7 +7,8 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE) += starfive_visionfive.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_DEVKITS) += starfive_devkits.dtb
+dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += starfive_visionfive2.dtb
dtb-$(CONFIG_TARGET_STARFIVE_EVB) += starfive_evb.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index e45b6cde3b..37586fdc15 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -129,3 +129,11 @@
&gmac0_rmii_refin {
u-boot,dm-spl;
};
+
+&gpio {
+ u-boot,dm-spl;
+};
+
+&gpioa {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 3f3098b96b..d8f62454fd 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -623,19 +623,6 @@
status = "disabled";
};
- i2c6: i2c@12060000 {
- compatible = "snps,designware-i2c";
- reg = <0x0 0x12060000 0x0 0x10000>;
- clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
- <&clkgen JH7110_I2C6_CLK_APB>;
- clock-names = "ref", "pclk";
- resets = <&rstgen RSTN_U6_DW_I2C_APB>;
- interrupts = <51>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
i2c0: i2c@10030000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x10030000 0x0 0x10000>;
@@ -675,6 +662,32 @@
status = "disabled";
};
+ i2c3: i2c@12030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12030000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
+ <&clkgen JH7110_I2C3_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U3_DW_I2C_APB>;
+ interrupts = <48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@12040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12040000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
+ <&clkgen JH7110_I2C4_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U4_DW_I2C_APB>;
+ interrupts = <49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c5: i2c@12050000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x12050000 0x0 0x10000>;
@@ -688,6 +701,19 @@
status = "disabled";
};
+ i2c6: i2c@12060000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12060000 0x0 0x10000>;
+ clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
+ <&clkgen JH7110_I2C6_CLK_APB>;
+ clock-names = "ref", "pclk";
+ resets = <&rstgen RSTN_U6_DW_I2C_APB>;
+ interrupts = <51>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
/* unremovable emmc as mmcblk0 */
sdio0: sdio0@16010000 {
compatible = "snps,dw-mshc";
@@ -856,13 +882,15 @@
"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
<&clkgen JH7110_U0_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC0_PTP>,
<&clkgen JH7110_U0_GMAC5_CLK_AHB>,
<&clkgen JH7110_U0_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC0_GTXC>;
+ <&clkgen JH7110_GMAC0_GTXC>,
+ <&clkgen JH7110_GMAC0_RMII_RTX>;
resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
<&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
reset-names = "ahb", "stmmaceth";
@@ -897,13 +925,15 @@
"ptp_ref",
"stmmaceth",
"pclk",
- "gtxc";
+ "gtxc",
+ "rmii_rtx";
clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
<&clkgen JH7110_GMAC5_CLK_TX>,
<&clkgen JH7110_GMAC5_CLK_PTP>,
<&clkgen JH7110_GMAC5_CLK_AHB>,
<&clkgen JH7110_GMAC5_CLK_AXI>,
- <&clkgen JH7110_GMAC1_GTXC>;
+ <&clkgen JH7110_GMAC1_GTXC>,
+ <&clkgen JH7110_GMAC1_RMII_RTX>;
resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
<&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
reset-names = "ahb", "stmmaceth";
diff --git a/arch/riscv/dts/starfive_visionfive-u-boot.dtsi b/arch/riscv/dts/starfive_devkits-u-boot.dtsi
index a3efa43b5e..f508ab3554 100644
--- a/arch/riscv/dts/starfive_visionfive-u-boot.dtsi
+++ b/arch/riscv/dts/starfive_devkits-u-boot.dtsi
@@ -27,12 +27,3 @@
};
};
-&sdio0 {
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
-};
-
-&sdio1 {
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
-}; \ No newline at end of file
diff --git a/arch/riscv/dts/starfive_devkits.dts b/arch/riscv/dts/starfive_devkits.dts
new file mode 100644
index 0000000000..489a8f90be
--- /dev/null
+++ b/arch/riscv/dts/starfive_devkits.dts
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+#include <dt-bindings/gpio/gpio.h>
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "StarFive JH7110 DevKits";
+ compatible = "starfive,jh7110";
+
+ aliases {
+ spi0="/soc/spi@13010000";
+ gpio0="/soc/gpio@13040000";
+ ethernet0=&gmac0;
+ ethernet1=&gmac1;
+ mmc0=&sdio0;
+ mmc1=&sdio1;
+ i2c5=&i2c5;
+ };
+
+ chosen {
+ stdout-path = "/soc/serial@10000000:115200";
+ starfive,boot-hart-id = <1>;
+ };
+
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ soc {
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&cpu0 {
+ status = "okay";
+};
+
+&clkgen {
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&stg_apb>, <&gmac0_rmii_refin>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "stg_apb", "gmac0_rmii_refin";
+};
+
+&gpio {
+ status = "okay";
+ gpio-controller;
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ pinmux = <GPIOMUX(22, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins1 {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins2 {
+ pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins3 {
+ pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins4 {
+ pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins5 {
+ pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ hdmi_pins: hdmi-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
+ GPOEN_SYS_HDMI_DDC_SCL,
+ GPI_SYS_HDMI_DDC_SCL)>,
+ <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
+ GPOEN_SYS_HDMI_DDC_SDA,
+ GPI_SYS_HDMI_DDC_SDA)>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ cec-pins {
+ pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
+ GPOEN_SYS_HDMI_CEC_SDA,
+ GPI_SYS_HDMI_CEC_SDA)>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ hpd-pins {
+ pinmux = <GPIOMUX(15, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_HDMI_HPD)>;
+ input-enable;
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+
+ seeed_panel: seeed_panel@45 {
+ compatible = "starfive,seeed";
+ reg = <0x45>;
+ sel-gpios = <&ext_gpio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ lt8911exb_i2c@29 {
+ compatible = "lontium,lt8911exb";
+ reg = <0x29>;
+ reset-gpios = <&gpio 41 1>;
+ pwm-gpios = <&gpio 33 1>;
+ bl-gpios = <&ext_gpio 6 GPIO_ACTIVE_LOW>;
+
+ };
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+
+ pmic_axp15060: axp15060_reg@36 {
+ compatible = "stf,axp15060-regulator";
+ reg = <0x36>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ ext_gpio: ext_gpio@74 {
+ compatible = "ti,tca9539";
+ reg = <0x74>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&sdio0 {
+ assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ fifo-depth = <32>;
+ bus-width = <4>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+};
+
+&sdio1 {
+ assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ fifo-depth = <32>;
+ bus-width = <4>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+};
+
+&gmac0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ rxc_dly_en = <0>;
+ rx_delay_sel = <0xb>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0xa>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x1>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ rgmii_sw_dr_2 = <0x0>;
+ rgmii_sw_dr = <0x3>;
+ rgmii_sw_dr_rxc = <0x7>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0>;
+ rxc_dly_en = <0>;
+ rx_delay_sel = <0x2>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x0>;
+ };
+};
+
+&uart0 {
+ reg-offset = <0>;
+ current-speed = <115200>;
+ status = "okay";
+};
+
+&gpioa {
+ status = "disabled";
+};
+
+&usbdrd30 {
+ clocks = <&clkgen JH7110_USB_125M>,
+ <&clkgen JH7110_USB0_CLK_APP_125>,
+ <&clkgen JH7110_USB0_CLK_LPM>,
+ <&clkgen JH7110_USB0_CLK_STB>,
+ <&clkgen JH7110_USB0_CLK_USB_APB>,
+ <&clkgen JH7110_USB0_CLK_AXI>,
+ <&clkgen JH7110_USB0_CLK_UTMI_APB>,
+ <&clkgen JH7110_PCIE0_CLK_APB>;
+ clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
+ resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
+ <&rstgen RSTN_U0_CDN_USB_APB>,
+ <&rstgen RSTN_U0_CDN_USB_AXI>,
+ <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
+ <&rstgen RSTN_U0_PLDA_PCIE_APB>;
+ reset-names = "pwrup","apb","axi","utmi", "phy";
+ starfive,usb2-only = <0>;
+ status = "okay";
+};
+
+&usbdrd_cdns3 {
+ dr_mode = "unknown";
+ dr_num_mode = <1>;
+};
+
+&timer {
+ status = "disabled";
+};
+
+&wdog {
+ status = "disabled";
+};
+
+&clkvout {
+ status = "okay";
+};
+
+&pdm {
+ status = "disabled";
+};
+
+&dc8200 {
+ status = "okay";
+};
+&mipi_dsi0 {
+ status = "okay";
+ rockchip,panel = <&seeed_panel>;
+ data-lanes-num = <1>;
+ status = "okay";
+};
+
+&hdmi{
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ power-gpios = <&ext_gpio 0 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
diff --git a/arch/riscv/dts/starfive_evb.dts b/arch/riscv/dts/starfive_evb.dts
index b62f79b362..2241073470 100644
--- a/arch/riscv/dts/starfive_evb.dts
+++ b/arch/riscv/dts/starfive_evb.dts
@@ -399,7 +399,7 @@
status = "okay";
rm68200_panel: rm68200_panel@45 {
- compatible = "raydium,rm68200";
+ compatible = "starfive,seeed";
reg = <0x45>;
};
diff --git a/arch/riscv/dts/starfive_visionfive.dts b/arch/riscv/dts/starfive_visionfive.dts
deleted file mode 100644
index 70eb2567b8..0000000000
--- a/arch/riscv/dts/starfive_visionfive.dts
+++ /dev/null
@@ -1,104 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-/*
- * Copyright (C) 2022 StarFive Technology Co., Ltd.
- */
-
-/dts-v1/;
-
-#include "jh7110.dtsi"
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "StarFive VisionFive V2";
- compatible = "starfive,jh7110";
-
- aliases {
- spi0="/soc/spi@13010000";
- gpio0="/soc/gpio@13040000";
- ethernet0="/soc/ethernet@16030000";
- mmc0="/soc/sdio0@16010000";
- mmc1="/soc/sdio1@16020000";
- };
-
- chosen {
- stdout-path = "/soc/serial@10000000:115200";
- };
-
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x40000000 0x1 0x0>;
- };
-
- soc {
- };
-};
-
-&cpu0 {
- status = "okay";
-};
-
-&clkgen {
- clocks = <&osc>, <&gmac1_rmii_refin>,
- <&stg_apb>, <&gmac0_rmii_refin>;
- clock-names = "osc", "gmac1_rmii_refin",
- "stg_apb", "gmac0_rmii_refin";
-};
-
-&sdio0 {
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
- bus-width = <8>;
- status = "okay";
-};
-
-&sdio1 {
- clock-frequency = <4000000>;
- max-frequency = <1000000>;
- bus-width = <4>;
- status = "okay";
-};
-
-&gmac0 {
- phy-reset-gpios = <&gpio 63 0>;
- status = "okay";
-};
-
-&gpio {
- compatible = "starfive,jh7110-gpio";
- gpio-controller;
-};
-
-&uart0 {
- reg-offset = <0>;
- current-speed = <115200>;
- status = "okay";
-};
-
-&gpioa {
- status = "disabled";
-};
-
-&usbdrd30 {
- status = "okay";
-};
-
-&usbdrd_cdns3 {
- dr_mode = "host";
-};
-
-&timer {
- status = "disabled";
-};
-
-&wdog {
- status = "disabled";
-};
-
-&clkvout {
- status = "disabled";
-};
-
-&pdm {
- status = "disabled";
-};
diff --git a/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
new file mode 100644
index 0000000000..7da12cf29f
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive2-u-boot.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include "jh7110-u-boot.dtsi"
+/ {
+ chosen {
+ stdout-path = "/soc/serial@10000000:115200";
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ spi0="/soc/qspi@11860000";
+ u-boot,dm-spl;
+ };
+
+ config {
+ u-boot,dm-spl;
+ u-boot,spl-payload-offset = <0x100000>; /* loader2 @1044KB */
+ };
+
+ memory@80000000 {
+ u-boot,dm-spl;
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+ u-boot,dm-spl;
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ u-boot,dm-spl;
+ };
+};
diff --git a/arch/riscv/dts/starfive_visionfive2.dts b/arch/riscv/dts/starfive_visionfive2.dts
new file mode 100644
index 0000000000..ec8538d9dd
--- /dev/null
+++ b/arch/riscv/dts/starfive_visionfive2.dts
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "jh7110.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "StarFive VisionFive V2";
+ compatible = "starfive,jh7110";
+
+ aliases {
+ spi0="/soc/spi@13010000";
+ gpio0="/soc/gpio@13040000";
+ ethernet0=&gmac0;
+ ethernet1=&gmac1;
+ mmc0=&sdio0;
+ mmc1=&sdio1;
+ i2c0 = &i2c5;
+ };
+
+ chosen {
+ stdout-path = "/soc/serial@10000000:115200";
+ starfive,boot-hart-id = <1>;
+ };
+
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ reserved-memory {
+ #size-cells = <2>;
+ #address-cells = <2>;
+ ranges;
+
+ opensbi {
+ reg = <0x00 0x40000000 0x00 0x80000>;
+ no-map;
+ };
+ };
+
+ soc {
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&cpu0 {
+ status = "okay";
+};
+
+&clkgen {
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&stg_apb>, <&gmac0_rmii_refin>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "stg_apb", "gmac0_rmii_refin";
+};
+
+&gpio {
+ status = "okay";
+ gpio-controller;
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE, GPI_SYS_UART0_RX)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ mmc0_pins: mmc0-pins {
+ mmc0-pins-rest {
+ pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ sdcard1_pins: sdcard1-pins {
+ sdcard1-pins0 {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE, GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins1 {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD, GPI_SYS_SDIO1_CMD)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins2 {
+ pinmux = <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0, GPI_SYS_SDIO1_DATA0)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins3 {
+ pinmux = <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1, GPI_SYS_SDIO1_DATA1)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins4 {
+ pinmux = <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2, GPI_SYS_SDIO1_DATA2)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ sdcard1-pins5 {
+ pinmux = <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3, GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_perst_default: pcie0_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_perst_active: pcie0_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_default: pcie1_perst_default {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_perst_active: pcie1_perst_active {
+ perst-pins {
+ pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ hdmi_pins: hdmi-0 {
+
+
+ cec-pins {
+ pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
+ GPOEN_SYS_HDMI_CEC_SDA,
+ GPI_SYS_HDMI_CEC_SDA)>;
+ bias-pull-up;
+ input-enable;
+ };
+
+ hpd-pins {
+ pinmux = <GPIOMUX(15, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_HDMI_HPD)>;
+ input-enable;
+ };
+ };
+};
+
+&sdio0 {
+ assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ fifo-depth = <32>;
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&sdio1 {
+ assigned-clocks = <&clkgen JH7110_SDIO1_CLK_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ fifo-depth = <32>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdcard1_pins>;
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy0: ethernet-phy@0 {
+ rgmii_sw_dr_2 = <0x0>;
+ rgmii_sw_dr = <0x3>;
+ rgmii_sw_dr_rxc = <0x6>;
+ rxc_dly_en = <0>;
+ rx_delay_sel = <0xa>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0xa>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x1>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@1 {
+ rgmii_sw_dr_2 = <0x0>;
+ rgmii_sw_dr = <0x3>;
+ rgmii_sw_dr_rxc = <0x6>;
+ tx_delay_sel_fe = <5>;
+ tx_delay_sel = <0>;
+ rxc_dly_en = <0>;
+ rx_delay_sel = <0x2>;
+ tx_inverted_10 = <0x1>;
+ tx_inverted_100 = <0x1>;
+ tx_inverted_1000 = <0x0>;
+ };
+};
+
+&uart0 {
+ reg-offset = <0>;
+ current-speed = <115200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ status = "okay";
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ pmic: axp15060_reg@36 {
+ compatible = "stf,axp15060-regulator";
+ reg = <0x36>;
+ };
+
+};
+
+&gpioa {
+ status = "disabled";
+};
+
+&usbdrd30 {
+ starfive,usb2-only = <1>;
+ status = "okay";
+};
+
+&usbdrd_cdns3 {
+ dr_mode = "peripheral";
+};
+
+&pcie0 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie0_perst_default>;
+ pinctrl-1 = <&pcie0_perst_active>;
+ pinctrl-2 = <&pcie0_wake_default>;
+ pinctrl-3 = <&pcie0_clkreq_default>;
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+ pinctrl-0 = <&pcie1_perst_default>;
+ pinctrl-1 = <&pcie1_perst_active>;
+ pinctrl-2 = <&pcie1_wake_default>;
+ pinctrl-3 = <&pcie1_clkreq_default>;
+ status = "okay";
+};
+
+&timer {
+ status = "disabled";
+};
+
+&wdog {
+ status = "disabled";
+};
+
+&clkvout {
+ status = "okay";
+};
+
+&pdm {
+ status = "disabled";
+};
+
+&mipi_dsi0 {
+ status = "okay";
+ rockchip,panel = <&rm68200_panel>;
+ data-lanes-num = <1>;
+ display-timings {
+ timing0 {
+ bits-per-pixel = <24>;
+ clock-frequency = <160000000>;
+ hfront-porch = <120>;
+ hsync-len = <20>;
+ hback-porch = <21>;
+ hactive = <1200>;
+ vfront-porch = <21>;
+ vsync-len = <3>;
+ vback-porch = <18>;
+ vactive = <1920>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+
+};
+
+&hdmi{
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <3000>;
+ i2c-scl-falling-time-ns = <3000>;
+ auto_calc_scl_lhcnt;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+
+ rm68200_panel: rm68200_panel@45 {
+ compatible = "starfive,seeed";
+ reg = <0x45>;
+
+ };
+
+
+};
+
diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h
new file mode 100644
index 0000000000..bae918f153
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 StarFive Technology Co., Ltd.
+ *
+ * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
+ */
+
+#ifndef _ASM_RISCV_EEPROM_H
+#define _ASM_RISCV_EEPROM_H
+
+u8 get_pcb_revision_from_eeprom(void);
+int get_data_from_eeprom(int offset, int len, unsigned char *data);
+
+#endif /* _ASM_RISCV_EEPROM_H */
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-29 14:06:32 +0300