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-rw-r--r--arch/riscv/cpu/cpu.c3
-rw-r--r--arch/riscv/cpu/start.S5
-rw-r--r--arch/riscv/dts/binman.dtsi6
3 files changed, 3 insertions, 11 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 8e49b6d736..8d90c5e6b8 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -17,9 +17,6 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
-#ifdef CONFIG_OF_PRIOR_STAGE
-phys_addr_t prior_stage_fdt_address __section(".data");
-#endif
#ifndef CONFIG_XIP
u32 hart_lottery __section(".data") = 0;
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 308b0a97a5..76850ec9be 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -142,11 +142,6 @@ call_harts_early_init:
bnez tp, secondary_hart_loop
#endif
-#ifdef CONFIG_OF_PRIOR_STAGE
- la t0, prior_stage_fdt_address
- SREG s1, 0(t0)
-#endif
-
jal board_init_f_init_reserve
SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index d26cfdb78a..5757ef65ea 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -48,7 +48,7 @@
};
};
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@fdt-SEQ {
description = "NAME";
type = "flat_dt";
@@ -60,7 +60,7 @@
configurations {
default = "conf-1";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
@conf-SEQ {
#else
conf-1 {
@@ -68,7 +68,7 @@
description = "NAME";
firmware = "opensbi";
loadables = "uboot";
-#ifndef CONFIG_OF_PRIOR_STAGE
+#ifndef CONFIG_OF_BOARD
fdt = "fdt-SEQ";
#endif
};