diff options
Diffstat (limited to 'arch')
40 files changed, 2345 insertions, 105 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 02f8306f15..b4808d4c75 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -82,8 +82,6 @@ config GICV3 config GIC_V3_ITS bool "ARM GICV3 ITS" - select REGMAP - select SYSCON select IRQ help ARM GICV3 Interrupt translation service (ITS). @@ -922,6 +920,27 @@ config ARCH_NEXELL select DM select GPIO_EXTRA_HEADER +config ARCH_APPLE + bool "Apple SoCs" + select ARM64 + select BLK + select CLK + select CMD_USB + select DM + select DM_KEYBOARD + select DM_SERIAL + select DM_USB + select DM_VIDEO + select IOMMU + select LINUX_KERNEL_IMAGE_HEADER + select OF_CONTROL + select OF_BOARD + select POSITION_INDEPENDENT + select USB + imply CMD_DM + imply CMD_GPT + imply DISTRO_DEFAULTS + config ARCH_OWL bool "Actions Semi OWL SoCs" select DM @@ -2018,6 +2037,8 @@ config ISW_ENTRY_ADDR image headers. endif +source "arch/arm/mach-apple/Kconfig" + source "arch/arm/mach-aspeed/Kconfig" source "arch/arm/mach-at91/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 6c9a00c5a4..ad757e982e 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -55,6 +55,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y) # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_APPLE) += apple machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_BCM283X) += bcm283x diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9820d3290e..a08ed3f544 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -41,27 +41,36 @@ DECLARE_GLOBAL_DATA_PTR; #endif #ifdef CONFIG_GIC_V3_ITS -int ls_gic_rd_tables_init(void *blob) +#define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K) +#define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K) +#define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \ + PROPTABLE_MAX_SZ, SZ_1M) +static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size) { - struct fdt_memory lpi_base; - fdt_addr_t addr; - fdt_size_t size; - int offset, ret; + int err; + struct fdt_memory gic_rd_tables; - offset = fdt_path_offset(gd->fdt_blob, "/syscon@0x80000000"); - addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, offset, "reg", - 0, &size, false); + gic_rd_tables.start = base; + gic_rd_tables.end = base + size - 1; + err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables, + NULL, 0, NULL, 0); + if (err < 0) + debug("%s: failed to add reserved memory: %d\n", __func__, err); - lpi_base.start = addr; - lpi_base.end = addr + size - 1; - ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, - 0, NULL, 0); - if (ret) { - debug("%s: failed to add reserved memory\n", __func__); + return err; +} + +int ls_gic_rd_tables_init(void *blob) +{ + u64 gic_lpi_base; + int ret; + + gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K); + ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE); + if (ret) return ret; - } - ret = gic_lpi_tables_init(); + ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores()); if (ret) debug("%s: failed to init gic-lpi-tables\n", __func__); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a88aecc5bd..cc34da7bd8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -28,6 +28,13 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5800-peach-pi.dtb \ exynos5422-odroidxu3.dtb dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb +dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb + +dtb-$(CONFIG_ARCH_APPLE) += \ + t8103-j274.dtb \ + t8103-j293.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ da850-evm.dtb \ @@ -473,6 +480,7 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb +dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb diff --git a/arch/arm/dts/exynos78x0-axy17lte.dts b/arch/arm/dts/exynos78x0-axy17lte.dts new file mode 100644 index 0000000000..7fae8db874 --- /dev/null +++ b/arch/arm/dts/exynos78x0-axy17lte.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos78x0 SoC device tree source + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + */ + +/dts-v1/; +#include "exynos78x0.dtsi" +/ { + compatible = "samsung,exynos78x0", "samsung,exynos7880", "samsung,exynos7870"; + + aliases { + console = &uart2; + }; + + chosen { + stdout-path = &uart2; + }; +}; + +&gpioi2c0 { + status = "okay"; +}; + +&fin_pll { + clock-frequency = <26000000>; +}; + diff --git a/arch/arm/dts/exynos78x0-gpio.dtsi b/arch/arm/dts/exynos78x0-gpio.dtsi new file mode 100644 index 0000000000..a7f75c5ca9 --- /dev/null +++ b/arch/arm/dts/exynos78x0-gpio.dtsi @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* ALIVE */ + gpio@139F0000 { + etc0: etc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + etc1: etc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa2: gpa2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpa3: gpa3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpq0: gpq0 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* CCORE */ + gpio@10630000 { + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* DISP/AUD */ + gpio@148C0000 { + gpz0: gpz0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpz1: gpz1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpz2: gpz2 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* FSYS0 */ + gpio@13750000 { + gpr0: gpr0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr1: gpr1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr2: gpr2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr3: gpr3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpr4: gpr4 { + gpio-controller; + #gpio-cells = <2>; + }; + }; + + /* TOP */ + gpio@139B0000 { + gpb0: gpb0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc4: gpc4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc5: gpc5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc6: gpc6 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc8: gpc8 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpc9: gpc9 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd2: gpd2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd3: gpd3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd4: gpd4 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpd5: gpd5 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpe0: gpe0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf3: gpf3 { + gpio-controller; + #gpio-cells = <2>; + }; + + gpf4: gpf4 { + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; diff --git a/arch/arm/dts/exynos78x0-pinctrl.dtsi b/arch/arm/dts/exynos78x0-pinctrl.dtsi new file mode 100644 index 0000000000..4958c55119 --- /dev/null +++ b/arch/arm/dts/exynos78x0-pinctrl.dtsi @@ -0,0 +1,280 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung's Exynos7880 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + * + * Samsung's Exynos7880 SoC pin-mux and pin-config options are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* ALIVE */ + pinctrl@139F0000 { + uart2_bus: uart2-bus { + samsung,pins = "gpa1-1", "gpa1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + dwmmc2_cd_ext_irq: dwmmc2_cd_ext_irq { + samsung,pins = "gpa3-3"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + key_power: key-power { + samsung,pins = "gpa0-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_voldown: key-voldown { + samsung,pins = "gpa2-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_volup: key-volup { + samsung,pins = "gpa2-0"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + key_home: key-home { + samsung,pins = "gpa1-7"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + }; + + /* TOP */ + pinctrl@139B0000 { + i2c0_bus: i2c0-bus { + samsung,pins = "gpc1-1", "gpc1-0"; + samsung,pin-function = <2>; + }; + + sd0_rst: sd0_rst { + samsung,pins = "gpc0-2"; + samsung,pin-function = <0>; + }; + }; + + /* DISP/AUD */ + pinctrl@148C0000 { + i2s_pmic_bus: i2s-pmic-bus { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + i2s_pmic_bus_idle: i2s-pmic-bus_idle { + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3", "gpz1-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + }; + + /* FSYS0 */ + pinctrl@13750000 { + sd0_clk: sd0-clk { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpr0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpr0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_1x: sd0-clk_fast_slew_rate_1x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd0_clk_fast_slew_rate_2x: sd0-clk_fast_slew_rate_2x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd0_clk_fast_slew_rate_3x: sd0-clk_fast_slew_rate_3x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd0_clk_fast_slew_rate_4x: sd0-clk_fast_slew_rate_4x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_clk_fast_slew_rate_5x: sd0-clk_fast_slew_rate_5x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd0_clk_fast_slew_rate_6x: sd0-clk_fast_slew_rate_6x { + samsung,pins = "gpr0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <5>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpr1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpr2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpr2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpr3-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpr4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpr4-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpr4-3", "gpr4-4", "gpr4-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <2>; + }; + + sd2_clk_output: sd2-clk-output { + samsung,pins = "gpr4-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_cmd_output: sd2-cmd-output { + samsung,pins = "gpr4-1"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_1x: sd2-clk_fast_slew_rate_1x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + sd2_clk_fast_slew_rate_2x: sd2-clk_fast_slew_rate_2x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <1>; + }; + + sd2_clk_fast_slew_rate_3x: sd2-clk_fast_slew_rate_3x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <2>; + }; + + sd2_clk_fast_slew_rate_4x: sd2-clk_fast_slew_rate_4x { + samsung,pins = "gpr4-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + }; +}; diff --git a/arch/arm/dts/exynos78x0.dtsi b/arch/arm/dts/exynos78x0.dtsi new file mode 100644 index 0000000000..fb9c9cbdf9 --- /dev/null +++ b/arch/arm/dts/exynos78x0.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos7880 SoC device tree source + * + * Copyright (c) 2020 Dzmitry Sankouski (dsankouski@gmail.com) + */ + +/dts-v1/; +#include "skeleton.dtsi" +#include "exynos78x0-pinctrl.dtsi" +#include "exynos78x0-gpio.dtsi" +/ { + compatible = "samsung,exynos7880"; + + fin_pll: xxti { + compatible = "fixed-clock"; + clock-output-names = "fin_pll"; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + /* Dummy clock for uart */ + fin_uart: uart_dummy_fin { + compatible = "fixed-clock"; + clock-output-names = "fin_uart"; + clock-frequency = <132710400>; + u-boot,dm-pre-reloc; + #clock-cells = <0>; + }; + + uart2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + u-boot,dm-pre-reloc; + clocks = <&fin_uart>, <&fin_uart>; // driver uses 1st clock + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_bus>; + }; + + gpioi2c0: i2c-0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + status = "disabled"; + gpios = < + &gpc1 0 0 /* sda */ + &gpc1 1 0 /* scl */ + >; + i2c-gpio,delay-us = <5>; + + s2mu004@3d { + compatible = "samsung,s2mu004mfd"; + }; + }; + + /* ALIVE */ + pinctrl_0: pinctrl@139F0000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x139F0000 0x1000>; + }; + + /* DISP/AUD */ + pinctrl_2: pinctrl@148C0000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x148C0000 0x1000>; + }; + + /* FSYS0 */ + pinctrl_4: pinctrl@13750000 { + compatible = "samsung,exynos78x0-pinctrl"; + reg = <0x13750000 0x1000>; + }; + + /* ALIVE */ + gpio_0: gpio@139F0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x139F0000 0x1000>; + }; + + /* DISP/AUD */ + gpio_2: gpio@148C0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x148C0000 0x1000>; + }; + + /* FSYS0 */ + gpio_4: gpio@13750000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x13750000 0x1000>; + }; + + /* TOP */ + gpio_6: gpio@139B0000 { + compatible = "samsung,exynos78x0-gpio"; + reg = <0x139B0000 0x1000>; + }; +}; diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 50f9b527cd..53b052ed32 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -44,12 +44,6 @@ IRQ_TYPE_LEVEL_LOW)>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <2>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 64caa600ad..3a5a50fb83 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -27,12 +27,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <8>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 7374d580e0..278daeeb6e 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -27,12 +27,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x100000>; - max-gic-redistributors = <8>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index a6f0e9bc56..3b5f0d119e 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -43,12 +43,6 @@ interrupts = <1 9 0x4>; }; - gic_lpi_base: syscon@0x80000000 { - compatible = "gic-lpi-base"; - reg = <0x0 0x80000000 0x0 0x200000>; - max-gic-redistributors = <16>; - }; - timer { compatible = "arm,armv8-timer"; interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi new file mode 100644 index 0000000000..1185b71216 --- /dev/null +++ b/arch/arm/dts/sdm845.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 chip device tree source + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * + */ + +/dts-v1/; + +#include "skeleton64.dtsi" + +/ { + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + gcc: clock-controller@100000 { + u-boot,dm-pre-reloc; + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + gpio_north: gpio_north@3900000 { + u-boot,dm-pre-reloc; + #gpio-cells = <2>; + compatible = "qcom,sdm845-pinctrl"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + gpio-ranges = <&gpio_north 0 0 150>; + gpio-bank-name = "soc_north."; + }; + + tlmm_north: pinctrl_north@3900000 { + u-boot,dm-pre-reloc; + compatible = "qcom,tlmm-sdm845"; + reg = <0x3900000 0x400000>; + gpio-count = <150>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm_north 0 0 150>; + + /* DEBUG UART */ + qup_uart9: qup-uart9-default { + pinmux { + pins = "GPIO_4", "GPIO_5"; + function = "qup9"; + }; + }; + }; + + debug_uart: serial@a84000 { + compatible = "qcom,msm-geni-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se_phys"; + clock-names = "se-clk"; + clocks = <&gcc 0x58>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9>; + qcom,wrapper-core = <0x8a>; + status = "disabled"; + }; + + spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>; + reg-names = "cnfg", "core", "obsrvr"; + #address-cells = <0x1>; + #size-cells = <0x1>; + + qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + pmic0: pm8998@0 { + compatible = "qcom,spmi-pmic"; + reg = <0x0 0x1>; + #address-cells = <0x1>; + #size-cells = <0x1>; + + pm8998_pon: pm8998_pon@800 { + compatible = "qcom,pm8998-pwrkey"; + reg = <0x800 0x100>; + #gpio-cells = <2>; + gpio-controller; + gpio-bank-name = "pm8998_key."; + }; + + pm8998_gpios: pm8998_gpios@c000 { + compatible = "qcom,pm8998-gpio"; + reg = <0xc000 0x1a00>; + gpio-controller; + gpio-count = <21>; + #gpio-cells = <2>; + gpio-bank-name = "pm8998."; + }; + }; + + pmic1: pm8998@1 { + compatible = "qcom,spmi-pmic"; + reg = <0x1 0x0>; + #address-cells = <0x2>; + #size-cells = <0x0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi new file mode 100644 index 0000000000..d8d75e018a --- /dev/null +++ b/arch/arm/dts/starqltechn-uboot.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot addition to handle Samsung S9 SM-G9600 (starqltechn) pins + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * + */ + +/ +{ + soc { + u-boot,dm-pre-reloc; + gcc { + clock-controller@100000 { + u-boot,dm-pre-reloc; + }; + serial@0xa84000 { + u-boot,dm-pre-reloc; + }; + gpio_north@3900000 { + u-boot,dm-pre-reloc; + }; + pinctrl@3900000 { + u-boot,dm-pre-reloc; + }; + }; + }; +}; + +&pm8998_pon { + key_vol_down { + gpios = <&pm8998_pon 1 0>; + label = "key_vol_down"; + }; + key_power { + gpios = <&pm8998_pon 0 0>; + label = "key_power"; + }; +}; diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts new file mode 100644 index 0000000000..387420f30b --- /dev/null +++ b/arch/arm/dts/starqltechn.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung S9 SM-G9600 (starqltechn) board device tree source + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * + */ + +/dts-v1/; + +#include "sdm845.dtsi" + +/ { + model = "Samsung S9 (SM-G9600)"; + compatible = "qcom,sdm845-mtp", "qcom,sdm845", "qcom,mtp"; + #address-cells = <2>; + #size-cells = <2>; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + aliases { + serial0 = &debug_uart; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000 0 0xfe1bffff>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + serial@0xa84000 { + status = "ok"; + }; + + pinctrl@3900000 { + muic_i2c: muic_i2c { + pins = "GPIO_33", "GPIO_34"; + drive-strength = <0x2>; + function = "gpio"; + bias-disable; + }; + }; + }; +}; + +#include "starqltechn-uboot.dtsi" diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts new file mode 100644 index 0000000000..aef1ae29b6 --- /dev/null +++ b/arch/arm/dts/t8103-j274.dts @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple Mac mini (M1, 2020) + * + * target-type: J274 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" + +/ { + compatible = "apple,j274", "apple,t8103", "apple,arm-platform"; + model = "Apple Mac mini (M1, 2020)"; + + aliases { + serial0 = &serial0; + ethernet0 = ð0; + wifi0 = &wifi0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +&pcie0_dart_0 { + status = "okay"; +}; + +&pcie0_dart_1 { + status = "okay"; +}; + +&pcie0_dart_2 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + pci0: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + pwren-gpios = <&smc 13 0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci1: pci@1,0 { + device_type = "pci"; + reg = <0x800 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 153 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; + + pci2: pci@2,0 { + device_type = "pci"; + reg = <0x1000 0x0 0x0 0x0 0x0>; + reset-gpios = <&pinctrl_ap 33 0>; + max-link-speed = <1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&pci0 { + wifi0: network@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + local-mac-address = [00 00 00 00 00 00]; + }; +}; + +&pci2 { + eth0: ethernet@0,0 { + reg = <0x30000 0x0 0x0 0x0 0x0>; + local-mac-address = [00 00 00 00 00 00]; + }; +}; + +&dwc3_0_dart_0 { + status = "okay"; +}; + +&dwc3_0_dart_1 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; +}; + +&dwc3_1_dart_0 { + status = "okay"; +}; + +&dwc3_1_dart_1 { + status = "okay"; +}; + +&dwc3_1 { + status = "okay"; +}; diff --git a/arch/arm/dts/t8103-j293.dts b/arch/arm/dts/t8103-j293.dts new file mode 100644 index 0000000000..4a22596cf4 --- /dev/null +++ b/arch/arm/dts/t8103-j293.dts @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple Macbook Pro (M1, 2020) + * + * target-type: J293 + * + * Copyright The Asahi Linux Contributors + */ + +/dts-v1/; + +#include "t8103.dtsi" + +/ { + compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; + model = "Apple Macbook Pro (M1, 2020)"; + + aliases { + serial0 = &serial0; + wifi0 = &wifi0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0x2 0>; /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; + +&pcie0_dart_0 { + status = "okay"; +}; + +&pcie0 { + status = "okay"; + + pci0: pci@0,0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + pwren-gpios = <&smc 13 0>; + reset-gpios = <&pinctrl_ap 152 0>; + max-link-speed = <2>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&pci0 { + wifi0: network@0,0 { + reg = <0x10000 0x0 0x0 0x0 0x0>; + local-mac-address = [00 00 00 00 00 00]; + }; +}; + +&dwc3_0_dart_0 { + status = "okay"; +}; + +&dwc3_0_dart_1 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; +}; + +&dwc3_1_dart_0 { + status = "okay"; +}; + +&dwc3_1_dart_1 { + status = "okay"; +}; + +&dwc3_1 { + status = "okay"; +}; diff --git a/arch/arm/dts/t8103.dtsi b/arch/arm/dts/t8103.dtsi new file mode 100644 index 0000000000..7d9cb272f9 --- /dev/null +++ b/arch/arm/dts/t8103.dtsi @@ -0,0 +1,560 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8103 "M1" SoC + * + * Other names: H13G, "Tonga" + * + * Copyright The Asahi Linux Contributors + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/apple-aic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/apple.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + compatible = "apple,t8103", "apple,arm-platform"; + + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu1: cpu@1 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu2: cpu@2 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu3: cpu@3 { + compatible = "apple,icestorm"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu4: cpu@10100 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10100>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu5: cpu@10101 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10101>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu6: cpu@10102 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10102>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + + cpu7: cpu@10103 { + compatible = "apple,firestorm"; + device_type = "cpu"; + reg = <0x0 0x10103>; + enable-method = "spin-table"; + cpu-release-addr = <0 0>; /* To be filled by loader */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "hyp-phys", "hyp-virt", "phys", "virt"; + interrupts = <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, + <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; + }; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges; + dma-ranges; + dma-coherent; + nonposted-mmio; + + serial0: serial@235200000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35200000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkref>, <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + serial2: serial@235208000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x35208000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 607 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkref>, <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0", "clk_uart_baud1"; + power-domains = <&ps_uart2>; + status = "disabled"; + }; + + aic: interrupt-controller@23b100000 { + compatible = "apple,t8103-aic", "apple,aic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x2 0x3b100000 0x0 0x8000>; + }; + + pmgr: power-controller@23b700000 { + compatible = "apple,t8103-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0x2 0x3b700000 0x0 0x14000>; + + ps_pcie_ref: power-controller@1a0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1a0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "pcie_ref"; + }; + + ps_imx: power-controller@1b8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1b8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "imx"; + apple,always-on; + }; + + ps_sio: power-controller@1c0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x1c0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "sio"; + }; + + ps_uart_p: power-controller@220 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x220>; + #power-domain-cells = <0>; + #reset-cells = <0>; + power-domains = <&ps_sio>; + apple,domain-name = "uart_p"; + }; + + ps_uart0: power-controller@270 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x270>; + #power-domain-cells = <0>; + #reset-cells = <0>; + power-domains = <&ps_uart_p>; + apple,domain-name = "uart0"; + }; + + ps_uart1: power-controller@278 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x278>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart1"; + power-domains = <&ps_uart_p>; + }; + + ps_uart2: power-controller@280 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x280>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart2"; + power-domains = <&ps_uart_p>; + }; + + ps_uart3: power-controller@288 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x288>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "uart3"; + power-domains = <&ps_uart_p>; + }; + + ps_apcie: power-controller@348 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x348>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "apcie"; + power-domains = <&ps_imx>; + }; + + ps_apcie_gp: power-controller@3e8 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3e8>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "apcie_gp"; + power-domains = <&ps_apcie>; + }; + + ps_ans2: power-controller@3f0 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x3f0>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "ans2"; + power-domains = <&ps_apcie_st>; + }; + + ps_apcie_st: power-controller@418 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x418>; + #power-domain-cells = <0>; + #reset-cells = <0>; + apple,domain-name = "apcie_st"; + power-domains = <&ps_apcie>; + }; + }; + + pinctrl_ap: pinctrl@23c100000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 212>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins: i2c0_pins { + pinmux = <APPLE_PINMUX(188, 1)>, + <APPLE_PINMUX(192, 1)>; + }; + + pcie_pins: pcie-pins { + pinmux = <APPLE_PINMUX(150, 1)>, + <APPLE_PINMUX(151, 1)>, + <APPLE_PINMUX(32, 1)>; + }; + }; + + pinctrl_aop: pinctrl@24a820000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x4a820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 42>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_nub: pinctrl@23d1f0000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3d1f0000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 23>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; + }; + + pinctrl_smc: pinctrl@23e820000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3e820000 0x0 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 16>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; + }; + + i2c0: i2c@20a110000 { + compatible = "apple,i2c-v0"; + reg = <0x2 0x35010000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 627 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkref>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + #address-cells = <0x1>; + #size-cells = <0x0>; + + hpm0: hpm@38 { + compatible = "ti,tps6598x"; + reg = <0x38>; + }; + + hpm1: hpm@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + }; + }; + + ans_mbox: mbox@277400000 { + compatible = "apple,iop-mailbox-m1"; + reg = <0x2 0x77400000 0x0 0x20000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 583 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 586 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_ans2>; + #mbox-cells = <1>; + endpoints = <32>; + }; + + ans@27bcc0000 { + compatible = "apple,nvme-m1"; + reg = <0x2 0x7bcc0000 0x0 0x40000>, + <0x2 0x7bc50000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 590 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&ps_apcie_st>; + mboxes = <&ans_mbox 32>; + }; + + pcie0_dart_0: iommu@681008000 { + compatible = "apple,t8103-dart", "apple,dart-m1"; + reg = <0x6 0x81008000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + pcie0_dart_1: iommu@682008000 { + compatible = "apple,t8103-dart", "apple,dart-m1"; + reg = <0x6 0x82008000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + pcie0_dart_2: iommu@683008000 { + compatible = "apple,t8103-dart", "apple,dart-m1"; + reg = <0x6 0x83008000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + smc_mbox: mbox@23e400000 { + compatible = "apple,iop-mailbox-m1"; + reg = <0x2 0x3e400000 0x0 0x20000>; + #mbox-cells = <1>; + endpoints = <32>; + }; + + smc: smc@23e050000 { + compatible = "apple,smc-m1"; + reg = <0x2 0x3e050000 0x0 0x4000>; + mboxes = <&smc_mbox 32>; + gpio-controller; + #gpio-cells = <2>; + gpio-13 = <0x00800000>; + }; + + pcie0: pcie@690000000 { + compatible = "apple,t8103-pcie", "apple,pcie"; + + reg = <0x6 0x90000000 0x0 0x1000000>, + <0x6 0x80000000 0x0 0x4000>, + <0x6 0x81000000 0x0 0x8000>, + <0x6 0x82000000 0x0 0x8000>, + <0x6 0x83000000 0x0 0x8000>; + reg-names = "config", "rc", "port0", "port1", "port2"; + + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; + + msi-controller; + msi-parent = <&pcie0>; + msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; + + iommu-map = <0x100 &pcie0_dart_0 1 1>, + <0x200 &pcie0_dart_1 1 1>, + <0x300 &pcie0_dart_2 1 1>; + iommu-map-mask = <0xff00>; + + bus-range = <0 3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 + 0x0 0x20000000>, + <0x02000000 0x0 0xc0000000 0x6 0xc0000000 + 0x0 0x40000000>; + + power-domains = <&ps_apcie>, <&ps_apcie_gp>, <&ps_pcie_ref>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + + device_type = "pci"; + status = "disabled"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible = "apple,t8103-dart"; + reg = <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 781 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + dwc3_0: usb@382280000{ + compatible = "snps,dwc3"; + reg = <0x3 0x82280000 0x0 0x100000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 777 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + iommus = <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + status = "disabled"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible = "apple,t8103-dart"; + reg = <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 861 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + dwc3_1: usb@502280000{ + compatible = "snps,dwc3"; + reg = <0x5 0x02280000 0x0 0x100000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 857 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + iommus = <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + status = "disabled"; + }; + + reboot@23d2b0000 { + compatible = "apple,reboot-v0"; + reg = <0x2 0x3d2b0000 0x0 0x4000>; + }; + + spi@23510c000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 617 IRQ_TYPE_LEVEL_HIGH>; + cs-gpios = <&pinctrl_ap 49 GPIO_ACTIVE_HIGH>; + }; + + spmi@23d0d8000 { + compatible = "apple,t8103-spmi", "apple,spmi"; + reg = <0x2 0x3d0d9300 0x0 0x100>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 343 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <2>; + #size-cells = <0>; + + pmu@f { + compatible = "apple,sera-pmu"; + reg = <0xf SPMI_USID>; + }; + }; + }; +}; diff --git a/arch/arm/include/asm/arch-m1/uart.h b/arch/arm/include/asm/arch-m1/uart.h new file mode 100644 index 0000000000..d2a17a221e --- /dev/null +++ b/arch/arm/include/asm/arch-m1/uart.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 Samsung Electronics + * Minkyu Kang <mk7.kang@samsung.com> + * Heungjun Kim <riverful.kim@samsung.com> + */ + +#ifndef __ASM_ARCH_UART_H_ +#define __ASM_ARCH_UART_H_ + +#ifndef __ASSEMBLY__ +/* baudrate rest value */ +union br_rest { + unsigned short slot; /* udivslot */ + unsigned char value; /* ufracval */ +}; + +struct s5p_uart { + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; + unsigned int utxh; + unsigned int urxh; + unsigned int ubrdiv; + union br_rest rest; + unsigned char res3[0x3fd0]; +}; + +static inline int s5p_uart_divslot(void) +{ + return 0; +} + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/arm/include/asm/gic-v3.h b/arch/arm/include/asm/gic-v3.h index 35efec78c3..5131fabec4 100644 --- a/arch/arm/include/asm/gic-v3.h +++ b/arch/arm/include/asm/gic-v3.h @@ -127,9 +127,9 @@ #define GIC_REDISTRIBUTOR_OFFSET 0x20000 #ifdef CONFIG_GIC_V3_ITS -int gic_lpi_tables_init(void); +int gic_lpi_tables_init(u64 base, u32 max_redist); #else -int gic_lpi_tables_init(void) +int gic_lpi_tables_init(u64 base, u32 max_redist) { return 0; } diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index 2d3fdb600e..f6211a2d92 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -5,8 +5,6 @@ #include <common.h> #include <cpu_func.h> #include <dm.h> -#include <regmap.h> -#include <syscon.h> #include <asm/gic.h> #include <asm/gic-v3.h> #include <asm/io.h> @@ -19,22 +17,15 @@ static u32 lpi_id_bits; #define LPI_PROPBASE_SZ ALIGN(BIT(LPI_NRBITS), SZ_64K) #define LPI_PENDBASE_SZ ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K) -/* Number of GIC re-distributors */ -#define MAX_GIC_REDISTRIBUTORS 8 - /* * gic_v3_its_priv - gic details * * @gicd_base: gicd base address * @gicr_base: gicr base address - * @lpi_base: gic lpi base address - * @num_redist: number of gic re-distributors */ struct gic_v3_its_priv { ulong gicd_base; ulong gicr_base; - ulong lpi_base; - u32 num_redist; }; static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv) @@ -68,39 +59,13 @@ static int gic_v3_its_get_gic_addr(struct gic_v3_its_priv *priv) return 0; } -static int gic_v3_its_get_gic_lpi_addr(struct gic_v3_its_priv *priv) -{ - struct regmap *regmap; - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_SYSCON, - DM_DRIVER_GET(gic_lpi_syscon), &dev); - if (ret) { - pr_err("%s: failed to get %s syscon device\n", __func__, - DM_DRIVER_GET(gic_lpi_syscon)->name); - return ret; - } - - regmap = syscon_get_regmap(dev); - if (!regmap) { - pr_err("%s: failed to regmap for %s syscon device\n", __func__, - DM_DRIVER_GET(gic_lpi_syscon)->name); - return -ENODEV; - } - priv->lpi_base = regmap->ranges[0].start; - - priv->num_redist = dev_read_u32_default(dev, "max-gic-redistributors", - MAX_GIC_REDISTRIBUTORS); - - return 0; -} - /* * Program the GIC LPI configuration tables for all * the re-distributors and enable the LPI table + * base: Configuration table address + * num_redist: number of redistributors */ -int gic_lpi_tables_init(void) +int gic_lpi_tables_init(u64 base, u32 num_redist) { struct gic_v3_its_priv priv; u32 gicd_typer; @@ -109,15 +74,12 @@ int gic_lpi_tables_init(void) int i; u64 redist_lpi_base; u64 pend_base; - ulong pend_tab_total_sz; + ulong pend_tab_total_sz = num_redist * LPI_PENDBASE_SZ; void *pend_tab_va; if (gic_v3_its_get_gic_addr(&priv)) return -EINVAL; - if (gic_v3_its_get_gic_lpi_addr(&priv)) - return -EINVAL; - gicd_typer = readl((uintptr_t)(priv.gicd_base + GICD_TYPER)); /* GIC support for Locality specific peripheral interrupts (LPI's) */ if (!(gicd_typer & GICD_TYPER_LPIS)) { @@ -130,7 +92,7 @@ int gic_lpi_tables_init(void) * Once the LPI table is enabled, can not program the * LPI configuration tables again, unless the GIC is reset. */ - for (i = 0; i < priv.num_redist; i++) { + for (i = 0; i < num_redist; i++) { u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; if ((readl((uintptr_t)(priv.gicr_base + offset))) & @@ -146,7 +108,7 @@ int gic_lpi_tables_init(void) ITS_MAX_LPI_NRBITS); /* Set PropBase */ - val = (priv.lpi_base | + val = (base | GICR_PROPBASER_INNERSHAREABLE | GICR_PROPBASER_RAWAWB | ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); @@ -163,8 +125,7 @@ int gic_lpi_tables_init(void) } } - redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ; - pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ; + redist_lpi_base = base + LPI_PROPBASE_SZ; pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz, MAP_NOCACHE); memset(pend_tab_va, 0, pend_tab_total_sz); @@ -172,7 +133,7 @@ int gic_lpi_tables_init(void) unmap_physmem(pend_tab_va, MAP_NOCACHE); pend_base = priv.gicr_base + GICR_PENDBASER; - for (i = 0; i < priv.num_redist; i++) { + for (i = 0; i < num_redist; i++) { u32 offset = i * GIC_REDISTRIBUTOR_OFFSET; val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) | @@ -207,14 +168,3 @@ U_BOOT_DRIVER(arm_gic_v3_its) = { .id = UCLASS_IRQ, .of_match = gic_v3_its_ids, }; - -static const struct udevice_id gic_lpi_syscon_ids[] = { - { .compatible = "gic-lpi-base" }, - {} -}; - -U_BOOT_DRIVER(gic_lpi_syscon) = { - .name = "gic-lpi-base", - .id = UCLASS_SYSCON, - .of_match = gic_lpi_syscon_ids, -}; diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig new file mode 100644 index 0000000000..66cab91b2a --- /dev/null +++ b/arch/arm/mach-apple/Kconfig @@ -0,0 +1,18 @@ +if ARCH_APPLE + +config SYS_TEXT_BASE + default 0x00000000 + +config SYS_CONFIG_NAME + default "apple" + +config SYS_SOC + default "m1" + +config SYS_MALLOC_LEN + default 0x4000000 + +config SYS_MALLOC_F_LEN + default 0x4000 + +endif diff --git a/arch/arm/mach-apple/Makefile b/arch/arm/mach-apple/Makefile new file mode 100644 index 0000000000..e74a8c9df1 --- /dev/null +++ b/arch/arm/mach-apple/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += board.o +obj-y += lowlevel_init.o diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c new file mode 100644 index 0000000000..0bfbc473ec --- /dev/null +++ b/arch/arm/mach-apple/board.c @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +#include <common.h> +#include <dm.h> +#include <efi_loader.h> + +#include <asm/armv8/mmu.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/system.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region apple_mem_map[] = { + { + /* I/O */ + .virt = 0x200000000, + .phys = 0x200000000, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x500000000, + .phys = 0x500000000, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x680000000, + .phys = 0x680000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x6a0000000, + .phys = 0x6a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x6c0000000, + .phys = 0x6c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x800000000, + .phys = 0x800000000, + .size = 8UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Empty entry for framebuffer */ + 0, + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = apple_mem_map; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + ofnode node; + int index, ret; + fdt_addr_t base; + fdt_size_t size; + + ret = fdtdec_setup_mem_size_base(); + if (ret) + return ret; + + /* Update RAM mapping */ + index = ARRAY_SIZE(apple_mem_map) - 3; + apple_mem_map[index].virt = gd->ram_base; + apple_mem_map[index].phys = gd->ram_base; + apple_mem_map[index].size = gd->ram_size; + + node = ofnode_path("/chosen/framebuffer"); + if (!ofnode_valid(node)) + return 0; + + base = ofnode_get_addr_size(node, "reg", &size); + if (base == FDT_ADDR_T_NONE) + return 0; + + /* Add framebuffer mapping */ + index = ARRAY_SIZE(apple_mem_map) - 2; + apple_mem_map[index].virt = base; + apple_mem_map[index].phys = base; + apple_mem_map[index].size = size; + apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#define APPLE_WDT_BASE 0x23d2b0000ULL + +#define APPLE_WDT_SYS_CTL_ENABLE BIT(2) + +typedef struct apple_wdt { + u32 reserved0[3]; + u32 chip_ctl; + u32 sys_tmr; + u32 sys_cmp; + u32 reserved1; + u32 sys_ctl; +} apple_wdt_t; + +void reset_cpu(void) +{ + apple_wdt_t *wdt = (apple_wdt_t *)APPLE_WDT_BASE; + + writel(0, &wdt->sys_cmp); + writel(APPLE_WDT_SYS_CTL_ENABLE, &wdt->sys_ctl); + + while(1) + wfi(); +} + +extern long fw_dtb_pointer; + +void *board_fdt_blob_setup(int *err) +{ + /* Return DTB pointer passed by m1n1 */ + *err = 0; + return (void *)fw_dtb_pointer; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + /* + * Top part of RAM is used by firmware for things like the + * framebuffer. This gives us plenty of room to play with. + */ + return 0x980000000; +} diff --git a/arch/arm/mach-apple/lowlevel_init.S b/arch/arm/mach-apple/lowlevel_init.S new file mode 100644 index 0000000000..e1c0d91cef --- /dev/null +++ b/arch/arm/mach-apple/lowlevel_init.S @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org> + */ + +.align 8 +.global fw_dtb_pointer +fw_dtb_pointer: + .quad 0 + +.global save_boot_params +save_boot_params: + /* Stash DTB pointer passed by m1n1 */ + adr x1, fw_dtb_pointer + str x0, [x1] + + b save_boot_params_ret diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 7df0e17617..7f3aee5712 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -151,6 +151,33 @@ config TARGET_ESPRESSO7420 select PINCTRL_EXYNOS7420 select SUPPORT_SPL +config TARGET_A5Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS78x0 + select SUPPORT_SPL + +config TARGET_A7Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS78x0 + select SUPPORT_SPL + +config TARGET_A3Y17LTE + bool "Samsung SM-A520F board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS7880 + select SUPPORT_SPL + endchoice endif @@ -167,6 +194,7 @@ source "board/samsung/arndale/Kconfig" source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" +source "board/samsung/axy17lte/Kconfig" config SPL_LDSCRIPT default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 46b8169d19..e3bd995143 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -29,3 +29,69 @@ static struct mm_region exynos7420_mem_map[] = { struct mm_region *mem_map = exynos7420_mem_map; #endif + +#ifdef CONFIG_EXYNOS7870 +static struct mm_region exynos7870_mem_map[] = { + { + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x3E400000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + + { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = exynos7870_mem_map; +#endif + +#ifdef CONFIG_EXYNOS7880 +static struct mm_region exynos7880_mem_map[] = { + { + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x3E400000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + + { + /* List terminator */ + }, +}; + +struct mm_region *mem_map = exynos7880_mem_map; +#endif diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index cad3f0a488..73c4b9af3e 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -199,8 +199,8 @@ u32 spl_boot_device(void) return BOOT_DEVICE_MMC1; #endif #ifdef CONFIG_SPL_SATA - case BOOT_FROM_SATA: - return BOOT_FROM_SATA; + case BOOT_DEVICE_SATA: + return BOOT_DEVICE_SATA; #endif #ifdef CONFIG_SPL_SPI_FLASH_SUPPORT case BOOT_DEVICE_SPI: diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0ec74fa5d3..12cf02a56a 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,6 +9,14 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000 +config SDM845 + bool "Qualcomm Snapdragon 845 SoC" + default n + select LINUX_KERNEL_IMAGE_HEADER + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default 0x80000000 + choice prompt "Snapdragon board select" @@ -36,9 +44,22 @@ config TARGET_DRAGONBOARD820C - 3GiB RAM - 32GiB UFS drive +config TARGET_STARQLTECHN + bool "Samsung S9 SM-G9600(starqltechn)" + help + Support for Samsung S9 SM-G9600(starqltechn) board. + Features: + - Qualcomm Snapdragon SDM845 SoC + - 4GiB RAM + - 64GiB UFS drive + select MISC_INIT_R + select SDM845 + select DM_ETH if NET + endchoice source "board/qualcomm/dragonboard410c/Kconfig" source "board/qualcomm/dragonboard820c/Kconfig" +source "board/samsung/starqltechn/Kconfig" endif diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 709919fce4..962855eb8c 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,6 +2,9 @@ # # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> +obj-$(CONFIG_SDM845) += clock-sdm845.o +obj-$(CONFIG_SDM845) += sysmap-sdm845.o +obj-$(CONFIG_SDM845) += init_sdm845.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o @@ -12,3 +15,4 @@ obj-y += dram.o obj-y += pinctrl-snapdragon.o obj-y += pinctrl-apq8016.o obj-y += pinctrl-apq8096.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c new file mode 100644 index 0000000000..9572639238 --- /dev/null +++ b/arch/arm/mach-snapdragon/clock-sdm845.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm SDM845 + * + * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org> + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * + * Based on Little Kernel driver, simplified + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/io.h> +#include <linux/bitops.h> +#include "clock-snapdragon.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +struct freq_tbl { + uint freq; + uint src; + u8 pre_div; + u16 m; + u16 n; +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75), + F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75), + { } +}; + +static const struct bcr_regs uart2_regs = { + .cfg_rcgr = SE9_UART_APPS_CFG_RCGR, + .cmd_rcgr = SE9_UART_APPS_CMD_RCGR, + .M = SE9_UART_APPS_M, + .N = SE9_UART_APPS_N, + .D = SE9_UART_APPS_D, +}; + +const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate) +{ + if (!f) + return NULL; + + if (!f->freq) + return f; + + for (; f->freq; f++) + if (rate <= f->freq) + return f; + + /* Default to our fastest rate */ + return f - 1; +} + +static int clk_init_uart(struct msm_clk_priv *priv, uint rate) +{ + const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + + clk_rcg_set_rate_mnd(priv->base, &uart2_regs, + freq->pre_div, freq->m, freq->n, freq->src); + + return 0; +} + +ulong msm_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + switch (clk->id) { + case 0x58: /*UART2*/ + return clk_init_uart(priv, rate); + default: + return 0; + } +} diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index 2b76371718..3deb08ac4a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -135,6 +135,7 @@ static const struct udevice_id msm_clk_ids[] = { { .compatible = "qcom,gcc-apq8016" }, { .compatible = "qcom,gcc-msm8996" }, { .compatible = "qcom,gcc-apq8096" }, + { .compatible = "qcom,gcc-sdm845" }, { } }; diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 58fab40a2e..2ac53b538d 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Qualcomm APQ8016, APQ8096 + * Qualcomm APQ8016, APQ8096, SDM845 * * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> */ @@ -9,6 +9,7 @@ #define CFG_CLK_SRC_CXO (0 << 8) #define CFG_CLK_SRC_GPLL0 (1 << 8) +#define CFG_CLK_SRC_GPLL0_EVEN (6 << 8) #define CFG_CLK_SRC_MASK (7 << 8) struct pll_vote_clk { diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h new file mode 100644 index 0000000000..7165985bcd --- /dev/null +++ b/arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Qualcomm SDM845 sysmap + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + */ +#ifndef _MACH_SYSMAP_SDM845_H +#define _MACH_SYSMAP_SDM845_H + +#define TLMM_BASE_ADDR (0x1010000) + +/* Strength (sdc1) */ +#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) + +/* Clocks: (from CLK_CTL_BASE) */ +#define GPLL0_STATUS (0x0000) +#define APCS_GPLL_ENA_VOTE (0x52000) +#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004) + +#define SDCC2_BCR (0x14000) /* block reset */ +#define SDCC2_APPS_CBCR (0x14004) /* branch control */ +#define SDCC2_AHB_CBCR (0x14008) +#define SDCC2_CMD_RCGR (0x1400c) +#define SDCC2_CFG_RCGR (0x14010) +#define SDCC2_M (0x14014) +#define SDCC2_N (0x14018) +#define SDCC2_D (0x1401C) + +#define RCG2_CFG_REG 0x4 +#define M_REG 0x8 +#define N_REG 0xc +#define D_REG 0x10 + +#define SE9_AHB_CBCR (0x25004) +#define SE9_UART_APPS_CBCR (0x29004) +#define SE9_UART_APPS_CMD_RCGR (0x18148) +#define SE9_UART_APPS_CFG_RCGR (0x1814C) +#define SE9_UART_APPS_M (0x18150) +#define SE9_UART_APPS_N (0x18154) +#define SE9_UART_APPS_D (0x18158) + +#endif diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c new file mode 100644 index 0000000000..5f53c21947 --- /dev/null +++ b/arch/arm/mach-snapdragon/init_sdm845.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Common init part for boards based on SDM845 + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + */ + +#include <init.h> +#include <env.h> +#include <common.h> +#include <asm/system.h> +#include <asm/gpio.h> +#include <dm.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +void reset_cpu(void) +{ + psci_system_reset(); +} + +__weak int board_init(void) +{ + return 0; +} + +/* Check for vol- and power buttons */ +__weak int misc_init_r(void) +{ + struct udevice *pon; + struct gpio_desc resin; + int node, ret; + + ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon); + if (ret < 0) { + printf("Failed to find PMIC pon node. Check device tree\n"); + return 0; + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_vol_down"); + if (node < 0) { + printf("Failed to find key_vol_down node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_vol_down button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_vol_down", "1"); + printf("Volume down button pressed\n"); + } else { + env_set("key_vol_down", "0"); + } + + node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon), + "key_power"); + if (node < 0) { + printf("Failed to find key_power node. Check device tree\n"); + return 0; + } + if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0, + &resin, 0)) { + printf("Failed to request key_power button.\n"); + return 0; + } + if (dm_gpio_get_value(&resin)) { + env_set("key_power", "1"); + printf("Power button pressed\n"); + } else { + env_set("key_power", "0"); + } + + return 0; +} diff --git a/arch/arm/mach-snapdragon/pinctrl-sdm845.c b/arch/arm/mach-snapdragon/pinctrl-sdm845.c new file mode 100644 index 0000000000..40f2f012fa --- /dev/null +++ b/arch/arm/mach-snapdragon/pinctrl-sdm845.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 pinctrl + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com> + * + */ + +#include "pinctrl-snapdragon.h" +#include <common.h> + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + {"qup9", 1}, + {"gpio", 0}, +}; + +static const char *sdm845_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sdm845_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector); + return pin_name; +} + +static unsigned int sdm845_get_function_mux(unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +struct msm_pinctrl_data sdm845_data = { + .pin_count = 150, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sdm845_get_function_name, + .get_function_mux = sdm845_get_function_mux, + .get_pin_name = sdm845_get_pin_name, +}; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index e6b87c3573..d1c560dd40 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -116,6 +116,9 @@ static struct pinctrl_ops msm_pinctrl_ops = { static const struct udevice_id msm_pinctrl_ids[] = { { .compatible = "qcom,tlmm-apq8016", .data = (ulong)&apq8016_data }, { .compatible = "qcom,tlmm-apq8096", .data = (ulong)&apq8096_data }, +#ifdef CONFIG_SDM845 + { .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data }, +#endif { } }; diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h index 61d466f4d8..ea524312a0 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h @@ -27,5 +27,6 @@ struct pinctrl_function { extern struct msm_pinctrl_data apq8016_data; extern struct msm_pinctrl_data apq8096_data; +extern struct msm_pinctrl_data sdm845_data; #endif diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c new file mode 100644 index 0000000000..721ac41166 --- /dev/null +++ b/arch/arm/mach-snapdragon/sysmap-sdm845.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Qualcomm SDM845 memory map + * + * (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com> + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region sdm845_mem_map[] = { + { + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ + .size = 0x200000000UL, /* 8GiB - maximum allowed memory */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = sdm845_mem_map; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index e27d106466..8cd688e8d2 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -764,6 +764,11 @@ vss-microvolts = <0>; }; + iommu: iommu@0 { + compatible = "sandbox,iommu"; + #iommu-cells = <0>; + }; + irq: irq { compatible = "sandbox,irq"; interrupt-controller; @@ -1226,6 +1231,7 @@ usb_1: usb@1 { compatible = "sandbox,usb"; + iommus = <&iommu>; hub { compatible = "usb-hub"; usb,device-class = <9>; |