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-rw-r--r--arch/arm/cpu/armv7m/cache.c5
-rw-r--r--arch/arm/cpu/armv8/sec_firmware.c2
-rw-r--r--arch/arm/dts/Makefile3
-rw-r--r--arch/arm/dts/mt8518-ap1-emmc.dts104
-rw-r--r--arch/arm/dts/mt8518.dtsi98
-rw-r--r--arch/arm/mach-davinci/Kconfig1
-rw-r--r--arch/arm/mach-davinci/include/mach/sdmmc_defs.h6
-rw-r--r--arch/arm/mach-mediatek/Kconfig10
-rw-r--r--arch/arm/mach-mediatek/Makefile1
-rw-r--r--arch/arm/mach-mediatek/mt8518/Makefile4
-rw-r--r--arch/arm/mach-mediatek/mt8518/init.c71
-rw-r--r--arch/arm/mach-mediatek/mt8518/lowlevel_init.S32
-rw-r--r--arch/arm/mach-rockchip/Kconfig2
-rw-r--r--arch/arm/mach-rockchip/bootrom.c4
-rw-r--r--arch/arm/mach-rockchip/rk3399/Kconfig6
-rw-r--r--arch/arm/mach-rockchip/spl-boot-order.c2
16 files changed, 336 insertions, 15 deletions
diff --git a/arch/arm/cpu/armv7m/cache.c b/arch/arm/cpu/armv7m/cache.c
index 6dc2ca8e73..f4ba3ad50e 100644
--- a/arch/arm/cpu/armv7m/cache.c
+++ b/arch/arm/cpu/armv7m/cache.c
@@ -332,6 +332,11 @@ void icache_disable(void)
isb(); /* subsequent instructions fetch see cache disable effect */
}
#else
+void invalidate_icache_all(void)
+{
+ return;
+}
+
void icache_enable(void)
{
return;
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 11f9b4df38..4dcda70b91 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -354,7 +354,7 @@ bool sec_firmware_support_hwrng(void)
return true;
#endif
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
- return true;
+ return true;
}
return false;
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d8846df1bd..3dc9c4d41c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,7 +835,8 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
- mt8516-pumpkin.dtb
+ mt8516-pumpkin.dtb \
+ mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 0000000000..f017ee4431
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+/dts-v1/;
+
+#include <config.h>
+#include "mt8518.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8518 AP1 EMMC";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&pinctrl {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 0000000000..c2d17fda4a
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ *
+ */
+
+#include <dt-bindings/clock/mt8518-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0xc000000 0x40000>, /* GICD */
+ <0xc100000 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>,
+ <&topckgen CLK_TOP_CLK32K>,
+ <&topckgen CLK_TOP_APXGPT>;
+ clock-names = "clk13m",
+ "clk32k",
+ "bus";
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8518-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ mmc0: mmc@11120000 {
+ compatible = "mediatek,mt8516-mmc";
+ reg = <0x11120000 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_MSDC0>,
+ <&topckgen CLK_TOP_MSDC0>,
+ <&topckgen CLK_TOP_MSDC0_B>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11005000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11005000 0x1000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART0_SEL>,
+ <&topckgen CLK_TOP_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index adc50922c8..8a81c07881 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -14,6 +14,7 @@ config TARGET_OMAPL138_LCDK
bool "OMAPL138 LCDK"
select SOC_DA8XX
select SUPPORT_SPL
+ select SPL_BOARD_INIT
config TARGET_LEGOEV3
bool "LEGO MINDSTORMS EV3"
diff --git a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
index 5755c45f91..46f6391aa2 100644
--- a/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
+++ b/arch/arm/mach-davinci/include/mach/sdmmc_defs.h
@@ -149,15 +149,9 @@ struct davinci_mmc {
uint input_clk; /* Input clock to MMC controller */
uint host_caps; /* Host capabilities */
uint voltages; /* Host supported voltages */
- uint version; /* MMC Controller version */
struct mmc_config cfg;
};
-enum {
- MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
- MMC_CTLR_VERSION_2, /* DA830 */
-};
-
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
#endif /* _SDMMC_DEFS_H */
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef7651f0..ad453a60c1 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,10 +38,20 @@ config TARGET_MT8516
Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
chip and several DDR3 and DDR4 options.
+config TARGET_MT8518
+ bool "MediaTek MT8518 SoC"
+ select ARM64
+ help
+ The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
+ chip and several DDR3 and DDR4 options.
+
endchoice
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
+source "board/mediatek/mt8518/Kconfig"
source "board/mediatek/pumpkin/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc407..b9b2355e03 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
+obj-$(CONFIG_TARGET_MT8518) += mt8518/
diff --git a/arch/arm/mach-mediatek/mt8518/Makefile b/arch/arm/mach-mediatek/mt8518/Makefile
new file mode 100644
index 0000000000..007eb4a367
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt8518/init.c b/arch/arm/mach-mediatek/mt8518/init.c
new file mode 100644
index 0000000000..5a97c8cb26
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/init.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Configuration for MediaTek MT8518 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <ram.h>
+#include <asm/arch/misc.h>
+#include <asm/armv8/mmu.h>
+#include <asm/sections.h>
+#include <dm/uclass.h>
+#include <dt-bindings/clock/mt8518-clk.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = gd->ram_base;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT8518\n");
+ return 0;
+}
+
+static struct mm_region mt8518_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+
+struct mm_region *mem_map = mt8518_mem_map;
diff --git a/arch/arm/mach-mediatek/mt8518/lowlevel_init.S b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
new file mode 100644
index 0000000000..ad392120f4
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt8518/lowlevel_init.S
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee <mingming.lee@mediatek.com>
+ */
+
+/*
+ * Switch from AArch64 EL2 to AArch32 EL2
+ * @param inputs:
+ * x0: argument, zero
+ * x1: machine nr
+ * x2: fdt address
+ * x3: input argument
+ * x4: kernel entry point
+ * @param outputs for secure firmware:
+ * x0: function id
+ * x1: kernel entry point
+ * x2: machine nr
+ * x3: fdt address
+*/
+.global armv8_el2_to_aarch32
+armv8_el2_to_aarch32:
+ mov x3, x2
+ mov x2, x1
+ mov x1, x4
+ mov x4, #0
+ /* Define in src\bsp\trustzone\atf\v1.2\ */
+ /* mt8xxx\plat\mediatek\common\sip_svc.h */
+ /* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
+ ldr x0, =0xC2000200
+ SMC #0
+ ret
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 493699472c..d8d68ba447 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -312,7 +312,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
common board is a basic TPL board init which can be shared for most
- of SoCs to avoid copy-pase for different SoCs.
+ of SoCs to avoid copy-paste for different SoCs.
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c
index 9ccb45e6ac..10614c99d9 100644
--- a/arch/arm/mach-rockchip/bootrom.c
+++ b/arch/arm/mach-rockchip/bootrom.c
@@ -39,8 +39,8 @@ void back_to_bootrom(enum rockchip_bootrom_cmd brom_cmd)
* to check it and back to bootrom at very early bootstage(before
* some basic configurations(such as interrupts) been
* changed by TPL/SPL, as the bootrom download operation
- * relys on many default settings(such as interrupts) by
- * it's self.
+ * relies on many default settings(such as interrupts) by
+ * itself.
*/
static bool check_back_to_brom_dnl_flag(void)
{
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 01af3f1464..868e85fc2a 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -6,9 +6,9 @@ choice
config TARGET_EVB_RK3399
bool "RK3399 evaluation board"
help
- RK3399evb is a evaluation board for Rockchp rk3399,
- with full function and phisical connectors support like type-C ports,
- usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial...
+ RK3399evb is a evaluation board for Rockchip RK3399,
+ with full function and physical connectors support like Type-C ports,
+ USB.0 host ports, LVDS, JTAG, MAC, SD card, HDMI, USB-to-serial...
config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c
index fa8e096426..c147d5821e 100644
--- a/arch/arm/mach-rockchip/spl-boot-order.c
+++ b/arch/arm/mach-rockchip/spl-boot-order.c
@@ -35,7 +35,7 @@ static int spl_node_to_boot_device(int node)
/*
* This should eventually move into the SPL code, once SPL becomes
* aware of the block-device layer. Until then (and to avoid unneeded
- * delays in getting this feature out, it lives at the board-level).
+ * delays in getting this feature out), it lives at the board-level.
*/
if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) {
struct udevice *dev;
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-07 00:18:19 +0300