diff options
Diffstat (limited to 'arch')
256 files changed, 17862 insertions, 566 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 80702c23d3..abbc89a889 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -16,8 +16,8 @@ config POSITION_INDEPENDENT help U-Boot expects to be linked to a specific hard-coded address, and to be loaded to and run from that address. This option lifts that - restriction, thus allowing the code to be loaded to and executed - from almost any address. This logic relies on the relocation + restriction, thus allowing the code to be loaded to and executed from + almost any 4K aligned address. This logic relies on the relocation information that is embedded in the binary to support U-Boot relocating itself to the top-of-RAM later during execution. @@ -767,8 +767,11 @@ config ARCH_IPQ40XX select DM select DM_GPIO select DM_SERIAL + select DM_RESET + select MSM_SMEM select PINCTRL select CLK + select SMEM select OF_CONTROL imply CMD_DM @@ -940,9 +943,9 @@ config ARCH_QEMU config ARCH_RMOBILE bool "Renesas ARM SoCs" - select BOARD_EARLY_INIT_F if !RZA1 select DM select DM_SERIAL + imply BOARD_EARLY_INIT_F imply CMD_DM imply FAT_WRITE imply SYS_THUMB_BUILD @@ -1152,7 +1155,8 @@ config ARCH_ZYNQMP select OF_CONTROL select SPL_BOARD_INIT if SPL select SPL_CLK if SPL - select SPL_DM_SPI if SPI + select SPL_DM if SPL + select SPL_DM_SPI if SPI && SPL_DM select SPL_DM_SPI_FLASH if SPL_DM_SPI select SPL_DM_MAILBOX if SPL select SPL_FIRMWARE if SPL @@ -1997,10 +2001,6 @@ source "board/tcl/sl50/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" -source "board/xilinx/Kconfig" -source "board/xilinx/zynq/Kconfig" -source "board/xilinx/zynqmp/Kconfig" -source "board/xilinx/versal/Kconfig" source "board/phytium/durian/Kconfig" source "board/xen/xenguest_arm64/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 87fb321c63..ba42c185c4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -56,7 +56,7 @@ int ls_gic_rd_tables_init(void *blob) lpi_base.start = addr; lpi_base.end = addr + size - 1; - ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL); + ret = fdtdec_add_reserved_memory(blob, "lpi_rd_table", &lpi_base, NULL, false); if (ret) { debug("%s: failed to add reserved memory\n", __func__); return ret; diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 002698b501..e5c2856cf5 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -59,6 +59,23 @@ reset: save_boot_params_ret: #if CONFIG_POSITION_INDEPENDENT + /* Verify that we're 4K aligned. */ + adr x0, _start + ands x0, x0, #0xfff + b.eq 1f +0: + /* + * FATAL, can't continue. + * U-Boot needs to be loaded at a 4K aligned address. + * + * We use ADRP and ADD to load some symbol addresses during startup. + * The ADD uses an absolute (non pc-relative) lo12 relocation + * thus requiring 4K alignment. + */ + wfi + b 0b +1: + /* * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and * executed at a different address than it was linked at. @@ -67,8 +84,10 @@ pie_fixup: adr x0, _start /* x0 <- Runtime value of _start */ ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */ sub x9, x0, x1 /* x9 <- Run-vs-link offset */ - adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ - adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ + adrp x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */ + add x2, x2, #:lo12:__rel_dyn_start + adrp x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */ + add x3, x3, #:lo12:__rel_dyn_end pie_fix_loop: ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */ ldr x4, [x2], #8 /* x4 <- addend */ diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f8f529435b..72b6fe1a3e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -938,7 +938,7 @@ dtb-$(CONFIG_ARCH_BCM6858) += \ dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb -dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb +dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb diff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts index 37484cb6f5..2a1b3a53e9 100644 --- a/arch/arm/dts/am335x-icev2.dts +++ b/arch/arm/dts/am335x-icev2.dts @@ -436,3 +436,53 @@ reg = <3>; }; }; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_default>; + + sn65hvs882@1 { + compatible = "pisosr-gpio"; + gpio-controller; + #gpio-cells = <2>; + + load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + + reg = <1>; + spi-max-frequency = <1000000>; + spi-cpol; + }; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "winbond,w25q64", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "u-boot"; + reg = <0x80000 0x100000>; + read-only; + }; + + partition@2 { + label = "u-boot-env"; + reg = <0x180000 0x20000>; + read-only; + }; + + partition@3 { + label = "misc"; + reg = <0x1A0000 0x660000>; + }; + }; +}; diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 8ac4215745..51a5244766 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,5 @@ -#include <dt-bindings/clock/ast2500-scu.h> +// SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/clock/aspeed-clock.h> #include <dt-bindings/reset/ast2500-reset.h> #include "ast2500.dtsi" @@ -25,7 +26,7 @@ reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; #reset-cells = <1>; - clocks = <&scu PLL_MPLL>; + clocks = <&scu ASPEED_CLK_MPLL>; resets = <&rst AST_RESET_SDRAM>; }; @@ -39,7 +40,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740100>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; @@ -47,7 +48,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740200>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; }; @@ -56,23 +57,23 @@ }; &uart1 { - clocks = <&scu PCLK_UART1>; + clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; }; &uart2 { - clocks = <&scu PCLK_UART2>; + clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; }; &uart3 { - clocks = <&scu PCLK_UART3>; + clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; }; &uart4 { - clocks = <&scu PCLK_UART4>; + clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; }; &uart5 { - clocks = <&scu PCLK_UART5>; + clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; }; &timer { @@ -80,9 +81,9 @@ }; &mac0 { - clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; &mac1 { - clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 4972a7559f..0a5faa2134 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -131,3 +131,31 @@ dr_mode = "peripheral"; u-boot,dm-spl; }; + +&wkup_gpio_pins_default { + u-boot,dm-spl; +}; + +&wkup_gpio0 { + u-boot,dm-spl; +}; + +&mcu_fss0_hpb0_pins_default { + u-boot,dm-spl; +}; + +&fss { + u-boot,dm-spl; +}; + +&hbmc { + u-boot,dm-spl; + + flash@0,0 { + u-boot,dm-spl; + }; +}; + +&hbmc_mux { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts b/arch/arm/dts/k3-j7200-common-proc-board.dts index 3f1d03c960..cc3d933cbb 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-common-proc-board.dts @@ -13,6 +13,13 @@ stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; + + aliases { + remoteproc0 = &mcu_r5fss0_core0; + remoteproc1 = &mcu_r5fss0_core1; + remoteproc2 = &main_r5fss0_core0; + remoteproc3 = &main_r5fss0_core1; + }; }; &wkup_pmx0 { diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index aaa1fdd5a3..c25f03cf23 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -340,4 +340,44 @@ dr_mode = "otg"; }; }; + + main_r5fss0: r5fss@5c00000 { + compatible = "ti,j7200-r5fss"; + lockstep-mode = <0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x5c00000 0x00 0x5c00000 0x20000>, + <0x5d00000 0x00 0x5d00000 0x20000>; + power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>; + + main_r5fss0_core0: r5f@5c00000 { + compatible = "ti,j7200-r5f"; + reg = <0x5c00000 0x00010000>, + <0x5c10000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <245>; + ti,sci-proc-ids = <0x06 0xFF>; + resets = <&k3_reset 245 1>; + firmware-name = "j7200-main-r5f0_0-fw"; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + main_r5fss0_core1: r5f@5d00000 { + compatible = "ti,j7200-r5f"; + reg = <0x5d00000 0x00008000>, + <0x5d10000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <246>; + ti,sci-proc-ids = <0x07 0xFF>; + resets = <&k3_reset 246 1>; + firmware-name = "j7200-main-r5f0_1-fw"; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; }; diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi index 4c899c8aca..75c0c8597d 100644 --- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi @@ -269,4 +269,44 @@ ti,cpts-periodic-outputs = <2>; }; }; + + mcu_r5fss0: r5fss@41000000 { + compatible = "ti,j7200-r5fss"; + lockstep-mode = <1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x41000000 0x00 0x41000000 0x20000>, + <0x41400000 0x00 0x41400000 0x20000>; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + + mcu_r5fss0_core0: r5f@41000000 { + compatible = "ti,j7200-r5f"; + reg = <0x41000000 0x00010000>, + <0x41010000 0x00010000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <250>; + ti,sci-proc-ids = <0x01 0xff>; + resets = <&k3_reset 250 1>; + firmware-name = "j7200-mcu-r5f0_0-fw"; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + + mcu_r5fss0_core1: r5f@41400000 { + compatible = "ti,j7200-r5f"; + reg = <0x41400000 0x00008000>, + <0x41410000 0x00008000>; + reg-names = "atcm", "btcm"; + ti,sci = <&dmsc>; + ti,sci-dev-id = <251>; + ti,sci-proc-ids = <0x02 0xff>; + resets = <&k3_reset 251 1>; + firmware-name = "j7200-mcu-r5f0_1-fw"; + atcm-enable = <1>; + btcm-enable = <1>; + loczrama = <1>; + }; + }; }; diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts index f5e4166926..db63d93777 100644 --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts @@ -18,6 +18,12 @@ chosen { stdout-path = &main_uart0; tick-timer = &timer1; + firmware-loader = &fs_loader0; + }; + + fs_loader0: fs_loader@0 { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; }; a72_0: a72@0 { @@ -107,6 +113,31 @@ J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ >; }; + + mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ + J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ + J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ + J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ + >; + }; + + wkup_gpio_pins_default: wkup-gpio-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ + >; + }; }; &main_pmx0 { @@ -214,4 +245,19 @@ maximum-speed = "high-speed"; }; +&hbmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; + ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ + <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ + + flash@0,0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + }; +}; + #include "k3-j7200-common-proc-board-u-boot.dtsi" diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index a285b1afa8..33db74a267 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -302,7 +302,7 @@ main_r5fss1: r5fss@5e00000 { compatible = "ti,j721e-r5fss"; - lockstep-mode = <1>; + lockstep-mode = <0>; #address-cells = <1>; #size-cells = <1>; ranges = <0x5e00000 0x00 0x5e00000 0x20000>, diff --git a/arch/arm/dts/qcom-ipq4019.dtsi b/arch/arm/dts/qcom-ipq4019.dtsi index 5f78bc5ab9..e0e4188e5d 100644 --- a/arch/arm/dts/qcom-ipq4019.dtsi +++ b/arch/arm/dts/qcom-ipq4019.dtsi @@ -10,6 +10,8 @@ #include "skeleton.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/pinctrl-snapdragon.h> +#include <dt-bindings/clock/qcom,ipq4019-gcc.h> +#include <dt-bindings/reset/qcom,ipq4019-reset.h> / { #address-cells = <1>; @@ -38,6 +40,11 @@ }; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -52,6 +59,14 @@ u-boot,dm-pre-reloc; }; + reset: gcc-reset@1800000 { + compatible = "qcom,gcc-reset-ipq4019"; + reg = <0x1800000 0x60000>; + #clock-cells = <1>; + #reset-cells = <1>; + u-boot,dm-pre-reloc; + }; + pinctrl: qcom,tlmm@1000000 { compatible = "qcom,tlmm-ipq4019"; reg = <0x1000000 0x300000>; @@ -61,7 +76,7 @@ blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78af000 0x200>; - clock = <&gcc 26>; + clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>; bit-rate = <0xFF>; status = "disabled"; u-boot,dm-pre-reloc; @@ -75,5 +90,81 @@ gpio-bank-name="soc"; #gpio-cells = <2>; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&reset USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3: usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2: usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + }; + }; }; }; diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi index a603d94797..8e80f50132 100644 --- a/arch/arm/dts/r8a774a1.dtsi +++ b/arch/arm/dts/r8a774a1.dtsi @@ -10,6 +10,8 @@ #include <dt-bindings/clock/r8a774a1-cpg-mssr.h> #include <dt-bindings/power/r8a774a1-sysc.h> +#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 + / { compatible = "renesas,r8a774a1"; #address-cells = <2>; @@ -2250,7 +2252,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; @@ -2262,7 +2264,7 @@ status = "disabled"; }; - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; @@ -2274,7 +2276,7 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; @@ -2286,7 +2288,7 @@ status = "disabled"; }; - sdhi3: sd@ee160000 { + sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi new file mode 100644 index 0000000000..23119c0ae7 --- /dev/null +++ b/arch/arm/dts/r8a774b1.dtsi @@ -0,0 +1,2630 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774b1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a774b1-cpg-mssr.h> +#include <dt-bindings/power/r8a774b1-sysc.h> + +#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 + +/ { + compatible = "renesas,r8a774b1"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774B1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774b1-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774b1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774b1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774b1-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774b1-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774b1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a774b1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774b1", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774b1", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774b1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774b1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774b1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@e7740000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@e6570000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@e67b0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: iommu@ec670000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: iommu@fd800000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A774B1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@febd0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: iommu@fe990000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774b1", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a774b1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 0x40>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin7>; + }; + }; + }; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774B1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774b1", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774b1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774b1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774b1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a774b1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 615>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 611>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a774b1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774b1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + }; + }; + + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774b1-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774B1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a774b1"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; + status = "disabled"; + + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774b1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <2439>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <2439>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <2439>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + }; + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi new file mode 100644 index 0000000000..0f86cfd524 --- /dev/null +++ b/arch/arm/dts/r8a774e1.dtsi @@ -0,0 +1,1664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774e1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/r8a774e1-cpg-mssr.h> +#include <dt-bindings/power/r8a774e1-sysc.h> + +#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 + +/ { + compatible = "renesas,r8a774e1"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + core2 { + cpu = <&a57_2>; + }; + core3 { + cpu = <&a57_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774e1-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774e1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774e1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774e1-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774e1-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774e1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a774e1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774e1", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x200>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_phy0: usb-phy@e65ee000 { + reg = <0 0xe65ee000 0 0x90>; + #phy-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@e7740000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@e6570000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@e67b0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp0: iommu@ec670000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: iommu@fd800000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: iommu@fd950000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv2: iommu@fd960000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv3: iommu@fd970000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A774E1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vc1: iommu@fe6f0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A774E1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@febd0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@febe0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: iommu@fe990000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + #iommu-cells = <1>; + }; + + ipmmu_vp1: iommu@fe980000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774e1", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a774e1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 0x40>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + status = "disabled"; + + /* placeholder */ + + rcar_sound,ssi { + ssi2: ssi-2 { + /* placeholder */ + }; + }; + }; + + xhci0: usb@ee000000 { + reg = <0 0xee000000 0 0xc00>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_peri0: usb@ee020000 { + reg = <0 0xee020000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ohci0: usb@ee080000 { + reg = <0 0xee080000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ohci1: usb@ee0a0000 { + reg = <0 0xee0a0000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci0: usb@ee080100 { + reg = <0 0xee080100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci1: usb@ee0a0100 { + reg = <0 0xee0a0100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy0: usb-phy@ee080200 { + reg = <0 0xee080200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + iommus = <&ipmmu_ds1 32>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + iommus = <&ipmmu_ds1 33>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + iommus = <&ipmmu_ds1 34>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + iommus = <&ipmmu_ds1 35>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + hdmi0: hdmi@fead0000 { + reg = <0 0xfead0000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + reg = <0 0xfeb00000 0 0x80000>; + status = "disabled"; + + /* placeholder */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <6313>; + + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts index e039e33d59..36c8a44a90 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77950-salvator-x.dts" #include "r8a77950-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts index b7f26c11b1..d3191c55d5 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts index d3b09246f5..439fd6c3ad 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77960-salvator-x.dts" #include "r8a77960-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts index bd1d634574..aab9c95931 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index d6f0708555..8cbef83b9c 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts index 954d8b685c..38966bf644 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 0ea0cc9cb1..6afc0be66e 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -18,6 +18,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts index 2f53970809..10fb9cb3b6 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dts @@ -7,3 +7,8 @@ #include "r8a77995-draak.dts" #include "r8a77995-u-boot.dtsi" + +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; diff --git a/arch/arm/dts/sama7g5-pinfunc.h b/arch/arm/dts/sama7g5-pinfunc.h new file mode 100644 index 0000000000..89293e5470 --- /dev/null +++ b/arch/arm/dts/sama7g5-pinfunc.h @@ -0,0 +1,924 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__FLEXCOM0_IO0 PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__CANTX3 PINMUX_PIN(PIN_PA0, 3, 1) +#define PIN_PA0__PWML0 PINMUX_PIN(PIN_PA0, 5, 2) +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__FLEXCOM0_IO1 PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__CANRX3 PINMUX_PIN(PIN_PA1, 3, 1) +#define PIN_PA1__D14 PINMUX_PIN(PIN_PA1, 4, 1) +#define PIN_PA1__PWMH0 PINMUX_PIN(PIN_PA1, 5, 3) +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_RSTN PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__FLEXCOM0_IO2 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__PDMC1_CLK PINMUX_PIN(PIN_PA2, 3, 1) +#define PIN_PA2__D15 PINMUX_PIN(PIN_PA2, 4, 1) +#define PIN_PA2__PWMH1 PINMUX_PIN(PIN_PA2, 5, 3) +#define PIN_PA2__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA2, 6, 3) +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT0 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__FLEXCOM0_IO3 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__PDMC1_DS0 PINMUX_PIN(PIN_PA3, 3, 1) +#define PIN_PA3__NWR1_NBS1 PINMUX_PIN(PIN_PA3, 4, 1) +#define PIN_PA3__PWML3 PINMUX_PIN(PIN_PA3, 5, 3) +#define PIN_PA3__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA3, 6, 3) +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT1 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__FLEXCOM0_IO4 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__PDMC1_DS1 PINMUX_PIN(PIN_PA4, 3, 1) +#define PIN_PA4__NCS2 PINMUX_PIN(PIN_PA4, 4, 1) +#define PIN_PA4__PWMH3 PINMUX_PIN(PIN_PA4, 5, 3) +#define PIN_PA4__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA4, 6, 3) +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT2 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA5, 2, 1) +#define PIN_PA5__CANTX2 PINMUX_PIN(PIN_PA5, 3, 1) +#define PIN_PA5__A23 PINMUX_PIN(PIN_PA5, 4, 1) +#define PIN_PA5__PWMEXTRG0 PINMUX_PIN(PIN_PA5, 5, 3) +#define PIN_PA5__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA5, 6, 3) +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT3 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA6, 2, 1) +#define PIN_PA6__CANRX2 PINMUX_PIN(PIN_PA6, 3, 1) +#define PIN_PA6__A24 PINMUX_PIN(PIN_PA6, 4, 1) +#define PIN_PA6__PWMEXTRG1 PINMUX_PIN(PIN_PA6, 5, 3) +#define PIN_PA6__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA6, 6, 3) +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT4 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +#define PIN_PA7__CANTX1 PINMUX_PIN(PIN_PA7, 3, 1) +#define PIN_PA7__NWAIT PINMUX_PIN(PIN_PA7, 4, 1) +#define PIN_PA7__PWMFI0 PINMUX_PIN(PIN_PA7, 5, 3) +#define PIN_PA7__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA7, 6, 3) +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT5 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +#define PIN_PA8__CANRX1 PINMUX_PIN(PIN_PA8, 3, 1) +#define PIN_PA8__NCS0 PINMUX_PIN(PIN_PA8, 4, 1) +#define PIN_PA8__PWMIF1 PINMUX_PIN(PIN_PA8, 5, 3) +#define PIN_PA8__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA8, 6, 3) +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT6 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__CANTX0 PINMUX_PIN(PIN_PA9, 3, 1) +#define PIN_PA9__SMCK PINMUX_PIN(PIN_PA9, 4, 1) +#define PIN_PA9__SPDIF_RX PINMUX_PIN(PIN_PA9, 5, 1) +#define PIN_PA9__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA9, 6, 3) +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_DAT7 PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__CANRX0 PINMUX_PIN(PIN_PA10, 3, 1) +#define PIN_PA10__NCS1 PINMUX_PIN(PIN_PA10, 4, 1) +#define PIN_PA10__SPDIF_TX PINMUX_PIN(PIN_PA10, 5, 1) +#define PIN_PA10__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA10, 6, 3) +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_DS PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__A0_NBS0 PINMUX_PIN(PIN_PA11, 4, 1) +#define PIN_PA11__TIOA0 PINMUX_PIN(PIN_PA11, 5, 1) +#define PIN_PA11__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA11, 6, 3) +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +#define PIN_PA12__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__FLEXCOM3_IO5 PINMUX_PIN(PIN_PA12, 4, 1) +#define PIN_PA12__PWML2 PINMUX_PIN(PIN_PA12, 5, 3) +#define PIN_PA12__FLEXCOM6_IO0 PINMUX_PIN(PIN_PA12, 6, 3) +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__SDMMC0_1V8SEL PINMUX_PIN(PIN_PA13, 1, 1) +#define PIN_PA13__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA13, 2, 1) +#define PIN_PA13__FLEXCOM3_IO6 PINMUX_PIN(PIN_PA13, 4, 1) +#define PIN_PA13__PWMH2 PINMUX_PIN(PIN_PA13, 5, 3) +#define PIN_PA13__FLEXCOM6_IO1 PINMUX_PIN(PIN_PA13, 6, 3) +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__SDMMC0_CD PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__A25 PINMUX_PIN(PIN_PA14, 4, 1) +#define PIN_PA14__PWML1 PINMUX_PIN(PIN_PA14, 5, 3) +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__G0_TXEN PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__ISC_MCK PINMUX_PIN(PIN_PA15, 3, 1) +#define PIN_PA15__A1 PINMUX_PIN(PIN_PA15, 4, 1) +#define PIN_PA15__TIOB0 PINMUX_PIN(PIN_PA15, 5, 1) +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__G0_TX0 PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__ISC_D0 PINMUX_PIN(PIN_PA16, 3, 1) +#define PIN_PA16__A2 PINMUX_PIN(PIN_PA16, 4, 1) +#define PIN_PA16__TCLK0 PINMUX_PIN(PIN_PA16, 5, 1) +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__G0_TX1 PINMUX_PIN(PIN_PA17, 1, 1) +#define PIN_PA17__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA17, 2, 1) +#define PIN_PA17__ISC_D1 PINMUX_PIN(PIN_PA17, 3, 1) +#define PIN_PA17__A3 PINMUX_PIN(PIN_PA17, 4, 1) +#define PIN_PA17__TIOA1 PINMUX_PIN(PIN_PA17, 5, 1) +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__G0_RXDV PINMUX_PIN(PIN_PA18, 1, 1) +#define PIN_PA18__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA18, 2, 1) +#define PIN_PA18__ISC_D2 PINMUX_PIN(PIN_PA18, 3, 1) +#define PIN_PA18__A4 PINMUX_PIN(PIN_PA18, 4, 1) +#define PIN_PA18__TIOB1 PINMUX_PIN(PIN_PA18, 5, 1) +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__G0_RX0 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA19, 2, 1) +#define PIN_PA19__ISC_D3 PINMUX_PIN(PIN_PA19, 3, 1) +#define PIN_PA19__A5 PINMUX_PIN(PIN_PA19, 4, 1) +#define PIN_PA19__TCLK1 PINMUX_PIN(PIN_PA19, 5, 1) +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__G0_RX1 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__FLEXCOM4_IO0 PINMUX_PIN(PIN_PA20, 2, 1) +#define PIN_PA20__ISC_D4 PINMUX_PIN(PIN_PA20, 3, 1) +#define PIN_PA20__A6 PINMUX_PIN(PIN_PA20, 4, 1) +#define PIN_PA20__TIOA2 PINMUX_PIN(PIN_PA20, 5, 1) +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__G0_RXER PINMUX_PIN(PIN_PA21, 1, 1) +#define PIN_PA21__FLEXCOM4_IO1 PINMUX_PIN(PIN_PA21, 2, 1) +#define PIN_PA21__ISC_D5 PINMUX_PIN(PIN_PA21, 3, 1) +#define PIN_PA21__A7 PINMUX_PIN(PIN_PA21, 4, 1) +#define PIN_PA21__TIOB2 PINMUX_PIN(PIN_PA21, 5, 1) +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__G0_MDC PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__FLEXCOM4_IO2 PINMUX_PIN(PIN_PA22, 2, 1) +#define PIN_PA22__ISC_D6 PINMUX_PIN(PIN_PA22, 3, 1) +#define PIN_PA22__A8 PINMUX_PIN(PIN_PA22, 4, 1) +#define PIN_PA22__TCLK2 PINMUX_PIN(PIN_PA22, 5, 1) +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__G0_MDIO PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__FLEXCOM4_IO3 PINMUX_PIN(PIN_PA23, 2, 1) +#define PIN_PA23__ISC_D7 PINMUX_PIN(PIN_PA23, 3, 1) +#define PIN_PA23__A9 PINMUX_PIN(PIN_PA23, 4, 1) +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__G0_TXCK PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__FLEXCOM4_IO4 PINMUX_PIN(PIN_PA24, 2, 1) +#define PIN_PA24__ISC_HSYNC PINMUX_PIN(PIN_PA24, 3, 1) +#define PIN_PA24__A10 PINMUX_PIN(PIN_PA24, 4, 1) +#define PIN_PA24__FLEXCOM0_IO5 PINMUX_PIN(PIN_PA24, 5, 1) +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__G0_125CK PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__FLEXCOM5_IO4 PINMUX_PIN(PIN_PA25, 2, 1) +#define PIN_PA25__ISC_VSYNC PINMUX_PIN(PIN_PA25, 3, 1) +#define PIN_PA25__A11 PINMUX_PIN(PIN_PA25, 4, 1) +#define PIN_PA25__FLEXCOM0_IO6 PINMUX_PIN(PIN_PA25, 5, 1) +#define PIN_PA25__FLEXCOM7_IO0 PINMUX_PIN(PIN_PA25, 6, 3) +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__G0_TX2 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__FLEXCOM5_IO2 PINMUX_PIN(PIN_PA26, 2, 1) +#define PIN_PA26__ISC_FIELD PINMUX_PIN(PIN_PA26, 3, 1) +#define PIN_PA26__A12 PINMUX_PIN(PIN_PA26, 4, 1) +#define PIN_PA26__TF0 PINMUX_PIN(PIN_PA26, 5, 1) +#define PIN_PA26__FLEXCOM7_IO1 PINMUX_PIN(PIN_PA26, 6, 3) +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__G0_TX3 PINMUX_PIN(PIN_PA27, 1, 1) +#define PIN_PA27__FLEXCOM5_IO3 PINMUX_PIN(PIN_PA27, 2, 1) +#define PIN_PA27__ISC_PCK PINMUX_PIN(PIN_PA27, 3, 1) +#define PIN_PA27__A13 PINMUX_PIN(PIN_PA27, 4, 1) +#define PIN_PA27__TK0 PINMUX_PIN(PIN_PA27, 5, 1) +#define PIN_PA27__FLEXCOM8_IO0 PINMUX_PIN(PIN_PA27, 6, 3) +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__G0_RX2 PINMUX_PIN(PIN_PA28, 1, 1) +#define PIN_PA28__FLEXCOM5_IO0 PINMUX_PIN(PIN_PA28, 2, 1) +#define PIN_PA28__ISC_D8 PINMUX_PIN(PIN_PA28, 3, 1) +#define PIN_PA28__A14 PINMUX_PIN(PIN_PA28, 4, 1) +#define PIN_PA28__RD0 PINMUX_PIN(PIN_PA28, 5, 1) +#define PIN_PA28__FLEXCOM8_IO1 PINMUX_PIN(PIN_PA28, 6, 3) +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__G0_RX3 PINMUX_PIN(PIN_PA29, 1, 1) +#define PIN_PA29__FLEXCOM5_IO1 PINMUX_PIN(PIN_PA29, 2, 1) +#define PIN_PA29__ISC_D9 PINMUX_PIN(PIN_PA29, 3, 1) +#define PIN_PA29__A15 PINMUX_PIN(PIN_PA29, 4, 1) +#define PIN_PA29__RF0 PINMUX_PIN(PIN_PA29, 5, 1) +#define PIN_PA29__FLEXCOM9_IO0 PINMUX_PIN(PIN_PA29, 6, 3) +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__G0_RXCK PINMUX_PIN(PIN_PA30, 1, 1) +#define PIN_PA30__FLEXCOM6_IO4 PINMUX_PIN(PIN_PA30, 2, 1) +#define PIN_PA30__ISC_D10 PINMUX_PIN(PIN_PA30, 3, 1) +#define PIN_PA30__A16 PINMUX_PIN(PIN_PA30, 4, 1) +#define PIN_PA30__RK0 PINMUX_PIN(PIN_PA30, 5, 1) +#define PIN_PA30__FLEXCOM9_IO1 PINMUX_PIN(PIN_PA30, 6, 3) +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__G0_TXER PINMUX_PIN(PIN_PA31, 1, 1) +#define PIN_PA31__FLEXCOM6_IO2 PINMUX_PIN(PIN_PA31, 2, 1) +#define PIN_PA31__ISC_D11 PINMUX_PIN(PIN_PA31, 3, 1) +#define PIN_PA31__A17 PINMUX_PIN(PIN_PA31, 4, 1) +#define PIN_PA31__TD0 PINMUX_PIN(PIN_PA31, 5, 1) +#define PIN_PA31__FLEXCOM10_IO0 PINMUX_PIN(PIN_PA31, 6, 3) +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__G0_COL PINMUX_PIN(PIN_PB0, 1, 1) +#define PIN_PB0__FLEXCOM6_IO3 PINMUX_PIN(PIN_PB0, 2, 2) +#define PIN_PB0__EXT_IRQ0 PINMUX_PIN(PIN_PB0, 3, 1) +#define PIN_PB0__A18 PINMUX_PIN(PIN_PB0, 4, 1) +#define PIN_PB0__SPDIF_RX PINMUX_PIN(PIN_PB0, 5, 2) +#define PIN_PB0__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB0, 6, 3) +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__G0_CRS PINMUX_PIN(PIN_PB1, 1, 1) +#define PIN_PB1__FLEXCOM6_IO1 PINMUX_PIN(PIN_PB1, 2, 2) +#define PIN_PB1__EXT_IRQ1 PINMUX_PIN(PIN_PB1, 3, 1) +#define PIN_PB1__A19 PINMUX_PIN(PIN_PB1, 4, 1) +#define PIN_PB1__SPDIF_TX PINMUX_PIN(PIN_PB1, 5, 2) +#define PIN_PB1__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB1, 6, 3) +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__G0_TSUCOMP PINMUX_PIN(PIN_PB2, 1, 1) +#define PIN_PB2__FLEXCOM6_IO0 PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__ADTRG PINMUX_PIN(PIN_PB2, 3, 1) +#define PIN_PB2__A20 PINMUX_PIN(PIN_PB2, 4, 1) +#define PIN_PB2__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB2, 6, 3) +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__RF1 PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__FLEXCOM11_IO0 PINMUX_PIN(PIN_PB3, 2, 1) +#define PIN_PB3__PCK2 PINMUX_PIN(PIN_PB3, 3, 2) +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 4, 1) +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__TF1 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__FLEXCOM11_IO1 PINMUX_PIN(PIN_PB4, 2, 1) +#define PIN_PB4__PCK3 PINMUX_PIN(PIN_PB4, 3, 2) +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 4, 1) +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__TK1 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__FLEXCOM11_IO2 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__PCK4 PINMUX_PIN(PIN_PB5, 3, 2) +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 4, 1) +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__RK1 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__FLEXCOM11_IO3 PINMUX_PIN(PIN_PB6, 2, 1) +#define PIN_PB6__PCK5 PINMUX_PIN(PIN_PB6, 3, 2) +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 4, 1) +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__TD1 PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__FLEXCOM11_IO4 PINMUX_PIN(PIN_PB7, 2, 1) +#define PIN_PB7__FLEXCOM3_IO5 PINMUX_PIN(PIN_PB7, 3, 2) +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 4, 1) +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__RD1 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__FLEXCOM3_IO6 PINMUX_PIN(PIN_PB8, 3, 2) +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 4, 1) +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__QSPI0_IO3 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB9, 2, 1) +#define PIN_PB9__PDMC0_CLK PINMUX_PIN(PIN_PB9, 3, 1) +#define PIN_PB9__NCS3_NANDCS PINMUX_PIN(PIN_PB9, 4, 1) +#define PIN_PB9__PWML0 PINMUX_PIN(PIN_PB9, 5, 2) +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__QSPI0_IO2 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__FLEXCOM8_IO2 PINMUX_PIN(PIN_PB10, 2, 1) +#define PIN_PB10__PDMC0_DS0 PINMUX_PIN(PIN_PB10, 3, 1) +#define PIN_PB10__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PB10, 4, 1) +#define PIN_PB10__PWMH0 PINMUX_PIN(PIN_PB10, 5, 2) +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__QSPI0_IO1 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__FLEXCOM8_IO3 PINMUX_PIN(PIN_PB11, 2, 1) +#define PIN_PB11__PDMC0_DS1 PINMUX_PIN(PIN_PB11, 3, 1) +#define PIN_PB11__NRD_NANDOE PINMUX_PIN(PIN_PB11, 4, 1) +#define PIN_PB11__PWML1 PINMUX_PIN(PIN_PB11, 5, 2) +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__QSPI0_IO0 PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__FLEXCOM8_IO4 PINMUX_PIN(PIN_PB12, 2, 1) +#define PIN_PB12__FLEXCOM6_IO5 PINMUX_PIN(PIN_PB12, 3, 1) +#define PIN_PB12__A21_NANDALE PINMUX_PIN(PIN_PB12, 4, 1) +#define PIN_PB12__PWMH1 PINMUX_PIN(PIN_PB12, 5, 2) +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__QSPI0_CS PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__FLEXCOM9_IO0 PINMUX_PIN(PIN_PB13, 2, 1) +#define PIN_PB13__FLEXCOM6_IO6 PINMUX_PIN(PIN_PB13, 3, 1) +#define PIN_PB13__A22_NANDCLE PINMUX_PIN(PIN_PB13, 4, 1) +#define PIN_PB13__PWML2 PINMUX_PIN(PIN_PB13, 5, 2) +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__QSPI0_SCK PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__FLEXCOM9_IO1 PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__D0 PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__PWMH2 PINMUX_PIN(PIN_PB14, 5, 2) +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__QSPI0_SCKN PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__FLEXCOM9_IO2 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__D1 PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__PWML3 PINMUX_PIN(PIN_PB15, 5, 2) +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__QSPI0_IO4 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__FLEXCOM9_IO3 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__PCK0 PINMUX_PIN(PIN_PB16, 3, 1) +#define PIN_PB16__D2 PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__PWMH3 PINMUX_PIN(PIN_PB16, 5, 2) +#define PIN_PB16__EXT_IRQ0 PINMUX_PIN(PIN_PB16, 6, 2) +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__QSPI0_IO5 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__FLEXCOM9_IO4 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__PCK1 PINMUX_PIN(PIN_PB17, 3, 1) +#define PIN_PB17__D3 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__PWMEXTRG0 PINMUX_PIN(PIN_PB17, 5, 2) +#define PIN_PB17__EXT_IRQ1 PINMUX_PIN(PIN_PB17, 6, 2) +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__QSPI0_IO6 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__FLEXCOM10_IO0 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__PCK2 PINMUX_PIN(PIN_PB18, 3, 1) +#define PIN_PB18__D4 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__PWMEXTRG1 PINMUX_PIN(PIN_PB18, 5, 2) +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__QSPI0_IO7 PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__FLEXCOM10_IO1 PINMUX_PIN(PIN_PB19, 2, 1) +#define PIN_PB19__PCK3 PINMUX_PIN(PIN_PB19, 3, 1) +#define PIN_PB19__D5 PINMUX_PIN(PIN_PB19, 4, 1) +#define PIN_PB19__PWMFI0 PINMUX_PIN(PIN_PB19, 5, 2) +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__QSPI0_DQS PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__FLEXCOM10_IO2 PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__D6 PINMUX_PIN(PIN_PB20, 4, 1) +#define PIN_PB20__PWMFI1 PINMUX_PIN(PIN_PB20, 5, 2) +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__QSPI0_INT PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__FLEXCOM10_IO3 PINMUX_PIN(PIN_PB21, 2, 1) +#define PIN_PB21__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB21, 3, 1) +#define PIN_PB21__D7 PINMUX_PIN(PIN_PB21, 4, 1) +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__QSPI1_IO3 PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__FLEXCOM10_IO4 PINMUX_PIN(PIN_PB22, 2, 1) +#define PIN_PB22__FLEXCOM9_IO6 PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__NANDRDY PINMUX_PIN(PIN_PB22, 4, 1) +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__QSPI1_IO2 PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB23, 2, 1) +#define PIN_PB23__I2SMCC0_CK PINMUX_PIN(PIN_PB23, 3, 1) +#define PIN_PB23__PCK4 PINMUX_PIN(PIN_PB23, 6, 1) +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__QSPI1_IO1 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB24, 2, 1) +#define PIN_PB24__I2SMCC0_WS PINMUX_PIN(PIN_PB24, 3, 1) +#define PIN_PB24__PCK5 PINMUX_PIN(PIN_PB24, 6, 1) +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__QSPI1_IO0 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__FLEXCOM7_IO2 PINMUX_PIN(PIN_PB25, 2, 1) +#define PIN_PB25__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PB25, 3, 1) +#define PIN_PB25__PCK6 PINMUX_PIN(PIN_PB25, 6, 1) +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__QSPI1_CS PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__FLEXCOM7_IO3 PINMUX_PIN(PIN_PB26, 2, 1) +#define PIN_PB26__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PB26, 3, 1) +#define PIN_PB26__PWMEXTRG0 PINMUX_PIN(PIN_PB26, 5, 1) +#define PIN_PB26__PCK7 PINMUX_PIN(PIN_PB26, 6, 1) +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__QSPI1_SCK PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__FLEXCOM7_IO4 PINMUX_PIN(PIN_PB27, 2, 1) +#define PIN_PB27__I2SMCC0_MCK PINMUX_PIN(PIN_PB27, 3, 1) +#define PIN_PB27__PWMEXTRG1 PINMUX_PIN(PIN_PB27, 5, 1) +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__SDMMC1_RSTN PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__ADTRG PINMUX_PIN(PIN_PB28, 2, 2) +#define PIN_PB28__PWMFI0 PINMUX_PIN(PIN_PB28, 5, 1) +#define PIN_PB28__FLEXCOM7_IO0 PINMUX_PIN(PIN_PB28, 6, 4) +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__SDMMC1_CMD PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB29, 2, 2) +#define PIN_PB29__FLEXCOM0_IO5 PINMUX_PIN(PIN_PB29, 3, 2) +#define PIN_PB29__TIOA3 PINMUX_PIN(PIN_PB29, 4, 2) +#define PIN_PB29__PWMFI1 PINMUX_PIN(PIN_PB29, 5, 1) +#define PIN_PB29__FLEXCOM7_IO1 PINMUX_PIN(PIN_PB29, 6, 4) +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__SDMMC1_CK PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB30, 2, 2) +#define PIN_PB30__FLEXCOM0_IO6 PINMUX_PIN(PIN_PB30, 3, 2) +#define PIN_PB30__TIOB3 PINMUX_PIN(PIN_PB30, 4, 1) +#define PIN_PB30__PWMH0 PINMUX_PIN(PIN_PB30, 5, 1) +#define PIN_PB30__FLEXCOM8_IO0 PINMUX_PIN(PIN_PB30, 6, 4) +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__SDMMC1_DAT0 PINMUX_PIN(PIN_PB31, 1, 1) +#define PIN_PB31__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB31, 2, 2) +#define PIN_PB31__FLEXCOM9_IO5 PINMUX_PIN(PIN_PB31, 3, 2) +#define PIN_PB31__TCLK3 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__PWML0 PINMUX_PIN(PIN_PB31, 5, 1) +#define PIN_PB31__FLEXCOM8_IO1 PINMUX_PIN(PIN_PB31, 6, 4) +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__SDMMC1_DAT1 PINMUX_PIN(PIN_PC0, 1, 1) +#define PIN_PC0__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC0, 2, 2) +#define PIN_PC0__TIOA4 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__PWML1 PINMUX_PIN(PIN_PC0, 5, 1) +#define PIN_PC0__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC0, 6, 4) +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__SDMMC1_DAT2 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC1, 2, 2) +#define PIN_PC1__TIOB4 PINMUX_PIN(PIN_PC1, 4, 1) +#define PIN_PC1__PWMH1 PINMUX_PIN(PIN_PC1, 5, 1) +#define PIN_PC1__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC1, 6, 4) +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__SDMMC1_DAT3 PINMUX_PIN(PIN_PC2, 1, 1) +#define PIN_PC2__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC2, 2, 2) +#define PIN_PC2__TCLK4 PINMUX_PIN(PIN_PC2, 4, 1) +#define PIN_PC2__PWML2 PINMUX_PIN(PIN_PC2, 5, 1) +#define PIN_PC2__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC2, 6, 4) +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__SDMMC1_WP PINMUX_PIN(PIN_PC3, 1, 1) +#define PIN_PC3__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC3, 2, 2) +#define PIN_PC3__TIOA5 PINMUX_PIN(PIN_PC3, 4, 1) +#define PIN_PC3__PWMH2 PINMUX_PIN(PIN_PC3, 5, 1) +#define PIN_PC3__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC3, 6, 4) +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__SDMMC1_CD PINMUX_PIN(PIN_PC4, 1, 1) +#define PIN_PC4__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC4, 2, 2) +#define PIN_PC4__FLEXCOM9_IO6 PINMUX_PIN(PIN_PC4, 3, 2) +#define PIN_PC4__TIOB5 PINMUX_PIN(PIN_PC4, 4, 1) +#define PIN_PC4__PWML3 PINMUX_PIN(PIN_PC4, 5, 1) +#define PIN_PC4__FLEXCOM11_IO0 PINMUX_PIN(PIN_PC4, 6, 4) +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__SDMMC1_1V8SEL PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC5, 2, 2) +#define PIN_PC5__FLEXCOM6_IO5 PINMUX_PIN(PIN_PC5, 3, 2) +#define PIN_PC5__TCLK5 PINMUX_PIN(PIN_PC5, 4, 1) +#define PIN_PC5__PWMH3 PINMUX_PIN(PIN_PC5, 5, 1) +#define PIN_PC5__FLEXCOM11_IO1 PINMUX_PIN(PIN_PC5, 6, 4) +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__FLEXCOM4_IO4 PINMUX_PIN(PIN_PC6, 2, 2) +#define PIN_PC6__FLEXCOM6_IO6 PINMUX_PIN(PIN_PC6, 3, 2) +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__I2SMCC0_DIN0 PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC7, 2, 2) +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__I2SMCC0_DIN1 PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC8, 2, 2) +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PC9, 1, 1) +#define PIN_PC9__FLEXCOM7_IO2 PINMUX_PIN(PIN_PC9, 2, 2) +#define PIN_PC9__FLEXCOM1_IO0 PINMUX_PIN(PIN_PC9, 6, 4) +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PC10, 1, 1) +#define PIN_PC10__FLEXCOM7_IO3 PINMUX_PIN(PIN_PC10, 2, 2) +#define PIN_PC10__FLEXCOM1_IO1 PINMUX_PIN(PIN_PC10, 6, 4) +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__I2SMCC1_CK PINMUX_PIN(PIN_PC11, 1, 1) +#define PIN_PC11__FLEXCOM7_IO4 PINMUX_PIN(PIN_PC11, 2, 2) +#define PIN_PC11__FLEXCOM2_IO0 PINMUX_PIN(PIN_PC11, 6, 4) +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__I2SMCC1_WS PINMUX_PIN(PIN_PC12, 1, 1) +#define PIN_PC12__FLEXCOM8_IO2 PINMUX_PIN(PIN_PC12, 2, 2) +#define PIN_PC12__FLEXCOM2_IO1 PINMUX_PIN(PIN_PC12, 6, 4) +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__I2SMCC1_MCK PINMUX_PIN(PIN_PC13, 1, 1) +#define PIN_PC13__FLEXCOM8_IO1 PINMUX_PIN(PIN_PC13, 2, 2) +#define PIN_PC13__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC13, 6, 4) +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PC14, 1, 1) +#define PIN_PC14__FLEXCOM8_IO0 PINMUX_PIN(PIN_PC14, 2, 2) +#define PIN_PC14__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC14, 6, 4) +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PC15, 1, 1) +#define PIN_PC15__FLEXCOM8_IO3 PINMUX_PIN(PIN_PC15, 2, 2) +#define PIN_PC15__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC15, 6, 4) +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__I2SMCC_DOUT2 PINMUX_PIN(PIN_PC16, 1, 1) +#define PIN_PC16__FLEXCOM8_IO4 PINMUX_PIN(PIN_PC16, 2, 2) +#define PIN_PC16__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC16, 6, 4) +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PC17, 1, 1) +#define PIN_PC17__EXT_IRQ0 PINMUX_PIN(PIN_PC17, 2, 3) +#define PIN_PC17__FLEXCOM5_IO0 PINMUX_PIN(PIN_PC17, 6, 4) +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__I2SMCC1_DIN0 PINMUX_PIN(PIN_PC18, 1, 1) +#define PIN_PC18__FLEXCOM9_IO0 PINMUX_PIN(PIN_PC18, 2, 2) +#define PIN_PC18__FLEXCOM5_IO1 PINMUX_PIN(PIN_PC18, 6, 4) +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__I2SMCC1_DIN1 PINMUX_PIN(PIN_PC19, 1, 1) +#define PIN_PC19__FLEXCOM9_IO1 PINMUX_PIN(PIN_PC19, 2, 2) +#define PIN_PC19__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC19, 6, 4) +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__I2SMCC1_DIN2 PINMUX_PIN(PIN_PC20, 1, 1) +#define PIN_PC20__FLEXCOM9_IO4 PINMUX_PIN(PIN_PC20, 2, 2) +#define PIN_PC20__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC20, 6, 4) +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__I2SMCC1_DIN3 PINMUX_PIN(PIN_PC21, 1, 1) +#define PIN_PC21__FLEXCOM9_IO2 PINMUX_PIN(PIN_PC21, 2, 2) +#define PIN_PC21__D3 PINMUX_PIN(PIN_PC21, 4, 2) +#define PIN_PC21__FLEXCOM6_IO0 PINMUX_PIN(PIN_PC21, 6, 5) +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__I2SMCC0_DIN2 PINMUX_PIN(PIN_PC22, 1, 1) +#define PIN_PC22__FLEXCOM9_IO3 PINMUX_PIN(PIN_PC22, 2, 2) +#define PIN_PC22__D4 PINMUX_PIN(PIN_PC22, 4, 2) +#define PIN_PC22__FLEXCOM6_IO1 PINMUX_PIN(PIN_PC22, 6, 5) +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__I2SMCC0_DIN3 PINMUX_PIN(PIN_PC23, 1, 1) +#define PIN_PC23__FLEXCOM0_IO5 PINMUX_PIN(PIN_PC23, 2, 3) +#define PIN_PC23__D5 PINMUX_PIN(PIN_PC23, 4, 2) +#define PIN_PC23__FLEXCOM7_IO0 PINMUX_PIN(PIN_PC23, 6, 5) +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__FLEXCOM0_IO6 PINMUX_PIN(PIN_PC24, 2, 3) +#define PIN_PC24__EXT_IRQ1 PINMUX_PIN(PIN_PC24, 3, 3) +#define PIN_PC24__D6 PINMUX_PIN(PIN_PC24, 4, 2) +#define PIN_PC24__FLEXCOM7_IO1 PINMUX_PIN(PIN_PC24, 6, 5) +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__NTRST PINMUX_PIN(PIN_PC25, 1, 1) +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__TCK_SWCLK PINMUX_PIN(PIN_PC26, 1, 1) +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__TMS_SWDIO PINMUX_PIN(PIN_PC27, 1, 1) +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__TDI PINMUX_PIN(PIN_PC28, 1, 1) +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__TDO PINMUX_PIN(PIN_PC29, 1, 1) +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__FLEXCOM10_IO0 PINMUX_PIN(PIN_PC30, 2, 2) +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__FLEXCOM10_IO1 PINMUX_PIN(PIN_PC31, 2, 2) +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD0, 2, 2) +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD1, 2, 2) +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__SDMMC2_RSTN PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__PCK0 PINMUX_PIN(PIN_PD2, 2, 2) +#define PIN_PD2__CANTX4 PINMUX_PIN(PIN_PD2, 3, 1) +#define PIN_PD2__D7 PINMUX_PIN(PIN_PD2, 4, 2) +#define PIN_PD2__TIOA0 PINMUX_PIN(PIN_PD2, 5, 2) +#define PIN_PD2__FLEXCOM8_IO0 PINMUX_PIN(PIN_PD2, 6, 5) +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__SDMMC2_CMD PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD3, 2, 2) +#define PIN_PD3__CANRX4 PINMUX_PIN(PIN_PD3, 3, 1) +#define PIN_PD3__NANDRDY PINMUX_PIN(PIN_PD3, 4, 2) +#define PIN_PD3__TIOB0 PINMUX_PIN(PIN_PD3, 5, 2) +#define PIN_PD3__FLEXCOM8_IO1 PINMUX_PIN(PIN_PD3, 6, 5) +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__SDMMC2_CK PINMUX_PIN(PIN_PD4, 1, 1) +#define PIN_PD4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD4, 2, 2) +#define PIN_PD4__CANTX5 PINMUX_PIN(PIN_PD4, 3, 1) +#define PIN_PD4__NCS3_NANDCS PINMUX_PIN(PIN_PD4, 4, 2) +#define PIN_PD4__TCLK0 PINMUX_PIN(PIN_PD4, 5, 2) +#define PIN_PD4__FLEXCOM9_IO0 PINMUX_PIN(PIN_PD4, 6, 5) +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__SDMMC2_DAT0 PINMUX_PIN(PIN_PD5, 1, 1) +#define PIN_PD5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PD5, 2, 2) +#define PIN_PD5__CANRX5 PINMUX_PIN(PIN_PD5, 3, 1) +#define PIN_PD5__NWE_NWR0_NANDWE PINMUX_PIN(PIN_PD5, 4, 2) +#define PIN_PD5__TIOA1 PINMUX_PIN(PIN_PD5, 5, 2) +#define PIN_PD5__FLEXCOM9_IO1 PINMUX_PIN(PIN_PD5, 6, 5) +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__SDMMC2_DAT1 PINMUX_PIN(PIN_PD6, 1, 1) +#define PIN_PD6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PD6, 2, 2) +#define PIN_PD6__SPDIF_RX PINMUX_PIN(PIN_PD6, 3, 3) +#define PIN_PD6__NRD_NANDOE PINMUX_PIN(PIN_PD6, 4, 2) +#define PIN_PD6__TIOB1 PINMUX_PIN(PIN_PD6, 5, 2) +#define PIN_PD6__FLEXCOM10_IO0 PINMUX_PIN(PIN_PD6, 6, 5) +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__SDMMC2_DAT2 PINMUX_PIN(PIN_PD7, 1, 1) +#define PIN_PD7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__SPDIF_TX PINMUX_PIN(PIN_PD7, 2, 2) +#define PIN_PD7__A21_NANDALE PINMUX_PIN(PIN_PD7, 4, 2) +#define PIN_PD7__TCLK1 PINMUX_PIN(PIN_PD7, 5, 2) +#define PIN_PD7__FLEXCOM10_IO1 PINMUX_PIN(PIN_PD7, 6, 5) +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__SDMMC2_DAT3 PINMUX_PIN(PIN_PD8, 1, 1) +#define PIN_PD8__I2SMCC0_DIN0 PINMUX_PIN(PIN_PD8, 3, 1) +#define PIN_PD8__A11_NANDCLE PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__TIOA2 PINMUX_PIN(PIN_PD8, 5, 2) +#define PIN_PD8__FLEXCOM11_IO0 PINMUX_PIN(PIN_PD8, 6, 5) +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__SDMMC2_WP PINMUX_PIN(PIN_PD9, 1, 1) +#define PIN_PD9__I2SMCC0_DIN1 PINMUX_PIN(PIN_PD9, 3, 2) +#define PIN_PD9__D0 PINMUX_PIN(PIN_PD9, 4, 2) +#define PIN_PD9__TIOB2 PINMUX_PIN(PIN_PD9, 5, 2) +#define PIN_PD9__FLEXCOM11_IO1 PINMUX_PIN(PIN_PD9, 6, 5) +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__SDMMC2_CD PINMUX_PIN(PIN_PD10, 1, 1) +#define PIN_PD10__PCK6 PINMUX_PIN(PIN_PD10, 2, 2) +#define PIN_PD10__I2SMCC0_DIN2 PINMUX_PIN(PIN_PD10, 3, 2) +#define PIN_PD10__D1 PINMUX_PIN(PIN_PD10, 4, 2) +#define PIN_PD10__TCLK2 PINMUX_PIN(PIN_PD10, 5, 2) +#define PIN_PD10__FLEXCOM0_IO0 PINMUX_PIN(PIN_PD10, 6, 3) +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__SDMMC2_1V8SEL PINMUX_PIN(PIN_PD11, 1, 1) +#define PIN_PD11__PCK7 PINMUX_PIN(PIN_PD11, 2, 2) +#define PIN_PD11__I2SMCC0_DIN3 PINMUX_PIN(PIN_PD11, 3, 2) +#define PIN_PD11__D2 PINMUX_PIN(PIN_PD11, 4, 2) +#define PIN_PD11__TIOA3 PINMUX_PIN(PIN_PD11, 5, 2) +#define PIN_PD11__FLEXCOM0_IO1 PINMUX_PIN(PIN_PD11, 6, 3) +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__PCK1 PINMUX_PIN(PIN_PD12, 1, 2) +#define PIN_PD12__FLEXCOM1_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +#define PIN_PD12__CANTX0 PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__TIOB3 PINMUX_PIN(PIN_PD12, 5, 2) +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__I2SMCC0_CK PINMUX_PIN(PIN_PD13, 1, 2) +#define PIN_PD13__FLEXCOM1_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +#define PIN_PD13__PWML0 PINMUX_PIN(PIN_PD13, 3, 4) +#define PIN_PD13__CANRX0 PINMUX_PIN(PIN_PD13, 4, 2) +#define PIN_PD13__TCLK3 PINMUX_PIN(PIN_PD13, 5, 2) +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__I2SMCC0_MCK PINMUX_PIN(PIN_PD14, 1, 2) +#define PIN_PD14__FLEXCOM1_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +#define PIN_PD14__PWMH0 PINMUX_PIN(PIN_PD14, 3, 4) +#define PIN_PD14__CANTX1 PINMUX_PIN(PIN_PD14, 4, 2) +#define PIN_PD14__TIOA4 PINMUX_PIN(PIN_PD14, 5, 2) +#define PIN_PD14__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD14, 6, 5) +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__I2SMCC0_WS PINMUX_PIN(PIN_PD15, 1, 2) +#define PIN_PD15__FLEXCOM1_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +#define PIN_PD15__PWML1 PINMUX_PIN(PIN_PD15, 3, 4) +#define PIN_PD15__CANRX1 PINMUX_PIN(PIN_PD15, 4, 2) +#define PIN_PD15__TIOB4 PINMUX_PIN(PIN_PD15, 5, 2) +#define PIN_PD15__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD15, 6, 5) +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__I2SMCC0_DOUT0 PINMUX_PIN(PIN_PD16, 1, 2) +#define PIN_PD16__FLEXCOM1_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +#define PIN_PD16__PWMH1 PINMUX_PIN(PIN_PD16, 3, 4) +#define PIN_PD16__CANTX2 PINMUX_PIN(PIN_PD16, 4, 2) +#define PIN_PD16__TCLK4 PINMUX_PIN(PIN_PD16, 5, 2) +#define PIN_PD16__FLEXCOM3_IO0 PINMUX_PIN(PIN_PD16, 6, 5) +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__I2SMCC0_DOUT1 PINMUX_PIN(PIN_PD17, 1, 2) +#define PIN_PD17__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD17, 2, 2) +#define PIN_PD17__PWML2 PINMUX_PIN(PIN_PD17, 3, 4) +#define PIN_PD17__CANRX2 PINMUX_PIN(PIN_PD17, 4, 2) +#define PIN_PD17__TIOA5 PINMUX_PIN(PIN_PD17, 5, 2) +#define PIN_PD17__FLEXCOM3_IO1 PINMUX_PIN(PIN_PD17, 6, 5) +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__I2SMCC0_DOUT2 PINMUX_PIN(PIN_PD18, 1, 2) +#define PIN_PD18__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD18, 2, 2) +#define PIN_PD18__PWMH2 PINMUX_PIN(PIN_PD18, 3, 4) +#define PIN_PD18__CANTX3 PINMUX_PIN(PIN_PD18, 4, 2) +#define PIN_PD18__TIOB5 PINMUX_PIN(PIN_PD18, 5, 2) +#define PIN_PD18__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD18, 6, 5) +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__I2SMCC0_DOUT3 PINMUX_PIN(PIN_PD19, 1, 2) +#define PIN_PD19__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD19, 2, 2) +#define PIN_PD19__PWML3 PINMUX_PIN(PIN_PD19, 3, 4) +#define PIN_PD19__CANRX3 PINMUX_PIN(PIN_PD19, 4, 2) +#define PIN_PD19__TCLK5 PINMUX_PIN(PIN_PD19, 5, 2) +#define PIN_PD19__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD19, 6, 5) +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__PCK0 PINMUX_PIN(PIN_PD20, 1, 3) +#define PIN_PD20__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD20, 2, 2) +#define PIN_PD20__PWMH3 PINMUX_PIN(PIN_PD20, 3, 4) +#define PIN_PD20__CANTX4 PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD20, 6, 5) +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__PCK1 PINMUX_PIN(PIN_PD21, 1, 3) +#define PIN_PD21__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD21, 2, 2) +#define PIN_PD21__CANRX4 PINMUX_PIN(PIN_PD21, 4, 2) +#define PIN_PD21__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD21, 6, 5) +#define PIN_PD21__G1_TXEN PINMUX_PIN(PIN_PD21, 7, 1) +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__PDMC0_CLK PINMUX_PIN(PIN_PD22, 1, 2) +#define PIN_PD22__PWMEXTRG0 PINMUX_PIN(PIN_PD22, 3, 4) +#define PIN_PD22__RD1 PINMUX_PIN(PIN_PD22, 4, 2) +#define PIN_PD22__CANTX5 PINMUX_PIN(PIN_PD22, 6, 2) +#define PIN_PD22__G1_TX0 PINMUX_PIN(PIN_PD22, 7, 1) +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__PDMC0_DS0 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD23__PWMEXTRG1 PINMUX_PIN(PIN_PD23, 3, 4) +#define PIN_PD23__RF1 PINMUX_PIN(PIN_PD23, 4, 2) +#define PIN_PD23__ISC_MCK PINMUX_PIN(PIN_PD23, 5, 2) +#define PIN_PD23__CANRX5 PINMUX_PIN(PIN_PD23, 6, 2) +#define PIN_PD23__G1_TX1 PINMUX_PIN(PIN_PD23, 7, 1) +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__PDMC0_DS1 PINMUX_PIN(PIN_PD24, 1, 2) +#define PIN_PD24__PWMFI0 PINMUX_PIN(PIN_PD24, 3, 4) +#define PIN_PD24__RK1 PINMUX_PIN(PIN_PD24, 4, 2) +#define PIN_PD24__ISC_D0 PINMUX_PIN(PIN_PD24, 5, 2) +#define PIN_PD24__G1_RXDV PINMUX_PIN(PIN_PD24, 7, 1) +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__PDMC1_CLK PINMUX_PIN(PIN_PD25, 1, 2) +#define PIN_PD25__FLEXCOM5_IO0 PINMUX_PIN(PIN_PD25, 2, 2) +#define PIN_PD25__PWMFI1 PINMUX_PIN(PIN_PD25, 3, 4) +#define PIN_PD25__TD1 PINMUX_PIN(PIN_PD25, 4, 2) +#define PIN_PD25__ISC_D1 PINMUX_PIN(PIN_PD25, 5, 2) +#define PIN_PD25__G1_RX0 PINMUX_PIN(PIN_PD25, 7, 1) +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__PDMC1_DS0 PINMUX_PIN(PIN_PD26, 1, 2) +#define PIN_PD26__FLEXCOM5_IO1 PINMUX_PIN(PIN_PD26, 2, 2) +#define PIN_PD26__ADTRG PINMUX_PIN(PIN_PD26, 3, 3) +#define PIN_PD26__TF1 PINMUX_PIN(PIN_PD26, 4, 2) +#define PIN_PD26__ISC_D2 PINMUX_PIN(PIN_PD26, 5, 2) +#define PIN_PD26__G1_RX1 PINMUX_PIN(PIN_PD26, 7, 1) +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__PDMC1_DS1 PINMUX_PIN(PIN_PD27, 1, 2) +#define PIN_PD27__FLEXCOM5_IO2 PINMUX_PIN(PIN_PD27, 2, 2) +#define PIN_PD27__TIOA0 PINMUX_PIN(PIN_PD27, 3, 3) +#define PIN_PD27__TK1 PINMUX_PIN(PIN_PD27, 4, 2) +#define PIN_PD27__ISC_D3 PINMUX_PIN(PIN_PD27, 5, 2) +#define PIN_PD27__G1_RXER PINMUX_PIN(PIN_PD27, 7, 1) +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__RD0 PINMUX_PIN(PIN_PD28, 1, 2) +#define PIN_PD28__FLEXCOM5_IO3 PINMUX_PIN(PIN_PD28, 2, 2) +#define PIN_PD28__TIOB0 PINMUX_PIN(PIN_PD28, 3, 3) +#define PIN_PD28__I2SMCC1_CK PINMUX_PIN(PIN_PD28, 4, 2) +#define PIN_PD28__ISC_D4 PINMUX_PIN(PIN_PD28, 5, 2) +#define PIN_PD28__PWML3 PINMUX_PIN(PIN_PD28, 6, 5) +#define PIN_PD28__G1_MDC PINMUX_PIN(PIN_PD28, 7, 1) +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__RF0 PINMUX_PIN(PIN_PD29, 1, 2) +#define PIN_PD29__FLEXCOM5_IO4 PINMUX_PIN(PIN_PD29, 2, 2) +#define PIN_PD29__TCLK0 PINMUX_PIN(PIN_PD29, 3, 3) +#define PIN_PD29__I2SMCC1_WS PINMUX_PIN(PIN_PD29, 4, 2) +#define PIN_PD29__ISC_D5 PINMUX_PIN(PIN_PD29, 5, 2) +#define PIN_PD29__PWMH3 PINMUX_PIN(PIN_PD29, 6, 5) +#define PIN_PD29__G1_MDIO PINMUX_PIN(PIN_PD29, 7, 1) +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__RK0 PINMUX_PIN(PIN_PD30, 1, 2) +#define PIN_PD30__FLEXCOM6_IO0 PINMUX_PIN(PIN_PD30, 2, 2) +#define PIN_PD30__TIOA1 PINMUX_PIN(PIN_PD30, 3, 3) +#define PIN_PD30__I2SMCC1_MCK PINMUX_PIN(PIN_PD30, 4, 2) +#define PIN_PD30__ISC_D6 PINMUX_PIN(PIN_PD30, 5, 2) +#define PIN_PD30__PWMEXTRG0 PINMUX_PIN(PIN_PD30, 6, 5) +#define PIN_PD30__G1_TXCK PINMUX_PIN(PIN_PD30, 7, 1) +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__TD0 PINMUX_PIN(PIN_PD31, 1, 2) +#define PIN_PD31__FLEXCOM6_IO1 PINMUX_PIN(PIN_PD31, 2, 2) +#define PIN_PD31__TIOB1 PINMUX_PIN(PIN_PD31, 3, 3) +#define PIN_PD31__I2SMCC1_DOUT0 PINMUX_PIN(PIN_PD31, 4, 2) +#define PIN_PD31__ISC_D7 PINMUX_PIN(PIN_PD31, 5, 2) +#define PIN_PD31__PWM_EXTRG1 PINMUX_PIN(PIN_PD31, 6, 5) +#define PIN_PD31__G1_TX2 PINMUX_PIN(PIN_PD31, 7, 1) +#define PIN_PE0 128 +#define PIN_PE0__GPIO PINMUX_PIN(PIN_PE0, 0, 0) +#define PIN_PE0__TF0 PINMUX_PIN(PIN_PE0, 1, 2) +#define PIN_PE0__FLEXCOM6_IO2 PINMUX_PIN(PIN_PE0, 2, 2) +#define PIN_PE0__TCLK1 PINMUX_PIN(PIN_PE0, 3, 3) +#define PIN_PE0__I2SMCC1_DOUT1 PINMUX_PIN(PIN_PE0, 4, 2) +#define PIN_PE0__ISC_HSYNC PINMUX_PIN(PIN_PE0, 5, 2) +#define PIN_PE0__PWMFI0 PINMUX_PIN(PIN_PE0, 6, 5) +#define PIN_PE0__G1_TX3 PINMUX_PIN(PIN_PE0, 7, 1) +#define PIN_PE1 129 +#define PIN_PE1__GPIO PINMUX_PIN(PIN_PE1, 0, 0) +#define PIN_PE1__TK0 PINMUX_PIN(PIN_PE1, 1, 2) +#define PIN_PE1__FLEXCOM6_IO3 PINMUX_PIN(PIN_PE1, 2, 2) +#define PIN_PE1__TIOA2 PINMUX_PIN(PIN_PE1, 3, 3) +#define PIN_PE1__I2SMCC1_DOUT2 PINMUX_PIN(PIN_PE1, 4, 2) +#define PIN_PE1__ISC_VSYNC PINMUX_PIN(PIN_PE1, 5, 2) +#define PIN_PE1__PWMFI1 PINMUX_PIN(PIN_PE1, 6, 5) +#define PIN_PE1__G1_RX2 PINMUX_PIN(PIN_PE1, 7, 1) +#define PIN_PE2 130 +#define PIN_PE2__GPIO PINMUX_PIN(PIN_PE2, 0, 0) +#define PIN_PE2__PWML0 PINMUX_PIN(PIN_PE2, 1, 5) +#define PIN_PE2__FLEXCOM6_IO4 PINMUX_PIN(PIN_PE2, 2, 2) +#define PIN_PE2__TIOB2 PINMUX_PIN(PIN_PE2, 3, 3) +#define PIN_PE2__I2SMCC1_DOUT3 PINMUX_PIN(PIN_PE2, 4, 2) +#define PIN_PE2__ISC_FIELD PINMUX_PIN(PIN_PE2, 5, 2) +#define PIN_PE2__G1_RX3 PINMUX_PIN(PIN_PE2, 7, 1) +#define PIN_PE3 131 +#define PIN_PE3__GPIO PINMUX_PIN(PIN_PE3, 0, 0) +#define PIN_PE3__PWMH0 PINMUX_PIN(PIN_PE3, 1, 5) +#define PIN_PE3__FLEXCOM0_IO0 PINMUX_PIN(PIN_PE3, 2, 4) +#define PIN_PE3__TCLK2 PINMUX_PIN(PIN_PE3, 3, 3) +#define PIN_PE3__I2SMCC1_DIN0 PINMUX_PIN(PIN_PE3, 4, 2) +#define PIN_PE3__ISC_PCK PINMUX_PIN(PIN_PE3, 5, 2) +#define PIN_PE3__G1_RXCK PINMUX_PIN(PIN_PE3, 7, 1) +#define PIN_PE4 132 +#define PIN_PE4__GPIO PINMUX_PIN(PIN_PE4, 0, 0) +#define PIN_PE4__PWML1 PINMUX_PIN(PIN_PE4, 1, 5) +#define PIN_PE4__FLEXCOM0_IO1 PINMUX_PIN(PIN_PE4, 2, 4) +#define PIN_PE4__TIOA3 PINMUX_PIN(PIN_PE4, 3, 3) +#define PIN_PE4__I2SMCC1_DIN1 PINMUX_PIN(PIN_PE4, 4, 2) +#define PIN_PE4__ISC_D8 PINMUX_PIN(PIN_PE4, 5, 2) +#define PIN_PE4__G1_TXER PINMUX_PIN(PIN_PE4, 7, 1) +#define PIN_PE5 133 +#define PIN_PE5__GPIO PINMUX_PIN(PIN_PE5, 0, 0) +#define PIN_PE5__PWMH1 PINMUX_PIN(PIN_PE5, 1, 5) +#define PIN_PE5__FLEXCOM0_IO2 PINMUX_PIN(PIN_PE5, 2, 4) +#define PIN_PE5__TIOB3 PINMUX_PIN(PIN_PE5, 3, 3) +#define PIN_PE5__I2SMCC1_DIN2 PINMUX_PIN(PIN_PE5, 4, 2) +#define PIN_PE5__ISC_D9 PINMUX_PIN(PIN_PE5, 5, 2) +#define PIN_PE5__G1_COL PINMUX_PIN(PIN_PE5, 7, 1) +#define PIN_PE6 134 +#define PIN_PE6__GPIO PINMUX_PIN(PIN_PE6, 0, 0) +#define PIN_PE6__PWML2 PINMUX_PIN(PIN_PE6, 1, 5) +#define PIN_PE6__FLEXCOM0_IO3 PINMUX_PIN(PIN_PE6, 2, 4) +#define PIN_PE6__TCLK3 PINMUX_PIN(PIN_PE6, 3, 3) +#define PIN_PE6__I2SMCC1_DIN3 PINMUX_PIN(PIN_PE6, 4, 2) +#define PIN_PE6__ISC_D10 PINMUX_PIN(PIN_PE6, 5, 2) +#define PIN_PE6__G1_CRS PINMUX_PIN(PIN_PE6, 7, 1) +#define PIN_PE7 135 +#define PIN_PE7__GPIO PINMUX_PIN(PIN_PE7, 0, 0) +#define PIN_PE7__PWMH2 PINMUX_PIN(PIN_PE7, 1, 5) +#define PIN_PE7__FLEXCOM0_IO4 PINMUX_PIN(PIN_PE7, 2, 4) +#define PIN_PE7__TIOA4 PINMUX_PIN(PIN_PE7, 3, 3) +#define PIN_PE7__ISC_D11 PINMUX_PIN(PIN_PE7, 5, 2) +#define PIN_PE7__G1_TSUCOMP PINMUX_PIN(PIN_PE7, 7, 1) + diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index e9525b5d06..154832983c 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1573,6 +1573,20 @@ }; }; + spi4_pins_a: spi4-0 { + pins { + pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ + <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ + bias-disable; + }; + }; + stusb1600_pins_a: stusb1600-0 { pins { pinmux = <STM32_PINMUX('I', 11, ANALOG)>; @@ -1580,6 +1594,133 @@ }; }; + uart4_pins_a: uart4-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ + }; + }; + + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_pins_c: uart4-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ + bias-disable; + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ + <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ + <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ + bias-disable; + }; + }; + + uart7_pins_b: uart7-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_pins_c: uart7-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_idle_pins_c: uart7-idle-2 { + pins1 { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + uart7_sleep_pins_c: uart7-sleep-2 { + pins { + pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ + bias-disable; + }; + }; + usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ @@ -1628,6 +1769,42 @@ }; }; + usart2_pins_c: usart2-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_c: usart2-idle-2 { + pins1 { + pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_c: usart2-sleep-2 { + pins { + pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; + usart3_pins_a: usart3-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ @@ -1641,6 +1818,78 @@ }; }; + usart3_pins_b: usart3-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_b: usart3-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_b: usart3-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ + }; + }; + + usart3_pins_c: usart3-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_c: usart3-idle-2 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_c: usart3-sleep-2 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ @@ -1782,18 +2031,4 @@ bias-disable; }; }; - - spi4_pins_a: spi4-0 { - pins { - pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ - <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ - bias-disable; - drive-push-pull; - slew-rate = <1>; - }; - pins2 { - pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ - bias-disable; - }; - }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 39d9e545ed..206d3d3c78 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1153,7 +1153,7 @@ }; pwr_mcu: pwr_mcu@50001014 { - compatible = "syscon"; + compatible = "st,stm32mp151-pwr-mcu", "syscon"; reg = <0x50001014 0x4>; }; @@ -1372,6 +1372,8 @@ dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; }; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index d03d4cd260..4c8be9c8eb 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -18,6 +18,8 @@ aliases { ethernet0 = ðernet0; serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; }; chosen { diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 9a8a26710a..045636555d 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -19,6 +19,9 @@ aliases { ethernet0 = ðernet0; serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart7; + serial3 = &usart2; }; chosen { @@ -84,3 +87,11 @@ }; }; }; + +&usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; + status = "disabled"; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 072d646379..dd911c9932 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -361,8 +361,10 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 46f81ce92e..a55e80ce26 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -19,6 +19,7 @@ aliases { serial0 = &uart4; + serial1 = &usart3; ethernet0 = ðernet0; }; @@ -343,6 +344,20 @@ }; }; +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_b>; + pinctrl-1 = <&usart3_sleep_pins_b>; + pinctrl-2 = <&usart3_idle_pins_b>; + /* + * HW flow control USART3_RTS is optional, and isn't default wired to + * the connector. SB23 needs to be soldered in order to use it, and R77 + * (ETH_CLK) should be removed. + */ + uart-has-rtscts; + status = "disabled"; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index d660dfb74e..aa4aa83e05 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -62,7 +62,7 @@ led { compatible = "gpio-leds"; - blue { + led-blue { label = "heartbeat"; gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; @@ -391,6 +391,19 @@ }; }; +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clock-frequency = <400000>; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + &i2s2 { clocks = <&rcc SPI2>, <&rcc SPI2_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; clock-names = "pclk", "i2sclk", "x8k", "x11k"; @@ -610,20 +623,39 @@ }; &uart4 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep", "idle"; pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; status = "okay"; }; +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_c>; + pinctrl-1 = <&uart7_sleep_pins_c>; + pinctrl-2 = <&uart7_idle_pins_c>; + status = "disabled"; +}; + +&usart3 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart3_pins_c>; + pinctrl-1 = <&usart3_sleep_pins_c>; + pinctrl-2 = <&usart3_idle_pins_c>; + uart-has-rtscts; + status = "disabled"; +}; + &usbh_ehci { phys = <&usbphyc_port0>; status = "okay"; }; &usbotg_hs { - dr_mode = "peripheral"; phys = <&usbphyc_port1 0>; phy-names = "usb2-phy"; + usb-role-switch; status = "okay"; }; diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi index fdd4c80aa4..c97943b3c1 100644 --- a/arch/arm/dts/sunxi-u-boot.dtsi +++ b/arch/arm/dts/sunxi-u-boot.dtsi @@ -5,14 +5,74 @@ mmc1 = &mmc2; }; - binman { + binman: binman { + multiple-images; + }; +}; + +&binman { + u-boot-sunxi-with-spl { filename = "u-boot-sunxi-with-spl.bin"; pad-byte = <0xff>; blob { filename = "spl/sunxi-spl.bin"; }; +#ifdef CONFIG_ARM64 + fit { + description = "Configuration to load ATF before U-Boot"; + #address-cells = <1>; + fit,fdt-list = "of-list"; + + images { + uboot { + description = "U-Boot (64-bit)"; + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + + u-boot-nodtb { + }; + }; + atf { + description = "ARM Trusted Firmware"; + type = "firmware"; + arch = "arm64"; + compression = "none"; +/* TODO: Do this with an overwrite in this board's dtb? */ +#ifdef CONFIG_MACH_SUN50I_H6 + load = <0x104000>; + entry = <0x104000>; +#else + load = <0x44000>; + entry = <0x44000>; +#endif + atf-bl31 { + missing-msg = "atf-bl31-sunxi"; + }; + }; + + @fdt-SEQ { + description = "NAME"; + type = "flat_dt"; + compression = "none"; + }; + }; + + configurations { + default = "config-1"; + @config-SEQ { + description = "NAME"; + firmware = "uboot"; + loadables = "atf"; + fdt = "fdt-SEQ"; + }; + }; + }; +#else u-boot-img { offset = <CONFIG_SPL_PAD_TO>; }; +#endif }; }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index a8bbb14f6c..aae3c626f5 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -230,16 +230,16 @@ #io-channel-cells = <1>; label = "ina226-vccint"; reg = <0x40>; - shunt-resistor = <5000>; /* R440 */ - /* 0.78V @ 32A 1 of 6 Phases*/ + shunt-resistor = <500>; /* R440 */ + /* 0.80V @ 32A 1 of 6 Phases*/ }; vcc_soc: ina226@41 { /* u161 */ compatible = "ti,ina226"; #io-channel-cells = <1>; label = "ina226-vcc-soc"; reg = <0x41>; - shunt-resistor = <2000>; /* R1186 */ - /* 0.78V @ 18A */ + shunt-resistor = <500>; /* R1702 */ + /* 0.80V @ 18A */ }; vcc_pmc: ina226@42 { /* u163 */ compatible = "ti,ina226"; @@ -554,6 +554,31 @@ reg = <7>; }; }; + i2c-mux@75 { /* u214 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { /* SFP0_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* SFP0 */ + }; + i2c@1 { /* SFP1_IIC */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* SFP1 */ + }; + i2c@2 { /* QSFP1_I2C */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* QSFP1 */ + }; + /* 3 - 7 unused */ + }; }; &xilinx_ams { diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 04afa518ac..9d2319c0e8 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -73,7 +73,12 @@ ENTRY(_main) #elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #elif defined(CONFIG_INIT_SP_RELATIVE) +#if CONFIG_POSITION_INDEPENDENT + adrp x0, __bss_start /* x0 <- Runtime &__bss_start */ + add x0, x0, #:lo12:__bss_start +#else adr x0, __bss_start +#endif add x0, x0, #CONFIG_SYS_INIT_SP_BSS_OFFSET #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) @@ -102,7 +107,8 @@ ENTRY(_main) adr lr, relocation_return #if CONFIG_POSITION_INDEPENDENT /* Add in link-vs-runtime offset */ - adr x0, _start /* x0 <- Runtime value of _start */ + adrp x0, _start /* x0 <- Runtime value of _start */ + add x0, x0, #:lo12:_start ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */ sub x9, x9, x0 /* x9 <- Run-vs-link offset */ add lr, lr, x9 diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c index a3adaa8a99..8536a70a19 100644 --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c @@ -19,7 +19,7 @@ #include <asm/arch/wdt.h> #include <linux/err.h> #include <linux/kernel.h> -#include <dt-bindings/clock/ast2500-scu.h> +#include <dt-bindings/clock/aspeed-clock.h> /* These configuration parameters are taken from Aspeed SDK */ #define DDR4_MR46_MODE 0x08000000 diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 85524004f9..be1415f909 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -47,6 +47,10 @@ config SAM9X60 bool select CPU_ARM926EJS +config SAMA7G5 + bool + select CPU_V7A + config SAMA5D2 bool select CPU_V7A diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile index 9ced3dc0c1..55477560a8 100644 --- a/arch/arm/mach-at91/armv7/Makefile +++ b/arch/arm/mach-at91/armv7/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_SAMA5D2) += sama5d2_devices.o obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o +obj-$(CONFIG_SAMA7G5) += sama7g5_devices.o obj-y += clock.o obj-y += cpu.o obj-y += reset.o diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c index a8f4356ce9..8b7355042b 100644 --- a/arch/arm/mach-at91/armv7/cpu.c +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -29,6 +29,7 @@ int arch_cpu_init(void) void arch_preboot_os(void) { +#if (IS_ENABLED(CONFIG_ATMEL_PIT_TIMER)) ulong cpiv; at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; @@ -40,6 +41,7 @@ void arch_preboot_os(void) * without waiting for wrapping back to 0 */ writel(cpiv + 0x1000, &pit->mr); +#endif } #if defined(CONFIG_DISPLAY_CPUINFO) diff --git a/arch/arm/mach-at91/armv7/sama7g5_devices.c b/arch/arm/mach-at91/armv7/sama7g5_devices.c new file mode 100644 index 0000000000..a58f671f72 --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama7g5_devices.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Microchip Technology, Inc. + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +char *get_cpu_name(void) +{ + return "SAMA7G5"; +} + diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index 01e00c508a..f7b411cf7d 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -40,6 +40,7 @@ void configure_ddrcfg_input_buffers(bool open); #endif int at91_set_ethaddr(int offset); +int at91_set_eth1addr(int offset); void at91_spi_nor_set_ethaddr(void); int at91_video_show_board_info(void); diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index 88acca8549..0a16c8ff08 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h @@ -24,6 +24,8 @@ # include <asm/arch/at91sam9x5.h> #elif defined(CONFIG_SAM9X60) # include <asm/arch/sam9x60.h> +#elif defined(CONFIG_SAMA7G5) +# include <asm/arch/sama7g5.h> #elif defined(CONFIG_SAMA5D2) # include <asm/arch/sama5d2.h> #elif defined(CONFIG_SAMA5D3) diff --git a/arch/arm/mach-at91/include/mach/sama7g5.h b/arch/arm/mach-at91/include/mach/sama7g5.h new file mode 100644 index 0000000000..ae43e8700b --- /dev/null +++ b/arch/arm/mach-at91/include/mach/sama7g5.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Chip-specific header file for the SAMA7G5 SoC + * + * Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries + * Eugen Hristev <eugen.hristev@microchip.com> + */ + +#ifndef __SAMA7G5_H__ +#define __SAMA7G5_H__ + +/* + * Peripheral identifiers/interrupts. + */ +#define ATMEL_ID_FLEXCOM0 38 +#define ATMEL_ID_FLEXCOM1 39 +#define ATMEL_ID_FLEXCOM2 40 +#define ATMEL_ID_FLEXCOM3 41 + +#define ATMEL_ID_SDMMC0 80 +#define ATMEL_ID_SDMMC1 81 + +#define ATMEL_ID_PIT64B0 70 +#define ATMEL_ID_PIT64B ATMEL_ID_PIT64B0 + +#define ATMEL_CHIPID_CIDR 0xe0020000 +#define ATMEL_CHIPID_EXID 0xe0020004 +/* + * User Peripherals physical base addresses. + */ +#define ATMEL_BASE_PIOA 0xe0014000 +#define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40) +#define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40) +#define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40) +#define ATMEL_BASE_PIOE (ATMEL_BASE_PIOD + 0x40) + +#define ATMEL_PIO_PORTS 5 + +#define CPU_HAS_PCR + +#define ATMEL_BASE_PMC 0xe0018000 + +#define ATMEL_BASE_WDT 0xe001c000 +#define ATMEL_BASE_RSTC 0xe001d000 +#define ATMEL_BASE_WDTS 0xe001d180 +#define ATMEL_BASE_SCKCR 0xe001d050 + +#define ATMEL_BASE_SDMMC0 0xe1204000 +#define ATMEL_BASE_SDMMC1 0xe1208000 + +#define ATMEL_BASE_PIT64B0 0xe1800000 + +#define ATMEL_BASE_FLEXCOM0 0xe1818000 +#define ATMEL_BASE_FLEXCOM1 0xe181c000 +#define ATMEL_BASE_FLEXCOM2 0xe1820000 +#define ATMEL_BASE_FLEXCOM3 0xe1824000 +#define ATMEL_BASE_FLEXCOM4 0xe2018000 + +#define ATMEL_BASE_TZC400 0xe3000000 + +#define ATMEL_BASE_UMCTL2 0xe3800000 +#define ATMEL_BASE_UMCTL2_MP 0xe38003f8 +#define ATMEL_BASE_PUBL 0xe3804000 + +#define ATMEL_NUM_FLEXCOM 12 +#define ATMEL_PIO_PORTS 5 + +#define ATMEL_BASE_PIT64BC ATMEL_BASE_PIT64B0 + +#ifndef __ASSEMBLY__ +char *get_cpu_name(void); +#endif + +#endif /* #ifndef __SAMA7G5_H__ */ diff --git a/arch/arm/mach-ipq40xx/clock-ipq4019.c b/arch/arm/mach-ipq40xx/clock-ipq4019.c index 7cf98a203c..83a688e625 100644 --- a/arch/arm/mach-ipq40xx/clock-ipq4019.c +++ b/arch/arm/mach-ipq40xx/clock-ipq4019.c @@ -13,6 +13,8 @@ #include <dm.h> #include <errno.h> +#include <dt-bindings/clock/qcom,ipq4019-gcc.h> + struct msm_clk_priv { phys_addr_t base; }; @@ -20,7 +22,7 @@ struct msm_clk_priv { ulong msm_set_rate(struct clk *clk, ulong rate) { switch (clk->id) { - case 26: /*UART1*/ + case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/ /* This clock is already initialized by SBL1 */ return 0; break; diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 95f830b7ff..a0da3df593 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -2,8 +2,9 @@ /* * K3: ARM64 MMU setup * - * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla <lokeshvutla@ti.com> + * Suman Anna <s-anna@ti.com> * (This file is derived from arch/arm/mach-zynqmp/cpu.c) * */ @@ -66,6 +67,8 @@ struct mm_region *mem_map = am654_mem_map; #endif /* CONFIG_SOC_K3_AM6 */ #ifdef CONFIG_SOC_K3_J721E + +#ifdef CONFIG_TARGET_J721E_A72_EVM /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) @@ -122,4 +125,58 @@ struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = j721e_mem_map; +#endif /* CONFIG_TARGET_J721E_A72_EVM */ + +#ifdef CONFIG_TARGET_J7200_A72_EVM +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) + +/* ToDo: Add 64bit IO */ +struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xa0000000UL, + .phys = 0xa0000000UL, + .size = 0x04800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0xa4800000UL, + .phys = 0xa4800000UL, + .size = 0x5b800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = j7200_mem_map; +#endif /* CONFIG_TARGET_J7200_A72_EVM */ + #endif /* CONFIG_SOC_K3_J721E */ diff --git a/arch/arm/mach-k3/include/mach/j721e_spl.h b/arch/arm/mach-k3/include/mach/j721e_spl.h index 3fa85ca3b6..e8947917a6 100644 --- a/arch/arm/mach-k3/include/mach/j721e_spl.h +++ b/arch/arm/mach-k3/include/mach/j721e_spl.h @@ -15,6 +15,7 @@ #define BOOT_DEVICE_ETHERNET 0x04 #define BOOT_DEVICE_I2C 0x06 #define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH /* With BootMode B = 1 */ #define BOOT_DEVICE_MMC2 0x10 diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index c4cc11f1de..b4fde46fcb 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -196,8 +196,8 @@ int board_usb_init(int index, enum usb_init_type init) for (i = 0; i < 2; i++) { ret = generic_phy_init(&usb_phys[i]); if (ret) { - pr_err("Can't init USB PHY%d for %s\n", - i, ofnode_get_name(dwc2_node)); + pr_debug("Can't init USB PHY%d for %s\n", + i, ofnode_get_name(dwc2_node)); return ret; } } @@ -205,8 +205,8 @@ int board_usb_init(int index, enum usb_init_type init) for (i = 0; i < 2; i++) { ret = generic_phy_power_on(&usb_phys[i]); if (ret) { - pr_err("Can't power USB PHY%d for %s\n", - i, ofnode_get_name(dwc2_node)); + pr_debug("Can't power USB PHY%d for %s\n", + i, ofnode_get_name(dwc2_node)); return ret; } } diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index a7b56b6bb3..2888390d24 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -14,6 +14,7 @@ #include <init.h> #include <net.h> #include <ns16550.h> +#include <omap3_spi.h> #include <spl.h> #include <asm/arch/cpu.h> #include <asm/arch/hardware.h> @@ -49,6 +50,12 @@ #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC #define AM43XX_RDWRLVLFULL_START 0x80000000 +/* SPI flash. */ +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +#define AM33XX_SPI0_BASE 0x48030000 +#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET) +#endif + DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = { #endif }; #endif +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct omap3_spi_plat omap3_spi_pdata = { + .regs = (struct mcspi *)AM33XX_SPI0_OFFSET, + .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT, +}; + +U_BOOT_DEVICE(am33xx_spi) = { + .name = "omap3_spi", + .platdata = &omap3_spi_pdata, +}; +#endif #endif #if !CONFIG_IS_ENABLED(DM_GPIO) diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index ce9312f9d8..5bde24ae0e 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -10,6 +10,7 @@ #define PRR_MASK 0x7fff #define R8A7796_REV_1_0 0x5200 #define R8A7796_REV_1_1 0x5210 +#define R8A7796_REV_1_3 0x5211 static u32 rmobile_get_prr(void) { @@ -28,8 +29,9 @@ u32 rmobile_get_cpu_type(void) u32 rmobile_get_cpu_rev_integer(void) { const u32 prr = rmobile_get_prr(); + const u32 rev = prr & PRR_MASK; - if ((prr & PRR_MASK) == R8A7796_REV_1_1) + if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3) return 1; else return ((prr & 0x000000F0) >> 4) + 1; @@ -38,9 +40,12 @@ u32 rmobile_get_cpu_rev_integer(void) u32 rmobile_get_cpu_rev_fraction(void) { const u32 prr = rmobile_get_prr(); + const u32 rev = prr & PRR_MASK; - if ((prr & PRR_MASK) == R8A7796_REV_1_1) + if (rev == R8A7796_REV_1_1) return 1; + else if (rev == R8A7796_REV_1_3) + return 3; else return prr & 0x0000000F; } diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S index 213ec143e2..1df2c40345 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S +++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S @@ -31,6 +31,12 @@ ENTRY(save_boot_params) b save_boot_params_ret ENDPROC(save_boot_params) +.pushsection .text.s_init, "ax" +WEAK(s_init) + ret +ENDPROC(s_init) +.popsection + ENTRY(lowlevel_init) mov x29, lr /* Save LR */ diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig index e1d66e8d32..ebd2da3887 100644 --- a/arch/arm/mach-versal/Kconfig +++ b/arch/arm/mach-versal/Kconfig @@ -62,4 +62,7 @@ config VERSAL_NO_DDR This option configures MMU with no DDR to avoid speculative access to DDR memory where DDR is not present. +source "board/xilinx/Kconfig" +source "board/xilinx/versal/Kconfig" + endif diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 79f831e6df..e54310383b 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -70,4 +70,7 @@ config BOOT_INIT_FILE config ZYNQ_SDHCI_MAX_FREQ default 52000000 +source "board/xilinx/Kconfig" +source "board/xilinx/zynq/Kconfig" + endif diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 77b7cb1307..3befc12028 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -17,8 +17,7 @@ #define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28 -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(FPGA) xilinx_desc fpga = { .family = xilinx_zynq, .iface = devcfg, @@ -111,8 +110,7 @@ static int __maybe_unused cpu_desc_id(void) #if defined(CONFIG_ARCH_EARLY_INIT_R) int arch_early_init_r(void) { -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(FPGA) int cpu_id = cpu_desc_id(); if (cpu_id < 0) diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 239ce3436a..cb8cfd2f35 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -34,7 +34,7 @@ void board_init_f(ulong dummy) void spl_board_init(void) { preloader_console_init(); -#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT) +#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA) arch_early_init_r(); #endif board_init(); diff --git a/arch/arm/mach-zynqmp-r5/cpu.c b/arch/arm/mach-zynqmp-r5/cpu.c index b3402d7189..87c1d75f9f 100644 --- a/arch/arm/mach-zynqmp-r5/cpu.c +++ b/arch/arm/mach-zynqmp-r5/cpu.c @@ -11,11 +11,9 @@ DECLARE_GLOBAL_DATA_PTR; struct mpu_region_config region_config[] = { - { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_1GB }, - { 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO, - O_I_WB_RD_WR_ALLOC, REGION_512MB }, - { 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO, + { 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW, + SHARED_WRITE_BUFFERED, REGION_4GB }, + { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_1GB }, }; @@ -23,8 +21,7 @@ int arch_cpu_init(void) { gd->cpu_clk = CONFIG_CPU_FREQ_HZ; - setup_mpu_regions(region_config, sizeof(region_config) / - sizeof(struct mpu_region_config)); + setup_mpu_regions(region_config, ARRAY_SIZE(region_config)); return 0; } diff --git a/arch/arm/mach-zynqmp/Kconfig b/arch/arm/mach-zynqmp/Kconfig index d82a737a69..f1301f6661 100644 --- a/arch/arm/mach-zynqmp/Kconfig +++ b/arch/arm/mach-zynqmp/Kconfig @@ -171,4 +171,7 @@ config SD1_LSHFT_MODE endchoice +source "board/xilinx/Kconfig" +source "board/xilinx/zynqmp/Kconfig" + endif diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 64e5320acc..7d7ab9da6e 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -65,7 +65,7 @@ struct xfsbl_atf_handoff_params { struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; }; -#ifdef CONFIG_SPL_OS_BOOT +#ifdef CONFIG_SPL_ATF struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, uintptr_t bl33_entry, uintptr_t fdt_addr) diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h index 8e6be0ae26..632bb236fb 100644 --- a/arch/microblaze/include/asm/io.h +++ b/arch/microblaze/include/asm/io.h @@ -50,14 +50,24 @@ #define outw(x, addr) ((void)writew(x, addr)) #define outl(x, addr) ((void)writel(x, addr)) -/* Some #definitions to keep strange Xilinx code happy */ -#define in_8(addr) readb(addr) -#define in_be16(addr) readw(addr) -#define in_be32(addr) readl(addr) +#define out_arch(type, endian, addr, x) \ + __raw_write##type(cpu_to_##endian(x), addr) +#define in_arch(type, endian, addr) \ + endian##_to_cpu(__raw_read##type(addr)) + +#define out_le16(addr, x) out_arch(w, le16, addr, x) +#define out_le32(addr, x) out_arch(l, le32, addr, x) + +#define in_le16(addr) in_arch(w, le16, addr) +#define in_le32(addr) in_arch(l, le32, addr) + +#define in_8(addr) readb(addr) +#define in_be16(addr) in_arch(w, be16, addr) +#define in_be32(addr) in_arch(l, be32, addr) #define out_8(addr, x) outb(x, addr) -#define out_be16(addr, x) outw(x, addr) -#define out_be32(addr, x) outl(x, addr) +#define out_be16(addr, x) out_arch(w, be16, addr, x) +#define out_be32(addr, x) out_arch(l, be32, addr, x) #define inb_p(port) inb((port)) #define outb_p(val, port) outb((val), (port)) diff --git a/arch/mips/lib/boot.c b/arch/mips/lib/boot.c index db862f6379..6ef9109022 100644 --- a/arch/mips/lib/boot.c +++ b/arch/mips/lib/boot.c @@ -17,7 +17,7 @@ unsigned long do_go_exec(ulong (*entry)(int, char * const []), * whole SDRAM area, since we don't know the size of the image * that was loaded. */ - flush_cache(gd->bd->bi_memstart, gd->ram_top - gd->bd->bi_memstart); + flush_cache(gd->ram_base, gd->ram_top - gd->ram_base); return entry(argc, argv); } diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 0a13f6edb7..d5c99d891c 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -242,7 +242,7 @@ static int boot_reloc_fdt(bootm_headers_t *images) #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) int arch_fixup_fdt(void *blob) { - u64 mem_start = virt_to_phys((void *)gd->bd->bi_memstart); + u64 mem_start = virt_to_phys((void *)gd->ram_base); u64 mem_size = gd->ram_size; return fdt_fixup_memory_banks(blob, &mem_start, &mem_size, 1); diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 18808da37d..2bae08e278 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -101,34 +101,42 @@ config TARGET_IDS8313 config TARGET_KMETER1 bool "Support kmeter1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMCOGE5NE bool "Support kmcoge5ne" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEGR1 bool "Support kmtegr1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUXX1 bool "Support tuxx1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMSUPX5 bool "Support kmsupx5" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUGE1 bool "Support tuge1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMOPTI2 bool "Support kmopti2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEPR2 bool "Support kmtepr2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TQM834X bool "Support TQM834x" diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 304029977e..aeb42b109d 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -27,7 +27,9 @@ obj-y += cpu_init.o obj-y += speed.o obj-y += interrupts.o obj-y += ecc.o +ifndef CONFIG_PINCTRL obj-$(CONFIG_QE) += qe_io.o +endif obj-$(CONFIG_FSL_SERDES) += serdes.o ifndef CONFIG_ARCH_MPC8308 obj-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 438b14b162..840f907acb 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -9,10 +9,14 @@ #include <ioports.h> #include <asm/io.h> #include <asm/processor.h> +#include <fsl_qe.h> #ifdef CONFIG_USB_EHCI_FSL #include <usb/ehci-ci.h> #endif #include <linux/delay.h> +#ifdef CONFIG_QE +#include <fsl_qe.h> +#endif #include "lblaw/lblaw.h" #include "elbc/elbc.h" @@ -26,9 +30,8 @@ DECLARE_GLOBAL_DATA_PTR; extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); -extern void qe_init(uint qe_base); -extern void qe_reset(void); +#if !defined(CONFIG_PINCTRL) static void config_qe_ioports(void) { u8 port, pin; @@ -45,6 +48,7 @@ static void config_qe_ioports(void) } } #endif +#endif /* * Breathe some life into the CPU... @@ -191,10 +195,13 @@ void cpu_init_f (volatile immap_t * im) __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif +#if !defined(CONFIG_PINCTRL) #ifdef CONFIG_QE /* Config QE ioports */ config_qe_ioports(); #endif +#endif + /* Set up preliminary BR/OR regs */ init_early_memctl_regs(); diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c index ebdedb2888..4ea7b27ef4 100644 --- a/arch/powerpc/cpu/mpc83xx/fdt.c +++ b/arch/powerpc/cpu/mpc83xx/fdt.c @@ -121,7 +121,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_serial_clock(), 1); #endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #if defined(CONFIG_BOOTCOUNT_LIMIT) && \ (defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X)) diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 88aa689551..52360703a7 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -12,57 +12,93 @@ #include <asm/immap_83xx.h> #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) + +/** qe_cfg_iopin configure one io pin setting + * + * @par_io: pointer to parallel I/O base + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir, + int open_drain, int assign) { - u32 pin_2bit_mask; - u32 pin_2bit_dir; - u32 pin_2bit_assign; - u32 pin_1bit_mask; - u32 tmp_val; - volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + u32 dbit_mask; + u32 dbit_dir; + u32 dbit_asgn; + u32 bit_mask; + u32 tmp_val; + int offset; + + offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2); /* Calculate pin location and 2bit mask and dir */ - pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); - pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); + dbit_mask = (u32)(0x3 << offset); + dbit_dir = (u32)(dir << offset); /* Setup the direction */ - tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \ + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? in_be32(&par_io->ioport[port].dir2) : in_be32(&par_io->ioport[port].dir1); - if (pin > (NUM_OF_PINS/2) -1) { - out_be32(&par_io->ioport[port].dir2, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir2, pin_2bit_dir | tmp_val); + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val); } else { - out_be32(&par_io->ioport[port].dir1, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); + out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val); } /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1))); /* Setup the open drain */ tmp_val = in_be32(&par_io->ioport[port].podr); - if (open_drain) { - out_be32(&par_io->ioport[port].podr, pin_1bit_mask | tmp_val); - } else { - out_be32(&par_io->ioport[port].podr, ~pin_1bit_mask & tmp_val); - } + if (open_drain) + out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val); + else + out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val); /* Setup the assignment */ - tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? - in_be32(&par_io->ioport[port].ppar2): + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? + in_be32(&par_io->ioport[port].ppar2) : in_be32(&par_io->ioport[port].ppar1); - pin_2bit_assign = (u32)(assign - << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2)); + dbit_asgn = (u32)(assign << offset); /* Clear and set 2 bits mask */ - if (pin > (NUM_OF_PINS/2) - 1) { - out_be32(&par_io->ioport[port].ppar2, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar2, pin_2bit_assign | tmp_val); + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val); } else { - out_be32(&par_io->ioport[port].ppar1, ~pin_2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar1, pin_2bit_assign | tmp_val); + out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val); } } + +#if !defined(CONFIG_PINCTRL) +/** qe_config_iopin configure one io pin setting + * + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); +} +#endif diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index c3cc119d65..ea8bc6c152 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -23,7 +23,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Returns 0 if exception not found and fixup otherwise. */ extern unsigned long search_exception_table(unsigned long); -#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) +#define END_OF_MEM (gd->ram_base + gd->ram_size) /* * Trap & Exception support diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 753d0750b2..54c7fd9522 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -40,14 +40,6 @@ config TARGET_P4080DS imply CMD_SATA imply PANIC_HANG -config TARGET_P5020DS - bool "Support P5020DS" - select PHYS_64BIT - select ARCH_P5020 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - imply CMD_SATA - imply PANIC_HANG - config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT @@ -109,22 +101,6 @@ config TARGET_P1010RDB_PB imply CMD_SATA imply PANIC_HANG -config TARGET_P1023RDB - bool "Support P1023RDB" - select ARCH_P1023 - select FSL_DDR_INTERACTIVE - imply CMD_EEPROM - imply PANIC_HANG - -config TARGET_P1020MBG - bool "Support P1020MBG-PC" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P1020RDB_PC bool "Support P1020RDB-PC" select SUPPORT_SPL @@ -143,42 +119,6 @@ config TARGET_P1020RDB_PD imply CMD_SATA imply PANIC_HANG -config TARGET_P1020UTM - bool "Support P1020UTM" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1021RDB - bool "Support P1021RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1021 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1024RDB - bool "Support P1024RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1024 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - -config TARGET_P1025RDB - bool "Support P1025RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1025 - imply CMD_EEPROM - imply CMD_SATA - imply SATA_SIL - config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL @@ -1506,7 +1446,6 @@ source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" -source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9569c1a64b..0d8353ceb2 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -672,10 +672,10 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) "clock-frequency", get_bus_freq(0), 1); #endif - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #ifdef CONFIG_MP - ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); + ft_fixup_cpu(blob, (u64)gd->ram_base + (u64)gd->ram_size); ft_fixup_num_cores(blob); #endif diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index f37a45e269..db6ed1fc92 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -37,7 +37,7 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) +#define END_OF_MEM (gd->ram_base + get_effective_memsize()) static __inline__ void set_tsr(unsigned long val) { diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c index 24e53115ec..010b6d4fe6 100644 --- a/arch/powerpc/cpu/mpc86xx/fdt.c +++ b/arch/powerpc/cpu/mpc86xx/fdt.c @@ -8,6 +8,8 @@ #include <fdt_support.h> #include <asm/mp.h> +DECLARE_GLOBAL_DATA_PTR; + extern void ft_fixup_num_cores(void *blob); extern void ft_srio_setup(void *blob); @@ -27,7 +29,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) do_fixup_by_prop_u32(blob, "device_type", "soc", 4, "bus-frequency", bd->bi_busfreq, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); #ifdef CONFIG_SYS_NS16550 do_fixup_by_compat_u32(blob, "ns16550", diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c index c0161e3379..3ee0ec859c 100644 --- a/arch/powerpc/cpu/mpc86xx/traps.c +++ b/arch/powerpc/cpu/mpc86xx/traps.c @@ -30,7 +30,7 @@ extern unsigned long search_exception_table(unsigned long); * amount of memory on the system if we're unable to keep all * the memory mapped in. */ -#define END_OF_MEM (gd->bd->bi_memstart + get_effective_memsize()) +#define END_OF_MEM (gd->ram_base + get_effective_memsize()) /* * Trap & Exception support diff --git a/arch/powerpc/cpu/mpc8xx/fdt.c b/arch/powerpc/cpu/mpc8xx/fdt.c index 4d952a3882..226e258f0e 100644 --- a/arch/powerpc/cpu/mpc8xx/fdt.c +++ b/arch/powerpc/cpu/mpc8xx/fdt.c @@ -25,5 +25,5 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency", gd->arch.brg_clk, 1); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); } diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 2b24e755fa..b2d1dc5b48 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -343,6 +343,7 @@ int fixup_cpu(void) return 0; } +#ifndef CONFIG_DM_ETH /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() @@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis) #endif return 0; } +#endif diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 7eb005f450..266d345f72 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,11 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb +dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb +dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb +dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb +dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb +dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb @@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb +dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb +dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi new file mode 100644 index 0000000000..c44ce7d8dc --- /dev/null +++ b/arch/powerpc/dts/km8309-uboot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8309 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8309@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km8321-uboot.dtsi b/arch/powerpc/dts/km8321-uboot.dtsi new file mode 100644 index 0000000000..348826057a --- /dev/null +++ b/arch/powerpc/dts/km8321-uboot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8321 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8321@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&enet_piggy2 { + status = "okay"; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + compatible = "fsl,mpc8360-par_io"; + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/powerpc/dts/km8321.dtsi b/arch/powerpc/dts/km8321.dtsi new file mode 100644 index 0000000000..e49361359d --- /dev/null +++ b/arch/powerpc/dts/km8321.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km8321 common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <528000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8321@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8321-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_d: gpio-controller@48 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + mdio: mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@00 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km8321-uboot.dtsi" diff --git a/arch/powerpc/dts/km836x-uboot.dtsi b/arch/powerpc/dts/km836x-uboot.dtsi new file mode 100644 index 0000000000..ac5339eff6 --- /dev/null +++ b/arch/powerpc/dts/km836x-uboot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8360@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km836x.dtsi b/arch/powerpc/dts/km836x.dtsi new file mode 100644 index 0000000000..a8c83fc7e3 --- /dev/null +++ b/arch/powerpc/dts/km836x.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; /* 32 bytes */ + i-cache-line-size = <32>; /* 32 bytes */ + d-cache-size = <32768>; /* L1, 32K */ + i-cache-size = <32768>; /* L1, 32K */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + clock-frequency = <0>; /* Filled in by U-Boot */ + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by U-Boot */ + }; + + soc: soc8360@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x00200000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>;/* Filled in by U-Boot */ + + /* power management control module*/ + pmc: power@b00 { + compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8360-par_io"; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_c: gpio-controller@30 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1430 0x18>; + gpio-controller; + }; + }; + + qe: qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0x0 0x100000 0x100000>; + reg = <0x100000 0x480>; + clock-frequency = <0>; /* Filled in by U-Boot */ + brg-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x0000c000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0xc000>; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = < + 32 0x8 /* ucc1 */ + 33 0x8 /* ucc2 */ + 34 0x8 /* ucc3 */ + 35 0x8 /* ucc4 */ + 40 0x8 /* ucc1 */ + >; + interrupt-parent = <&ipic>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + + bootcount@0x1bff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x1bff8 0x08>; + }; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km836x-uboot.dtsi" diff --git a/arch/powerpc/dts/kmcoge5ne-uboot.dtsi b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi new file mode 100644 index 0000000000..6a5e74f434 --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + }; +}; + +&enet_switch { + status = "disabled"; +}; + +&enet_mate { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmcoge5ne.dts b/arch/powerpc/dts/kmcoge5ne.dts new file mode 100644 index 0000000000..467e5bd9d2 --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMCOGE5ne Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "kmcoge5ne"; + compatible = "ABB,kmcoge5ne"; + + aliases { + ethernet0 = &enet_admin; + ethernet1 = &enet_mate; + ethernet2 = &enet_switch; + serial0 = &serial0; + }; +}; + +&soc { + /* brg for hdlc clk */ + brg@0 { + compatible = "fsl,mpc-brg"; + brg-name = "brg16"; + brg-frequency = <20000000>; /* 20 MHz */ + pio-handle = <&pio_brg>; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the fan unit */ + fanu-ivm@50 { + label = "FANUV"; + compatible = "dummy"; + reg = <0x50>; + }; + + /* fan unit (GPIOs and so on) */ + fanu@20 { + label = "FANUV_CTRL"; + compatible = "dummy"; + reg = <0x20>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + backplane@50 { + label = "BP_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */ + 0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */ + 0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */ + 0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */ + 0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */ + 0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */ + 0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */ + 0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */ + 0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */ + 0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */ + 0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */ + 2 9 1 0 3 0 /* GTX_CLK (CLK10) */ + 2 8 2 0 1 0 /* GTX125 (CLK9) */ + >; + }; + + pio_ucc4: ucc_pin@3 { /* RMII, admin front port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */ + 4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */ + >; + }; + + pio_brg: brg_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 25 1 0 1 0 /* BRG (PC25, out, f1) */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* mng-switch port (UCC1, MDIO 0x10, RGMII) */ + enet_switch: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + /*id=0, full-dup, 1G, no-pause, no-asym_p*/ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* admin and debug port (UCC4, MDIO 0x00, RMII) */ + enet_admin: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_admin>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* mate backplane port (UCC5, MDIO 0x08, RMII) */ + enet_mate: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_mate>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* admin front port (UCC4, MDIO 0x00, RMII) */ + phy_admin: ethernet-phy@00 { + reg = <0x0>; + }; + + /* mate bp port (UCC5, MDIO 0x08, RMII) */ + phy_mate: ethernet-phy@08 { + reg = <0x08>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 3 0 0xa0000000 0x10000000 + 4 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmcoge5ne-uboot.dtsi" diff --git a/arch/powerpc/dts/kmeter1-uboot.dtsi b/arch/powerpc/dts/kmeter1-uboot.dtsi new file mode 100644 index 0000000000..898fa7dc7a --- /dev/null +++ b/arch/powerpc/dts/kmeter1-uboot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmeter1 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + /delete-property/ ethernet3; + /delete-property/ ethernet4; + /delete-property/ ethernet5; + /delete-property/ ethernet6; + }; +}; + +&enet_estar1 { + status = "disabled"; +}; + +&enet_estar2 { + status = "disabled"; +}; + +&enet_eth1 { + status = "disabled"; +}; + +&enet_eth2 { + status = "disabled"; +}; + +&enet_eth3 { + status = "disabled"; +}; + +&enet_eth4 { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmeter1.dts b/arch/powerpc/dts/kmeter1.dts new file mode 100644 index 0000000000..f1f79952ab --- /dev/null +++ b/arch/powerpc/dts/kmeter1.dts @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMETER1 Device Tree Source + * + * 2008-2011 DENX Software Engineering GmbH + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "KMETER1"; + compatible = "ABB,KMETER1"; + + aliases { + ethernet0 = &enet_piggy2; + ethernet1 = &enet_estar1; + ethernet2 = &enet_estar2; + ethernet3 = &enet_eth1; + ethernet4 = &enet_eth2; + ethernet5 = &enet_eth3; + ethernet6 = &enet_eth4; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "Top"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "Control"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "Power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "Front"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 3 1 0 1 0 /* TxD0 */ + 0 4 1 0 1 0 /* TxD1 */ + 0 5 1 0 1 0 /* TxD2 */ + 0 6 1 0 1 0 /* TxD3 */ + 0 9 2 0 1 0 /* RxD0 */ + 0 10 2 0 1 0 /* RxD1 */ + 0 11 2 0 1 0 /* RxD2 */ + 0 12 2 0 1 0 /* RxD3 */ + 0 7 1 0 1 0 /* TX_EN */ + 0 8 1 0 1 0 /* TX_ER */ + 0 15 2 0 1 0 /* RX_DV */ + 0 16 2 0 1 0 /* RX_ER */ + 0 0 2 0 1 0 /* RX_CLK */ + 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ + 2 8 2 0 1 0 /* GTX125 - CLK9 */ + >; + }; + + pio_ucc2: ucc_pin@1 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 17 1 0 1 0 /* TxD0 */ + 0 18 1 0 1 0 /* TxD1 */ + 0 19 1 0 1 0 /* TxD2 */ + 0 20 1 0 1 0 /* TxD3 */ + 0 23 2 0 1 0 /* RxD0 */ + 0 24 2 0 1 0 /* RxD1 */ + 0 25 2 0 1 0 /* RxD2 */ + 0 26 2 0 1 0 /* RxD3 */ + 0 21 1 0 1 0 /* TX_EN */ + 0 22 1 0 1 0 /* TX_ER */ + 0 29 2 0 1 0 /* RX_DV */ + 0 30 2 0 1 0 /* RX_ER */ + 0 31 2 0 1 0 /* RX_CLK */ + 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ + 2 3 2 0 1 0 /* GTX125 - CLK4 */ + >; + }; + + pio_ucc4: ucc_pin@3 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + >; + }; + + pio_ucc6: ucc_pin@5 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ + 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ + 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ + 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ + 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ + 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ + 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ + >; + }; + + pio_ucc7: ucc_pin@6 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ + 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ + 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ + 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ + 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ + 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ + 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ + >; + }; + + pio_ucc8: ucc_pin@7 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ + 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ + 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ + 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ + 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ + 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ + 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */ + >; + }; + + /* UCC3 as HDLC controller for ICN */ + pio5: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 1 0 1 0 1 0 /* TxD0 */ + 1 6 2 0 1 0 /* RxD0 */ + 1 12 2 0 1 0 /* CTS */ + 2 11 2 0 1 0 /* TX-CLK12 */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + enet_estar1: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy_estar1>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + enet_estar2: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy_estar2>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc2>; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + enet_eth1: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth1>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + enet_eth2: ucc@3400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <6>; + reg = <0x3400 0x200>; + interrupts = <41>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc6>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + enet_eth3: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth3>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc7>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + enet_eth4: ucc@3600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <8>; + reg = <0x3600 0x200>; + interrupts = <43>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth4>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc8>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + phy_eth1: ethernet-phy@8 { + reg = <0x08>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + phy_eth2: ethernet-phy@9 { + reg = <0x09>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + phy_eth3: ethernet-phy@a { + reg = <0x0a>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + phy_eth4: ethernet-phy@b { + reg = <0x0b>; + }; + + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + phy_estar1: ethernet-phy@10 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x10>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + phy_estar2: ethernet-phy@11 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x11>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ + 1 0 0xe8000000 0x01000000 /* LB 1 */ + 3 0 0xa0000000 0x10000000>; /* LB 3 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmeter1-uboot.dtsi" diff --git a/arch/powerpc/dts/kmopti2.dts b/arch/powerpc/dts/kmopti2.dts new file mode 100644 index 0000000000..23e31872dd --- /dev/null +++ b/arch/powerpc/dts/kmopti2.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA OPTI2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMOPTI2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 PAXE */ + 3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupc5.dts b/arch/powerpc/dts/kmsupc5.dts new file mode 100644 index 0000000000..60ca0d3324 --- /dev/null +++ b/arch/powerpc/dts/kmsupc5.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPC5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPC5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + /* UCC4_RMII_CLK (CLK17) */ + 3 10 2 0 3 0 + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + * port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&spi0 { + pio-handle = <&pio_spi>; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupm5.dts b/arch/powerpc/dts/kmsupm5.dts new file mode 100644 index 0000000000..1cd11c3344 --- /dev/null +++ b/arch/powerpc/dts/kmsupm5.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPM5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPM5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts new file mode 100644 index 0000000000..c9b21cf500 --- /dev/null +++ b/arch/powerpc/dts/kmtegr1.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEGR1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +/ { + model = "KMTEGR1"; + compatible = "ABB,kmpbec8309"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_zynq; + ethernet1 = &enet_piggy2; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8309@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <264000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8309@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <400000>; + + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Inventory EEPROM of the + * unit itself + */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "front"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "bottom"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8309-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + gpio1: gpio-controller@c00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio-controller@d00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xd00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + #address-cells = <1>; + #size-cells = <0>; + + /* GPIO_15 chipselect for ZYNQ flash */ + gpios = <&gpio1 15 0>; + + zynq_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + reg = <0>; + spi-max-frequency = <4000000>; + m25p,fast-read; + partition@0 { + label = "bootloader"; + reg = <0x0 0x01000000>; + }; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + fsl,qe-num-snums = <32>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* ZYNQ (UCC1, MDIO 0x10, MII) */ + enet_zynq: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + /*id=0, full-dup, 100M, no-pause, no-asym_p*/ + fixed-link = <0 1 100 0 0>; + rx-clock-name = "clk9"; + tx-clock-name = "clk10"; + phy-connection-type = "mii"; + }; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + enet_piggy2: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + }; + + mdio@2320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2320 0x38>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + + /* Explicitly set the tbi-phy to a non-zero address + * so that it does not conflict with phy_piggy2 that + * is unfortunately at address 0 + */ + tbi1: tbi-phy@1 { + reg = <0x1>; + device_type = "tbi-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + }; + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 2 0 0xe0000000 0x10000000 + 3 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xc0000>; + }; + partition@c0000 { /* 256KB */ + label = "qe-fw"; + reg = <0xc0000 0x40000>; + }; + partition@100000 { /* 128KB */ + label = "env"; + reg = <0x100000 0x20000>; + }; + partition@120000 { /* 128KB */ + label = "envred"; + reg = <0x120000 0x20000>; + }; + partition@140000 { /* 64256KB */ + label = "ubi0"; + reg = <0x140000 0x3EC0000>; + }; + }; + }; +}; + +#include "km8309-uboot.dtsi" diff --git a/arch/powerpc/dts/kmtepr2.dts b/arch/powerpc/dts/kmtepr2.dts new file mode 100644 index 0000000000..5a272ec6cb --- /dev/null +++ b/arch/powerpc/dts/kmtepr2.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEPR2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMTEPR2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */ + 3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuge1.dts b/arch/powerpc/dts/kmtuge1.dts new file mode 100644 index 0000000000..8a7b5a42cb --- /dev/null +++ b/arch/powerpc/dts/kmtuge1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUGE1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUGE1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuxa1.dts b/arch/powerpc/dts/kmtuxa1.dts new file mode 100644 index 0000000000..c2681c5efb --- /dev/null +++ b/arch/powerpc/dts/kmtuxa1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUXA1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher <hs@denx.de> + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUXA1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 LPXF */ + 3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/p1010rdb-pa.dts b/arch/powerpc/dts/p1010rdb-pa.dts index c66c4923ac..360d254d91 100644 --- a/arch/powerpc/dts/p1010rdb-pa.dts +++ b/arch/powerpc/dts/p1010rdb-pa.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb-pa_36b.dts b/arch/powerpc/dts/p1010rdb-pa_36b.dts index b943de7cbb..062086a8c0 100644 --- a/arch/powerpc/dts/p1010rdb-pa_36b.dts +++ b/arch/powerpc/dts/p1010rdb-pa_36b.dts @@ -15,3 +15,4 @@ }; /include/ "p1010si-post.dtsi" +/include/ "p1010rdb.dtsi" diff --git a/arch/powerpc/dts/p1010rdb.dtsi b/arch/powerpc/dts/p1010rdb.dtsi index 4f58ee2446..c2aecde134 100644 --- a/arch/powerpc/dts/p1010rdb.dtsi +++ b/arch/powerpc/dts/p1010rdb.dtsi @@ -4,11 +4,78 @@ * * Copyright 2020 NXP */ +/ { + aliases { + spi0 = &espi0; + }; +}; + &soc { + mdio@24000 { + phy0: ethernet-phy@0 { + reg = <0x1>; + }; + + phy1: ethernet-phy@1 { + reg = <0x0>; + }; + + phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + tbi-phy@3 { + device_type = "tbi-phy"; + reg = <0x3>; + }; + }; + + mdio@25000 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-handle = <&phy0>; + phy-connection-type = "rgmii-id"; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy1>; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy2>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + i2c@3000 { rtc@68 { compatible = "pericom,pt7c4338"; reg = <0x68>; }; }; + + spi@7000 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; + }; }; diff --git a/arch/powerpc/dts/p1010si-post.dtsi b/arch/powerpc/dts/p1010si-post.dtsi index 0289441381..2e7eb0e2fb 100644 --- a/arch/powerpc/dts/p1010si-post.dtsi +++ b/arch/powerpc/dts/p1010si-post.dtsi @@ -23,8 +23,43 @@ single-cpu-affinity; last-interrupt-source = <255>; }; + + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <1>; + status = "disabled"; + }; + /include/ "pq3-i2c-0.dtsi" /include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: ethernet@b0000 { + queue-group@b0000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: ethernet@b1000 { + queue-group@b1000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: ethernet@b2000 { + queue-group@b2000 { + fsl,rx-bit-map = <0xff>; + fsl,tx-bit-map = <0xff>; + }; + + }; }; /* controller at 0x9000 */ diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index 1dce8e86e9..03b6886991 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -44,10 +44,35 @@ clock-frequency = <0>; }; - /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec2-0.dtsi" + enet0: enet0_grp2: ethernet@b0000 { + }; + +/include/ "pq3-etsec2-1.dtsi" + enet1: enet1_grp2: ethernet@b1000 { + }; + +/include/ "pq3-etsec2-2.dtsi" + enet2: enet2_grp2: ethernet@b2000 { + }; }; +/include/ "pq3-etsec2-grp2-0.dtsi" +/include/ "pq3-etsec2-grp2-1.dtsi" +/include/ "pq3-etsec2-grp2-2.dtsi" + /* PCIe controller base address 0x9000 */ &pci1 { compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index 7ebaa619df..ab42325366 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -30,6 +30,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dtsi b/arch/powerpc/dts/p1020rdb-pc.dtsi new file mode 100644 index 0000000000..6bf424fd3f --- /dev/null +++ b/arch/powerpc/dts/p1020rdb-pc.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24000 { + phy0: ethernet-phy@0 { + interrupt-parent = <&mpic>; + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupt-parent = <&mpic>; + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + + tbi0: tbi-phy@11 { + device_type = "tbi-phy"; + reg = <0x11>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index c0e5ef4cf4..708f9a9db1 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -30,6 +30,22 @@ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p1020rdb-pc.dtsi" /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 21174a09be..b05f3deed5 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -17,6 +17,51 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; + + mdio@24000 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25000 { + tbi1: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26000 { + tbi2: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + enet0: ethernet@b0000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@b1000 { + phy-handle = <&phy0>; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@b2000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; }; pci1: pcie@ffe09000 { @@ -30,6 +75,21 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; /include/ "p1020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index 4ed093dad4..6d46f7d8dd 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -38,8 +38,21 @@ clock-frequency = <0>; }; - /include/ "pq3-i2c-0.dtsi" - /include/ "pq3-i2c-1.dtsi" + espi0: spi@7000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + +/include/ "pq3-i2c-0.dtsi" +/include/ "pq3-i2c-1.dtsi" + +/include/ "pq3-etsec1-0.dtsi" +/include/ "pq3-etsec1-1.dtsi" +/include/ "pq3-etsec1-2.dtsi" }; /* PCIe controller base address 0x8000 */ diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 08befd4c59..b37931ac44 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -35,6 +35,22 @@ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dtsi b/arch/powerpc/dts/p2020rdb-pc.dtsi new file mode 100644 index 0000000000..0d2acc746e --- /dev/null +++ b/arch/powerpc/dts/p2020rdb-pc.dtsi @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges) + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&soc { + mdio@24520 { + phy0: ethernet-phy@0 { + interrupts = <3 1 0 0>; + reg = <0x0>; + }; + phy1: ethernet-phy@1 { + interrupts = <2 1 0 0>; + reg = <0x1>; + }; + }; + + mdio@25520 { + tbi0: tbi-phy@11 { + reg = <0x11>; + device_type = "tbi-phy"; + }; + }; + + mdio@26520 { + status = "disabled"; + }; + + enet0: ethernet@24000 { + phy-connection-type = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + enet1: ethernet@25000 { + tbi-handle = <&tbi0>; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + }; + + enet2: ethernet@26000 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + }; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 04b2519e1a..ecdc022d99 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -35,6 +35,22 @@ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ }; + + aliases { + spi0 = &espi0; + }; }; +/include/ "p2020rdb-pc.dtsi" /include/ "p2020-post.dtsi" + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; +}; diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 95931e299d..ad09b138fc 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -60,6 +60,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts index 9d59f9c833..0fa1f09852 100644 --- a/arch/powerpc/dts/p2041rdb.dts +++ b/arch/powerpc/dts/p2041rdb.dts @@ -26,6 +26,7 @@ phy_sgmii_1e = &phy_sgmii_1e; phy_sgmii_1f = &phy_sgmii_1f; phy_xgmii_2 = &phy_xgmii_2; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -111,4 +112,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 3152683b84..e34117b65a 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -60,6 +60,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@fe210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p3041ds.dts b/arch/powerpc/dts/p3041ds.dts index b984ddea98..069dae3b85 100644 --- a/arch/powerpc/dts/p3041ds.dts +++ b/arch/powerpc/dts/p3041ds.dts @@ -27,6 +27,7 @@ emi1_rgmii = &hydra_mdio_rgmii; emi1_sgmii = &hydra_mdio_sgmii; emi2_xgmii = &hydra_mdio_xgmii; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -142,4 +143,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p3041si-post.dtsi" diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 4a80561e18..8ab5cf541a 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -80,6 +80,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + esdhc: esdhc@114000 { compatible = "fsl,esdhc"; reg = <0x114000 0x1000>; diff --git a/arch/powerpc/dts/p4080ds.dts b/arch/powerpc/dts/p4080ds.dts index 53c51d479c..d5618f1e49 100644 --- a/arch/powerpc/dts/p4080ds.dts +++ b/arch/powerpc/dts/p4080ds.dts @@ -27,6 +27,7 @@ emi1_rgmii = &p4080mdio0; emi2_slot4 = &p4080xmdio1; emi2_slot5 = &p4080xmdio3; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -204,4 +205,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p4080si-post.dtsi" diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index 45988574a2..10402cf222 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -59,6 +59,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/p5040ds.dts b/arch/powerpc/dts/p5040ds.dts index 6ebc801a45..c2ec765d3e 100644 --- a/arch/powerpc/dts/p5040ds.dts +++ b/arch/powerpc/dts/p5040ds.dts @@ -39,6 +39,7 @@ hydra_sg_slot6 = &hydra_sg_slot6; hydra_xg_slot1 = &hydra_xg_slot1; hydra_xg_slot2 = &hydra_xg_slot2; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -265,4 +266,16 @@ }; }; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; +}; + /include/ "p5040si-post.dtsi" diff --git a/arch/powerpc/dts/pq3-etsec1-0.dtsi b/arch/powerpc/dts/pq3-etsec1-0.dtsi new file mode 100644 index 0000000000..8800243f34 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-0.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@24000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; +}; + +mdio@24520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x24520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-1.dtsi b/arch/powerpc/dts/pq3-etsec1-1.dtsi new file mode 100644 index 0000000000..2bc62d1a57 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-1.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@25000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x25000 0x1000>; + ranges = <0x0 0x25000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; +}; + +mdio@25520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x25520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-2.dtsi b/arch/powerpc/dts/pq3-etsec1-2.dtsi new file mode 100644 index 0000000000..d45865fe03 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-2.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@26000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <2>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x26000 0x1000>; + ranges = <0x0 0x26000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; +}; + +mdio@26520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x26520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec1-3.dtsi b/arch/powerpc/dts/pq3-etsec1-3.dtsi new file mode 100644 index 0000000000..853a27359d --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec1-3.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] + * + * Copyright 2011-2012 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +ethernet@27000 { + #address-cells = <1>; + #size-cells = <1>; + cell-index = <3>; + device_type = "network"; + model = "eTSEC"; + compatible = "gianfar"; + reg = <0x27000 0x1000>; + ranges = <0x0 0x27000 0x1000>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; +}; + +mdio@27520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-tbi"; + reg = <0x27520 0x20>; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-0.dtsi new file mode 100644 index 0000000000..f9d3d04650 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-0.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@24000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-mdio"; + reg = <0x24000 0x1000 0xb0030 0x4>; +}; + +ethernet@b0000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb0000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b0000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb0000 0x1000>; + interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-1.dtsi new file mode 100644 index 0000000000..6c01481909 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-1.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@25000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x25000 0x1000 0xb1030 0x4>; +}; + +ethernet@b1000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb1000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b1000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb1000 0x1000>; + interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-2.dtsi new file mode 100644 index 0000000000..2a597c0db6 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-2.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +mdio@26000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,etsec2-tbi"; + reg = <0x26000 0x1000 0xb1030 0x4>; +}; + +ethernet@b2000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "network"; + model = "eTSEC"; + compatible = "fsl,etsec2"; + reg = <0xb2000 0x1000>; + fsl,num_rx_queues = <0x8>; + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; + ranges; + + queue-group@b2000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb2000 0x1000>; + interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi new file mode 100644 index 0000000000..16752a7c45 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet0_grp2 { + queue-group@b4000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb4000 0x1000>; + interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi new file mode 100644 index 0000000000..0464938424 --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet1_grp2 { + queue-group@b5000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb5000 0x1000>; + interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi new file mode 100644 index 0000000000..fe8003c44a --- /dev/null +++ b/arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ] + * + * Copyright 2011 Freescale Semiconductor Inc. + * Copyright 2020 NXP + */ + +&enet2_grp2 { + queue-group@b6000 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0xb6000 0x1000>; + interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>; + }; +}; diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts index 32aaa4adaa..eeba99f84d 100644 --- a/arch/powerpc/dts/t1024rdb.dts +++ b/arch/powerpc/dts/t1024rdb.dts @@ -17,6 +17,7 @@ aliases { sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4; + spi0 = &espi0; }; soc: soc@ffe000000 { @@ -63,7 +64,18 @@ }; }; }; +}; +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + /* input clock */ + spi-max-frequency = <10000000>; + }; }; #include "t1024si-post.dtsi" diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 521825d85a..cf8962abe2 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,6 +49,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 16a8ed4c79..3584c06aa8 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index 0a08a69f31..2c7e5b4718 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -59,6 +59,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index a9e9b404f6..7e446b18df 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -69,6 +69,16 @@ voltage-ranges = <1800 1800 3300 3300>; }; + espi0: spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2 0 0>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts index 1819a081dd..f9e786b239 100644 --- a/arch/powerpc/dts/t2080qds.dts +++ b/arch/powerpc/dts/t2080qds.dts @@ -14,4 +14,37 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eon,en25s64", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <10000000>; + }; + }; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 49c1765b29..34ec6a74cb 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; /* 16MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 9b5902fe9e..498da4f795 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -99,6 +99,15 @@ clock-frequency = <0x0>; }; + espi0: spi@110000 { + compatible = "fsl,mpc8536-espi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x110000 0x1000>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts index f67d7ce2ae..635065a036 100644 --- a/arch/powerpc/dts/t4240rdb.dts +++ b/arch/powerpc/dts/t4240rdb.dts @@ -14,4 +14,19 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; /* input clock */ + }; }; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8c8ed99cd3..b903e6ec8d 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -298,8 +298,8 @@ void boot_prep_vxworks(bootm_headers_t *images) if (!images->ft_addr) return; - base = (u64)gd->bd->bi_memstart; - size = (u64)gd->bd->bi_memsize; + base = (u64)gd->ram_base; + size = (u64)gd->ram_size; off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 009a545fcf..aaa3b833a5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -155,10 +155,6 @@ config 64BIT config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL help The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. @@ -177,22 +173,10 @@ config ANDES_PLIC config ANDES_PLMT bool depends on RISCV_MMODE || SPL_RISCV_MMODE - select REGMAP - select SYSCON - select SPL_REGMAP if SPL - select SPL_SYSCON if SPL help The Andes PLMT block holds memory-mapped mtime register associated with timer tick. -config RISCV_RDTIME - bool - default y if RISCV_SMODE || SPL_RISCV_SMODE - help - The provides the riscv_get_time() API that is implemented using the - standard rdtime instruction. This is the case for S-mode U-Boot, and - is useful for processors that support rdtime in M-mode too. - config SYS_MALLOC_F_LEN default 0x1000 diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 8d8d71dcbf..5cb5bb51eb 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -3,7 +3,7 @@ config RISCV_NDS select ARCH_EARLY_INIT_R imply CPU imply CPU_RISCV - imply RISCV_TIMER + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) imply SPL_CPU_SUPPORT diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index bfa2d4a426..85592f5bee 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -72,6 +72,17 @@ static int riscv_cpu_probe(void) return 0; } +/* + * This is called on secondary harts just after the IPI is init'd. Currently + * there's nothing to do, since we just need to clear any existing IPIs, and + * that is handled by the sending of an ipi itself. + */ +#if CONFIG_IS_ENABLED(SMP) +static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1) +{ +} +#endif + int arch_cpu_init_dm(void) { int ret; @@ -111,6 +122,15 @@ int arch_cpu_init_dm(void) ret = riscv_init_ipi(); if (ret) return ret; + + /* + * Clear all pending IPIs on secondary harts. We don't do anything on + * the boot hart, since we never send an IPI to ourselves, and no + * interrupts are enabled + */ + ret = smp_call_function((ulong)dummy_pending_ipi_clear, 0, 0, 0); + if (ret) + return ret; #endif return 0; diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index 53e19635c8..ac3f183342 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -10,7 +10,7 @@ config SIFIVE_FU540 select SPL_RAM if SPL imply CPU imply CPU_RISCV - imply RISCV_TIMER + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) imply CMD_CPU imply SPL_CPU_SUPPORT diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig index b2cb155d6d..f4c2e2643c 100644 --- a/arch/riscv/cpu/generic/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -7,7 +7,7 @@ config GENERIC_RISCV select ARCH_EARLY_INIT_R imply CPU imply CPU_RISCV - imply RISCV_TIMER + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE) imply CMD_CPU imply SPL_CPU_SUPPORT diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index bf9fdf369b..bbc737ed9a 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -43,14 +43,32 @@ _start: csrr a0, CSR_MHARTID #endif - /* save hart id and dtb pointer */ + /* + * Save hart id and dtb pointer. The thread pointer register is not + * modified by C code. It is used by secondary_hart_loop. + */ mv tp, a0 mv s1, a1 + /* + * Set the global data pointer to a known value in case we get a very + * early trap. The global data pointer will be set its actual value only + * after it has been initialized. + */ + mv gp, zero + + /* + * Set the trap handler. This must happen after initializing gp because + * the handler may use it. + */ la t0, trap_entry csrw MODE_PREFIX(tvec), t0 - /* mask all interrupts */ + /* + * Mask all interrupts. Interrupts are disabled globally (in m/sstatus) + * for U-Boot, but we will need to read m/sip to determine if we get an + * IPI + */ csrw MODE_PREFIX(ie), zero #if CONFIG_IS_ENABLED(SMP) @@ -65,8 +83,6 @@ _start: #else li t0, SIE_SSIE #endif - /* Clear any pending IPIs */ - csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif @@ -87,10 +103,10 @@ call_board_init_f_0: jal board_init_f_alloc_reserve /* - * Set global data pointer here for all harts, uninitialized at this - * point. + * Save global data pointer for later. We don't set it here because it + * is not initialized yet. */ - mv gp, a0 + mv s0, a0 /* setup stack */ #if CONFIG_IS_ENABLED(SMP) @@ -111,6 +127,14 @@ call_board_init_f_0: amoswap.w s2, t1, 0(t0) bnez s2, wait_for_gd_init #else + /* + * FIXME: gp is set before it is initialized. If an XIP U-Boot ever + * encounters a pending IPI on boot it is liable to jump to whatever + * memory happens to be in ipi_data.addr on boot. It may also run into + * problems if it encounters an exception too early (because printf/puts + * accesses gd). + */ + mv gp, s0 bnez tp, secondary_hart_loop #endif @@ -127,16 +151,21 @@ call_board_init_f_0: #ifndef CONFIG_XIP la t0, available_harts_lock - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) wait_for_gd_init: la t0, available_harts_lock li t1, 1 -1: amoswap.w t1, t1, 0(t0) - fence r, rw +1: amoswap.w.aq t1, t1, 0(t0) bnez t1, 1b + /* + * Set the global data pointer only when gd_t has been initialized. + * This was already set by arch_setup_gd on the boot hart, but all other + * harts' global data pointers gets set here. + */ + mv gp, s0 + /* register available harts in the available_harts mask */ li t1, 1 sll t1, t1, tp @@ -144,8 +173,7 @@ wait_for_gd_init: or t2, t2, t1 SREG t2, GD_AVAILABLE_HARTS(gp) - fence rw, w - amoswap.w zero, zero, 0(t0) + amoswap.w.rl zero, zero, 0(t0) /* * Continue on hart lottery winner, others branch to @@ -395,6 +423,10 @@ secondary_hart_relocate: mv gp, a2 #endif +/* + * Interrupts are disabled globally, but they can still be read from m/sip. The + * wfi function will wake us up if we get an IPI, even if we do not trap. + */ secondary_hart_loop: wfi diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 5302677ee4..a06e1b11c6 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -55,9 +55,13 @@ reg = <0x0 0x10070000 0x0 0x1000>; fuse-count = <0x1000>; }; - clint@2000000 { + clint: clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; reg = <0x0 0x2000000 0x0 0xc0000>; u-boot,dm-spl; }; diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi index 5d0c928b29..1996149c95 100644 --- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi @@ -34,6 +34,10 @@ }; +&clint { + clocks = <&rtcclk>; +}; + &qspi0 { u-boot,dm-spl; diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 2546c7d4e0..84cff51c36 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -17,6 +17,8 @@ compatible = "kendryte,k210"; aliases { + cpu0 = &cpu0; + cpu1 = &cpu1; dma0 = &dmac0; gpio0 = &gpio0; gpio1 = &gpio1_0; @@ -126,14 +128,13 @@ read-only; }; - clint0: interrupt-controller@2000000 { + clint0: clint@2000000 { #interrupt-cells = <1>; compatible = "kendryte,k210-clint", "riscv,clint0"; reg = <0x2000000 0xC000>; - interrupt-controller; interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>; - clocks = <&sysclk K210_CLK_CPU>; + clocks = <&sysclk K210_CLK_CLINT>; }; plic0: interrupt-controller@C000000 { diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index b711fcc44d..d3a0b1d221 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -24,9 +24,6 @@ struct arch_global_data { #ifdef CONFIG_ANDES_PLIC void __iomem *plic; /* plic base address */ #endif -#ifdef CONFIG_ANDES_PLMT - void __iomem *plmt; /* plmt base address */ -#endif #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; #endif diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 1b428856b2..2dae0800ce 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -18,14 +18,21 @@ * IPI data structure. The hart ID is inserted by the hart handling the IPI and * calling the function. * + * @valid is used to determine whether a sent IPI originated from U-Boot. It is + * initialized to zero by board_init_f_alloc_reserve. When U-Boot sends its + * first IPI, it is set to 1. This prevents already-pending IPIs not sent by + * U-Boot from being taken. + * * @addr: Address of function * @arg0: First argument of function * @arg1: Second argument of function + * @valid: Whether this IPI is valid */ struct ipi_data { ulong addr; ulong arg0; ulong arg1; + unsigned int valid; }; /** diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h index 26a008ca59..c3629e4b53 100644 --- a/arch/riscv/include/asm/syscon.h +++ b/arch/riscv/include/asm/syscon.h @@ -7,13 +7,13 @@ #define _ASM_SYSCON_H /* - * System controllers in a RISC-V system + * System controllers in a RISC-V system. These should only be used for + * identifying IPI controllers. Other devices should use DM to probe. */ enum { RISCV_NONE, RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */ RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */ - RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */ }; #endif /* _ASM_SYSCON_H */ diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 6c503ff2b2..10ac5b06d3 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -15,7 +15,6 @@ obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else -obj-$(CONFIG_RISCV_RDTIME) += rdtime.o obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o endif diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index c2a8fe4d9e..267d6a191b 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -41,53 +41,45 @@ static int enable_ipi(int hart) return 0; } -static int init_plic(void) +int riscv_init_ipi(void) { - struct udevice *dev; - ofnode node; int ret; + long *base = syscon_get_first_range(RISCV_SYSCON_PLIC); + ofnode node; + struct udevice *dev; u32 reg; + if (IS_ERR(base)) + return PTR_ERR(base); + gd->arch.plic = base; + ret = uclass_find_first_device(UCLASS_CPU, &dev); if (ret) return ret; + else if (!dev) + return -ENODEV; - if (dev) { - ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { - const char *device_type; - - device_type = ofnode_read_string(node, "device_type"); - if (!device_type) - continue; + ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) { + const char *device_type; - if (strcmp(device_type, "cpu")) - continue; + device_type = ofnode_read_string(node, "device_type"); + if (!device_type) + continue; - /* skip if hart is marked as not available */ - if (!ofnode_is_available(node)) - continue; + if (strcmp(device_type, "cpu")) + continue; - /* read hart ID of CPU */ - ret = ofnode_read_u32(node, "reg", ®); - if (ret == 0) - enable_ipi(reg); - } + /* skip if hart is marked as not available */ + if (!ofnode_is_available(node)) + continue; - return 0; + /* read hart ID of CPU */ + ret = ofnode_read_u32(node, "reg", ®); + if (ret == 0) + enable_ipi(reg); } - return -ENODEV; -} - -int riscv_init_ipi(void) -{ - long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC); - - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.plic = ret; - - return init_plic(); + return 0; } int riscv_send_ipi(int hart) diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c index a7e90ca992..a28c14c1eb 100644 --- a/arch/riscv/lib/andes_plmt.c +++ b/arch/riscv/lib/andes_plmt.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019, Rick Chen <rick@andestech.com> + * Copyright (C) 2020, Sean Anderson <seanga2@gmail.com> * * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT). * The PLMT block holds memory-mapped mtime register @@ -9,46 +10,43 @@ #include <common.h> #include <dm.h> -#include <regmap.h> -#include <syscon.h> +#include <timer.h> #include <asm/io.h> -#include <asm/syscon.h> #include <linux/err.h> /* mtime register */ #define MTIME_REG(base) ((ulong)(base)) -DECLARE_GLOBAL_DATA_PTR; - -#define PLMT_BASE_GET(void) \ - do { \ - long *ret; \ - \ - if (!gd->arch.plmt) { \ - ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \ - if (IS_ERR(ret)) \ - return PTR_ERR(ret); \ - gd->arch.plmt = ret; \ - } \ - } while (0) - -int riscv_get_time(u64 *time) +static int andes_plmt_get_count(struct udevice *dev, u64 *count) { - PLMT_BASE_GET(); - - *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt)); + *count = readq((void __iomem *)MTIME_REG(dev->priv)); return 0; } +static const struct timer_ops andes_plmt_ops = { + .get_count = andes_plmt_get_count, +}; + +static int andes_plmt_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + static const struct udevice_id andes_plmt_ids[] = { - { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT }, + { .compatible = "riscv,plmt0" }, { } }; U_BOOT_DRIVER(andes_plmt) = { .name = "andes_plmt", - .id = UCLASS_SYSCON, + .id = UCLASS_TIMER, .of_match = andes_plmt_ids, + .ops = &andes_plmt_ops, + .probe = andes_plmt_probe, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 5b2420243f..d02062fd5b 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - &phandle); + &phandle, false); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 8ff40f0f36..35de98e8ce 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -78,7 +78,8 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, struct pt_regs *regs) printf("EPC: " REG_FMT " RA: " REG_FMT " TVAL: " REG_FMT "\n", epc, regs->ra, tval); - if (gd->flags & GD_FLG_RELOC) + /* Print relocation adjustments, but only if gd is initialized */ + if (gd && gd->flags & GD_FLG_RELOC) printf("EPC: " REG_FMT " RA: " REG_FMT " reloc adjusted\n\n", epc - gd->reloc_off, regs->ra - gd->reloc_off); diff --git a/arch/riscv/lib/rdtime.c b/arch/riscv/lib/rdtime.c deleted file mode 100644 index e128d7fce6..0000000000 --- a/arch/riscv/lib/rdtime.c +++ /dev/null @@ -1,38 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018, Anup Patel <anup@brainfault.org> - * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> - * - * The riscv_get_time() API implementation that is using the - * standard rdtime instruction. - */ - -#include <common.h> - -/* Implement the API required by RISC-V timer driver */ -int riscv_get_time(u64 *time) -{ -#ifdef CONFIG_64BIT - u64 n; - - __asm__ __volatile__ ( - "rdtime %0" - : "=r" (n)); - - *time = n; -#else - u32 lo, hi, tmp; - - __asm__ __volatile__ ( - "1:\n" - "rdtimeh %0\n" - "rdtime %1\n" - "rdtimeh %2\n" - "bne %0, %2, 1b" - : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); - - *time = ((u64)hi << 32) | lo; -#endif - - return 0; -} diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index b9a2c649cc..c9704c596f 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -8,9 +8,9 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> -#include <regmap.h> -#include <syscon.h> +#include <timer.h> #include <asm/io.h> #include <asm/syscon.h> #include <linux/err.h> @@ -24,68 +24,74 @@ DECLARE_GLOBAL_DATA_PTR; -int riscv_get_time(u64 *time) +int riscv_init_ipi(void) { - /* ensure timer register base has a sane value */ - riscv_init_ipi(); + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_driver(UCLASS_TIMER, + DM_GET_DRIVER(sifive_clint), &dev); + if (ret) + return ret; - *time = readq((void __iomem *)MTIME_REG(gd->arch.clint)); + gd->arch.clint = dev_read_addr_ptr(dev); + if (!gd->arch.clint) + return -EINVAL; return 0; } -int riscv_set_timecmp(int hart, u64 cmp) +int riscv_send_ipi(int hart) { - /* ensure timer register base has a sane value */ - riscv_init_ipi(); - - writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart)); + writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; } -int riscv_init_ipi(void) +int riscv_clear_ipi(int hart) { - if (!gd->arch.clint) { - long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT); - - if (IS_ERR(ret)) - return PTR_ERR(ret); - gd->arch.clint = ret; - } + writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; } -int riscv_send_ipi(int hart) +int riscv_get_ipi(int hart, int *pending) { - writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); return 0; } -int riscv_clear_ipi(int hart) +static int sifive_clint_get_count(struct udevice *dev, u64 *count) { - writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart)); + *count = readq((void __iomem *)MTIME_REG(dev->priv)); return 0; } -int riscv_get_ipi(int hart, int *pending) +static const struct timer_ops sifive_clint_ops = { + .get_count = sifive_clint_get_count, +}; + +static int sifive_clint_probe(struct udevice *dev) { - *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; - return 0; + return timer_timebase_fallback(dev); } static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, + { .compatible = "riscv,clint0" }, { } }; U_BOOT_DRIVER(sifive_clint) = { .name = "sifive_clint", - .id = UCLASS_SYSCON, + .id = UCLASS_TIMER, .of_match = sifive_clint_ids, + .probe = sifive_clint_probe, + .ops = &sifive_clint_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index ac22136314..8f33ce1fe3 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -54,6 +54,14 @@ static int send_ipi_many(struct ipi_data *ipi, int wait) gd->arch.ipi[reg].arg0 = ipi->arg0; gd->arch.ipi[reg].arg1 = ipi->arg1; + /* + * Ensure valid only becomes set when the IPI parameters are + * set. An IPI may already be pending on other harts, so we + * need a way to signal that the IPI device has been + * initialized, and that it is ok to call the function. + */ + __smp_store_release(&gd->arch.ipi[reg].valid, 1); + ret = riscv_send_ipi(reg); if (ret) { pr_err("Cannot send IPI to hart %d\n", reg); @@ -81,7 +89,13 @@ void handle_ipi(ulong hart) if (hart >= CONFIG_NR_CPUS) return; - __smp_mb(); + /* + * If valid is not set, then U-Boot has not requested the IPI. The + * IPI device may not be initialized, so all we can do is wait for + * U-Boot to initialize it and send an IPI + */ + if (!__smp_load_acquire(&gd->arch.ipi[hart].valid)) + return; smp_function = (void (*)(ulong, ulong, ulong))gd->arch.ipi[hart].addr; invalidate_icache_all(); diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9f45c48e4e..e6da47d592 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -121,6 +121,9 @@ <&gpio_c 5 GPIO_IN>, <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>, <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>; + test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>; + test5-gpios = <&gpio_a 19>; + int-value = <1234>; uint-value = <(-1234)>; int64-value = /bits/ 64 <0x1111222233334444>; @@ -270,6 +273,13 @@ compatible = "denx,u-boot-devres-test"; }; + another-test { + reg = <0 2>; + compatible = "denx,u-boot-fdt-test"; + test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>; + test5-gpios = <&gpio_a 19>; + }; + acpi_test1: acpi-test { compatible = "denx,u-boot-acpi-test"; acpi-ssdt-test-data = "ab"; @@ -356,6 +366,37 @@ sandbox_firmware: sandbox-firmware { compatible = "sandbox,firmware"; }; + + sandbox-scmi-agent@0 { + compatible = "sandbox,scmi-agent"; + #address-cells = <1>; + #size-cells = <0>; + + clk_scmi0: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + reset_scmi0: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + sandbox-scmi-agent@1 { + compatible = "sandbox,scmi-agent"; + #address-cells = <1>; + #size-cells = <0>; + + clk_scmi1: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + protocol@10 { + reg = <0x10>; + }; + }; }; pinctrl-gpio { @@ -533,7 +574,9 @@ }; cpus { + timebase-frequency = <2000000>; cpu-test1 { + timebase-frequency = <3000000>; compatible = "sandbox,cpu_sandbox"; u-boot,dm-pre-reloc; }; @@ -839,11 +882,16 @@ 0x58 8>; }; - timer { + timer@0 { compatible = "sandbox,timer"; clock-frequency = <1000000>; }; + timer@1 { + compatible = "sandbox,timer"; + sandbox,timebase-frequency-fallback; + }; + tpm2 { compatible = "sandbox,tpm2"; }; @@ -1036,6 +1084,12 @@ compatible = "sandbox,virtio2"; }; + sandbox_scmi { + compatible = "sandbox,scmi-devices"; + clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>; + resets = <&reset_scmi0 3>; + }; + pinctrl { compatible = "sandbox,pinctrl"; @@ -1122,6 +1176,19 @@ resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>; reset-names = "valid", "no_mask", "out_of_range"; }; + + some_regmapped-bus { + #address-cells = <0x1>; + #size-cells = <0x1>; + + ranges = <0x0 0x0 0x10>; + compatible = "simple-bus"; + + regmap-test_0 { + reg = <0 0x10>; + compatible = "sandbox,regmap_test"; + }; + }; }; #include "sandbox_pmic.dtsi" diff --git a/arch/sandbox/include/asm/cpu.h b/arch/sandbox/include/asm/cpu.h new file mode 100644 index 0000000000..c97ac7ba95 --- /dev/null +++ b/arch/sandbox/include/asm/cpu.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com> + */ + +#ifndef __SANDBOX_CPU_H +#define __SANDBOX_CPU_H + +void cpu_sandbox_set_current(const char *name); + +#endif /* __SANDBOX_CPU_H */ diff --git a/arch/sandbox/include/asm/reset.h b/arch/sandbox/include/asm/reset.h index c4205eabef..40d3e61c11 100644 --- a/arch/sandbox/include/asm/reset.h +++ b/arch/sandbox/include/asm/reset.h @@ -11,9 +11,12 @@ struct udevice; int sandbox_reset_query(struct udevice *dev, unsigned long id); +int sandbox_reset_is_requested(struct udevice *dev, unsigned long id); int sandbox_reset_test_get(struct udevice *dev); +int sandbox_reset_test_get_devm(struct udevice *dev); int sandbox_reset_test_get_bulk(struct udevice *dev); +int sandbox_reset_test_get_bulk_devm(struct udevice *dev); int sandbox_reset_test_assert(struct udevice *dev); int sandbox_reset_test_assert_bulk(struct udevice *dev); int sandbox_reset_test_deassert(struct udevice *dev); diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h new file mode 100644 index 0000000000..3e8b0068fd --- /dev/null +++ b/arch/sandbox/include/asm/scmi_test.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020, Linaro Limited + */ + +#ifndef __SANDBOX_SCMI_TEST_H +#define __SANDBOX_SCMI_TEST_H + +struct udevice; +struct sandbox_scmi_agent; +struct sandbox_scmi_service; + +/** + * struct sandbox_scmi_clk - Simulated clock exposed by SCMI + * @id: Identifier of the clock used in the SCMI protocol + * @enabled: Clock state: true if enabled, false if disabled + * @rate: Clock rate in Hertz + */ +struct sandbox_scmi_clk { + uint id; + bool enabled; + ulong rate; +}; + +/** + * struct sandbox_scmi_reset - Simulated reset controller exposed by SCMI + * @asserted: Reset control state: true if asserted, false if desasserted + */ +struct sandbox_scmi_reset { + uint id; + bool asserted; +}; + +/** + * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent + * @idx: Identifier for the SCMI agent, its index + * @clk: Simulated clocks + * @clk_count: Simulated clocks array size + * @clk: Simulated reset domains + * @clk_count: Simulated reset domains array size + */ +struct sandbox_scmi_agent { + uint idx; + struct sandbox_scmi_clk *clk; + size_t clk_count; + struct sandbox_scmi_reset *reset; + size_t reset_count; +}; + +/** + * struct sandbox_scmi_service - Reference to simutaed SCMI agents/services + * @agent: Pointer to SCMI sandbox agent pointers array + * @agent_count: Number of emulated agents exposed in array @agent. + */ +struct sandbox_scmi_service { + struct sandbox_scmi_agent **agent; + size_t agent_count; +}; + +/** + * struct sandbox_scmi_devices - Reference to devices probed through SCMI + * @clk: Array the clock devices + * @clk_count: Number of clock devices probed + * @reset: Array the reset controller devices + * @reset_count: Number of reset controller devices probed + */ +struct sandbox_scmi_devices { + struct clk *clk; + size_t clk_count; + struct reset_ctl *reset; + size_t reset_count; +}; + +#ifdef CONFIG_SCMI_FIRMWARE +/** + * sandbox_scmi_service_context - Get the simulated SCMI services context + * @return: Reference to backend simulated resources state + */ +struct sandbox_scmi_service *sandbox_scmi_service_ctx(void); + +/** + * sandbox_scmi_devices_get_ref - Get references to devices accessed through SCMI + * @dev: Reference to the test device used get test resources + * @return: Reference to the devices probed by the SCMI test + */ +struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev); +#else +static inline struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) +{ + return NULL; +} + +static inline +struct sandbox_scmi_devices *sandbox_scmi_devices_ctx(struct udevice *dev) +{ + return NULL; +} +#endif /* CONFIG_SCMI_FIRMWARE */ +#endif /* __SANDBOX_SCMI_TEST_H */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 76276c6027..eddf2a774e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -788,6 +788,13 @@ config GENERATE_ACPI_TABLE by the operating system. It defines platform-independent interfaces for configuration and power management monitoring. +config ACPI_GNVS_EXTERNAL + bool + help + Put the GNVS (Global Non-Volatile Sleeping) table separate from the + DSDT and add a pointer to the table from the DSDT. This allows + U-Boot to better control the address of the GNVS. + endmenu config HAVE_ACPI_RESUME @@ -976,4 +983,44 @@ config TPL_ACPI_GPE See https://queue.acm.org/blogposting.cfm?id=18977 for more info +config SA_PCIEX_LENGTH + hex + default 0x10000000 if (PCIEX_LENGTH_256MB) + default 0x8000000 if (PCIEX_LENGTH_128MB) + default 0x4000000 if (PCIEX_LENGTH_64MB) + default 0x10000000 + help + This option allows you to select length of PCIEX region. + +config PCIEX_LENGTH_256MB + bool + +config PCIEX_LENGTH_128MB + bool + +config PCIEX_LENGTH_64MB + bool + +config INTEL_GMA_ACPI + bool "Generate ACPI table for Intel GMA graphics" + help + The Intel GMA graphics driver in Linux expects an ACPI table + which describes the layout of the registers and the display + connected to the device. Enable this option to create this + table so that graphics works correctly. + +config INTEL_GENERIC_WIFI + bool "Enable generation of ACPI tables for Intel WiFi" + help + Select this option to provide code to a build generic WiFi ACPI table + for Intel WiFi devices. This is not a WiFi driver and offers no + network functionality. It is only here to generate the ACPI tables + required by Linux. + +config INTEL_GMA_SWSMISCI + bool + help + Select this option for Atom-based platforms which use the SWSMISCI + register (0xe0) rather than the SWSCI register (0xe8). + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 99d4e105c2..35a425cd1b 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -13,9 +13,12 @@ config INTEL_APOLLOLAKE select TPL_X86_TSC_TIMER_NATIVE select SPL_PCH_SUPPORT select TPL_PCH_SUPPORT + select PCIEX_LENGTH_256MB select PCH_SUPPORT select P2SB select SMP_AP_WORK + select INTEL_GMA_SWSMISCI + select ACPI_GNVS_EXTERNAL imply ENABLE_MRC_CACHE imply AHCI_PCI imply SCSI @@ -46,6 +49,7 @@ config INTEL_APOLLOLAKE imply CMD_CLK imply CLK_INTEL imply ACPI_GPE + imply INTEL_GMA_ACPI if INTEL_APOLLOLAKE diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 3aa2a55676..2ddf4af62c 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -16,6 +16,7 @@ obj-y += fsp_m.o endif endif ifndef CONFIG_SPL_BUILD +obj-y += acpi.o obj-y += fsp_s.o endif diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c new file mode 100644 index 0000000000..69b544f0d9 --- /dev/null +++ b/arch/x86/cpu/apollolake/acpi.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2017-2019 Siemens AG + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * Copyright 2019 Google LLC + * + * Modified from coreboot apollolake/acpi.c + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <log.h> +#include <p2sb.h> +#include <pci.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_s3.h> +#include <asm/acpi_table.h> +#include <asm/cpu_common.h> +#include <asm/intel_acpi.h> +#include <asm/intel_gnvs.h> +#include <asm/intel_pinctrl.h> +#include <asm/intel_pinctrl_defs.h> +#include <asm/intel_regs.h> +#include <asm/io.h> +#include <asm/mpspec.h> +#include <asm/tables.h> +#include <asm/arch/iomap.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pm.h> +#include <asm/arch/systemagent.h> +#include <dm/acpi.h> +#include <dm/uclass-internal.h> +#include <power/acpi_pmc.h> + +int arch_read_sci_irq_select(void) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + + return readl(upriv->pmc_bar0 + IRQ_REG); +} + +int arch_write_sci_irq_select(uint scis) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + writel(scis, upriv->pmc_bar0 + IRQ_REG); + + return 0; +} + +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *cpu; + int ret; + + /* Clear out GNV */ + memset(gnvs, '\0', sizeof(*gnvs)); + + /* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */ + +#ifdef CONFIG_CHROMEOS + /* Initialise Verified Boot data */ + chromeos_init_acpi(&gnvs->chromeos); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + /* Set unknown wake source */ + gnvs->pm1i = ~0ULL; + + /* CPU core count */ + gnvs->pcnt = 1; + ret = uclass_find_first_device(UCLASS_CPU, &cpu); + if (cpu) { + ret = cpu_get_count(cpu); + if (ret > 0) + gnvs->pcnt = ret; + } + + return 0; +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + + return generic_pm1_en; +} + +int arch_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_LOW; +} + +void fill_fadt(struct acpi_fadt *fadt) +{ + fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->pm_tmr_len = 4; + fadt->duty_width = 3; + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; +} + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &fadt->header; + + acpi_fadt_common(fadt, facs, dsdt); + intel_acpi_fill_fadt(fadt); + fill_fadt(fadt); + header->checksum = table_compute_checksum(fadt, header->length); +} + +int apl_acpi_fill_dmar(struct acpi_ctx *ctx) +{ + struct udevice *dev, *sa_dev; + u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK; + u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK; + bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED; + bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED; + void *tmp; + int ret; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa_dev); + if (ret) + return log_msg_ret("no sa", ret); + + /* IGD has to be enabled, GFXVTBAR set and enabled */ + if (dev && device_active(dev) && gfxvtbar && gfxvten) { + tmp = ctx->current; + + acpi_create_dmar_drhd(ctx, 0, 0, gfxvtbar); + ret = acpi_create_dmar_ds_pci(ctx, PCI_BDF(0, 2, 0)); + if (ret) + return log_msg_ret("ds_pci", ret); + acpi_dmar_drhd_fixup(ctx, tmp); + + /* Add RMRR entry */ + tmp = ctx->current; + acpi_create_dmar_rmrr(ctx->current, 0, sa_get_gsm_base(sa_dev), + sa_get_tolud_base(sa_dev) - 1); + acpi_create_dmar_ds_pci(ctx->current, PCI_BDF(0, 2, 0)); + acpi_dmar_rmrr_fixup(ctx, tmp); + } + + /* DEFVTBAR has to be set and enabled */ + if (defvtbar && defvten) { + struct udevice *p2sb_dev; + u16 ibdf, hbdf; + uint ioapic, hpet; + int ret; + + tmp = ctx->current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + * + * TODO(sjg@chromium.org): p2sb_unhide() ? + */ + ret = uclass_first_device_err(UCLASS_P2SB, &p2sb_dev); + if (ret) + return log_msg_ret("p2sb", ret); + + dm_pci_read_config16(p2sb_dev, PCH_P2SB_IBDF, &ibdf); + ioapic = PCI_TO_BDF(ibdf); + dm_pci_read_config16(p2sb_dev, PCH_P2SB_HBDF, &hbdf); + hpet = PCI_TO_BDF(hbdf); + /* TODO(sjg@chromium.org): p2sb_hide() ? */ + + acpi_create_dmar_drhd(ctx, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + acpi_create_dmar_ds_ioapic(ctx, 2, ioapic); + acpi_create_dmar_ds_msi_hpet(ctx, 0, hpet); + acpi_dmar_drhd_fixup(tmp, ctx->current); + } + + return 0; +} diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index 0a6d2ad7a4..8da2e64e22 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -6,14 +6,90 @@ #include <common.h> #include <cpu.h> #include <dm.h> +#include <log.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_table.h> #include <asm/cpu_common.h> #include <asm/cpu_x86.h> +#include <asm/intel_acpi.h> +#include <asm/msr.h> +#include <dm/acpi.h> + +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + +static struct acpi_cstate cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + }, + }, { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .addrl = 0x415, + }, + }, { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .addrl = 0x419, + }, + }, +}; static int apl_get_info(const struct udevice *dev, struct cpu_info *info) { return cpu_intel_get_info(info, INTEL_BCLK_MHZ); } +static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + uint core_id = dev->req_seq; + int cores_per_package; + int ret; + + cores_per_package = cpu_get_cores_per_package(); + ret = acpi_generate_cpu_header(ctx, core_id, cstate_map, + ARRAY_SIZE(cstate_map)); + + /* Generate P-state tables */ + generate_p_state_entries(ctx, core_id, cores_per_package); + + /* Generate T-state tables */ + generate_t_state_entries(ctx, core_id, cores_per_package, NULL, 0); + + acpigen_pop_len(ctx); + + if (device_is_last_sibling(dev)) { + ret = acpi_generate_cpu_package_final(ctx, cores_per_package); + + if (ret) + return ret; + } + + return 0; +} + +struct acpi_ops apl_cpu_acpi_ops = { + .fill_ssdt = acpi_cpu_fill_ssdt, +}; + static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, .get_info = apl_get_info, @@ -32,5 +108,6 @@ U_BOOT_DRIVER(cpu_x86_apl_drv) = { .of_match = cpu_x86_apl_ids, .bind = cpu_x86_bind, .ops = &cpu_x86_apl_ops, + ACPI_OPS_PTR(&apl_cpu_acpi_ops) .flags = DM_FLAG_PRE_RELOC, }; diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c index e54b0ac104..715ceab6ac 100644 --- a/arch/x86/cpu/apollolake/fsp_s.c +++ b/arch/x86/cpu/apollolake/fsp_s.c @@ -157,6 +157,8 @@ int arch_fsps_preinit(void) struct udevice *itss; int ret; + if (!ll_boot_init()) + return 0; ret = irq_first_device_type(X86_IRQT_ITSS, &itss); if (ret) return log_msg_ret("no itss", ret); diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index cb46ec6c0b..7fd67dcfb6 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -1,17 +1,45 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright 2019 Google LLC + * Copyright (C) 2015 - 2017 Intel Corp. + * Copyright (C) 2017 - 2019 Siemens AG + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) + * + * Portions from coreboot soc/intel/apollolake/chip.c */ +#define LOG_CATEGORY UCLASS_NORTHBRIDGE + #include <common.h> #include <dm.h> #include <dt-structs.h> #include <log.h> #include <spl.h> +#include <tables_csum.h> +#include <acpi/acpi_table.h> +#include <asm/acpi_nhlt.h> #include <asm/intel_pinctrl.h> #include <asm/intel_regs.h> +#include <asm/io.h> #include <asm/pci.h> +#include <asm/arch/acpi.h> #include <asm/arch/systemagent.h> +#include <dt-bindings/sound/nhlt.h> +#include <dm/acpi.h> + +enum { + PCIEXBAR = 0x60, + PCIEXBAR_LENGTH_256MB = 0, + PCIEXBAR_LENGTH_128MB, + PCIEXBAR_LENGTH_64MB, + + PCIEXBAR_PCIEXBAREN = 1 << 0, + + BGSM = 0xb4, /* Base GTT Stolen Memory */ + TSEG = 0xb8, /* TSEG base */ + TOLUD = 0xbc, +}; /** * struct apl_hostbridge_platdata - platform data for hostbridge @@ -32,15 +60,100 @@ struct apl_hostbridge_platdata { pci_dev_t bdf; }; -enum { - PCIEXBAR = 0x60, - PCIEXBAR_LENGTH_256MB = 0, - PCIEXBAR_LENGTH_128MB, - PCIEXBAR_LENGTH_64MB, +static const struct nhlt_format_config dmic_1ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 1, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-1ch-48khz-16b.dat", + }, +}; - PCIEXBAR_PCIEXBAREN = 1 << 0, +static const struct nhlt_dmic_array_config dmic_1ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_VENDOR_DEFINED, +}; - TSEG = 0xb8, /* TSEG base */ +static const struct nhlt_endp_descriptor dmic_1ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_1ch_mic_config, + .cfg_size = sizeof(dmic_1ch_mic_config), + .formats = dmic_1ch_formats, + .num_formats = ARRAY_SIZE(dmic_1ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_2ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.dat", + }, +}; + +static const struct nhlt_dmic_array_config dmic_2ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_2CH_SMALL, +}; + +static const struct nhlt_endp_descriptor dmic_2ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_2ch_mic_config, + .cfg_size = sizeof(dmic_2ch_mic_config), + .formats = dmic_2ch_formats, + .num_formats = ARRAY_SIZE(dmic_2ch_formats), + }, +}; + +static const struct nhlt_format_config dmic_4ch_formats[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 4, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-4ch-48khz-16b.dat", + }, +}; + +static const struct nhlt_dmic_array_config dmic_4ch_mic_config = { + .tdm_config = { + .config_type = NHLT_TDM_MIC_ARRAY, + }, + .array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED, +}; + +static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = { + { + .link = NHLT_LINK_PDM, + .device = NHLT_PDM_DEV, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_DMIC, + .cfg = &dmic_4ch_mic_config, + .cfg_size = sizeof(dmic_4ch_mic_config), + .formats = dmic_4ch_formats, + .num_formats = ARRAY_SIZE(dmic_4ch_formats), + }, }; static int apl_hostbridge_early_init_pinctrl(struct udevice *dev) @@ -165,6 +278,119 @@ static int apl_hostbridge_probe(struct udevice *dev) return 0; } +static int apl_acpi_hb_get_name(const struct udevice *dev, char *out_name) +{ + return acpi_copy_name(out_name, "RHUB"); +} + +#ifdef CONFIG_GENERATE_ACPI_TABLE +static int apl_acpi_hb_write_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct acpi_table_header *header; + struct acpi_dmar *dmar; + u32 val; + + /* + * Create DMAR table only if virtualization is enabled. Due to some + * constraints on Apollo Lake SoC (some stepping affected), VTD could + * not be enabled together with IPU. Doing so will override and disable + * VTD while leaving CAPID0_A still reporting that VTD is available. + * As in this case FSP will lock VTD to disabled state, we need to make + * sure that DMAR table generation only happens when at least DEFVTBAR + * is enabled. Otherwise the DMAR header will be generated while the + * content of the table will be missing. + */ + dm_pci_read_config32(dev, CAPID0_A, &val); + if ((val & VTD_DISABLE) || + !(readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED)) + return 0; + + log_debug("ACPI: * DMAR\n"); + dmar = (struct acpi_dmar *)ctx->current; + header = &dmar->header; + acpi_create_dmar(dmar, DMAR_INTR_REMAP); + ctx->current += sizeof(struct acpi_dmar); + apl_acpi_fill_dmar(ctx); + + /* (Re)calculate length and checksum */ + header->length = ctx->current - (void *)dmar; + header->checksum = table_compute_checksum((void *)dmar, header->length); + + acpi_align(ctx); + acpi_add_table(ctx, dmar); + + return 0; +} +#endif + +static int apl_acpi_setup_nhlt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + struct nhlt *nhlt = ctx->nhlt; + u32 channels; + ofnode node; + + node = ofnode_find_subnode(dev_ofnode(dev), "nhlt"); + if (ofnode_read_u32(node, "intel,dmic-channels", &channels)) + return log_msg_ret("channels", -EINVAL); + switch (channels) { + case 1: + return nhlt_add_endpoints(nhlt, dmic_1ch_descriptors, + ARRAY_SIZE(dmic_1ch_descriptors)); + case 2: + return nhlt_add_endpoints(nhlt, dmic_2ch_descriptors, + ARRAY_SIZE(dmic_2ch_descriptors)); + case 4: + return nhlt_add_endpoints(nhlt, dmic_4ch_descriptors, + ARRAY_SIZE(dmic_4ch_descriptors)); + } + + return log_msg_ret("channels", -EINVAL); +} + +static int apl_hostbridge_remove(struct udevice *dev) +{ + /* + * TODO(sjg@chromium.org): Consider adding code from coreboot's + * platform_fsp_notify_status() + */ + + return 0; +} + +static ulong sa_read_reg(struct udevice *dev, int reg) +{ + u32 val; + + /* All regions concerned for have 1 MiB alignment */ + dm_pci_read_config32(dev, BGSM, &val); + + return ALIGN_DOWN(val, 1 << 20); +} + +ulong sa_get_tolud_base(struct udevice *dev) +{ + return sa_read_reg(dev, TOLUD); +} + +ulong sa_get_gsm_base(struct udevice *dev) +{ + return sa_read_reg(dev, BGSM); +} + +ulong sa_get_tseg_base(struct udevice *dev) +{ + return sa_read_reg(dev, TSEG); +} + +struct acpi_ops apl_hostbridge_acpi_ops = { + .get_name = apl_acpi_hb_get_name, +#ifdef CONFIG_GENERATE_ACPI_TABLE + .write_tables = apl_acpi_hb_write_tables, +#endif + .setup_nhlt = apl_acpi_setup_nhlt, +}; + static const struct udevice_id apl_hostbridge_ids[] = { { .compatible = "intel,apl-hostbridge" }, { } @@ -176,5 +402,8 @@ U_BOOT_DRIVER(apl_hostbridge_drv) = { .of_match = apl_hostbridge_ids, .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata, .probe = apl_hostbridge_probe, + .remove = apl_hostbridge_remove, .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata), + ACPI_OPS_PTR(&apl_hostbridge_acpi_ops) + .flags = DM_FLAG_OS_PREPARE, }; diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index b81a458f2e..a29832c879 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -9,10 +9,14 @@ #include <dm.h> #include <log.h> #include <spl.h> +#include <acpi/acpi_table.h> +#include <asm/cpu_common.h> +#include <asm/intel_acpi.h> #include <asm/lpc_common.h> #include <asm/pci.h> #include <asm/arch/iomap.h> #include <asm/arch/lpc.h> +#include <dm/acpi.h> #include <linux/log2.h> void lpc_enable_fixed_io_ranges(uint io_enables) @@ -110,6 +114,19 @@ void lpc_io_setup_comm_a_b(void) lpc_enable_fixed_io_ranges(com_enable); } +static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name) +{ + return acpi_copy_name(out_name, "LPCB"); +} + +struct acpi_ops apl_lpc_acpi_ops = { + .get_name = apl_acpi_lpc_get_name, +#ifdef CONFIG_GENERATE_ACPI_TABLE + .write_tables = intel_southbridge_write_acpi_tables, +#endif + .inject_dsdt = southbridge_inject_dsdt, +}; + static const struct udevice_id apl_lpc_ids[] = { { .compatible = "intel,apl-lpc" }, { } @@ -120,4 +137,5 @@ U_BOOT_DRIVER(apl_lpc_drv) = { .name = "intel_apl_lpc", .id = UCLASS_LPC, .of_match = apl_lpc_ids, + ACPI_OPS_PTR(&apl_lpc_acpi_ops) }; diff --git a/arch/x86/cpu/apollolake/pmc.c b/arch/x86/cpu/apollolake/pmc.c index 192dec7109..576d018757 100644 --- a/arch/x86/cpu/apollolake/pmc.c +++ b/arch/x86/cpu/apollolake/pmc.c @@ -118,7 +118,8 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) int size; int ret; - ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base)); + ret = dev_read_u32_array(dev, "early-regs", base, + ARRAY_SIZE(base)); if (ret) return log_msg_ret("Missing/short early-regs", ret); if (spl_phase() == PHASE_TPL) { @@ -133,11 +134,6 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev) } upriv->acpi_base = base[4]; - /* Since PCI is not enabled, we must get the BDF manually */ - plat->bdf = pci_get_devfn(dev); - if (plat->bdf < 0) - return log_msg_ret("Cannot get PMC PCI address", plat->bdf); - /* Get the dwX values for pmc gpe settings */ size = dev_read_size(dev, "gpe0-dw"); if (size < 0) diff --git a/arch/x86/cpu/broadwell/cpu_from_spl.c b/arch/x86/cpu/broadwell/cpu_from_spl.c index 6567d50653..4d4cdafa2b 100644 --- a/arch/x86/cpu/broadwell/cpu_from_spl.c +++ b/arch/x86/cpu/broadwell/cpu_from_spl.c @@ -53,14 +53,12 @@ void board_debug_uart_init(void) int dram_init_banksize(void) { -#ifdef CONFIG_NR_DRAM_BANKS struct spl_handoff *ho; ho = bloblist_find(BLOBLISTT_SPL_HANDOFF, sizeof(*ho)); if (!ho) return log_msg_ret("Missing SPL hand-off info", -ENOENT); handoff_load_dram_banks(ho); -#endif return 0; } diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 69c14189d1..f869275396 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -189,6 +189,14 @@ __weak void board_final_init(void) { } +/* + * Implement a weak default function for boards that need to do some final + * processing before booting the OS. + */ +__weak void board_final_cleanup(void) +{ +} + int last_stage_init(void) { struct acpi_fadt __maybe_unused *fadt; @@ -218,6 +226,13 @@ int last_stage_init(void) } } + /* + * TODO(sjg@chromium.org): Move this to bootm_announce_and_cleanup() + * once APL FSP-S at 0x200000 does not overlap with the bzimage at + * 0x100000. + */ + board_final_cleanup(); + return 0; } #endif diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c index 8f342dd06e..7517b756f4 100644 --- a/arch/x86/cpu/i386/cpu.c +++ b/arch/x86/cpu/i386/cpu.c @@ -34,6 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; +#define CPUID_FEATURE_PAE BIT(6) +#define CPUID_FEATURE_PSE36 BIT(17) +#define CPUID_FEAURE_HTT BIT(28) + /* * Constructor for a conventional segment GDT (or LDT) entry * This is a macro so it can be used in initialisers @@ -388,6 +392,25 @@ static void setup_identity(void) } } +static uint cpu_cpuid_extended_level(void) +{ + return cpuid_eax(0x80000000); +} + +int cpu_phys_address_size(void) +{ + if (!has_cpuid()) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + + return 32; +} + /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */ static void setup_pci_ram_top(void) { diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 374803b876..4a5cf17e41 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -2,6 +2,8 @@ # # Copyright (c) 2016 Google, Inc +obj-$(CONFIG_INTEL_ACPIGEN) += acpi.o + ifdef CONFIG_HAVE_MRC obj-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += car.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o @@ -9,6 +11,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o +endif + ifdef CONFIG_INTEL_CAR_CQOS obj-$(CONFIG_TPL_BUILD) += car2.o ifndef CONFIG_SPL_BUILD @@ -20,6 +26,7 @@ obj-y += cpu.o obj-y += fast_spi.o obj-y += lpc.o obj-y += lpss.o +obj-$(CONFIG_INTEL_GENERIC_WIFI) += generic_wifi.o ifndef CONFIG_TARGET_EFI_APP obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c new file mode 100644 index 0000000000..a4d5fbd38a --- /dev/null +++ b/arch/x86/cpu/intel_common/acpi.c @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generic Intel ACPI table generation + * + * Copyright (C) 2017 Intel Corp. + * Copyright 2019 Google LLC + * + * Modified from coreboot src/soc/intel/common/block/acpi.c + */ + +#include <common.h> +#include <bloblist.h> +#include <cpu.h> +#include <dm.h> +#include <acpi/acpigen.h> +#include <asm/acpigen.h> +#include <asm/acpi_table.h> +#include <asm/cpu.h> +#include <asm/cpu_common.h> +#include <asm/intel_acpi.h> +#include <asm/ioapic.h> +#include <asm/mpspec.h> +#include <asm/smm.h> +#include <asm/turbo.h> +#include <asm/intel_gnvs.h> +#include <asm/arch/iomap.h> +#include <asm/arch/pm.h> +#include <asm/arch/systemagent.h> +#include <dm/acpi.h> +#include <linux/err.h> +#include <power/acpi_pmc.h> + +u32 acpi_fill_mcfg(u32 current) +{ + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + (CONFIG_SA_PCIEX_LENGTH >> 20) + - 1); + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + uint scis; + int ret; + + ret = arch_read_sci_irq_select(); + if (IS_ERR_VALUE(ret)) + return log_msg_ret("sci_irq", ret); + scis = ret; + scis &= SCI_IRQ_MASK; + scis >>= SCI_IRQ_SHIFT; + + /* Determine how SCI is routed. */ + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + log_warning("Invalid SCI route! Defaulting to IRQ9\n"); + sci_irq = 9; + break; + } + + log_debug("SCI is IRQ%d\n", sci_irq); + + return sci_irq; +} + +static unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci = acpi_sci_irq(); + u16 flags = MP_IRQ_TRIGGER_LEVEL; + + if (sci < 0) + return log_msg_ret("sci irq", sci); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + flags |= arch_madt_sci_irq_polarity(sci); + + /* SCI */ + current += + acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + + return current; +} + +u32 acpi_fill_madt(u32 current) +{ + /* Local APICs */ + current += acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *)current, 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + +void intel_acpi_fill_fadt(struct acpi_fadt *fadt) +{ + const u16 pmbase = IOMAP_ACPI_BASE; + + /* Use ACPI 3.0 revision. */ + fadt->header.revision = acpi_get_table_revision(ACPITAB_FADT); + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + + fadt->gpe0_blk = pmbase + GPE0_STS; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + + /* GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + + fadt->flush_size = 0x400; /* twice of cache size */ + fadt->flush_stride = 0x10; /* Cache line width */ + fadt->duty_offset = 1; + fadt->day_alrm = 0xd; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = IO_PORT_RESET; + fadt->reset_value = RST_CPU | SYS_RST; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_gpe1_blk.space_id = 1; +} + +int intel_southbridge_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + int ret; + + ret = acpi_write_dbg2_pci_uart(ctx, gd->cur_serial_dev, + ACPI_ACCESS_SIZE_DWORD_ACCESS); + if (ret) + return log_msg_ret("dbg2", ret); + + ret = acpi_write_hpet(ctx); + if (ret) + return log_msg_ret("hpet", ret); + + return 0; +} + +__weak u32 acpi_fill_soc_wake(u32 generic_pm1_en, + const struct chipset_power_state *ps) +{ + return generic_pm1_en; +} + +__weak int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + return 0; +} + +int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + struct acpi_global_nvs *gnvs; + int ret; + + ret = bloblist_ensure_size(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs), + (void **)&gnvs); + if (ret) + return log_msg_ret("bloblist", ret); + memset(gnvs, '\0', sizeof(*gnvs)); + + ret = acpi_create_gnvs(gnvs); + if (ret) + return log_msg_ret("gnvs", ret); + + /* + * TODO(sjg@chromum.org): tell SMI about it + * smm_setup_structures(gnvs, NULL, NULL); + */ + + /* Add it to DSDT */ + acpigen_write_scope(ctx, "\\"); + acpigen_write_name_dword(ctx, "NVSA", (uintptr_t)gnvs); + acpigen_pop_len(ctx); + + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return power; +} + +void generate_p_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, num_entries; + int ratio, power, clock, clock_max; + bool turbo; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = (ratio_max * cpu_get_bus_clock_khz()) / 1000; + turbo = (turbo_get_state() == TURBO_ENABLED); + + /* Calculate CPU TDP in mW */ + power_max = cpu_get_power_max(); + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_pct(ctx); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_ppc_nvs(ctx); + /* Write PSD indicating configured coordination type */ + acpigen_write_psd_package(ctx, core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name(ctx, "_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + do { + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (((ratio_max - ratio_min) % ratio_step) > 0) + num_entries += 1; + if (turbo) + num_entries += 1; + if (num_entries > PSS_MAX_ENTRIES) + ratio_step += 1; + } while (num_entries > PSS_MAX_ENTRIES); + + /* _PSS package count depends on Turbo */ + acpigen_write_package(ctx, num_entries); + + /* P[T] is Turbo state if enabled */ + if (turbo) { + ratio_turbo = cpu_get_max_turbo_ratio(); + + /* Add entry for Turbo ratio */ + acpigen_write_pss_package(ctx, clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + num_entries -= 1; + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_pss_package(ctx, clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + num_entries -= 1; + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * cpu_get_bus_clock_khz()) / 1000; + + acpigen_write_pss_package(ctx, clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION,/* lat1 */ + PSS_LATENCY_BUSMASTER,/* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(ctx); +} + +void generate_t_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package, struct acpi_tstate *entry, + int nentries) +{ + if (!nentries) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_tsd_package(ctx, core, cores_per_package, SW_ALL); + + /* Indicate FixedHW so OS will use MSR */ + acpigen_write_empty_ptc(ctx); + + /* Set NVS controlled T-state limit */ + acpigen_write_tpc(ctx, "\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_tss_package(ctx, entry, nentries); +} + +int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id, + const struct acpi_cstate *c_state_map, + int num_cstates) +{ + bool is_first = !core_id; + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor(ctx, core_id, is_first ? ACPI_BASE_ADDRESS : 0, + is_first ? 6 : 0); + + /* Generate C-state tables */ + acpigen_write_cst_package(ctx, c_state_map, num_cstates); + + return 0; +} + +int acpi_generate_cpu_package_final(struct acpi_ctx *ctx, int cores_per_package) +{ + /* + * PPKG is usually used for thermal management of the first and only + * package + */ + acpigen_write_processor_package(ctx, "PPKG", 0, cores_per_package); + + /* Add a method to notify processor nodes */ + acpigen_write_processor_cnot(ctx, cores_per_package); + + return 0; +} diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 509730aea9..39aa0f63c6 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -12,6 +12,7 @@ #include <dm.h> #include <errno.h> #include <log.h> +#include <acpi/acpigen.h> #include <asm/cpu.h> #include <asm/cpu_common.h> #include <asm/intel_regs.h> @@ -126,6 +127,7 @@ int cpu_intel_get_info(struct cpu_info *info, int bclk) info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000; info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU | 1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID; + info->address_width = cpu_phys_address_size(); return 0; } @@ -227,3 +229,80 @@ void cpu_set_eist(bool eist_status) msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP; msr_write(MSR_IA32_MISC_ENABLE, msr); } + +int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +int cpu_get_min_ratio(void) +{ + msr_t msr; + + /* Get bus ratio limits and calculate clock speeds */ + msr = msr_read(MSR_PLATFORM_INFO); + + return (msr.hi >> 8) & 0xff; /* Max Efficiency Ratio */ +} + +int cpu_get_max_ratio(void) +{ + u32 ratio_max; + msr_t msr; + + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = msr_read(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + + return ratio_max; +} + +int cpu_get_bus_clock_khz(void) +{ + /* + * CPU bus clock is set by default here to 100MHz. This function returns + * the bus clock in KHz. + */ + return INTEL_BCLK_MHZ * 1000; +} + +int cpu_get_power_max(void) +{ + int power_unit; + msr_t msr; + + msr = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = msr_read(MSR_PKG_POWER_SKU); + + return (msr.lo & 0x7fff) * 1000 / power_unit; +} + +int cpu_get_max_turbo_ratio(void) +{ + msr_t msr; + + msr = msr_read(MSR_TURBO_RATIO_LIMIT); + + return msr.lo & 0xff; +} + +int cpu_get_cores_per_package(void) +{ + struct cpuid_result result; + int cores = 1; + + if (gd->arch.x86_vendor != X86_VENDOR_INTEL) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c new file mode 100644 index 0000000000..61ec5391b0 --- /dev/null +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Generic WiFi ACPI info + * + * Copyright 2019 Google LLC + * Modified from coreboot src/drivers/wifi/generic.c + */ + +#include <common.h> +#include <log.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <dm.h> +#include <dm/acpi.h> + +/* WRDS Spec Revision */ +#define WRDS_REVISION 0x0 + +/* EWRD Spec Revision */ +#define EWRD_REVISION 0x0 + +/* WRDS Domain type */ +#define WRDS_DOMAIN_TYPE_WIFI 0x7 + +/* EWRD Domain type */ +#define EWRD_DOMAIN_TYPE_WIFI 0x7 + +/* WGDS Domain type */ +#define WGDS_DOMAIN_TYPE_WIFI 0x7 + +/* + * WIFI ACPI NAME = "WF" + hex value of last 8 bits of dev_path_encode + '\0' + * The above representation returns unique and consistent name every time + * generate_wifi_acpi_name is invoked. The last 8 bits of dev_path_encode is + * chosen since it contains the bus address of the device. + */ +#define WIFI_ACPI_NAME_MAX_LEN 5 + +/** + * struct generic_wifi_config - Data structure to contain common wifi config + * @wake: Wake pin for ACPI _PRW + * @maxsleep: Maximum sleep state to wake from + */ +struct generic_wifi_config { + unsigned int wake; + unsigned int maxsleep; +}; + +static int generic_wifi_fill_ssdt(struct acpi_ctx *ctx, + const struct udevice *dev, + const struct generic_wifi_config *config) +{ + char name[ACPI_NAME_MAX]; + char path[ACPI_PATH_MAX]; + pci_dev_t bdf; + u32 address; + int ret; + + ret = acpi_device_path(dev_get_parent(dev), path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + ret = acpi_get_name(dev, name); + if (ret) + return log_msg_ret("name", ret); + + /* Device */ + acpigen_write_scope(ctx, path); + acpigen_write_device(ctx, name); + acpigen_write_name_integer(ctx, "_UID", 0); + acpigen_write_name_string(ctx, "_DDN", + dev_read_string(dev, "acpi,ddn")); + + /* Address */ + bdf = dm_pci_get_bdf(dev); + address = (PCI_DEV(bdf) << 16) | PCI_FUNC(bdf); + acpigen_write_name_dword(ctx, "_ADR", address); + + /* Wake capabilities */ + if (config) + acpigen_write_prw(ctx, config->wake, config->maxsleep); + + acpigen_pop_len(ctx); /* Device */ + acpigen_pop_len(ctx); /* Scope */ + + return 0; +} + +static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct generic_wifi_config config; + bool have_config; + int ret; + + ret = dev_read_u32(dev, "acpi,wake", &config.wake); + have_config = !ret; + /* By default, all intel wifi chips wake from S3 */ + config.maxsleep = 3; + ret = generic_wifi_fill_ssdt(ctx, dev, have_config ? &config : NULL); + if (ret) + return log_msg_ret("wifi", ret); + + return 0; +} + +struct acpi_ops wifi_acpi_ops = { + .fill_ssdt = intel_wifi_acpi_fill_ssdt, +}; + +static const struct udevice_id intel_wifi_ids[] = { + { .compatible = "intel,generic-wifi" }, + { } +}; + +U_BOOT_DRIVER(intel_wifi) = { + .name = "intel_wifi", + .id = UCLASS_MISC, + .of_match = intel_wifi_ids, + ACPI_OPS_PTR(&wifi_acpi_ops) +}; diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c new file mode 100644 index 0000000000..4e6c64d9aa --- /dev/null +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.c + */ + +#include <common.h> +#include <binman.h> +#include <bloblist.h> +#include <dm.h> +#include <spi_flash.h> +#include <asm/intel_opregion.h> + +static char vbt_data[8 << 10]; + +static int locate_vbt(char **vbtp, int *sizep) +{ + struct binman_entry vbt; + struct udevice *dev; + u32 vbtsig = 0; + int size; + int ret; + + ret = binman_entry_find("intel-vbt", &vbt); + if (ret) + return log_msg_ret("find VBT", ret); + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("find flash", ret); + size = vbt.size; + if (size > sizeof(vbt_data)) + return log_msg_ret("vbt", -E2BIG); + ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data); + if (ret) + return log_msg_ret("read", ret); + + memcpy(&vbtsig, vbt_data, sizeof(vbtsig)); + if (vbtsig != VBT_SIGNATURE) { + log_err("Missing/invalid signature in VBT data file!\n"); + return -EINVAL; + } + + log_info("Found a VBT of %u bytes\n", size); + *sizep = size; + *vbtp = vbt_data; + + return 0; +} + +/* Write ASLS PCI register and prepare SWSCI register */ +static int intel_gma_opregion_register(struct udevice *dev, ulong opregion) +{ + int sci_reg; + + if (!device_active(dev)) + return -ENOENT; + + /* + * Intel BIOS Specification + * Chapter 5.3.7 "Initialise Hardware State" + */ + dm_pci_write_config32(dev, ASLS, opregion); + + /* + * Atom-based platforms use a combined SMI/SCI register, + * whereas non-Atom platforms use a separate SCI register + */ + if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) + sci_reg = SWSMISCI; + else + sci_reg = SWSCI; + + /* + * Intel's Windows driver relies on this: + * Intel BIOS Specification + * Chapter 5.4 "ASL Software SCI Handler" + */ + dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL); + + return 0; +} + +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion) +{ + struct optionrom_vbt *vbt = NULL; + char *vbt_buf; + int vbt_size; + int ret; + + ret = locate_vbt(&vbt_buf, &vbt_size); + if (ret) { + log_err("GMA: VBT couldn't be found\n"); + return log_msg_ret("find vbt", ret); + } + vbt = (struct optionrom_vbt *)vbt_buf; + + memset(opregion, '\0', sizeof(struct igd_opregion)); + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(opregion->header.signature)); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, + ARRAY_SIZE(vbt->coreblock_biosbuild)); + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + struct optionrom_vbt *ext_vbt; + + ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT, + vbt->hdr_vbt_size, + (void **)&ext_vbt); + if (ret) { + log_err("GMA: Unable to add Ext VBT to bloblist\n"); + return log_msg_ret("blob", ret); + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size which can fit in gvd1 */ + printf("copy to %p\n", opregion->vbt.gvd1); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); + } + + /* 8kb */ + opregion->header.size = sizeof(struct igd_opregion) / 1024; + + /* + * Left-shift version field to accommodate Intel Windows driver quirk + * when not using a VBIOS. + * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. + * + * No adverse effects when using VBIOS or booting Linux. + */ + opregion->header.version = IGD_OPREGION_VERSION << 24; + + /* We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* Initialise Mailbox 1 */ + opregion->mailbox1.clid = 1; + + /* Initialise Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + /* Write ASLS PCI register and prepare SWSCI register */ + ret = intel_gma_opregion_register(dev, (ulong)opregion); + if (ret) + return log_msg_ret("write asls", ret); + + return 0; +} diff --git a/arch/x86/cpu/mtrr.c b/arch/x86/cpu/mtrr.c index 2468d88a80..5180eb06fc 100644 --- a/arch/x86/cpu/mtrr.c +++ b/arch/x86/cpu/mtrr.c @@ -19,6 +19,7 @@ #include <common.h> #include <cpu_func.h> #include <log.h> +#include <sort.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/mp.h> @@ -66,9 +67,10 @@ static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size) void mtrr_read_all(struct mtrr_info *info) { + int reg_count = mtrr_get_var_count(); int i; - for (i = 0; i < MTRR_COUNT; i++) { + for (i = 0; i < reg_count; i++) { info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i)); info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i)); } @@ -76,10 +78,11 @@ void mtrr_read_all(struct mtrr_info *info) void mtrr_write_all(struct mtrr_info *info) { + int reg_count = mtrr_get_var_count(); struct mtrr_state state; int i; - for (i = 0; i < MTRR_COUNT; i++) { + for (i = 0; i < reg_count; i++) { mtrr_open(&state, true); wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base); wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask); @@ -124,6 +127,16 @@ static int mtrr_copy_to_aps(void) return 0; } +static int h_comp_mtrr(const void *p1, const void *p2) +{ + const struct mtrr_request *req1 = p1; + const struct mtrr_request *req2 = p2; + + s64 diff = req1->start - req2->start; + + return diff < 0 ? -1 : diff > 0 ? 1 : 0; +} + int mtrr_commit(bool do_caches) { struct mtrr_request *req = gd->arch.mtrr_req; @@ -139,12 +152,13 @@ int mtrr_commit(bool do_caches) debug("open\n"); mtrr_open(&state, do_caches); debug("open done\n"); + qsort(req, gd->arch.mtrr_req_count, sizeof(*req), h_comp_mtrr); for (i = 0; i < gd->arch.mtrr_req_count; i++, req++) set_var_mtrr(i, req->type, req->start, req->size); /* Clear the ones that are unused */ debug("clear\n"); - for (; i < MTRR_COUNT; i++) + for (; i < MTRR_MAX_COUNT; i++) wrmsrl(MTRR_PHYS_MASK_MSR(i), 0); debug("close\n"); mtrr_close(&state, do_caches); @@ -184,7 +198,7 @@ int mtrr_add_request(int type, uint64_t start, uint64_t size) return 0; } -static int get_var_mtrr_count(void) +int mtrr_get_var_count(void) { return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT; } @@ -195,7 +209,7 @@ static int get_free_var_mtrr(void) int vcnt; int i; - vcnt = get_var_mtrr_count(); + vcnt = mtrr_get_var_count(); /* Identify the first var mtrr which is not valid */ for (i = 0; i < vcnt; i++) { diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig index d2b7edecd6..571470c74b 100644 --- a/arch/x86/cpu/tangier/Kconfig +++ b/arch/x86/cpu/tangier/Kconfig @@ -12,6 +12,7 @@ config INTEL_TANGIER imply MMC_SDHCI_TANGIER imply USB imply USB_DWC3 + imply BINMAN if INTEL_TANGIER diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 1b4d3971b0..90a766c3c5 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -70,3 +70,8 @@ int x86_cpu_reinit_f(void) { return 0; } + +int cpu_phys_address_size(void) +{ + return CONFIG_CPU_ADDR_BITS; +} diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index a17a9c2800..893a59b162 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -15,14 +15,20 @@ #include "flashmap-16mb-rw.dtsi" #endif +#include <dt-bindings/clock/intel-clock.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/x86-irq.h> +#include <asm/e820.h> #include <asm/intel_pinctrl_defs.h> #include <asm/arch-apollolake/cpu.h> +#include <asm/arch-apollolake/gpe.h> #include <asm/arch-apollolake/gpio.h> #include <asm/arch-apollolake/iomap.h> #include <asm/arch-apollolake/pm.h> #include <dt-bindings/clock/intel-clock.h> #include <asm/arch-apollolake/fsp/fsp_m_upd.h> #include <asm/arch-apollolake/fsp/fsp_s_upd.h> +#include <dt-bindings/sound/nhlt.h> / { model = "Google Coral"; @@ -40,6 +46,14 @@ i2c5 = &i2c_5; i2c6 = &i2c_6; i2c7 = &i2c_7; + mmc1 = &sdmmc; + }; + + board: board { + compatible = "google,coral"; + recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>; + write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>; + phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>; }; config { @@ -48,6 +62,15 @@ chosen { stdout-path = &serial; + e820-entries = /bits/ 64 < + IOMAP_P2SB_BAR IOMAP_P2SB_SIZE E820_RESERVED + MCH_BASE_ADDRESS MCH_SIZE E820_RESERVED>; + u-boot,acpi-ssdt-order = <&cpu_0 &cpu_1 &cpu_2 &cpu_3 + &i2c_0 &i2c_1 &i2c_2 &i2c_3 &i2c_4 &i2c_5 + &sdmmc &maxim_codec &wifi &da_codec &tpm + &elan_touchscreen &raydium_touchscreen + &elan_touchpad &synaptics_touchpad &wacom_digitizer>; + u-boot,acpi-dsdt-order = <&board &lpc>; }; clk: clock { @@ -60,7 +83,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu_0: cpu@0 { u-boot,dm-pre-reloc; device_type = "cpu"; compatible = "intel,apl-cpu"; @@ -68,21 +91,21 @@ intel,apic-id = <0>; }; - cpu@1 { + cpu_1: cpu@1 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <1>; intel,apic-id = <2>; }; - cpu@2 { + cpu_2: cpu@2 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <2>; intel,apic-id = <4>; }; - cpu@3 { + cpu_3: cpu@3 { device_type = "cpu"; compatible = "intel,apl-cpu"; reg = <3>; @@ -128,6 +151,10 @@ */ fsp_s: fsp-s { }; + + nhlt { + intel,dmic-channels = <4>; + }; }; punit@0,1 { @@ -136,21 +163,29 @@ compatible = "intel,apl-punit"; }; + gma@2,0 { + reg = <0x00001000 0 0 0 0>; + compatible = "fsp-fb"; + }; + p2sb: p2sb@d,0 { u-boot,dm-pre-reloc; reg = <0x02006810 0 0 0 0>; compatible = "intel,p2sb"; early-regs = <IOMAP_P2SB_BAR 0x100000>; + pci,no-autoconfig; n { compatible = "intel,apl-pinctrl"; u-boot,dm-pre-reloc; intel,p2sb-port-id = <PID_GPIO_N>; + acpi,path = "\\_SB.GPO0"; gpio_n: gpio-n { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:00"; }; }; @@ -159,11 +194,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_NW>; #gpio-cells = <2>; + acpi,path = "\\_SB.GPO1"; gpio_nw: gpio-nw { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:01"; }; }; @@ -172,11 +209,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_W>; #gpio-cells = <2>; + acpi,path = "\\_SB.GPO2"; gpio_w: gpio-w { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:02"; }; }; @@ -185,11 +224,13 @@ compatible = "intel,apl-pinctrl"; intel,p2sb-port-id = <PID_GPIO_SW>; #gpio-cells = <2>; + acpi,path = "\\_SB.GPO3"; gpio_sw: gpio-sw { compatible = "intel,gpio"; u-boot,dm-pre-reloc; gpio-controller; #gpio-cells = <2>; + linux-name = "INT3452:03"; }; }; @@ -238,6 +279,24 @@ gpe0-en = <0x30>; }; + audio@e,0 { + reg = <0x7000 0 0 0 0>; + compatible = "simple-bus"; + acpi,name = "HDAS"; + i2s { + compatible = "fred"; + }; + maxim_codec: maxim-codec { + compatible = "maxim,max98357a"; + acpi,ddn = "Maxim Integrated 98357A Amplifier"; + sdmode-gpios = <&gpio_n GPIO_76 GPIO_ACTIVE_HIGH>; + sdmode-delay = <5>; + acpi,name = "MAXM"; + acpi,hid = "MX98357A"; + acpi,audio-link = <AUDIO_LINK_SSP5>; + }; + }; + spi: fast-spi@d,2 { u-boot,dm-pre-reloc; reg = <0x02006a10 0 0 0 0>; @@ -267,19 +326,63 @@ }; }; + /* WiFi */ + pcie-a0@14,0 { + reg = <0x0000a000 0 0 0 0>; + acpi,name = "RP01"; + wifi: wifi { + compatible = "intel,generic-wifi"; + acpi,ddn = "Intel WiFi"; + acpi,name = "WF00"; + acpi,wake = <GPE0_DW3_00>; + interrupts-extended = <&acpi_gpe 0x3c 0>; + }; + }; + i2c_0: i2c2@16,0 { compatible = "intel,apl-i2c"; reg = <0x0200b010 0 0 0 0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <104>; i2c-scl-falling-time-ns = <52>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; + #address-cells = <1>; + #size-cells = <0>; + da_codec: da-codec { + reg = <0x1a>; + compatible = "dlg,da7219"; + interrupts-extended = <&acpi_gpe GPIO_116_IRQ + (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; + acpi,name = "DLG7"; + acpi,ddn = "Dialog Semiconductor DA7219 Audio Codec"; + acpi,audio-link = <AUDIO_LINK_SSP1>; + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + da7219_aad { + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3e>; + dlg,btn-avg = <4>; + dlg,adc-1bit-rpt = <1>; + }; + }; }; i2c_1: i2c2@16,1 { compatible = "intel,apl-i2c"; reg = <0x0200b110 0 0 0 0>; clocks = <&clk CLK_I2C>; - status = "disabled"; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000 3400000>; + i2c-scl-rising-time-ns = <52>; + i2c-scl-falling-time-ns = <52>; }; i2c_2: i2c2@16,2 { @@ -288,53 +391,130 @@ #address-cells = <1>; #size-cells = <0>; clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <57>; i2c-scl-falling-time-ns = <28>; - tpm@50 { + tpm: tpm@50 { reg = <0x50>; compatible = "google,cr50"; u-boot,i2c-offset-len = <0>; ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>; - interrupts-extended = <&acpi_gpe 0x3c 0>; + interrupts-extended = <&acpi_gpe GPIO_28_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,hid = "GOOG0005"; + acpi,ddn = "I2C TPM"; + acpi,name = "TPMI"; }; }; i2c_3: i2c2@16,3 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b310 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <76>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000>; + elan_touchscreen: elan-touchscreen@10 { + compatible = "i2c-chip"; + reg = <0x10>; + acpi,hid = "ELAN0001"; + acpi,ddn = "ELAN Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <20>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <1>; + acpi,has-power-resource; + }; + + raydium_touchscreen: raydium-touchscreen@39 { + compatible = "i2c-chip"; + reg = <0x39>; + acpi,hid = "RAYD0001"; + acpi,ddn = "Raydium Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <1>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <50>; + acpi,has-power-resource; + }; }; i2c_4: i2c2@17,0 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b810 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-sda-hold-time-ns = <350>; i2c-scl-rising-time-ns = <114>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000>; + elan_touchpad: elan-touchpad@15 { + compatible = "i2c-chip"; + reg = <0x15>; + u-boot,i2c-offset-len = <0>; + acpi,hid = "ELAN0000"; + acpi,ddn = "ELAN Touchpad"; + interrupts-extended = <&acpi_gpe GPIO_18_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,wake = <GPE0_DW1_15>; + linux,probed; + }; + synaptics_touchpad: synaptics-touchpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + acpi,hid = "PNP0C50"; + acpi,ddn = "Synaptics Touchpad"; + interrupts-extended = <&acpi_gpe GPIO_18_IRQ + IRQ_TYPE_EDGE_FALLING>; + acpi,wake = <GPE0_DW1_15>; + linux,probed; + hid-descr-addr = <0x20>; + }; }; i2c_5: i2c2@17,1 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200b910 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; clocks = <&clk CLK_I2C>; i2c-scl-rising-time-ns = <76>; i2c-scl-falling-time-ns = <164>; + clock-frequency = <400000>; + i2c,speeds = <100000 400000 1000000>; + wacom_digitizer: wacom-digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x9>; + acpi,hid = "WCOM50C1"; + acpi,ddn = "WCOM Digitizer"; + interrupts-extended = <&acpi_gpe GPIO_13_IRQ + (IRQ_TYPE_LEVEL_LOW | X86_IRQ_TYPE_SHARED)>; + hid-descr-addr = <0x1>; + }; }; i2c_6: i2c2@17,2 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200ba10 0 0 0 0>; clocks = <&clk CLK_I2C>; status = "disabled"; }; i2c_7: i2c2@17,3 { compatible = "intel,apl-i2c"; - reg = <0x0200b110 0 0 0 0>; + reg = <0x0200bb10 0 0 0 0>; clocks = <&clk CLK_I2C>; status = "disabled"; }; @@ -347,6 +527,15 @@ reg-shift = <2>; clock-frequency = <1843200>; current-speed = <115200>; + acpi,name = "URT3"; + pci,no-autoconfig; + }; + + sdmmc: sdmmc@1b,0 { + reg = <0x0000d800 0 0 0 0>; + compatible = "intel,apl-sd"; + cd-gpios = <&gpio_n GPIO_177 GPIO_ACTIVE_LOW>; + acpi,name = "SDCD"; }; pch: pch@1f,0 { @@ -356,7 +545,7 @@ #address-cells = <1>; #size-cells = <1>; - lpc { + lpc: lpc { compatible = "intel,apl-lpc"; #address-cells = <1>; #size-cells = <0>; @@ -594,12 +783,17 @@ * [6:0] steps of delay for HS200, each 125ps */ /* Enable DPTF */ - dptf-enable; + fsps,dptf-enabled; fsps,emmc-tx-data-cntl1 = <0x0c16>; fsps,emmc-tx-data-cntl2 = <0x28162828>; fsps,emmc-rx-cmd-data-cntl1 = <0x00181717>; fsps,emmc-rx-cmd-data-cntl2 = <0x10008>; + /* Enable Audio Clock and Power gating */ + fsps,hd-audio-clk-gate = <1>; + fsps,hd-audio-pwr-gate = <1>; + fsps,bios-cfg-lock-down = <1>; + /* Enable WiFi */ fsps,pcie-root-port-en = [01 00 00 00 00 00]; fsps,pcie-rp-hot-plug = [00 00 00 00 00 00]; @@ -611,6 +805,10 @@ fsps,port-usb20-per-port-pe-txi-set = [07 07 06 06 07 07 07 01]; fsps,port-usb20-per-port-txi-set = [00 02 00 00 00 00 00 03]; + fsps,lpss-s0ix-enable = <1>; + fsps,usb-otg = <0>; + fsps,monitor-mwait-enable = <0>; + /* * TODO(sjg@chromium.org): Move this to the I2C nodes * Intel Common SoC Config diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts index df24aa0d26..e2f9469de3 100644 --- a/arch/x86/dts/edison.dts +++ b/arch/x86/dts/edison.dts @@ -22,6 +22,10 @@ serial2 = &serial2; }; + binman: binman { + multiple-images; + }; + chosen { stdout-path = &serial2; }; @@ -130,3 +134,33 @@ }; }; }; + +&binman { + u-boot-edison { + filename = "u-boot-edison.img"; + + /* This is the OSIP */ + blob { + filename = "edison-osip.dat"; + }; + + u-boot { + offset = <0x200>; + }; + + u-boot-env { + offset = <0x200200>; + filename = "edison-environment.txt"; + size = <0x10000>; + fill-byte = [ff]; + }; + + u-boot-env2 { + type = "u-boot-env"; + offset = <0x500200>; + filename = "edison-environment.txt"; + size = <0x10000>; + fill-byte = [ff]; + }; + }; +}; diff --git a/arch/x86/dts/emulation-u-boot.dtsi b/arch/x86/dts/emulation-u-boot.dtsi index 6b651a394f..7245fe51b3 100644 --- a/arch/x86/dts/emulation-u-boot.dtsi +++ b/arch/x86/dts/emulation-u-boot.dtsi @@ -7,17 +7,15 @@ #include <u-boot.dtsi> #ifdef CONFIG_ROM_SIZE -/ { - binman { +&rom { #ifdef CONFIG_SPL - u-boot-spl-with-ucode-ptr { - optional-ucode; - }; + u-boot-spl-with-ucode-ptr { + optional-ucode; + }; #else - u-boot-with-ucode-ptr { - optional-ucode; - }; -#endif + u-boot-with-ucode-ptr { + optional-ucode; }; +#endif }; #endif diff --git a/arch/x86/dts/quark-u-boot.dtsi b/arch/x86/dts/quark-u-boot.dtsi index 7ebc30166d..60ffffcc0e 100644 --- a/arch/x86/dts/quark-u-boot.dtsi +++ b/arch/x86/dts/quark-u-boot.dtsi @@ -6,11 +6,9 @@ #include <u-boot.dtsi> #ifdef CONFIG_ROM_SIZE -/ { - binman { - u-boot-with-ucode-ptr { - optional-ucode; - }; +&rom { + u-boot-with-ucode-ptr { + optional-ucode; }; }; #endif diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index fa8106c8b8..90badcc15c 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -6,7 +6,6 @@ #include <config.h> -#ifdef CONFIG_CHROMEOS / { binman { multiple-images; @@ -14,12 +13,6 @@ }; }; }; -#else -/ { - rom: binman { - }; -}; -#endif #ifdef CONFIG_ROM_SIZE &rom { diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl new file mode 100644 index 0000000000..2a0fd33265 --- /dev/null +++ b/arch/x86/include/asm/acpi/chromeos.asl @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + */ + +#ifdef CONFIG_CHROMEOS + +#define CONFIG_VBOOT_VBNV_OFFSET 0x26 + +#include <asm/acpi/vbnv_layout.h> + +/* GPIO package generated at run time. */ +External (OIPG) + +Device (CRHW) +{ + Name(_HID, EISAID("GGL0001")) + + Method(_STA, 0, Serialized) + { + Return (0xb) + } + + Method(CHSW, 0, Serialized) + { + Name (WSHC, Package() { VBT3 }) + Return (WSHC) + } + + Method(FWID, 0, Serialized) + { + Name (DIW1, "") + ToString(VBT5, 63, DIW1) + Name (DIWF, Package() { DIW1 }) + Return(DIWF) + } + + Method(FRID, 0, Serialized) + { + Name (DIR1, "") + ToString(VBT6, 63, DIR1) + Name (DIRF, Package() { DIR1 }) + Return (DIRF) + } + + Method(HWID, 0, Serialized) + { + Name (DIW0, "") + ToString(VBT4, 255, DIW0) + Name (DIWH, Package() { DIW0 }) + Return (DIWH) + } + + Method(BINF, 0, Serialized) + { + Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) + Return (FNIB) + } + + Method(GPIO, 0, Serialized) + { + Return (OIPG) + + } + + Method(VBNV, 0, Serialized) + { + Name(VNBV, Package() { + // See src/vendorcode/google/chromeos/Kconfig + // for the definition of these: + CONFIG_VBOOT_VBNV_OFFSET, + VBOOT_VBNV_BLOCK_SIZE + }) + Return(VNBV) + } + + Method(VDAT, 0, Serialized) + { + Name(TAD0,"") + ToBuffer(CHVD, TAD0) + Name (TADV, Package() { TAD0 }) + Return (TADV) + } + + Method(FMAP, 0, Serialized) + { + Name(PAMF, Package() { VBT9 }) + Return(PAMF) + } + + Method(MECK, 0, Serialized) + { + Name(HASH, Package() { MEHH }) + Return(HASH) + } + + Method(MLST, 0, Serialized) + { + Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", + "GPIO", "VBNV", "VDAT", "FMAP", "MECK" + }) + Return (TSLM) + } +} + +#include "ramoops.asl" + +#endif diff --git a/arch/x86/include/asm/acpi/cpu.asl b/arch/x86/include/asm/acpi/cpu.asl new file mode 100644 index 0000000000..b20b3572f2 --- /dev/null +++ b/arch/x86/include/asm/acpi/cpu.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) + +/* Notify OS to re-read CPU tables */ +Method (PNOT) +{ + \_PR.CNOT (0x81) +} + +/* Notify OS to re-read CPU _PPC limit */ +Method (PPCN) +{ + \_PR.CNOT (0x80) +} + +/* Notify OS to re-read Throttle Limit tables */ +Method (TNOT) +{ + \_PR.CNOT (0x82) +} diff --git a/arch/x86/include/asm/acpi/cros_ec/ac.asl b/arch/x86/include/asm/acpi/cros_ec/ac.asl new file mode 100644 index 0000000000..80e0ebd3ad --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR) + { + Return (ACEX) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/als.asl b/arch/x86/include/asm/acpi/cros_ec/als.asl new file mode 100644 index 0000000000..f3d40f889c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/als.asl @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Device (ALS) +{ + Name (_HID, "ACPI0008") + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + /* + * Returns the current ambient light illuminance reading in lux + * + * 0: Reading is below the range of sensitivity of the sensor + * -1: Reading is above the range or sensitivity of the sensor + */ + Method (_ALI, 0, NotSerialized) + { + Return (^^ALS0) + } + + /* + * Returns a recommended polling frequency in tenths of seconds + * + * 0: No need to poll, async notifications will indicate changes + */ + Name (_ALP, 10) + + /* + * Returns a package of packages where each tuple consists of a pair + * of integers mapping ambient light illuminance to display brightness. + * + * {<display luminance adjustment>, <ambient light illuminance>} + * + * Ambient light illuminance values are specified in lux. + * + * Display luminance adjustment values are relative percentages where + * 100 is no (0%) display brightness adjustment. Values <100 indicate + * negative adjustment (dimming) and values >100 indicate positive + * adjustment (brightening). + * + * This is currently unused by the Linux kernel ACPI ALS driver but + * is required by the ACPI specification so just define a basic two + * point response curve. + */ + Name (_ALR, Package () + { + Package () { 70, 30 }, // Min { -30% adjust at 30 lux } + Package () { 150, 1000 } // Max { +50% adjust at 1000 lux } + }) +} diff --git a/arch/x86/include/asm/acpi/cros_ec/battery.asl b/arch/x86/include/asm/acpi/cros_ec/battery.asl new file mode 100644 index 0000000000..f106088231 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/battery.asl @@ -0,0 +1,411 @@ +/*/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + */ + +// Scope (EC0) + +/* Mutex for EC battery index interface */ +Mutex (BATM, 0) + +// Wait for desired battery index to be presented in shared memory +// Arg0 = battery index +// Returns Zero on success, One on error. +Method (BTSW, 1) +{ +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (LEqual (BTIX, Arg0)) { + Return (Zero) + } + If (LGreaterEqual (Arg0, BTCN)) { + Return (One) + } + Store (Arg0, \_SB.PCI0.LPCB.EC0.BTID) + Store (5, Local0) // Timeout 5 msec + While (LNotEqual (BTIX, Arg0)) + { + Sleep (1) + Decrement (Local0) + If (LEqual (Local0, Zero)) + { + Return (One) + } + } +#else + If (LNotEqual (0, Arg0)) { + Return (One) + } +#endif + Return (Zero) +} + +// _STA implementation. +// Arg0 = battery index +Method (BSTA, 1, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Zero) + } + + If (And(Not(BTSW (Arg0)), BTEX)) { + Store (0x1F, Local0) + } Else { + Store (0x0F, Local0) + } + + Release (^BATM) + Return (Local0) +} + +// _BIF implementation. +// Arg0 = battery index +// Arg1 = PBIF +Method (BBIF, 2, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // Last Full Charge Capacity + Store (BTDF, Index (Arg1, 2)) + + // Design Voltage + Store (BTDV, Index (Arg1, 4)) + + // Design Capacity + Store (BTDA, Local0) + Store (Local0, Index (Arg1, 1)) + + // Design Capacity of Warning + Divide (Multiply (Local0, DWRN), 100, , Local2) + Store (Local2, Index (Arg1, 5)) + + // Design Capacity of Low + Divide (Multiply (Local0, DLOW), 100, , Local2) + Store (Local2, Index (Arg1, 6)) + + // Get battery info from mainboard + Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 9)) + Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 10)) + Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 12)) + + Release (^BATM) + Return (Arg1) +} + +// _BIX implementation. +// Arg0 = battery index +// Arg1 = PBIX +Method (BBIX, 2, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // Last Full Charge Capacity + Store (BTDF, Index (Arg1, 3)) + + // Design Voltage + Store (BTDV, Index (Arg1, 5)) + + // Design Capacity + Store (BTDA, Local0) + Store (Local0, Index (Arg1, 2)) + + // Design Capacity of Warning + Divide (Multiply (Local0, DWRN), 100, , Local2) + Store (Local2, Index (Arg1, 6)) + + // Design Capacity of Low + Divide (Multiply (Local0, DLOW), 100, , Local2) + Store (Local2, Index (Arg1, 7)) + + // Cycle Count + Store (BTCC, Index (Arg1, 8)) + + // Get battery info from mainboard + Store (ToString(Concatenate(BMOD, 0x00)), Index (Arg1, 16)) + Store (ToString(Concatenate(BSER, 0x00)), Index (Arg1, 17)) + Store (ToString(Concatenate(BMFG, 0x00)), Index (Arg1, 19)) + + Release (^BATM) + Return (Arg1) +} + +// _BST implementation. +// Arg0 = battery index +// Arg1 = PBST +// Arg2 = BSTP +// Arg3 = BFWK +Method (BBST, 4, Serialized) +{ + If (Acquire (^BATM, 1000)) { + Return (Arg1) + } + + If (BTSW (Arg0)) { + Release (^BATM) + Return (Arg1) + } + // + // 0: BATTERY STATE + // + // bit 0 = discharging + // bit 1 = charging + // bit 2 = critical level + // + Store (Zero, Local1) + + // Check if AC is present + If (ACEX) { + If (BFCG) { + Store (0x02, Local1) + } ElseIf (BFDC) { + Store (0x01, Local1) + } + } Else { + // Always discharging when on battery power + Store (0x01, Local1) + } + + // Check for critical battery level + If (BFCR) { + Or (Local1, 0x04, Local1) + } + Store (Local1, Index (Arg1, 0)) + + // Notify if battery state has changed since last time + If (LNotEqual (Local1, DeRefOf (Arg2))) { + Store (Local1, Arg2) + If (LEqual(Arg0, 0)) { + Notify (BAT0, 0x80) + } +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + Else { + Notify (BAT1, 0x80) + } +#endif + } + + // + // 1: BATTERY PRESENT RATE + // + Store (BTPR, Index (Arg1, 1)) + + // + // 2: BATTERY REMAINING CAPACITY + // + Store (BTRA, Local1) + If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) { + // On AC power and battery is neither charging + // nor discharging. Linux expects a full battery + // to report same capacity as last full charge. + // https://bugzilla.kernel.org/show_bug.cgi?id=12632 + Store (BTDF, Local2) + + // See if within ~6% of full + ShiftRight (Local2, 4, Local3) + If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), + LLess (Local1, Add (Local2, Local3)))) + { + Store (Local2, Local1) + } + } + Store (Local1, Index (Arg1, 2)) + + // + // 3: BATTERY PRESENT VOLTAGE + // + Store (BTVO, Index (Arg1, 3)) + + Release (^BATM) + Return (Arg1) +} + +Device (BAT0) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, // 0x00: Power Unit: mAh + 0xFFFFFFFF, // 0x01: Design Capacity + 0xFFFFFFFF, // 0x02: Last Full Charge Capacity + 0x00000001, // 0x03: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x04: Design Voltage + 0x00000003, // 0x05: Design Capacity of Warning + 0xFFFFFFFF, // 0x06: Design Capacity of Low + 0x00000001, // 0x07: Capacity Granularity 1 + 0x00000001, // 0x08: Capacity Granularity 2 + "", // 0x09: Model Number + "", // 0x0a: Serial Number + "LION", // 0x0b: Battery Type + "" // 0x0c: OEM Information + }) + + Name (PBIX, Package () { + 0x00000000, // 0x00: Revision + 0x00000001, // 0x01: Power Unit: mAh + 0xFFFFFFFF, // 0x02: Design Capacity + 0xFFFFFFFF, // 0x03: Last Full Charge Capacity + 0x00000001, // 0x04: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x05: Design Voltage + 0x00000003, // 0x06: Design Capacity of Warning + 0xFFFFFFFF, // 0x07: Design Capacity of Low + 0x00000000, // 0x08: Cycle Count + 0x00018000, // 0x09: Measurement Accuracy (98.3%?) + 0x000001F4, // 0x0a: Max Sampling Time (500ms) + 0x0000000a, // 0x0b: Min Sampling Time (10ms) + 0xFFFFFFFF, // 0x0c: Max Averaging Interval + 0xFFFFFFFF, // 0x0d: Min Averaging Interval + 0x00000001, // 0x0e: Capacity Granularity 1 + 0x00000001, // 0x0f: Capacity Granularity 2 + "", // 0x10 Model Number + "", // 0x11: Serial Number + "LION", // 0x12: Battery Type + "" // 0x13: OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // 0x00: Battery State + 0xFFFFFFFF, // 0x01: Battery Present Rate + 0xFFFFFFFF, // 0x02: Battery Remaining Capacity + 0xFFFFFFFF, // 0x03: Battery Present Voltage + }) + Name (BSTP, Zero) + + // Workaround for full battery status, disabled by default + Name (BFWK, Zero) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + Return (BSTA (0)) + } + + Method (_BIF, 0, Serialized) + { + Return (BBIF (0, PBIF)) + } + + Method (_BIX, 0, Serialized) + { + Return (BBIX (0, PBIX)) + } + + Method (_BST, 0, Serialized) + { + Return (BBST (0, PBST, RefOf (BSTP), BFWK)) + } +} + +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE +Device (BAT1) +{ + Name (_HID, EISAID ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, // 0x00: Power Unit: mAh + 0xFFFFFFFF, // 0x01: Design Capacity + 0xFFFFFFFF, // 0x02: Last Full Charge Capacity + 0x00000001, // 0x03: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x04: Design Voltage + 0x00000003, // 0x05: Design Capacity of Warning + 0xFFFFFFFF, // 0x06: Design Capacity of Low + 0x00000001, // 0x07: Capacity Granularity 1 + 0x00000001, // 0x08: Capacity Granularity 2 + "", // 0x09: Model Number + "", // 0x0a: Serial Number + "LION", // 0x0b: Battery Type + "" // 0x0c: OEM Information + }) + + Name (PBIX, Package () { + 0x00000000, // 0x00: Revision + 0x00000001, // 0x01: Power Unit: mAh + 0xFFFFFFFF, // 0x02: Design Capacity + 0xFFFFFFFF, // 0x03: Last Full Charge Capacity + 0x00000001, // 0x04: Battery Technology: Rechargeable + 0xFFFFFFFF, // 0x05: Design Voltage + 0x00000003, // 0x06: Design Capacity of Warning + 0xFFFFFFFF, // 0x07: Design Capacity of Low + 0x00000000, // 0x08: Cycle Count + 0x00018000, // 0x09: Measurement Accuracy (98.3%?) + 0x000001F4, // 0x0a: Max Sampling Time (500ms) + 0x0000000a, // 0x0b: Min Sampling Time (10ms) + 0xFFFFFFFF, // 0x0c: Max Averaging Interval + 0xFFFFFFFF, // 0x0d: Min Averaging Interval + 0x00000001, // 0x0e: Capacity Granularity 1 + 0x00000001, // 0x0f: Capacity Granularity 2 + "", // 0x10 Model Number + "", // 0x11: Serial Number + "LION", // 0x12: Battery Type + "" // 0x13: OEM Information + }) + + Name (PBST, Package () { + 0x00000000, // 0x00: Battery State + 0xFFFFFFFF, // 0x01: Battery Present Rate + 0xFFFFFFFF, // 0x02: Battery Remaining Capacity + 0xFFFFFFFF, // 0x03: Battery Present Voltage + }) + Name (BSTP, Zero) + + // Workaround for full battery status, disabled by default + Name (BFWK, Zero) + + // Method to enable full battery workaround + Method (BFWE) + { + Store (One, BFWK) + } + + // Method to disable full battery workaround + Method (BFWD) + { + Store (Zero, BFWK) + } + + Method (_STA, 0, Serialized) + { + Return (BSTA (1)) + } + + Method (_BIF, 0, Serialized) + { + Return (BBIF (1, PBIF)) + } + + Method (_BIX, 0, Serialized) + { + Return (BBIX (1, PBIX)) + } + + Method (_BST, 0, Serialized) + { + Return (BBST (1, PBST, RefOf (BSTP), BFWK)) + } +} +#endif diff --git a/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl new file mode 100644 index 0000000000..9f50185b70 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/cros_ec.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +Device (CREC) +{ + Name (_HID, "GOOG0004") + Name (_UID, 1) + Name (_DDN, "EC Command Device") +#ifdef EC_ENABLE_WAKE_PIN + Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) +#endif + +#ifdef EC_ENABLE_SYNC_IRQ + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive) + { + EC_SYNC_IRQ + } + }) +#endif + +#ifdef EC_ENABLE_SYNC_IRQ_GPIO + Name (_CRS, ResourceTemplate () + { + GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000, + "\\_SB.GPIO", 0x00, ResourceConsumer, ,) + { + EC_SYNC_IRQ + } + }) +#endif + +#ifdef EC_ENABLE_MKBP_DEVICE + Device (CKSC) + { + Name (_HID, "GOOG0007") + Name (_UID, 1) + Name (_DDN, "EC MKBP Device") + } +#endif + +#ifdef EC_ENABLE_CBAS_DEVICE + Device (CBAS) + { + Name (_HID, "GOOG000B") + Name (_UID, 1) + Name (_DDN, "EC Base Switch Device") + } +#endif + Method(_STA, 0) + { + Return (0xB) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/ec.asl b/arch/x86/include/asm/acpi/cros_ec/ec.asl new file mode 100644 index 0000000000..03f57f25a2 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/ec.asl @@ -0,0 +1,557 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +// Mainboard specific throttle handler +#ifdef DPTF_ENABLE_CHARGER +External (\_SB.DPTF.TCHG, DeviceObj) +#endif + + +Device (EC0) +{ + Name (_HID, EISAID ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_SCI_GPI) + Name (TOFS, EC_TEMP_SENSOR_OFFSET) + Name (TNCA, EC_TEMP_SENSOR_NOT_CALIBRATED) + Name (TNOP, EC_TEMP_SENSOR_NOT_POWERED) + Name (TBAD, EC_TEMP_SENSOR_ERROR) + Name (TNPR, EC_TEMP_SENSOR_NOT_PRESENT) + Name (DWRN, 15) // Battery capacity warning at 15% + Name (DLOW, 10) // Battery capacity low at 10% + + OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN) + Field (ERAM, ByteAcc, Lock, Preserve) + { + Offset (0x00), + RAMV, 8, // EC RAM Version + TSTB, 8, // Test Byte + TSTC, 8, // Complement of Test Byte + KBLV, 8, // Keyboard Backlight value + FAND, 8, // Set Fan Duty Cycle + PATI, 8, // Programmable Auxiliary Trip Sensor ID + PATT, 8, // Programmable Auxiliary Trip Threshold + PATC, 8, // Programmable Auxiliary Trip Commit + CHGL, 8, // Charger Current Limit + TBMD, 1, // Tablet mode + DDPN, 3, // Device DPTF Profile Number + // DFUD must be 0 for the other 31 values to be valid + Offset (0x0a), + DFUD, 1, // Device Features Undefined + FLSH, 1, // Flash commands present + PFAN, 1, // PWM Fan control present + KBLE, 1, // Keyboard Backlight present + LTBR, 1, // Lightbar present + LEDC, 1, // LED control + MTNS, 1, // Motion sensors present + KEYB, 1, // EC is keyboard controller + PSTR, 1, // Persistent storage + P80P, 1, // EC serves I/O Port 80h + THRM, 1, // EC supports thermal management + SBKL, 1, // Screen backlight switch present + WIFI, 1, // WIFI switch present + HOST, 1, // EC monitors host events (eg SCI, SMI) + GPIO, 1, // EC provides GPIO commands + I2CB, 1, // EC provides I2C controller access + CHRG, 1, // EC provides commands for charger control + BATT, 1, // Simply Battery support + SBAT, 1, // Smart Battery support + HANG, 1, // EC can detect host hang + PMUI, 1, // Power Information + DSEC, 1, // another EC exists downstream + UPDC, 1, // supports USB Power Delivery + UMUX, 1, // supports USB Mux + MSFF, 1, // Motion Sense has FIFO + TVST, 1, // supports temporary secure vstore + TCMV, 1, // USB Type C Muxing is virtual (host assisted) + RTCD, 1, // EC provides an RTC device + FPRD, 1, // EC provides a fingerprint reader device + TPAD, 1, // EC provides a touchpad device + RWSG, 1, // EC has RWSIG task enabled + DEVE, 1, // EC supports device events + // make sure we're within our space envelope + Offset (0x0e), + Offset (0x12), + BTID, 8, // Battery index that host wants to read + USPP, 8, // USB Port Power +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) + OperationRegion (EMEM, EmbeddedControl, + EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE) + Field (EMEM, ByteAcc, Lock, Preserve) +#else + OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) + Field (EMEM, ByteAcc, NoLock, Preserve) +#endif + { + #include "emem.asl" + } + +#ifdef EC_ENABLE_LID_SWITCH + /* LID Switch */ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (^^LIDS) + } + +#ifdef EC_ENABLE_WAKE_PIN + Name (_PRW, Package () { EC_ENABLE_WAKE_PIN, 0x5 }) +#endif + } +#endif + + Method (TINS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0) { Return (TIN0) } + Case (1) { Return (TIN1) } + Case (2) { Return (TIN2) } + Case (3) { Return (TIN3) } + Case (4) { Return (TIN4) } + Case (5) { Return (TIN5) } + Case (6) { Return (TIN6) } + Case (7) { Return (TIN7) } + Case (8) { Return (TIN8) } + Case (9) { Return (TIN9) } + Default { Return (TIN0) } + } + } + + Method (_CRS, 0, Serialized) + { + Name (ECMD, ResourceTemplate() + { + IO (Decode16, + EC_LPC_ADDR_ACPI_DATA, + EC_LPC_ADDR_ACPI_DATA, + 0, 1) + IO (Decode16, + EC_LPC_ADDR_ACPI_CMD, + EC_LPC_ADDR_ACPI_CMD, + 0, 1) + }) + Return (ECMD) + } + + Method (_REG, 2, NotSerialized) + { + // Initialize AC power state + Store (ACEX, \PWRS) + + // Initialize LID switch state + Store (LIDS, \LIDS) + } + + /* Read requested temperature and check against EC error values */ + Method (TSRD, 1, Serialized) + { + Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0) + + /* Check for sensor not calibrated */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (Zero) + } + + /* Check for sensor not present */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (Zero) + } + + /* Check for sensor not powered */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (Zero) + } + + /* Check for sensor bad reading */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (Zero) + } + + /* Adjust by offset to get Kelvin */ + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + /* Convert to 1/10 Kelvin */ + Multiply (Local0, 10, Local0) + + Return (Local0) + } + + // Lid Closed Event + Method (_Q01, 0, NotSerialized) + { + Store ("EC: LID CLOSE", Debug) + Store (LIDS, \LIDS) +#ifdef EC_ENABLE_LID_SWITCH + Notify (LID0, 0x80) +#endif + } + + // Lid Open Event + Method (_Q02, 0, NotSerialized) + { + Store ("EC: LID OPEN", Debug) + Store (LIDS, \LIDS) + Notify (CREC, 0x2) +#ifdef EC_ENABLE_LID_SWITCH + Notify (LID0, 0x80) +#endif + } + + // Power Button + Method (_Q03, 0, NotSerialized) + { + Store ("EC: POWER BUTTON", Debug) + } + + // AC Connected + Method (_Q04, 0, NotSerialized) + { + Store ("EC: AC CONNECTED", Debug) + Store (ACEX, \PWRS) + Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER + If (CondRefOf (\_SB.DPTF.TCHG)) { + Notify (\_SB.DPTF.TCHG, 0x80) + } +#endif + \PNOT () + } + + // AC Disconnected + Method (_Q05, 0, NotSerialized) + { + Store ("EC: AC DISCONNECTED", Debug) + Store (ACEX, \PWRS) + Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER + If (CondRefOf (\_SB.DPTF.TCHG)) { + Notify (\_SB.DPTF.TCHG, 0x80) + } +#endif + \PNOT () + } + + // Battery Low Event + Method (_Q06, 0, NotSerialized) + { + Store ("EC: BATTERY LOW", Debug) + Notify (BAT0, 0x80) + } + + // Battery Critical Event + Method (_Q07, 0, NotSerialized) + { + Store ("EC: BATTERY CRITICAL", Debug) + Notify (BAT0, 0x80) + } + + // Battery Info Event + Method (_Q08, 0, NotSerialized) + { + Store ("EC: BATTERY INFO", Debug) + Notify (BAT0, 0x81) +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (CondRefOf (BAT1)) { + Notify (BAT1, 0x81) + } +#endif + } + + // Thermal Overload Event + Method (_Q0A, 0, NotSerialized) + { + Store ("EC: THERMAL OVERLOAD", Debug) + Notify (\_TZ, 0x80) + } + + // Thermal Event + Method (_Q0B, 0, NotSerialized) + { + Store ("EC: THERMAL", Debug) + Notify (\_TZ, 0x80) + } + + // USB Charger + Method (_Q0C, 0, NotSerialized) + { + Store ("EC: USB CHARGER", Debug) + } + + // Key Pressed + Method (_Q0D, 0, NotSerialized) + { + Store ("EC: KEY PRESSED", Debug) + Notify (CREC, 0x2) + } + + // Thermal Shutdown Imminent + Method (_Q10, 0, NotSerialized) + { + Store ("EC: THERMAL SHUTDOWN", Debug) + Notify (\_TZ, 0x80) + } + + // Battery Shutdown Imminent + Method (_Q11, 0, NotSerialized) + { + Store ("EC: BATTERY SHUTDOWN", Debug) + Notify (BAT0, 0x80) + } + + // Throttle Start + Method (_Q12, 0, NotSerialized) + { +#ifdef EC_ENABLE_THROTTLING_HANDLER + Store ("EC: THROTTLE START", Debug) + \_TZ.THRT (1) +#endif + } + + // Throttle Stop + Method (_Q13, 0, NotSerialized) + { +#ifdef EC_ENABLE_THROTTLING_HANDLER + Store ("EC: THROTTLE STOP", Debug) + \_TZ.THRT (0) +#endif + } + +#ifdef EC_ENABLE_PD_MCU_DEVICE + // PD event + Method (_Q16, 0, NotSerialized) + { + Store ("EC: GOT PD EVENT", Debug) + Notify (ECPD, 0x80) + } +#endif + + // Battery Status + Method (_Q17, 0, NotSerialized) + { + Store ("EC: BATTERY STATUS", Debug) + Notify (BAT0, 0x80) +#ifdef EC_ENABLE_SECOND_BATTERY_DEVICE + If (CondRefOf (BAT1)) { + Notify (BAT1, 0x80) + } +#endif + } + + // MKBP interrupt. + Method (_Q1B, 0, NotSerialized) + { + Store ("EC: MKBP", Debug) + Notify (CREC, 0x80) + } + + // TABLET mode switch Event + Method (_Q1D, 0, NotSerialized) + { + Store ("EC: TABLET mode switch Event", Debug) + Notify (CREC, 0x2) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + \_SB.DPTF.TPET() +#endif +#ifdef EC_ENABLE_TBMC_DEVICE + Notify (TBMC, 0x80) +#endif + } + + /* + * Dynamic Platform Thermal Framework support + */ + + /* Mutex for EC PAT interface */ + Mutex (PATM, 1) + + /* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT0, 2, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + Store (ToInteger (Arg0), ^PATI) + + /* Temperature is passed in 1/10 Kelvin */ + Divide (ToInteger (Arg1), 10, , Local1) + + /* Adjust by EC temperature offset */ + Subtract (Local1, ^TOFS, ^PATT) + + /* Set commit value with SELECT=0 and ENABLE=1 */ + Store (0x02, ^PATC) + + Release (^PATM) + Return (1) + } + + /* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT1, 2, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + Store (ToInteger (Arg0), ^PATI) + + /* Temperature is passed in 1/10 Kelvin */ + Divide (ToInteger (Arg1), 10, , Local1) + + /* Adjust by EC temperature offset */ + Subtract (Local1, ^TOFS, ^PATT) + + /* Set commit value with SELECT=1 and ENABLE=1 */ + Store (0x03, ^PATC) + + Release (^PATM) + Return (1) + } + + /* Disable Aux Trip Points + * Arg0 = Temp Sensor ID + */ + Method (PATD, 1, Serialized) + { + If (Acquire (^PATM, 1000)) { + Return (0) + } + + Store (ToInteger (Arg0), ^PATI) + Store (0x00, ^PATT) + + /* Disable PAT0 */ + Store (0x00, ^PATC) + + /* Disable PAT1 */ + Store (0x01, ^PATC) + + Release (^PATM) + Return (1) + } + + /* + * Thermal Threshold Event + */ + Method (_Q09, 0, NotSerialized) + { + If (LNot(Acquire (^PATM, 1000))) { + /* Read sensor ID for event */ + Store (^PATI, Local0) + + /* When sensor ID returns 0xFF then no more events */ + While (LNotEqual (Local0, EC_TEMP_SENSOR_NOT_PRESENT)) + { +#ifdef HAVE_THERM_EVENT_HANDLER + \_SB.DPTF.TEVT (Local0) +#endif + + /* Keep reaading sensor ID for event */ + Store (^PATI, Local0) + } + + Release (^PATM) + } + } + + /* + * Set Charger Current Limit + * Arg0 = Current Limit in 64mA steps + */ + Method (CHGS, 1, Serialized) + { + Store (ToInteger (Arg0), ^CHGL) + } + + /* + * Disable Charger Current Limit + */ + Method (CHGD, 0, Serialized) + { + Store (0xFF, ^CHGL) + } + + /* Read current Tablet mode */ + Method (RCTM, 0, NotSerialized) + { + Return (^TBMD) + } + + /* Read current Device DPTF Profile Number */ + Method (RCDP, 0, NotSerialized) + { + /* + * DDPN = 0 is reserved for backwards compatibility. + * If DDPN == 0 use TBMD to load appropriate DPTF table. + */ + If (LEqual (^DDPN, 0)) { + Return (^TBMD) + } Else { + Subtract (^DDPN, 1, Local0) + Return (Local0) + } + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER) + /* + * Enable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPS, 1, Serialized) + { + Or (USPP, ShiftLeft (1, Arg0), USPP) + } + + /* + * Disable USB Port Power + * Arg0 = USB port ID + */ + Method (UPPC, 1, Serialized) + { + And (USPP, Not (ShiftLeft (1, Arg0)), USPP) + } +#endif + + #include "ac.asl" + #include "battery.asl" + #include "cros_ec.asl" + +#ifdef EC_ENABLE_ALS_DEVICE + #include "als.asl" +#endif + +#ifdef EC_ENABLE_KEYBOARD_BACKLIGHT + #include "keyboard_backlight.asl" +#endif + +#ifdef EC_ENABLE_PD_MCU_DEVICE + #include "pd.asl" +#endif + +#ifdef EC_ENABLE_TBMC_DEVICE + #include "tbmc.asl" +#endif +} diff --git a/arch/x86/include/asm/acpi/cros_ec/emem.asl b/arch/x86/include/asm/acpi/cros_ec/emem.asl new file mode 100644 index 0000000000..681ca1c9de --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/emem.asl @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2015 The Chromium OS Authors. All rights reserved. + */ + +/* + * EMEM data may be accessed through port 62/66 or through LPC at 900h. + */ + +Offset (0x00), +TIN0, 8, // Temperature 0 +TIN1, 8, // Temperature 1 +TIN2, 8, // Temperature 2 +TIN3, 8, // Temperature 3 +TIN4, 8, // Temperature 4 +TIN5, 8, // Temperature 5 +TIN6, 8, // Temperature 6 +TIN7, 8, // Temperature 7 +TIN8, 8, // Temperature 8 +TIN9, 8, // Temperature 9 +Offset (0x10), +FAN0, 16, // Fan Speed 0 +Offset (0x24), +BTVR, 8, // Battery structure version +Offset (0x30), +LIDS, 1, // Lid Switch State +PBTN, 1, // Power Button Pressed +WPDI, 1, // Write Protect Disabled +RECK, 1, // Keyboard Initiated Recovery +RECD, 1, // Dedicated Recovery Mode +Offset (0x40), +BTVO, 32, // Battery Present Voltage +BTPR, 32, // Battery Present Rate +BTRA, 32, // Battery Remaining Capacity +ACEX, 1, // AC Present +BTEX, 1, // Battery Present +BFDC, 1, // Battery Discharging +BFCG, 1, // Battery Charging +BFCR, 1, // Battery Level Critical +Offset (0x4d), +BTCN, 8, // Battery Count +BTIX, 8, // Battery index +Offset (0x50), +BTDA, 32, // Battery Design Capacity +BTDV, 32, // Battery Design Voltage +BTDF, 32, // Battery Last Full Charge Capacity +BTCC, 32, // Battery Cycle Count +BMFG, 64, // Battery Manufacturer String +BMOD, 64, // Battery Model String +BSER, 64, // Battery Serial String +BTYP, 64, // Battery Type String +Offset (0x80), +ALS0, 16, // ALS reading 0 in lux diff --git a/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl new file mode 100644 index 0000000000..e6edd9680c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/keyboard_backlight.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Google Inc. + */ + +Scope (\_SB) +{ + /* + * Chrome EC Keyboard Backlight interface + */ + Device (KBLT) + { + Name (_HID, "GOOG0002") + Name (_UID, 1) + + /* Ask EC if we even have a backlight + * Return 0xf (present, enabled, show in UI, functioning) or 0 + * + * With older EC codebases that don't support the Device + * Features bitfield, this reports the keyboard backlight as + * enabled since reads to undefined addresses in EC address + * space return 0xff and so KBLE will be 1. + */ + Method (_STA, 0, NotSerialized) + { + /* If query is unsupported, but this code is compiled + * in, assume the backlight exists physically. + */ + If (LEqual (1, \_SB.PCI0.LPCB.EC0.DFUD)) { + Return (0xf) + } + /* If EC reports that backlight exists, trust it */ + If (LEqual (1, \_SB.PCI0.LPCB.EC0.KBLE)) { + Return (0xf) + } + /* Otherwise: no device -> disable */ + Return (0) + } + + /* Read current backlight value */ + Method (KBQC, 0, NotSerialized) + { + Return (\_SB.PCI0.LPCB.EC0.KBLV) + } + + /* Write new backlight value */ + Method (KBCM, 1, NotSerialized) + { + Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV) + } + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/pd.asl b/arch/x86/include/asm/acpi/cros_ec/pd.asl new file mode 100644 index 0000000000..e55fde347c --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/pd.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Device (ECPD) +{ + Name (_HID, "GOOG0003") + Name (_UID, 1) + Name (_DDN, "EC PD Device") + Method(_STA, 0) + { + Return (0xB) + } +} diff --git a/arch/x86/include/asm/acpi/cros_ec/superio.asl b/arch/x86/include/asm/acpi/cros_ec/superio.asl new file mode 100644 index 0000000000..7ddab1e3cf --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/superio.asl @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. + */ + +/* + * Chrome OS Embedded Controller interface + * + * Constants that should be defined: + * + * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources + * EC_LPC_ADDR_MEMMAP : Base address of memory map range + * EC_MEMMAP_SIZE : Size of memory map range + * + * SIO_EC_HOST_ENABLE : Enable EC host command interface resources + * EC_LPC_ADDR_HOST_DATA : EC host command interface data port + * EC_LPC_ADDR_HOST_CMD : EC host command interface command port + * EC_HOST_CMD_REGION0 : EC host command buffer + * EC_HOST_CMD_REGION1 : EC host command buffer + * EC_HOST_CMD_REGION_SIZE : EC host command buffer size + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) { + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_MEMMAP_ENABLE + Device (ECMM) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 4) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, + 0x08, EC_MEMMAP_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + IO (Decode16, EC_LPC_ADDR_MEMMAP, EC_LPC_ADDR_MEMMAP, + 0x08, EC_MEMMAP_SIZE) + }) + } +#endif + +#ifdef SIO_EC_HOST_ENABLE + Device (ECUI) { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 3) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + EC_LPC_ADDR_HOST_DATA, EC_LPC_ADDR_HOST_DATA, + 0x01, 0x01) + IO (Decode16, + EC_LPC_ADDR_HOST_CMD, EC_LPC_ADDR_HOST_CMD, + 0x01, 0x01) + IO (Decode16, + EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, 0x08, + EC_HOST_CMD_REGION_SIZE) + IO (Decode16, + EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, 0x08, + EC_HOST_CMD_REGION_SIZE) + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, EC_LPC_ADDR_HOST_DATA, + EC_LPC_ADDR_HOST_DATA, 0x01, 0x01) + IO (Decode16, EC_LPC_ADDR_HOST_CMD, + EC_LPC_ADDR_HOST_CMD, 0x01, 0x01) + IO (Decode16, + EC_HOST_CMD_REGION0, EC_HOST_CMD_REGION0, + 0x08, EC_HOST_CMD_REGION_SIZE) + IO (Decode16, + EC_HOST_CMD_REGION1, EC_HOST_CMD_REGION1, + 0x08, EC_HOST_CMD_REGION_SIZE) + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_EC_ENABLE_COM1 + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } +#endif +} + +#ifdef SIO_EC_ENABLE_PS2K +Device (PS2K) // Keyboard +{ + Name (_UID, 0) + Name (_HID, "GOOG000A") + Name (_CID, Package() { EISAID("PNP0303"), EISAID("PNP030B") } ) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) +#ifdef SIO_EC_PS2K_IRQ + SIO_EC_PS2K_IRQ +#else + IRQ (Edge, ActiveHigh, Exclusive) {1} +#endif + } + EndDependentFn () + }) +} +#endif diff --git a/arch/x86/include/asm/acpi/cros_ec/tbmc.asl b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl new file mode 100644 index 0000000000..bfe38d668e --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_ec/tbmc.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2017 Google Inc. + */ + +Device (TBMC) +{ + Name (_HID, "GOOG0006") + Name (_UID, 1) + Name (_DDN, "Tablet Motion Control") + Method (TBMC) + { + If (LEqual (^^RCTM, One)) { + Return (0x1) + } Else { + Return (0x0) + } + } + Method(_STA, 0) + { + Return (0xB) + } +} diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl b/arch/x86/include/asm/acpi/cros_gnvs.asl new file mode 100644 index 0000000000..c20b64565e --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_gnvs.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +/* This is the ChromeOS specific ACPI information needed by + * the mainboard's chromeos.asl + */ + +VBT0, 32, // 0x000 - Boot Reason +VBT1, 32, // 0x004 - Active Main Firmware +VBT2, 32, // 0x008 - Active EC Firmware +VBT3, 16, // 0x00c - CHSW +VBT4, 2048, // 0x00e - HWID +VBT5, 512, // 0x10e - FWID +VBT6, 512, // 0x14e - FRID +VBT7, 32, // 0x18e - active main firmware type +VBT8, 32, // 0x192 - Recovery Reason +VBT9, 32, // 0x196 - FMAP base address +CHVD, 24576, // 0x19a - VDAT space filled by verified boot +VBTA, 32, // 0xd9a - pointer to smbios FWID +MEHH, 256, // 0xd9e - Management Engine Hash +RMOB, 32, // 0xdbe - RAM oops base address +RMOL, 32, // 0xdc2 - RAM oops length +ROVP, 32, // 0xdc6 - pointer to RO_VPD +ROVL, 32, // 0xdca - size of RO_VPD +RWVP, 32, // 0xdce - pointer to RW_VPD +RWVL, 32, // 0xdd2 - size of RW_VPD + // 0xdd6 diff --git a/arch/x86/include/asm/acpi/dptf/charger.asl b/arch/x86/include/asm/acpi/dptf/charger.asl new file mode 100644 index 0000000000..7f4a7ecd36 --- /dev/null +++ b/arch/x86/include/asm/acpi/dptf/charger.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + */ + +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Return charger performance states defined by mainboard */ + Method (PPSS) + { + Return (\_SB.CHPS) + } + + /* Return maximum charger current limit */ + Method (PPPC) + { + /* Convert size of PPSS table to index */ + Store (SizeOf (\_SB.CHPS), Local0) + Decrement (Local0) + + /* Check if charging is disabled (AC removed) */ + If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + /* Return last power state */ + Return (Local0) + } Else { + /* Return highest power state */ + Return (0) + } + + Return (0) + } + + /* Set charger current limit */ + Method (SPPC, 1) + { + /* Retrieve Control (index 4) for specified PPSS level */ + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + + /* Pass Control value to EC to limit charging */ + \_SB.PCI0.LPCB.EC0.CHGS (Local0) + } + + /* Initialize charger participant */ + Method (INIT) + { + /* Disable charge limit */ + \_SB.PCI0.LPCB.EC0.CHGD () + } +} diff --git a/arch/x86/include/asm/acpi/dptf/cpu.asl b/arch/x86/include/asm/acpi/dptf/cpu.asl new file mode 100644 index 0000000000..f77d353838 --- /dev/null +++ b/arch/x86/include/asm/acpi/dptf/cpu.asl @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + */ + +External (\_PR.CP00._PSS, PkgObj) +External (\_PR.CP00._TSS, PkgObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_SB.MPDL, IntObj) + +Device (DPTF_CPU_DEVICE) +{ + Name(_ADR, DPTF_CPU_ADDR) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + Return (0) + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + + Method (_PDL) + { + /* Check for mainboard specific _PDL override */ + If (CondRefOf (\_SB.MPDL)) { + Return (\_SB.MPDL) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* Return PPCC table defined by mainboard */ + Method (PPCC) + { + Return (\_SB.MPPC) + } + +#ifdef DPTF_CPU_CRITICAL + Method (_CRT) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL)) + } +#endif + +#ifdef DPTF_CPU_PASSIVE + Method (_PSV) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4)) + } +#endif +} diff --git a/arch/x86/include/asm/acpi/dptf/dptf.asl b/arch/x86/include/asm/acpi/dptf/dptf.asl new file mode 100644 index 0000000000..5f958d200b --- /dev/null +++ b/arch/x86/include/asm/acpi/dptf/dptf.asl @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + */ + +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* DPPM Active Policy */ + ToUUID ("3A95C389-E4B8-4629-A526-C52C88626BAE"), +#endif + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Arg0: Buffer containing UUID + * Arg1: Integer containing Revision ID of buffer format + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + Method (_OSC, 4, Serialized) + { + /* Check for Passive Policy UUID */ + If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + /* Initialize Thermal Devices */ + ^TINI () + +#ifdef DPTF_ENABLE_CHARGER + /* Initialize Charger Device */ + ^TCHG.INIT () +#endif + } + + Return (Arg3) + } + + /* Priority based _TRT */ + Name (TRTR, 1) + + Method (_TRT) + { + Return (\_SB.DTRT) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* _ART : Active Cooling Relationship Table */ + Method (_ART) + { + Return (\_SB.DART) + } +#endif + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Convert from 1/10 Kelvin to Degrees C for ACPI */ + Method (KTOC, 1) { + If (LLessEqual (Arg0, 2732)) { + Return (0) + } + + /* Convert to Celsius */ + Subtract (Arg0, 2732, Local0) + + /* Convert from 10th of degrees */ + Divide (Local0, 10,, Local0) + + Return (Local0) + } + + /* Include Thermal Participants */ + #include "thermal.asl" + +#ifdef DPTF_ENABLE_CHARGER + /* Include Charger Participant */ + #include "charger.asl" +#endif + +#ifdef DPTF_ENABLE_FAN_CONTROL + /* Include Fan Participant */ + #include "fan.asl" +#endif + +} + +Scope (\_SB.PCI0) +{ + #include "cpu.asl" +} diff --git a/arch/x86/include/asm/acpi/dptf/fan.asl b/arch/x86/include/asm/acpi/dptf/fan.asl new file mode 100644 index 0000000000..aa4aa12911 --- /dev/null +++ b/arch/x86/include/asm/acpi/dptf/fan.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +Device (TFN1) +{ + Name (_HID, "INT3404") + Name (_UID, 0) + Name (_STR, Unicode("Fan Control")) + + /* _FIF: Fan Information */ + Name (_FIF, Package () + { + 0, // Revision + 1, // Fine Grained Control + 2, // Step Size + 0 // No Low Speed Notification + }) + + /* Return Fan Performance States defined by mainboard */ + Method (_FPS) + { + Return (\_SB.DFPS) + } + + Name (TFST, Package () + { + 0, // Revision + 0x00, // Control + 0x00 // Speed + }) + + /* _FST: Fan current Status */ + Method (_FST, 0, Serialized,,PkgObj) + { + /* Fill in TFST with current control. */ + Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + Return (TFST) + } + + /* _FSL: Fan Speed Level */ + Method (_FSL, 1, Serialized) + { + Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND) + } + + Method (_STA) + { + If (LEqual (\DPTE, One)) + { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/arch/x86/include/asm/acpi/dptf/thermal.asl b/arch/x86/include/asm/acpi/dptf/thermal.asl new file mode 100644 index 0000000000..4c3c8db8f2 --- /dev/null +++ b/arch/x86/include/asm/acpi/dptf/thermal.asl @@ -0,0 +1,521 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + */ + +/* Thermal Threshold Event Handler */ +#define HAVE_THERM_EVENT_HANDLER +Method (TEVT, 1, NotSerialized) +{ + Store (ToInteger (Arg0), Local0) + +#ifdef DPTF_TSR0_SENSOR_ID + If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + Notify (^TSR0, 0x90) + } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + Notify (^TSR1, 0x90) + } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + Notify (^TSR2, 0x90) + } +#endif +#ifdef DPTF_TSR3_SENSOR_ID + If (LEqual (Local0, DPTF_TSR3_SENSOR_ID)) { + Notify (^TSR3, 0x90) + } +#endif +} + +/* Thermal device initialization - Disable Aux Trip Points */ +Method (TINI) +{ +#ifdef DPTF_TSR0_SENSOR_ID + ^TSR0.PATD () +#endif +#ifdef DPTF_TSR1_SENSOR_ID + ^TSR1.PATD () +#endif +#ifdef DPTF_TSR2_SENSOR_ID + ^TSR2.PATD () +#endif +#ifdef DPTF_TSR3_SENSOR_ID + ^TSR3.PATD () +#endif +} + +/* Thermal Trip Points Change Event Handler */ +Method (TPET) +{ +#ifdef DPTF_TSR0_SENSOR_ID + Notify (^TSR0, 0x81) +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Notify (^TSR1, 0x81) +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Notify (^TSR2, 0x81) +#endif +#ifdef DPTF_TSR3_SENSOR_ID + Notify (^TSR3, 0x81) +#endif +} + +/* + * Method to return trip temperature value depending upon the device mode. + * Arg0 --> Value to return when device is in tablet mode + * Arg1 --> Value to return when device is not in tablet mode. + */ +Method (DTRP, 2, Serialized) +{ +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) { + Return (CTOK (Arg0)) + } Else { +#endif + Return (CTOK (Arg1)) +#ifdef EC_ENABLE_MULTIPLE_DPTF_PROFILES + } +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID + +#ifndef DPTF_TSR0_TABLET_PASSIVE +#define DPTF_TSR0_TABLET_PASSIVE DPTF_TSR0_PASSIVE +#endif +#ifndef DPTF_TSR0_TABLET_CRITICAL +#define DPTF_TSR0_TABLET_CRITICAL DPTF_TSR0_CRITICAL +#endif + +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (DTRP (DPTF_TSR0_TABLET_PASSIVE, DPTF_TSR0_PASSIVE)) + } + + Method (_CRT) + { + Return (DTRP (DPTF_TSR0_TABLET_CRITICAL, DPTF_TSR0_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR0_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif +#endif +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID + +#ifndef DPTF_TSR1_TABLET_PASSIVE +#define DPTF_TSR1_TABLET_PASSIVE DPTF_TSR1_PASSIVE +#endif +#ifndef DPTF_TSR1_TABLET_CRITICAL +#define DPTF_TSR1_TABLET_CRITICAL DPTF_TSR1_CRITICAL +#endif + +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (DTRP (DPTF_TSR1_TABLET_PASSIVE, DPTF_TSR1_PASSIVE)) + } + + Method (_CRT) + { + Return (DTRP (DPTF_TSR1_TABLET_CRITICAL, DPTF_TSR1_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR1_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC6)) + } +#endif +#endif +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID + +#ifndef DPTF_TSR2_TABLET_PASSIVE +#define DPTF_TSR2_TABLET_PASSIVE DPTF_TSR2_PASSIVE +#endif +#ifndef DPTF_TSR2_TABLET_CRITICAL +#define DPTF_TSR2_TABLET_CRITICAL DPTF_TSR2_CRITICAL +#endif + +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (DTRP (DPTF_TSR2_TABLET_PASSIVE, DPTF_TSR2_PASSIVE)) + } + + Method (_CRT) + { + Return (DTRP (DPTF_TSR2_TABLET_CRITICAL, DPTF_TSR2_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR2_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR2_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR2_ACTIVE_AC6)) + } +#endif +#endif +} +#endif + +#ifdef DPTF_TSR3_SENSOR_ID + +#ifndef DPTF_TSR3_TABLET_PASSIVE +#define DPTF_TSR3_TABLET_PASSIVE DPTF_TSR3_PASSIVE +#endif +#ifndef DPTF_TSR3_TABLET_CRITICAL +#define DPTF_TSR3_TABLET_CRITICAL DPTF_TSR3_CRITICAL +#endif + +Device (TSR3) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 4) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR3_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR3_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (DTRP (DPTF_TSR3_TABLET_PASSIVE, DPTF_TSR3_PASSIVE)) + } + + Method (_CRT) + { + Return (DTRP (DPTF_TSR3_TABLET_CRITICAL, DPTF_TSR3_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR3_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR3_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR3_ACTIVE_AC6)) + } +#endif +#endif +} +#endif diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h index d56d35ca53..46383629cc 100644 --- a/arch/x86/include/asm/acpi/global_nvs.h +++ b/arch/x86/include/asm/acpi/global_nvs.h @@ -11,8 +11,11 @@ * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file * to declare the GNVS OperationRegion, as well as write_acpi_tables() * for the GNVS address runtime fix up. + * + * If using CONFIG_ACPI_GNVS_EXTERNAL, we don't need to locate the GNVS in + * DSDT, since it is created by code, so ACPI_GNVS_ADDR is unused. */ #define ACPI_GNVS_ADDR 0xdeadbeef -#define ACPI_GNVS_SIZE 0x100 +#define ACPI_GNVS_SIZE 0x1000 #endif /* _ACPI_GNVS_H_ */ diff --git a/arch/x86/include/asm/acpi/lpc.asl b/arch/x86/include/asm/acpi/lpc.asl new file mode 100644 index 0000000000..18cc78b3e1 --- /dev/null +++ b/arch/x86/include/asm/acpi/lpc.asl @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + */ + +/* Intel LPC/eSPI Bus Device - 0:1f.0 */ +#include <asm/arch/iomap.h> + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) + Name (_DDN, "LPC Bus Device") + + /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ + Device (FWH) + { + Name (_HID, EISAID ("INT0800")) + Name (_DDN, "Firmware Hub") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) + }) + } + + /* High Precision Event Timer */ + Device (HPET) + { + Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) + Name (_DDN, "High Precision Event Timer") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + Method (_STA, 0) + { + Return (0xF) + } + } + + /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ + Device (PIC) + { + Name (_HID, EISAID ("PNP0000")) + Name (_DDN, "8259 Interrupt Controller") + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + /* LPC device: Resource consumption */ + Device (LDRC) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 2) + Name (_DDN, "Legacy Device Resources") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, + 0x1, 0xff) + }) + } + + /* Real Time Clock Device */ + Device (RTC) + { + Name (_HID, EISAID ("PNP0B00")) + Name (_DDN, "Real Time Clock") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + /* Timer */ + Device (TIMR) + { + Name (_HID, EISAID ("PNP0100")) + Name (_DDN, "8254 Timer") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags () {0} + }) + } +} diff --git a/arch/x86/include/asm/acpi/pci_osc.asl b/arch/x86/include/asm/acpi/pci_osc.asl new file mode 100644 index 0000000000..864556fa83 --- /dev/null +++ b/arch/x86/include/asm/acpi/pci_osc.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corp. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +} diff --git a/arch/x86/include/asm/acpi/pcr.asl b/arch/x86/include/asm/acpi/pcr.asl new file mode 100644 index 0000000000..f66737b89c --- /dev/null +++ b/arch/x86/include/asm/acpi/pcr.asl @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation. + */ + +#include <intelblocks/pcr.h> + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (Add (IOMAP_P2SB_BAR, + ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + And (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Or (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} diff --git a/arch/x86/include/asm/acpi/ramoops.asl b/arch/x86/include/asm/acpi/ramoops.asl new file mode 100644 index 0000000000..55939e1aa3 --- /dev/null +++ b/arch/x86/include/asm/acpi/ramoops.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Scope (\_SB) +{ + Device(RMOP) + { + Name (_HID, "GOOG9999") + Name (_CID, "GOOG9999") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, MRES) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^MRES._BAS, RBAS) + CreateDwordField (^RBUF, ^MRES._LEN, RLEN) + Store (\RMOB, RBAS) + Store (\RMOL, RLEN) + Return (^RBUF) + } + Method(_STA, 0) + { + Return (0xB) + } + } +} diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl index 32e16a2c2f..31aa69a570 100644 --- a/arch/x86/include/asm/acpi/sleepstates.asl +++ b/arch/x86/include/asm/acpi/sleepstates.asl @@ -6,9 +6,11 @@ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl */ -Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) -#ifdef CONFIG_HAVE_ACPI_RESUME -Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +#else +Name(\_S3, Package(){0x5,0x0,0x0,0x0}) #endif -Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) -Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) +Name(\_S4, Package(){0x6,0x0,0x0,0x0}) +Name(\_S5, Package(){0x7,0x0,0x0,0x0}) diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 733085c178..1b49ccadc0 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -9,6 +9,8 @@ #ifndef __ASM_ACPI_TABLE_H__ #define __ASM_ACPI_TABLE_H__ +#ifndef __ACPI__ + struct acpi_facs; struct acpi_fadt; struct acpi_global_nvs; @@ -37,6 +39,27 @@ u32 acpi_fill_mcfg(u32 current); u32 acpi_fill_csrt(u32 current); /** + * acpi_write_hpet() - Write out a HPET table + * + * Write out the table for High-Precision Event Timers + * + * @ctx: Current ACPI context + * @return 0 if OK, -ve on error + */ +int acpi_write_hpet(struct acpi_ctx *ctx); + +/** + * acpi_write_dbg2_pci_uart() - Write out a DBG2 table + * + * @ctx: Current ACPI context + * @dev: Debug UART device to describe + * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS) + * @return 0 if OK, -ve on error + */ +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size); + +/** * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table * * @gnvs: Table to fill in @@ -55,4 +78,143 @@ ulong write_acpi_tables(ulong start); */ ulong acpi_get_rsdp_addr(void); +/** + * arch_read_sci_irq_select() - Read the system-control interrupt number + * + * @returns value of IRQ register in the PMC + */ +int arch_read_sci_irq_select(void); + +/** + * arch_write_sci_irq_select() - Set the system-control interrupt number + * + * @scis: New value for IRQ register in the PMC + */ +int arch_write_sci_irq_select(uint scis); + +/** + * arch_madt_sci_irq_polarity() - Return the priority to use for the MADT + * + * @sci: System-control interrupt number + * @return priority to use (MP_IRQ_POLARITY_...) + */ +int arch_madt_sci_irq_polarity(int sci); + +/** + * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU + * + * See here for the specification + * https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf + * + * @ctx: ACPI context pointer + * @flags: (DRHD_INCLUDE_...) + * @segment: PCI segment asscociated with this unit + * @bar: Base address of remapping hardware register-set for this unit + */ +void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment, + u64 bar); + +/** + * acpi_create_dmar_rmrr() - Set up an RMRR + * + * This sets up a Reserved-Memory Region Reporting structure, used to allow + * DMA to regions used by devices that the BIOS controls. + * + * @ctx: ACPI context pointer + * @segment: PCI segment asscociated with this unit + * @bar: Base address of mapping + * @limit: End address of mapping + */ +void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar, + u64 limit); + +/** + * acpi_dmar_drhd_fixup() - Set the length of an DRHD + * + * This sets the DRHD length field based on the current ctx->current + * + * @ctx: ACPI context pointer + * @base: Address of the start of the DRHD + */ +void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base); + +/** + * acpi_dmar_rmrr_fixup() - Set the length of an RMRR + * + * This sets the RMRR length field based on the current ctx->current + * + * @ctx: ACPI context pointer + * @base: Address of the start of the RMRR + */ +void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base); + +/** + * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device + * + * @ctx: ACPI context pointer + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge + * + * This is used to provide a mapping for a PCI bridge + * + * @ctx: ACPI context pointer + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device + * + * @ctx: ACPI context pointer + * @enumeration_id: Enumeration ID (typically 2) + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET + * + * Sets up a scope for a High-Precision Event Timer that supports + * Message-Signalled Interrupts + * + * @ctx: ACPI context pointer + * @enumeration_id: Enumeration ID (typically 0) + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf); + +/** + * acpi_fadt_common() - Handle common parts of filling out an FADT + * + * This sets up the Fixed ACPI Description Table + * + * @fadt: Pointer to place to put FADT + * @facs: Pointer to the FACS + * @dsdt: Pointer to the DSDT + */ +void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt); + +/** + * intel_acpi_fill_fadt() - Set up the contents of the FADT + * + * This sets up parts of the Fixed ACPI Description Table that are common to + * Intel chips + * + * @fadt: Pointer to place to put FADT + */ +void intel_acpi_fill_fadt(struct acpi_fadt *fadt); + +#endif /* !__ACPI__ */ + #endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/x86/include/asm/acpigen.h b/arch/x86/include/asm/acpigen.h new file mode 100644 index 0000000000..c531dd61d5 --- /dev/null +++ b/arch/x86/include/asm/acpigen.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Generation of x86-specific ACPI tables + * + * Copyright 2020 Google LLC + */ + +#ifndef __ASM_ACPIGEN_H__ +#define __ASM_ACPIGEN_H__ + +struct acpi_ctx; + +/** + * acpigen_write_empty_pct() - Write an empty PCT + * + * See ACPI v6.3 section 8.4.6.1: _PCT (Performance Control) + * + * This writes an empty table so that CPU performance works as expected + * + * @ctx: ACPI context pointer + */ +void acpigen_write_empty_pct(struct acpi_ctx *ctx); + +/** + * acpigen_write_empty_ptc() - Write an empty PTC + * + * See ACPI v6.3 section 8.4.5.1: _PTC (Processor Throttling Control) + * + * This writes an empty table so that CPU performance works as expected + * + * @ctx: ACPI context pointer + */ +void acpigen_write_empty_ptc(struct acpi_ctx *ctx); + +#endif /* __ASM_ACPI_H__ */ diff --git a/arch/x86/include/asm/arch-apollolake/acpi.h b/arch/x86/include/asm/arch-apollolake/acpi.h new file mode 100644 index 0000000000..ed852feee0 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_ACPI_H +#define _ASM_ARCH_ACPI_H + +struct acpi_ctx; + +/** + * apl_acpi_fill_dmar() - Set up the DMAR for APL + * + * @ctx: ACPI context pointer + */ +int apl_acpi_fill_dmar(struct acpi_ctx *ctx); + +#endif /* _ASM_ARCH_CPU_H */ diff --git a/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl new file mode 100644 index 0000000000..4c50bb45c0 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/dptf.asl @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +#define DPTF_CPU_DEVICE TCPU +#define DPTF_CPU_ADDR 0x00000001 + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif diff --git a/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl new file mode 100644 index 0000000000..7854f7e1c5 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/globalnvs.asl @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/intel/apollolake/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, ACPI_GNVS_SIZE) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + PCNT, 8, // 0x00 - Processor Count + PPCM, 8, // 0x01 - Max PPC State + LIDS, 8, // 0x02 - LID State + PWRS, 8, // 0x03 - AC Power State + DPTE, 8, // 0x04 - Enable DPTF + CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console + PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index + GPEI, 64, // 0x11 - 0x18 - GPE Wake Source + NHLA, 64, // 0x19 - 0x20 - NHLT Address + NHLL, 32, // 0x21 - 0x24 - NHLT Length + PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SCDP, 8, // 0x29 - SD_CD GPIO portid + SCDO, 8, // 0x2A - GPIO pad offset relative to the community + UIOR, 8, // 0x2B - UART debug controller init on S3 resume + EPCS, 8, // 0x2C - SGX Enabled status + EMNA, 64, // 0x2D - 0x34 EPC base address + ELNG, 64, // 0x35 - 0x3C EPC Length + + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include <asm/acpi/cros_gnvs.asl> +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl new file mode 100644 index 0000000000..b0f892166b --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/gpio.asl @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ +#include <asm/arch/gpio.h> +#include <asm/intel_pinctrl_defs.h> +// #include <intelblocks/pcr.h> +// #include <soc/pcr_ids.h> +#include <asm/arch/iomap.h> +#include <p2sb.h> +#include "gpiolib.asl" + +scope (\_SB) { + + Device (GPO0) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_0_DESC) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM0_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_1_DESC) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM1_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_2_DESC) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM2_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_HID, GPIO_COMM_NAME) + Name (_CID, GPIO_COMM_NAME) + Name (_DDN, GPIO_COMM_3_DESC) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_COMM3_PID, PCR_PORTID_SHIFT, Local0) + Or (IOMAP_P2SB_BAR, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Scope(\_SB.PCI0) { + /* PERST Assertion + * Note: PERST is Active High + */ + Method (PRAS, 0x1, Serialized) + { + /* + * Assert PERST + * local1 - to toggle Tx pin of Dw0 + * local2 - Address of PERST + */ + Store (Arg0, Local2) + Store (\_SB.GPC0 (Local2), Local1) + Or (Local1, PAD_CFG0_TX_STATE, Local1) + \_SB.SPC0 (Local2, Local1) + } + + /* PERST DE-Assertion */ + Method (PRDA, 0x1, Serialized) + { + /* + * De-assert PERST + * local1 - to toggle Tx pin of Dw0 + * local2 - Address of PERST + */ + Store (Arg0, Local2) + Store (\_SB.GPC0 (Local2), Local1) + And (Local1, Not (PAD_CFG0_TX_STATE), Local1) + \_SB.SPC0 (Local2, Local1) + } + } + + /* + * Sleep button device ASL code. We are using this device to + * add the _PRW method for a dummy wake event to kernel so that + * before going to sleep kernel does not clear bit 15 in ACPI + * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit. + */ + Device (SLP) + { + Name (_HID, EisaId ("PNP0C0E")) + + Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 }) + } +} + +Scope(\_GPE) +{ + /* + * Dummy method for the Tier 1 GPIO SCI enable bit. When kernel reads + * _L0F in scope GPE it sets bit for gpio_tier1_sci_en in ACPI enable + * register at 0x430. For APL ACPI enable register DW0 i.e., ACPI + * GPE0a_EN at 0x430 is reserved. + */ + Method(_L0F, 0) {} +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl new file mode 100644 index 0000000000..0eb808dc19 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/gpiolib.asl @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +Scope (\_SB) +{ + /* Get Pad Configuration DW0 register value */ + Method (GPC0, 0x1, Serialized) + { + /* Arg0 - GPIO DW0 address */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, Local0, 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Pad Configuration DW0 register value */ + Method (SPC0, 0x2, Serialized) + { + /* Arg0 - GPIO DW0 address */ + /* Arg1 - Value for DW0 register */ + Store (Arg0, Local0) + OperationRegion (PDW0, SystemMemory, Local0, 4) + Field (PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } + + /* Get Pad Configuration DW1 register value */ + Method (GPC1, 0x1, Serialized) + { + /* Arg0 - GPIO DW0 address */ + Store (Add (Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, Local0, 4) + Field (PDW1, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Pad Configuration DW1 register value */ + Method (SPC1, 0x2, Serialized) + { + /* Arg0 - GPIO DW0 address */ + /* Arg1 - Value for DW1 register */ + Store (Add (Arg0, 0x4), Local0) + OperationRegion (PDW1, SystemMemory, Local0, 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store (Arg1, TEMP) + } + + /* Get DW0 address of a given pad */ + Method (GDW0, 0x2, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + Store (0, Local1) + Or( Or (ShiftLeft (Arg0, 16), IOMAP_P2SB_BAR), + Local1, Local1) + Or( Add (PAD_CFG_BASE, Multiply (Arg1, Multiply ( + GPIO_NUM_PAD_CFG_REGS, 4))), Local1, Local1) + Return (Local1) + } + + /* Calculate HOSTSW_REG address */ + Method (CHSA, 0x1, Serialized) + { + /* Arg0 - GPIO pad offset relative to the community */ + Add (HOSTSW_OWN_REG_0, Multiply (Divide (Arg0, 32), 4), Local1) + Return (Local1) + } + + /* Get Host ownership register of GPIO Community */ + Method (GHO, 0x2, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + Store (CHSA (Arg1), Local1) + + OperationRegion (SHO0, SystemMemory, Or ( Or + (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4) + Field (SHO0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Return (TEMP) + } + + /* Set Host ownership register of GPIO Community */ + Method (SHO, 0x3, Serialized) + { + /* Arg0 - GPIO portid */ + /* Arg1 - GPIO pad offset relative to the community */ + /* Arg2 - Value for Host own register */ + Store (CHSA (Arg1), Local1) + + OperationRegion (SHO0, SystemMemory, Or ( Or + (IOMAP_P2SB_BAR, ShiftLeft (Arg0, 16)), Local1), 4) + Field (SHO0, AnyAcc, NoLock, Preserve) { + TEMP, 32 + } + Store (Arg2, TEMP) + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl new file mode 100644 index 0000000000..bc3eabba60 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/lpss.asl @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + +scope (\_SB.PCI0) { + + /* LPIO1 PWM */ + Device(PWM) { + Name (_ADR, 0x001A0000) + Name (_DDN, "Intel(R) PWM Controller") + } + + /* LPIO1 HS-UART #1 */ + Device(URT1) { + Name (_ADR, 0x00180000) + Name (_DDN, "Intel(R) HS-UART Controller #1") + } + + /* LPIO1 HS-UART #2 */ + Device(URT2) { + Name (_ADR, 0x00180001) + Name (_DDN, "Intel(R) HS-UART Controller #2") + } + + /* LPIO1 HS-UART #3 */ + Device(URT3) { + Name (_ADR, 0x00180002) + Name (_DDN, "Intel(R) HS-UART Controller #3") + } + + /* LPIO1 HS-UART #4 */ + Device(URT4) { + Name (_ADR, 0x00180003) + Name (_DDN, "Intel(R) HS-UART Controller #4") + } + + /* LPIO1 SPI */ + Device(SPI1) { + Name (_ADR, 0x00190000) + Name (_DDN, "Intel(R) SPI Controller #1") + } + + /* LPIO1 SPI #2 */ + Device(SPI2) { + Name (_ADR, 0x00190001) + Name (_DDN, "Intel(R) SPI Controller #2") + } + + /* LPIO1 SPI #3 */ + Device(SPI3) { + Name (_ADR, 0x00190002) + Name (_DDN, "Intel(R) SPI Controller #3") + } + + + /* LPIO2 I2C #0 */ + Device(I2C0) { + Name (_ADR, 0x00160000) + Name (_DDN, "Intel(R) I2C Controller #0") + } + + /* LPIO2 I2C #1 */ + Device(I2C1) { + Name (_ADR, 0x00160001) + Name (_DDN, "Intel(R) I2C Controller #1") + } + + /* LPIO2 I2C #2 */ + Device(I2C2) { + Name (_ADR, 0x00160002) + Name (_DDN, "Intel(R) I2C Controller #2") + } + + /* LPIO2 I2C #3 */ + Device(I2C3) { + Name (_ADR, 0x00160003) + Name (_DDN, "Intel(R) I2C Controller #3") + } + + /* LPIO2 I2C #4 */ + Device(I2C4) { + Name (_ADR, 0x00170000) + Name (_DDN, "Intel(R) I2C Controller #4") + } + + /* LPIO2 I2C #5 */ + Device(I2C5) { + Name (_ADR, 0x00170001) + Name (_DDN, "Intel(R) I2C Controller #5") + } + + /* LPIO2 I2C #6 */ + Device(I2C6) { + Name (_ADR, 0x00170002) + Name (_DDN, "Intel(R) I2C Controller #6") + } + + /* LPIO2 I2C #7 */ + Device(I2C7) { + Name (_ADR, 0x00170003) + Name (_DDN, "Intel(R) I2C Controller #7") + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl new file mode 100644 index 0000000000..ff5657abd0 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/northbridge.asl @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_BBN, 0) + +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, 0x1000000000)) + { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000000..cc3b7a769d --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pch_hda.asl @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016 Google Inc. + * + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate() { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, Cacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + } + ) + + /* can wake up from S3 state */ + Name (_PRW, Package() { GPE0A_AVS_PME_STS, 3 }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } + Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000000..21a1ca9ff9 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pci_irqs.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + +#include "soc_int.asl" + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, NPK_INT}, + Package(){0x0000FFFF, 1, 0, PUNIT_INT}, + Package(){0x0002FFFF, 0, 0, GEN_INT}, + Package(){0x0003FFFF, 0, 0, IUNIT_INT}, + Package(){0x000DFFFF, 1, 0, PMC_INT}, + Package(){0x000EFFFF, 0, 0, AUDIO_INT}, + Package(){0x000FFFFF, 0, 0, CSE_INT}, + Package(){0x0011FFFF, 0, 0, ISH_INT}, + Package(){0x0012FFFF, 0, 0, SATA_INT}, + Package(){0x0013FFFF, 0, 0, PIRQA_INT}, + Package(){0x0013FFFF, 1, 0, PIRQB_INT}, + Package(){0x0013FFFF, 2, 0, PIRQC_INT}, + Package(){0x0013FFFF, 3, 0, PIRQD_INT}, + Package(){0x0014FFFF, 0, 0, PIRQB_INT}, + Package(){0x0014FFFF, 1, 0, PIRQC_INT}, + Package(){0x0014FFFF, 2, 0, PIRQD_INT}, + Package(){0x0014FFFF, 3, 0, PIRQA_INT}, + Package(){0x0015FFFF, 0, 0, XHCI_INT}, + Package(){0x0015FFFF, 1, 0, XDCI_INT}, + Package(){0x0016FFFF, 0, 0, I2C0_INT}, + Package(){0x0016FFFF, 1, 0, I2C1_INT}, + Package(){0x0016FFFF, 2, 0, I2C2_INT}, + Package(){0x0016FFFF, 3, 0, I2C3_INT}, + Package(){0x0017FFFF, 0, 0, I2C4_INT}, + Package(){0x0017FFFF, 1, 0, I2C5_INT}, + Package(){0x0017FFFF, 2, 0, I2C6_INT}, + Package(){0x0017FFFF, 3, 0, I2C7_INT}, + Package(){0x0018FFFF, 0, 0, UART0_INT}, + Package(){0x0018FFFF, 1, 0, UART1_INT}, + Package(){0x0018FFFF, 2, 0, UART2_INT}, + Package(){0x0018FFFF, 3, 0, UART3_INT}, + Package(){0x0019FFFF, 0, 0, SPI0_INT}, + Package(){0x0019FFFF, 1, 0, SPI1_INT}, + Package(){0x0019FFFF, 2, 0, SPI2_INT}, + Package(){0x001BFFFF, 0, 0, SDCARD_INT}, + Package(){0x001CFFFF, 0, 0, EMMC_INT}, + Package(){0x001EFFFF, 0, 0, SDIO_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, + }) +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl new file mode 100644 index 0000000000..ecff59ab1c --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation + */ + +/* PCIe Ports */ + +Device (RP01) +{ + Name (_ADR, 0x00140000) + Name (_DDN, "PCIe-B 0") + + #include "pcie_port.asl" +} + +Device (RP03) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "PCIe-A 0") + + #include "pcie_port.asl" +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl new file mode 100644 index 0000000000..12a08b4aa8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pcie_port.asl @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation + */ + +/* Include in each PCIe Root Port device */ + +/* lowest D-state supported by + * PCIe root port during S0 state + */ +Name (_S0W, 4) + +Name (PDST, 0) /* present Detect status */ + +/* Dynamic Opregion needed to access registers + * when the controller is in D3 cold + */ +OperationRegion (PX01, PCI_Config, 0x00, 0xFF) +Field (PX01, AnyAcc, NoLock, Preserve) +{ + Offset(0x5A), + , 6, + PDS, 1, /* 6, Presence detect Change */ + Offset(0xE2), /* RPPGEN - Root Port Power Gating Enable */ + , 2, + L23E, 1, /* 2, L23_Rdy Entry Request (L23ER) */ + L23R, 1, /* 3, L23_Rdy to Detect Transition (L23R2DT) */ + Offset(0xF4), /* BLKPLLEN */ + , 10, + BPLL, 1, +} + +OperationRegion (PX02, PCI_Config, 0x338, 0x4) +Field (PX02, AnyAcc, NoLock, Preserve) +{ + , 26, + BDQA, 1 /* BLKDQDA */ +} + +PowerResource (PXP, 0, 0) +{ + /* Define the PowerResource for PCIe slot */ + Method (_STA, 0, Serialized) + { + Store (PDS, PDST) + If (LEqual (PDS, 1)) { + Return (0xf) + } Else { + Return (0) + } + } + + Method (_ON, 0, Serialized) + { + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* Enter this condition if device + * is connected + */ + + /* De-assert PERST */ + \_SB.PCI0.PRDA (\PRT0) + + Store (0, BDQA) /* Set BLKDQDA to 0 */ + Store (0, BPLL) /* Set BLKPLLEN to 0 */ + + /* Set L23_Rdy to Detect Transition + * (L23R2DT) + */ + Store (1, L23R) + Sleep (16) + Store (0, Local0) + + /* Delay for transition Detect + * and link to train + */ + While (L23R) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + } /* End PDS condition check */ + } + + Method (_OFF, 0, Serialized) + { + /* Set L23_Rdy Entry Request (L23ER) */ + If (LAnd (LEqual (PDST, 1), LNotEqual (\PRT0, 0))) { + /* enter this condition if device + * is connected + */ + Store (1, L23E) + Sleep (16) + Store (0, Local0) + While (L23E) { + If (Lgreater (Local0, 4)) { + Break + } + Sleep (16) + Increment (Local0) + } + Store (1, BDQA) /* Set BLKDQDA to 1 */ + Store (1, BPLL) /* Set BLKPLLEN to 1 */ + + /* Assert PERST */ + \_SB.PCI0.PRAS (\PRT0) + } /* End PDS condition check */ + } /* End of Method_OFF */ +} /* End PXP */ + +Name(_PR0, Package() { PXP }) +Name(_PR3, Package() { PXP }) diff --git a/arch/x86/include/asm/arch-apollolake/acpi/platform.asl b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl new file mode 100644 index 0000000000..b631a9fb38 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2016 Intel Corp + */ + +/* Enable ACPI _SWS methods */ +#include <soc/intel/common/acpi/acpi_wake_source.asl> +#include <soc/intel/common/acpi/platform.asl> diff --git a/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000000..4a592833cc --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corp. + */ + +#include <asm/arch/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 +#define PMIO_LIMIT 0x480 + +scope (\_SB) { + Device (IPC1) + { + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0, 0x2000, IBAR) + Memory32Fixed (ReadWrite, 0x0, 0x4, MDAT) + Memory32Fixed (ReadWrite, 0x0, 0x4, MINF) + IO (Decode16, IOMAP_ACPI_BASE, PMIO_LIMIT, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0, 0x2000, SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (SRAM_BASE_0, SBAS) + + Return (^RBUF) + } + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/scs.asl b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl new file mode 100644 index 0000000000..7d61861ea1 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/scs.asl @@ -0,0 +1,173 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +Scope (\_SB.PCI0) { + /* 0xD6- is the port address */ + /* 0x600- is the dynamic clock gating control register offset (GENR) */ + OperationRegion (SBMM, SystemMemory, + Or ( Or (IOMAP_P2SB_BAR, + ShiftLeft(0xD6, PCR_PORTID_SHIFT)), 0x0600), 0x18) + Field (SBMM, DWordAcc, NoLock, Preserve) + { + GENR, 32, + Offset (0x08), + , 5, /* bit[5] represents Force Card Detect SD Card */ + GRR3, 1, /* GPPRVRW3 for SD Card detect Bypass. It's active high */ + } + + /* SCC power gate control method, this method must be serialized as + * multiple device will control the GENR register + * + * Arguments: (2) + * Arg0: 0-AND 1-OR + * Arg1: Value + */ + Method (SCPG, 2, Serialized) + { + if (LEqual(Arg0, 0x1)) { + Or (^GENR, Arg1, ^GENR) + } ElseIf (LEqual(Arg0, 0x0)){ + And (^GENR, Arg1, ^GENR) + } + } + + /* eMMC */ + Device (SDHA) { + Name (_ADR, 0x001C0000) + Name (_DDN, "Intel(R) eMMC Controller - 80865ACC") + Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 9: Device Readiness Durations + * Returns a package of five integers covering + * various device related delays in PCIe Base Spec. + */ + If (LEqual (Arg2, 9)) { + /* + * Function 9 support for revision 3. + * ECN link for function definitions + * [https://pcisig.com/sites/default/files/ + * specification_documents/ + * ECN_fw_latency_optimization_final.pdf] + */ + If (LEqual (Arg1, 3)) { + /* + * Integer 0: FW reset time. + * Integer 1: FW data link up time. + * Integer 2: FW functional level reset + * time. + * Integer 3: FW D3 hot to D0 time. + * Integer 4: FW VF enable time. + * set ACPI constant Ones for elements + * where overriding the default value + * is not desired. + */ + Return (Package (5) {0, Ones, Ones, + Ones, Ones}) + } + } + } + Return (Buffer() { 0x00 }) + } + + Method (_PS0, 0, NotSerialized) + { + /* Clear clock gate + * Clear bit 6 and 0 + */ + ^^SCPG(0,0xFFFFFFBE) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate + * Restore clock gate + * Restore bit 6 and 0 + */ + ^^SCPG(1,0x00000041) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } + } /* Device (SDHA) */ + + /* SD CARD */ + Device (SDCD) + { + Name (_ADR, 0x001B0000) + Name (_S0W, 4) /* _S0W: S0 Device Wake State */ + Name (SCD0, 0) /* Store SD_CD DW0 address */ + + /* Set the host ownership of sdcard cd during kernel boot */ + Method (_INI, 0) + { + /* Check SDCard CD port is valid */ + If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + { + /* Store DW0 address of SD_CD */ + Store (GDW0 (\SCDP, \SCDO), SCD0) + /* Get the current SD_CD ownership */ + Store (\_SB.GHO (\SCDP, \SCDO), Local0) + /* Set host ownership as GPIO in HOSTSW_OWN reg */ + Or (Local0, ShiftLeft (1, Mod (\SCDO, 32)), Local0) + \_SB.SHO (\SCDP, \SCDO, Local0) + } + } + + Method (_PS0, 0, NotSerialized) + { + /* Check SDCard CD port is valid */ + If (LAnd (LNotEqual (\SCDP, 0), LNotEqual (\SCDO, 0) )) + { + /* Store DW0 into local0 to get rxstate of GPIO */ + Store (\_SB.GPC0 (SCD0), Local0) + /* Extract rxstate [bit 1] of sdcard card detect pin */ + And (Local0, PAD_CFG0_RX_STATE, Local0) + /* If the sdcard is present, rxstate is low. + * If sdcard is not present, rxstate is High. + * Write the inverted value of rxstate to GRR3. + */ + If (LEqual (Local0, 0)) { + Store (1, ^^GRR3) + } Else { + Store (0, ^^GRR3) + } + Sleep (2) + } + } + + Method (_PS3, 0, NotSerialized) + { + /* Clear GRR3 to Power Gate SD Controller */ + Store (0, ^^GRR3) + } + + Device (CARD) + { + Name (_ADR, 0x00000008) + Method (_RMV, 0, NotSerialized) + { + Return (1) + } + } + } /* Device (SDCD) */ +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl new file mode 100644 index 0000000000..df2fafb7f6 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/soc_int.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + +#ifndef _SOC_INT_DEFINE_ASL_ +#define _SOC_INT_DEFINE_ASL_ + +#define SDCARD_INT 3 /* Need to be shared by PMC and SCC only*/ +#define UART0_INT 4 /* Need to be shared by PMC and SCC only*/ +#define UART1_INT 5 /* Need to be shared by PMC and SCC only*/ +#define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ +#define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ +#define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 14 +#define NPK_INT 16 +#define PIRQA_INT 16 +#define PIRQB_INT 17 +#define PIRQC_INT 18 +#define SATA_INT 19 +#define GEN_INT 19 +#define PIRQD_INT 19 +#define XHCI_INT 17 /* Need to be shared by PMC and SCC only*/ +#define SMBUS_INT 20 /* PIRQE */ +#define CSE_INT 20 /* PIRQE */ +#define IUNIT_INT 21 /* PIRQF */ +#define PIRQF_INT 21 +#define PIRQG_INT 22 +#define PUNIT_INT 24 +#define AUDIO_INT 25 +#define ISH_INT 26 +#define I2C0_INT 27 +#define I2C1_INT 28 +#define I2C2_INT 29 +#define I2C3_INT 30 +#define I2C4_INT 31 +#define I2C5_INT 32 +#define I2C6_INT 33 +#define I2C7_INT 34 +#define SPI0_INT 35 +#define SPI1_INT 36 +#define SPI2_INT 37 +#define UFS_INT 38 +#define EMMC_INT 39 +#define PMC_INT 40 +#define SDIO_INT 42 +#define CNVI_INT 44 + +#endif /* _SOC_INT_DEFINE_ASL_ */ diff --git a/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl new file mode 100644 index 0000000000..08290194f6 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/southbridge.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + */ + +#include <p2sb.h> +#include <asm/arch/gpe.h> + +/* PCIE device */ +#include "pcie.asl" + +/* LPSS device */ +#include "lpss.asl" + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl" + +#include "xhci.asl" + +/* LPC */ +#include <asm/acpi/lpc.asl> + +/* eMMC */ +#include "scs.asl" + +/* PMC IPC controller */ +#include "pmc_ipc.asl" + +/* PCI _OSC */ +#include <asm/acpi/pci_osc.asl> diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl new file mode 100644 index 0000000000..6333126c3f --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corporation. + */ + +/* XHCI Controller 0:15.0 */ +Device (XHCI) { + Name (_ADR, 0x00150000) /* Device 21, Function 0 */ + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + /* Declare XHCI GPE status and enable bits are bit 13 */ + Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) + + Method (_STA, 0) + { + Return (0xF) + } + + Device (RHUB) + { + /* Root Hub */ + Name (_ADR, Zero) + +#if IS_ENABLED(CONFIG_SOC_INTEL_GLK) +#include "xhci_glk_ports.asl" +#else +#include "xhci_apl_ports.asl" +#endif + } +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl new file mode 100644 index 0000000000..3ab7d18fc8 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_apl_ports.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 9) } +Device (SS02) { Name (_ADR, 10) } +Device (SS03) { Name (_ADR, 11) } +Device (SS04) { Name (_ADR, 12) } +Device (SS05) { Name (_ADR, 13) } +Device (SS06) { Name (_ADR, 14) } diff --git a/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl new file mode 100644 index 0000000000..192267221f --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi/xhci_glk_ports.asl @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC. + * Copyright 2019 Intel Corp. + */ + +/* USB2 */ +Device (HS01) { Name (_ADR, 1) } +Device (HS02) { Name (_ADR, 2) } +Device (HS03) { Name (_ADR, 3) } +Device (HS04) { Name (_ADR, 4) } +Device (HS05) { Name (_ADR, 5) } +Device (HS06) { Name (_ADR, 6) } +Device (HS07) { Name (_ADR, 7) } +Device (HS08) { Name (_ADR, 8) } +Device (HS09) { Name (_ADR, 9) } + +/* USB3 */ +Device (SS01) { Name (_ADR, 10) } +Device (SS02) { Name (_ADR, 11) } +Device (SS03) { Name (_ADR, 12) } +Device (SS04) { Name (_ADR, 13) } +Device (SS05) { Name (_ADR, 14) } +Device (SS06) { Name (_ADR, 15) } diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h index fe62194b02..ef8eb228db 100644 --- a/arch/x86/include/asm/arch-apollolake/global_nvs.h +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -10,27 +10,6 @@ #ifndef _GLOBAL_NVS_H_ #define _GLOBAL_NVS_H_ -struct __packed acpi_global_nvs { - /* Miscellaneous */ - u8 pcnt; /* 0x00 - Processor Count */ - u8 ppcm; /* 0x01 - Max PPC State */ - u8 lids; /* 0x02 - LID State */ - u8 pwrs; /* 0x03 - AC Power State */ - u8 dpte; /* 0x04 - Enable DPTF */ - u32 cbmc; /* 0x05 - 0x08 - U-Boot Console */ - u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ - u64 nhla; /* 0x19 - 0x20 - NHLT Address */ - u32 nhll; /* 0x21 - 0x24 - NHLT Length */ - u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ - u8 scdp; /* 0x29 - SD_CD GPIO portid */ - u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ - u8 uior; /* 0x2b - UART debug controller init on S3 resume */ - u8 ecps; /* 0x2c - SGX Enabled status */ - u64 emna; /* 0x2d - 0x34 EPC base address */ - u64 elng; /* 0x35 - 0x3c EPC Length */ - u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ - u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ -}; +#include <asm/intel_gnvs.h> #endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-apollolake/gpe.h b/arch/x86/include/asm/arch-apollolake/gpe.h new file mode 100644 index 0000000000..f5792960be --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/gpe.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Intel Corporation + * Copyright 2020 Google LLC + * + * Taken from coreboot apl gpe.h + */ + +#ifndef _ASM_ARCH_GPE_H_ +#define _ASM_ARCH_GPE_H_ + +/* bit position in GPE0a_STS register */ +#define GPE0A_PCIE_SCI_STS 0 +#define GPE0A_SWGPE_STS 2 +#define GPE0A_PCIE_WAKE0_STS 3 +#define GPE0A_PUNIT_SCI_STS 4 +#define GPE0A_PCIE_WAKE1_STS 6 +#define GPE0A_PCIE_WAKE2_STS 7 +#define GPE0A_PCIE_WAKE3_STS 8 +#define GPE0A_PCIE_GPE_STS 9 +#define GPE0A_BATLOW_STS 10 +#define GPE0A_CSE_PME_STS 11 +#define GPE0A_XDCI_PME_STS 12 +#define GPE0A_XHCI_PME_STS 13 +#define GPE0A_AVS_PME_STS 14 +#define GPE0A_GPIO_TIER1_SCI_STS 15 +#define GPE0A_SMB_WAK_STS 16 +#define GPE0A_SATA_PME_STS 17 +#define GPE0A_CNVI_PME_STS 18 + +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_127_96 */ +#define GPE0_DW3_00 96 +#define GPE0_DW3_01 97 +#define GPE0_DW3_02 98 +#define GPE0_DW3_03 99 +#define GPE0_DW3_04 100 +#define GPE0_DW3_05 101 +#define GPE0_DW3_06 102 +#define GPE0_DW3_07 103 +#define GPE0_DW3_08 104 +#define GPE0_DW3_09 105 +#define GPE0_DW3_10 106 +#define GPE0_DW3_11 107 +#define GPE0_DW3_12 108 +#define GPE0_DW3_13 109 +#define GPE0_DW3_14 110 +#define GPE0_DW3_15 111 +#define GPE0_DW3_16 112 +#define GPE0_DW3_17 113 +#define GPE0_DW3_18 114 +#define GPE0_DW3_19 115 +#define GPE0_DW3_20 116 +#define GPE0_DW3_21 117 +#define GPE0_DW3_22 118 +#define GPE0_DW3_23 119 +#define GPE0_DW3_24 120 +#define GPE0_DW3_25 121 +#define GPE0_DW3_26 122 +#define GPE0_DW3_27 123 +#define GPE0_DW3_28 124 +#define GPE0_DW3_29 125 +#define GPE0_DW3_30 126 +#define GPE0_DW3_31 127 + +#define GPE_MAX GPE0_DW3_31 + +#endif diff --git a/arch/x86/include/asm/arch-apollolake/gpio.h b/arch/x86/include/asm/arch-apollolake/gpio.h index 10879c168e..ab5860c0fd 100644 --- a/arch/x86/include/asm/arch-apollolake/gpio.h +++ b/arch/x86/include/asm/arch-apollolake/gpio.h @@ -482,4 +482,7 @@ #define GPIO_72_IRQ 0x65 #define GPIO_73_IRQ 0x66 +/* This is needed by ACPI */ +#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ + #endif /* _ASM_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h b/arch/x86/include/asm/arch-apollolake/iomap.h index 4ce1017055..21c5f33021 100644 --- a/arch/x86/include/asm/arch-apollolake/iomap.h +++ b/arch/x86/include/asm/arch-apollolake/iomap.h @@ -11,11 +11,27 @@ /* Put p2sb at 0xd0000000 in TPL */ #define IOMAP_P2SB_BAR 0xd0000000 +#define IOMAP_P2SB_SIZE 0x10000000 #define IOMAP_SPI_BASE 0xfe010000 #define IOMAP_ACPI_BASE 0x400 #define IOMAP_ACPI_SIZE 0x100 +#define ACPI_BASE_ADDRESS IOMAP_ACPI_BASE + +#define PMC_BAR0 0xfe042000 + +#define MCH_BASE_ADDRESS 0xfed10000 +#define MCH_SIZE 0x8000 + +#ifdef __ACPI__ +#define HPET_BASE_ADDRESS 0xfed00000 + +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) +#endif /* * Use UART2. To use UART1 you need to set '2' to '1', change device tree serial diff --git a/arch/x86/include/asm/arch-apollolake/pm.h b/arch/x86/include/asm/arch-apollolake/pm.h index 6718290c4f..9a8d971e91 100644 --- a/arch/x86/include/asm/arch-apollolake/pm.h +++ b/arch/x86/include/asm/arch-apollolake/pm.h @@ -1,12 +1,15 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) + * Copyright 2019 Google LLC */ #ifndef _ASM_ARCH_PM_H #define _ASM_ARCH_PM_H +#include <power/acpi_pmc.h> + #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 #define PMC_GPE_NW_31_0 3 @@ -16,4 +19,39 @@ #define PMC_GPE_N_63_32 7 #define PMC_GPE_W_31_0 9 +#define IRQ_REG 0x106c +#define SCI_IRQ_SHIFT 24 +#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT) +#define SCIS_IRQ9 9 +#define SCIS_IRQ10 10 +#define SCIS_IRQ11 11 +#define SCIS_IRQ20 20 +#define SCIS_IRQ21 21 +#define SCIS_IRQ22 22 +#define SCIS_IRQ23 23 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#ifndef __ASSEMBLY__ +/* Track power state from reset to log events */ +struct __packed chipset_power_state { + u16 pm1_sts; + u16 pm1_en; + u32 pm1_cnt; + u32 gpe0_sts[GPE0_REG_MAX]; + u32 gpe0_en[GPE0_REG_MAX]; + u16 tco1_sts; + u16 tco2_sts; + u32 prsts; + u32 gen_pmcon1; + u32 gen_pmcon2; + u32 gen_pmcon3; + u32 prev_sleep_state; +}; +#endif /* !__ASSEMBLY__ */ + #endif diff --git a/arch/x86/include/asm/arch-apollolake/systemagent.h b/arch/x86/include/asm/arch-apollolake/systemagent.h index 9e7bd62751..788a63d799 100644 --- a/arch/x86/include/asm/arch-apollolake/systemagent.h +++ b/arch/x86/include/asm/arch-apollolake/systemagent.h @@ -35,4 +35,35 @@ */ void enable_bios_reset_cpl(void); +/** + * sa_get_tolud_base() - Get the TOLUD base address + * + * This returns the Top Of Low Useable DRAM, marking the top of usable DRAM + * below 4GB + * + * @dev: hostbridge device + * @return TOLUD address + */ +ulong sa_get_tolud_base(struct udevice *dev); + +/** + * sa_get_gsm_base() - Get the GSM base address + * + * This returns the base of GTT Stolen Memory, marking the start of memory used + * for Graphics Translation Tables. + * + * @dev: hostbridge device + * @return GSM address + */ +ulong sa_get_gsm_base(struct udevice *dev); + +/** + * sa_get_tseg_base() - Get the TSEG base address + * + * This returns the top address of DRAM available below 4GB + * + * @return TSEG base + */ +ulong sa_get_tseg_base(struct udevice *dev); + #endif diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h index d961dddc9e..7a3c1f5155 100644 --- a/arch/x86/include/asm/bootparam.h +++ b/arch/x86/include/asm/bootparam.h @@ -24,6 +24,11 @@ struct setup_data { __u8 data[0]; }; +/** + * struct setup_header - Information needed by Linux to boot + * + * See https://www.kernel.org/doc/html/latest/x86/boot.html + */ struct setup_header { __u8 setup_sects; __u16 root_flags; @@ -43,15 +48,16 @@ struct setup_header { __u16 kernel_version; __u8 type_of_loader; __u8 loadflags; -#define LOADED_HIGH (1<<0) -#define QUIET_FLAG (1<<5) -#define KEEP_SEGMENTS (1<<6) -#define CAN_USE_HEAP (1<<7) +#define LOADED_HIGH BIT(0) +#define KASLR_FLAG BIT(1) +#define QUIET_FLAG BIT(5) +#define KEEP_SEGMENTS BIT(6) /* Obsolete */ +#define CAN_USE_HEAP BIT(7) __u16 setup_move_size; __u32 code32_start; __u32 ramdisk_image; __u32 ramdisk_size; - __u32 bootsect_kludge; + __u32 bootsect_kludge; /* Obsolete */ __u16 heap_end_ptr; __u8 ext_loader_ver; __u8 ext_loader_type; @@ -59,7 +65,13 @@ struct setup_header { __u32 initrd_addr_max; __u32 kernel_alignment; __u8 relocatable_kernel; - __u8 _pad2[3]; + u8 min_alignment; +#define XLF_KERNEL_64 BIT(0) +#define XLF_CAN_BE_LOADED_ABOVE_4G BIT(1) +#define XLF_EFI_HANDOVER_32 BIT(2) +#define XLF_EFI_HANDOVER_64 BIT(3) +#define XLF_EFI_KEXEC BIT(4) + u16 xloadflags; __u32 cmdline_size; __u32 hardware_subarch; __u64 hardware_subarch_data; @@ -69,6 +81,7 @@ struct setup_header { __u64 pref_address; __u32 init_size; __u32 handover_offset; + u32 kernel_info_offset; } __attribute__((packed)); struct sys_desc_table { diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 21a05dab7d..5b001bbee2 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -288,4 +288,13 @@ u32 cpu_get_family_model(void); */ u32 cpu_get_stepping(void); +/** + * cpu_phys_address_size() - Get the physical address size in bits + * + * This is 32 for older CPUs but newer ones may support 36. + * + * @return address size (typically 32 or 36) + */ +int cpu_phys_address_size(void); + #endif diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index cdd99a90b7..48f56c2aad 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -128,4 +128,60 @@ void cpu_set_eist(bool eist_status); */ void cpu_set_p_state_to_turbo_ratio(void); +/** + * cpu_get_coord_type() - Get the type of coordination for P-State transition + * + * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency) + * + * @return HW_ALL (always) + */ +int cpu_get_coord_type(void); + +/** + * cpu_get_min_ratio() - get minimum support frequency ratio for CPU + * + * @return minimum ratio + */ +int cpu_get_min_ratio(void); + +/** + * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio + * + * If a nominal TDP ratio is available, it is returned. Otherwise this returns + * the maximum non-turbo frequency ratio for this processor + * + * @return max ratio + */ +int cpu_get_max_ratio(void); + +/** + * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz + * + * This is the value the clock ratio is multiplied with + * + * @return bus-block frequency in KHz + */ +int cpu_get_bus_clock_khz(void); + +/** + * cpu_get_power_max() - Get maximum CPU TDP + * + * @return maximum CPU TDP (Thermal-design power) in mW + */ +int cpu_get_power_max(void); + +/** + * cpu_get_max_turbo_ratio() - Get maximum turbo ratio + * + * @return maximum ratio + */ +int cpu_get_max_turbo_ratio(void); + +/** + * cpu_get_cores_per_package() - Get the number of CPU cores in each package + * + * @return number of cores + */ +int cpu_get_cores_per_package(void); + #endif diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h index 9d29f82f97..a66c0d2489 100644 --- a/arch/x86/include/asm/e820.h +++ b/arch/x86/include/asm/e820.h @@ -8,6 +8,7 @@ #define E820_ACPI 3 #define E820_NVS 4 #define E820_UNUSABLE 5 +#define E820_COUNT 6 /* Number of types */ #ifndef __ASSEMBLY__ #include <linux/types.h> @@ -21,10 +22,9 @@ struct e820_entry { #define ISA_START_ADDRESS 0xa0000 #define ISA_END_ADDRESS 0x100000 -#endif /* __ASSEMBLY__ */ - /* Implementation defined function to install an e820 map */ unsigned int install_e820_map(unsigned int max_entries, struct e820_entry *); +#endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_E820_H */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index 4941e2d74f..3a9b61903c 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -10,9 +10,18 @@ enum fsp_phase { /* Notification code for post PCI enuermation */ - INIT_PHASE_PCI = 0x20, - /* Notification code before transferring control to the payload */ - INIT_PHASE_BOOT = 0x40 + INIT_PHASE_PCI = 0x20, + /* + * Notification code before transferring control to the payload. + * This is issued at the end of init before starting main(), i.e. + * the command line / boot script. + */ + INIT_PHASE_BOOT = 0x40, + /* + * Notification code before existing boot services. This is issued + * just before removing devices and booting the kernel. + */ + INIT_PHASE_END_FIRMWARE = 0xf0, }; struct fsp_notify_params { diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index d248520e97..ea3983e04f 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -99,4 +99,29 @@ struct __packed hob_graphics_info { EFI_GUID(0x39f62cce, 0x6825, 0x4669, \ 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07) +/* The following GUIDs are observed with FSP 2.1 / Apollo Lake */ +#define FSP_HOB_RESOURCE_OWNER_SMM_PEI_SMRAM_GUID \ + EFI_GUID(0x6dadf1d1, 0xd4cc, 0x4910, \ + 0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d) + +#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID1 \ + EFI_GUID(0xea296d92, 0x0b69, 0x423c, \ + 0x8c, 0x28, 0x33, 0xb4, 0xe0, 0xa9, 0x12, 0x68) + +#define FSP_HOB_RESOURCE_OWNER_PCD_DATABASE_GUID2 \ + EFI_GUID(0x9b3ada4f, 0xae56, 0x4c24, \ + 0x8d, 0xea, 0xf0, 0x3b, 0x75, 0x58, 0xae, 0x50) + +#define FSP_HOB_RESOURCE_OWNER_PEIM_DXE_GUID \ + EFI_GUID(0x86d70125, 0xbaa3, 0x4296, \ + 0xa6, 0x2f, 0x60, 0x2b, 0xeb, 0xbb, 0x90, 0x81) + +#define FSP_HOB_RESOURCE_OWNER_ALLOC_STACK_GUID \ + EFI_GUID(0x4ed4bf27, 0x4092, 0x42e9, \ + 0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x00, 0xc9, 0xbd) + +#define FSP_HOB_RESOURCE_OWNER_SMBIOS_MEMORY_GUID \ + EFI_GUID(0x01a1108c, 0x9dee, 0x4984, \ + 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89) + #endif diff --git a/arch/x86/include/asm/intel_acpi.h b/arch/x86/include/asm/intel_acpi.h new file mode 100644 index 0000000000..a5781f1af4 --- /dev/null +++ b/arch/x86/include/asm/intel_acpi.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> + */ + +#ifndef __ASM_INTEL_ACPI_H__ +#define __ASM_INTEL_ACPI_H__ + +struct acpi_cstate; +struct acpi_ctx; +struct acpi_tstate; +struct udevice; + +/** + * acpi_generate_cpu_header() - Start generating an ACPI CPU entry + * + * Generates the ACPI information for a CPU. After this, the caller should + * generate_p_state_entries(), generate_t_state_entries and then + * acpigen_pop_len() to close off this package. + * + * @ctx: ACPI context pointer + * @core_id: CPU core number, as numbered by the SoC + * @c_state_map: Information about each C state + * @num_cstates: Number of entries in @c_state_map + * @return 0 if OK, -ve on error + */ +int acpi_generate_cpu_header(struct acpi_ctx *ctx, int core_id, + const struct acpi_cstate *c_state_map, + int num_cstates); + +/** + * acpi_generate_cpu_package_final() - Write out the CPU PPKG entry + * + * This writes information about the CPUs in the package + * + * @ctx: ACPI context pointer + * @cores_per_package: Number of CPU cores in each package in the SoC + */ +int acpi_generate_cpu_package_final(struct acpi_ctx *ctx, + int cores_per_package); + +void generate_p_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package); +void generate_t_state_entries(struct acpi_ctx *ctx, int core, + int cores_per_package, struct acpi_tstate *entry, + int nentries); +int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx); + +int intel_southbridge_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx); + +#endif /* __ASM_INTEL_ACPI_H__ */ diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h new file mode 100644 index 0000000000..c1e9d65779 --- /dev/null +++ b/arch/x86/include/asm/intel_gnvs.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation. + * + * Taken from coreboot intelblocks/nvs.h + * Copyright 2019 Google LLC + */ + +#ifndef _INTEL_GNVS_H_ +#define _INTEL_GNVS_H_ + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ + u8 uior; /* 0x2b - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2c - SGX Enabled status */ + u64 emna; /* 0x2d - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3C EPC Length */ + u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ +#ifdef CONFIG_CHROMEOS + /* ChromeOS-specific (0x100 - 0xfff) */ + struct chromeos_acpi chromeos; +#else + u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ +#endif +}; + +#ifdef CONFIG_CHROMEOS +check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +#endif + +#endif /* _INTEL_GNVS_H_ */ diff --git a/arch/x86/include/asm/intel_opregion.h b/arch/x86/include/asm/intel_opregion.h new file mode 100644 index 0000000000..fb3e38617e --- /dev/null +++ b/arch/x86/include/asm/intel_opregion.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.h + */ + +#ifndef _ASM_INTEL_OPREGION_H_ +#define _ASM_INTEL_OPREGION_H_ + +#define VBT_SIGNATURE 0x54425624 + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define SWSMISCI 0xe0 /* SWSMISCI Register */ +#define GSSCIE BIT(0) /* SCI Event trigger */ +#define SMISCISEL BIT(15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +struct __packed opregion_header { + u8 signature[16]; /* Offset 0 OpRegion signature */ + u32 size; /* Offset 16 OpRegion size */ + u32 version; /* Offset 20 OpRegion structure version */ + u8 sbios_version[32]; /* Offset 24 System BIOS build version */ + u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ + u8 driver_version[16]; /* Offset 72 Graphic drvr build version */ + u32 mailboxes; /* Offset 88 Mailboxes supported */ + u32 dmod; /* Offset 92 Driver Model */ + u32 pcon; /* Offset 96 Platform Capabilities */ + u16 dver[16]; /* Offset 100 GOP Version */ + u8 reserved[124]; /* Offset 132 Reserved */ +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 BIT(0) +#define IGD_MBOX2 BIT(1) +#define IGD_MBOX3 BIT(2) +#define IGD_MBOX4 BIT(3) +#define IGD_MBOX5 BIT(4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public ACPI methods */ +struct __packed opregion_mailbox1 { + u32 drdy; /* Offset 0 Driver readiness */ + u32 csts; /* Offset 4 Status */ + u32 cevt; /* Offset 8 Current event */ + u8 reserved[20]; /* Offset 12 Reserved */ + u32 didl; /* Offset 32 Supported display device 1 */ + u32 ddl2; /* Offset 36 Supported display device 2 */ + u32 ddl3; /* Offset 40 Supported display device 3 */ + u32 ddl4; /* Offset 44 Supported display device 4 */ + u32 ddl5; /* Offset 48 Supported display device 5 */ + u32 ddl6; /* Offset 52 Supported display device 6 */ + u32 ddl7; /* Offset 56 Supported display device 7 */ + u32 ddl8; /* Offset 60 Supported display device 8 */ + u32 cpdl; /* Offset 64 Currently present display device 1 */ + u32 cpl2; /* Offset 68 Currently present display device 2 */ + u32 cpl3; /* Offset 72 Currently present display device 3 */ + u32 cpl4; /* Offset 76 Currently present display device 4 */ + u32 cpl5; /* Offset 80 Currently present display device 5 */ + u32 cpl6; /* Offset 84 Currently present display device 6 */ + u32 cpl7; /* Offset 88 Currently present display device 7 */ + u32 cpl8; /* Offset 92 Currently present display device 8 */ + u32 cadl; /* Offset 96 Currently active display device 1 */ + u32 cal2; /* Offset 100 Currently active display device 2 */ + u32 cal3; /* Offset 104 Currently active display device 3 */ + u32 cal4; /* Offset 108 Currently active display device 4 */ + u32 cal5; /* Offset 112 Currently active display device 5 */ + u32 cal6; /* Offset 116 Currently active display device 6 */ + u32 cal7; /* Offset 120 Currently active display device 7 */ + u32 cal8; /* Offset 124 Currently active display device 8 */ + u32 nadl; /* Offset 128 Next active device 1 */ + u32 ndl2; /* Offset 132 Next active device 2 */ + u32 ndl3; /* Offset 136 Next active device 3 */ + u32 ndl4; /* Offset 140 Next active device 4 */ + u32 ndl5; /* Offset 144 Next active device 5 */ + u32 ndl6; /* Offset 148 Next active device 6 */ + u32 ndl7; /* Offset 152 Next active device 7 */ + u32 ndl8; /* Offset 156 Next active device 8 */ + u32 aslp; /* Offset 160 ASL sleep timeout */ + u32 tidx; /* Offset 164 Toggle table index */ + u32 chpd; /* Offset 168 Current hot plug enable indicator */ + u32 clid; /* Offset 172 Current lid state indicator */ + u32 cdck; /* Offset 176 Current docking state indicator */ + u32 sxsw; /* Offset 180 Display Switch notification on Sx State + * resume + */ + u32 evts; /* Offset 184 Events supported by ASL */ + u32 cnot; /* Offset 188 Current OS Notification */ + u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ + u32 ddl9; /* Offset 196 Extended Supported display device 1 */ + u32 dd10; /* Offset 200 Extended Supported display device 2 */ + u32 dd11; /* Offset 204 Extended Supported display device 3 */ + u32 dd12; /* Offset 208 Extended Supported display device 4 */ + u32 dd13; /* Offset 212 Extended Supported display device 5 */ + u32 dd14; /* Offset 216 Extended Supported display device 6 */ + u32 dd15; /* Offset 220 Extended Supported display device 7 */ + u32 cpl9; /* Offset 224 Extended Currently present device 1 */ + u32 cp10; /* Offset 228 Extended Currently present device 2 */ + u32 cp11; /* Offset 232 Extended Currently present device 3 */ + u32 cp12; /* Offset 236 Extended Currently present device 4 */ + u32 cp13; /* Offset 240 Extended Currently present device 5 */ + u32 cp14; /* Offset 244 Extended Currently present device 6 */ + u32 cp15; /* Offset 248 Extended Currently present device 7 */ + u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ +}; + +/* mailbox 2: software sci interface */ +struct __packed opregion_mailbox2 { + u32 scic; /* Offset 0 Software SCI function number parameters */ + u32 parm; /* Offset 4 Software SCI function number parameters */ + u32 dslp; /* Offset 8 Driver sleep timeout */ + u8 reserved[244]; /* Offset 12 Reserved */ +}; + +/* mailbox 3: power conservation */ +struct __packed opregion_mailbox3 { + u32 ardy; /* Offset 0 Driver readiness */ + u32 aslc; /* Offset 4 ASLE interrupt command / status */ + u32 tche; /* Offset 8 Technology enabled indicator */ + u32 alsi; /* Offset 12 Current ALS illuminance reading */ + u32 bclp; /* Offset 16 Backlight britness to set */ + u32 pfit; /* Offset 20 Panel fitting Request */ + u32 cblv; /* Offset 24 Brightness Current State */ + /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */ + u16 bclm[20]; + u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ + u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ + u8 plut[74]; /* Offset 76 Panel Look Up Table */ + /* Offset 150 PWM Frequency and Minimum Brightness */ + u32 pfmb; + u32 ccdv; /* Offset 154 Color Correction Default Values */ + u32 pcft; /* Offset 158 Power Conservation Features */ + u32 srot; /* Offset 162 Supported Rotation angle */ + u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ + u64 fdsp; /* Offset 170 FFS Display Physical address */ + u32 fdss; /* Offset 178 FFS Display Size */ + u32 stat; /* Offset 182 State Indicator */ + /* + * Offset 186 (Igd opregion offset 0x3BAh) + * Physical address of Raw VBT data + */ + u64 rvda; + /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */ + u32 rvds; + u8 reserved[58]; /* Offset 198 Reserved */ +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID BIT(31) +#define IGD_WORD_FIELD_VALID BIT(15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +struct __packed opregion_vbt { + u8 gvd1[6 << 10]; +}; + +/* Mailbox 5: BIOS to Driver Notification Extension */ +struct __packed opregion_mailbox5 { + u32 phed; /* Offset 7168 Panel Header */ + u8 bddc[256]; /* Offset 7172 Panel EDID */ + u8 reserved[764]; /* Offset 7428 764 bytes */ +}; + +/* IGD OpRegion */ +struct __packed igd_opregion { + struct opregion_header header; + struct opregion_mailbox1 mailbox1; + struct opregion_mailbox2 mailbox2; + struct opregion_mailbox3 mailbox3; + struct opregion_vbt vbt; + struct opregion_mailbox5 mailbox5; +}; + +/* Intel Video BIOS (Option ROM) */ +struct __packed optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +struct __packed optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +struct __packed optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +/** + * intel_gma_init_igd_opregion() - Initialise IGD OpRegion + * + * This is called from ACPI code and OS drivers + * + * @return 0 if OK, -ve on error + */ +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion); + +#endif /* _ASM_INTEL_OPREGION_H_ */ diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 48db1dd82f..3a98aacdef 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -36,8 +36,8 @@ #define MTRR_BASE_TYPE_MASK 0x7 -/* Number of MTRRs supported */ -#define MTRR_COUNT 8 +/* Maximum number of MTRRs supported - see also mtrr_get_var_count() */ +#define MTRR_MAX_COUNT 10 #define NUM_FIXED_MTRRS 11 #define RANGES_PER_FIXED_MTRR 8 @@ -87,7 +87,7 @@ struct mtrr { * @mtrr: Information about each mtrr */ struct mtrr_info { - struct mtrr mtrr[MTRR_COUNT]; + struct mtrr mtrr[MTRR_MAX_COUNT]; }; /** @@ -180,6 +180,15 @@ int mtrr_set_valid(int cpu_select, int reg, bool valid); */ int mtrr_set(int cpu_select, int reg, u64 base, u64 mask); +/** + * mtrr_get_var_count() - Get the number of variable MTRRs + * + * Some CPUs have more than 8 MTRRs. This function returns the actual number + * + * @return number of variable MTRRs + */ +int mtrr_get_var_count(void); + #endif #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) diff --git a/arch/x86/include/asm/smm.h b/arch/x86/include/asm/smm.h new file mode 100644 index 0000000000..1e539fda06 --- /dev/null +++ b/arch/x86/include/asm/smm.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SMM definitions (U-Boot does not support SMM itself) + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2019 Google LLC + * + * Modified from coreboot smm.h + */ + +#ifndef _ASM_SMM_H +#define _ASM_SMM_H + +#define APM_CNT 0xb2 +#define APM_CNT_CST_CONTROL 0x85 +#define APM_CNT_PST_CONTROL 0x80 +#define APM_CNT_ACPI_DISABLE 0x1e +#define APM_CNT_ACPI_ENABLE 0xe1 +#define APM_CNT_MBI_UPDATE 0xeb +#define APM_CNT_GNVS_UPDATE 0xea +#define APM_CNT_FINALIZE 0xcb +#define APM_CNT_LEGACY 0xcc +#define APM_CNT_SMMSTORE 0xed +#define APM_CNT_ELOG_GSMI 0xef +#define APM_STS 0xb3 + +#endif /* _ASM_SMM_H */ diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 80e128ccf3..64c0e6e857 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -30,10 +30,38 @@ #define BZIMAGE_LOAD_ADDR 0x100000 #define ZIMAGE_LOAD_ADDR 0x10000 +/** + * load_zimage() - Load a zImage or bzImage + * + * This copies an image into the standard location ready for setup + * + * @image: Address of image to load + * @kernel_size: Size of kernel including setup block (or 0 if the kernel is + * new enough to have a 'syssize' value) + * @load_addressp: Returns the address where the kernel has been loaded + * @return address of setup block, or NULL if something went wrong + */ struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp); + +/** + * setup_zimage() - Set up a loaded zImage or bzImage ready for booting + * + * @setup_base: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + * @cmd_line: Place to put the command line, or NULL to use the one in the setup + * block + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @load_address: Address where the bzImage is moved before booting, either + * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR + * @cmdline_force: Address of 'override' command line, or 0 to use the one in + * the * setup block + * @return 0 (always) + */ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, - unsigned long initrd_addr, unsigned long initrd_size); + ulong initrd_addr, ulong initrd_size, ulong cmdline_force); + void setup_video(struct screen_info *screen_info); void setup_efi_info(struct efi_info *efi_info); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 1185a88c27..1bcbb49a61 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -38,6 +38,7 @@ obj-y += sfi.o obj-y += acpi.o obj-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.o ifndef CONFIG_QEMU +obj-y += acpigen.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi_table.o endif obj-y += tables.o diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index c445aa6870..6d405b09fd 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -6,7 +6,10 @@ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> */ +#define LOG_CATEGORY LOGC_ACPI + #include <common.h> +#include <bloblist.h> #include <cpu.h> #include <dm.h> #include <log.h> @@ -15,6 +18,7 @@ #include <serial.h> #include <version.h> #include <acpi/acpigen.h> +#include <acpi/acpi_device.h> #include <acpi/acpi_table.h> #include <asm/acpi/global_nvs.h> #include <asm/ioapic.h> @@ -65,14 +69,17 @@ int acpi_create_madt_lapics(u32 current) { struct udevice *dev; int total_length = 0; + int cpu_num = 0; for (uclass_find_first_device(UCLASS_CPU, &dev); dev; uclass_find_next_device(&dev)) { struct cpu_platdata *plat = dev_get_parent_platdata(dev); - int length = acpi_create_madt_lapic( - (struct acpi_madt_lapic *)current, - plat->cpu_id, plat->cpu_id); + int length; + + length = acpi_create_madt_lapic( + (struct acpi_madt_lapic *)current, cpu_num++, + plat->cpu_id); current += length; total_length += length; } @@ -210,6 +217,105 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); } +/** + * acpi_create_tcpa() - Create a TCPA table + * + * @tcpa: Pointer to place to put table + * + * Trusted Computing Platform Alliance Capabilities Table + * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI + * Firmware Specification 3.0 + */ +static int acpi_create_tcpa(struct acpi_tcpa *tcpa) +{ + struct acpi_table_header *header = &tcpa->header; + u32 current = (u32)tcpa + sizeof(struct acpi_tcpa); + int size = 0x10000; /* Use this as the default size */ + void *log; + int ret; + + if (!CONFIG_IS_ENABLED(BLOBLIST)) + return -ENXIO; + memset(tcpa, '\0', sizeof(struct acpi_tcpa)); + + /* Fill out header fields */ + acpi_fill_header(header, "TCPA"); + header->length = sizeof(struct acpi_tcpa); + header->revision = 1; + + ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log); + if (ret) + return log_msg_ret("blob", ret); + + tcpa->platform_class = 0; + tcpa->laml = size; + tcpa->lasa = (ulong)log; + + /* (Re)calculate length and checksum */ + header->length = current - (u32)tcpa; + header->checksum = table_compute_checksum((void *)tcpa, header->length); + + return 0; +} + +static int get_tpm2_log(void **ptrp, int *sizep) +{ + const int tpm2_default_log_len = 0x10000; + int size; + int ret; + + *sizep = 0; + size = tpm2_default_log_len; + ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp); + if (ret) + return log_msg_ret("blob", ret); + *sizep = size; + + return 0; +} + +static int acpi_create_tpm2(struct acpi_tpm2 *tpm2) +{ + struct acpi_table_header *header = &tpm2->header; + int tpm2_log_len; + void *lasa; + int ret; + + memset((void *)tpm2, 0, sizeof(struct acpi_tpm2)); + + /* + * Some payloads like SeaBIOS depend on log area to use TPM2. + * Get the memory size and address of TPM2 log area or initialize it. + */ + ret = get_tpm2_log(&lasa, &tpm2_log_len); + if (ret) + return ret; + + /* Fill out header fields. */ + acpi_fill_header(header, "TPM2"); + memcpy(header->aslc_id, ASLC_ID, 4); + + header->length = sizeof(struct acpi_tpm2); + header->revision = acpi_get_table_revision(ACPITAB_TPM2); + + /* Hard to detect for coreboot. Just set it to 0 */ + tpm2->platform_class = 0; + + /* Must be set to 0 for FIFO-interface support */ + tpm2->control_area = 0; + tpm2->start_method = 6; + memset(tpm2->msp, 0, sizeof(tpm2->msp)); + + /* Fill the log area size and start address fields. */ + tpm2->laml = tpm2_log_len; + tpm2->lasa = (uintptr_t)lasa; + + /* Calculate checksum. */ + header->checksum = table_compute_checksum((void *)tpm2, header->length); + + return 0; +} + __weak u32 acpi_fill_csrt(u32 current) { return 0; @@ -394,11 +500,13 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_fadt *fadt; struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; + struct acpi_tcpa *tcpa; struct acpi_madt *madt; struct acpi_csrt *csrt; struct acpi_spcr *spcr; void *start; ulong addr; + int ret; int i; start = map_sysmem(start_addr, 0); @@ -430,17 +538,31 @@ ulong write_acpi_tables(ulong start_addr) dsdt->length - sizeof(struct acpi_table_header)); acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header)); + dsdt->length = ctx->current - (void *)dsdt; + acpi_align(ctx); - /* Pack GNVS into the ACPI table area */ - for (i = 0; i < dsdt->length; i++) { - u32 *gnvs = (u32 *)((u32)dsdt + i); - if (*gnvs == ACPI_GNVS_ADDR) { - ulong addr = (ulong)map_to_sysmem(ctx->current); - - debug("Fix up global NVS in DSDT to %#08lx\n", addr); - *gnvs = addr; - break; + if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) { + /* Pack GNVS into the ACPI table area */ + for (i = 0; i < dsdt->length; i++) { + u32 *gnvs = (u32 *)((u32)dsdt + i); + + if (*gnvs == ACPI_GNVS_ADDR) { + *gnvs = map_to_sysmem(ctx->current); + debug("Fix up global NVS in DSDT to %#08x\n", + *gnvs); + break; + } } + + /* + * Fill in platform-specific global NVS variables. If this fails + * we cannot return the error but this should only happen while + * debugging. + */ + addr = acpi_create_gnvs(ctx->current); + if (IS_ERR_VALUE(addr)) + printf("Error: Gailed to create GNVS\n"); + acpi_inc_align(ctx, sizeof(struct acpi_global_nvs)); } /* @@ -448,12 +570,9 @@ ulong write_acpi_tables(ulong start_addr) * the GNVS address. Set the checksum to zero since it is part of the * region being checksummed. */ - dsdt->length = ctx->current - (void *)dsdt; dsdt->checksum = 0; dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); - acpi_align(ctx); - /* * Fill in platform-specific global NVS variables. If this fails we * cannot return the error but this should only happen while debugging. @@ -484,12 +603,36 @@ ulong write_acpi_tables(ulong start_addr) acpi_inc_align(ctx, mcfg->header.length); acpi_add_table(ctx, mcfg); + if (IS_ENABLED(CONFIG_TPM_V2)) { + struct acpi_tpm2 *tpm2; + + debug("ACPI: * TPM2\n"); + tpm2 = (struct acpi_tpm2 *)ctx->current; + ret = acpi_create_tpm2(tpm2); + if (!ret) { + acpi_inc_align(ctx, tpm2->header.length); + acpi_add_table(ctx, tpm2); + } else { + log_warning("TPM2 table creation failed\n"); + } + } + debug("ACPI: * MADT\n"); madt = ctx->current; acpi_create_madt(madt); acpi_inc_align(ctx, madt->header.length); acpi_add_table(ctx, madt); + debug("ACPI: * TCPA\n"); + tcpa = (struct acpi_tcpa *)ctx->current; + ret = acpi_create_tcpa(tcpa); + if (ret) { + log_warning("Failed to create TCPA table (err=%d)\n", ret); + } else { + acpi_inc_align(ctx, tcpa->header.length); + acpi_add_table(ctx, tcpa); + } + debug("ACPI: * CSRT\n"); csrt = ctx->current; if (!acpi_create_csrt(csrt)) { @@ -518,3 +661,213 @@ ulong acpi_get_rsdp_addr(void) { return acpi_rsdp_addr; } + +/** + * acpi_write_hpet() - Write out a HPET table + * + * Write out the table for High-Precision Event Timers + * + * @hpet: Place to put HPET table + */ +static int acpi_create_hpet(struct acpi_hpet *hpet) +{ + struct acpi_table_header *header = &hpet->header; + struct acpi_gen_regaddr *addr = &hpet->addr; + + /* + * See IA-PC HPET (High Precision Event Timers) Specification v1.0a + * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf + */ + memset((void *)hpet, '\0', sizeof(struct acpi_hpet)); + + /* Fill out header fields. */ + acpi_fill_header(header, "HPET"); + + header->aslc_revision = ASL_REVISION; + header->length = sizeof(struct acpi_hpet); + header->revision = acpi_get_table_revision(ACPITAB_HPET); + + /* Fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; + addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32; + + hpet->id = *(u32 *)CONFIG_HPET_ADDRESS; + hpet->number = 0; + hpet->min_tick = 0; /* HPET_MIN_TICKS */ + + header->checksum = table_compute_checksum(hpet, + sizeof(struct acpi_hpet)); + + return 0; +} + +int acpi_write_hpet(struct acpi_ctx *ctx) +{ + struct acpi_hpet *hpet; + int ret; + + log_debug("ACPI: * HPET\n"); + + hpet = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_hpet)); + acpi_create_hpet(hpet); + ret = acpi_add_table(ctx, hpet); + if (ret) + return log_msg_ret("add", ret); + + return 0; +} + +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size) +{ + struct acpi_dbg2_header *dbg2 = ctx->current; + char path[ACPI_PATH_MAX]; + struct acpi_gen_regaddr address; + phys_addr_t addr; + int ret; + + if (!device_active(dev)) { + log_info("Device not enabled\n"); + return -EACCES; + } + /* + * PCI devices don't remember their resource allocation information in + * U-Boot at present. We assume that MMIO is used for the UART and that + * the address space is 32 bytes: ns16550 uses 8 registers of up to + * 32-bits each. This is only for debugging so it is not a big deal. + */ + addr = dm_pci_read_bar32(dev, 0); + printf("UART addr %lx\n", (ulong)addr); + + memset(&address, '\0', sizeof(address)); + address.space_id = ACPI_ADDRESS_SPACE_MEMORY; + address.addrl = (uint32_t)addr; + address.addrh = (uint32_t)((addr >> 32) & 0xffffffff); + address.access_size = access_size; + + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT, + ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path); + + acpi_inc_align(ctx, dbg2->header.length); + acpi_add_table(ctx, dbg2); + + return 0; +} + +void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &fadt->header; + + memset((void *)fadt, '\0', sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->aslc_id, ASLC_ID, 4); + header->aslc_revision = 1; + + fadt->firmware_ctrl = (unsigned long)facs; + fadt->dsdt = (unsigned long)dsdt; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + + /* Use ACPI 3.0 revision */ + fadt->header.revision = 4; +} + +void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment, + u64 bar) +{ + struct dmar_entry *drhd = ctx->current; + + memset(drhd, '\0', sizeof(*drhd)); + drhd->type = DMAR_DRHD; + drhd->length = sizeof(*drhd); /* will be fixed up later */ + drhd->flags = flags; + drhd->segment = segment; + drhd->bar = bar; + acpi_inc(ctx, drhd->length); +} + +void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar, + u64 limit) +{ + struct dmar_rmrr_entry *rmrr = ctx->current; + + memset(rmrr, '\0', sizeof(*rmrr)); + rmrr->type = DMAR_RMRR; + rmrr->length = sizeof(*rmrr); /* will be fixed up later */ + rmrr->segment = segment; + rmrr->bar = bar; + rmrr->limit = limit; + acpi_inc(ctx, rmrr->length); +} + +void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base) +{ + struct dmar_entry *drhd = base; + + drhd->length = ctx->current - base; +} + +void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base) +{ + struct dmar_rmrr_entry *rmrr = base; + + rmrr->length = ctx->current - base; +} + +static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type, + uint enumeration_id, pci_dev_t bdf) +{ + /* we don't support longer paths yet */ + const size_t dev_scope_length = sizeof(struct dev_scope) + 2; + struct dev_scope *ds = ctx->current; + + memset(ds, '\0', dev_scope_length); + ds->type = type; + ds->length = dev_scope_length; + ds->enumeration = enumeration_id; + ds->start_bus = PCI_BUS(bdf); + ds->path[0].dev = PCI_DEV(bdf); + ds->path[0].fn = PCI_FUNC(bdf); + + return ds->length; +} + +int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf); +} + +int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf); +} + +int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf); +} + +int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf); +} diff --git a/arch/x86/lib/acpigen.c b/arch/x86/lib/acpigen.c new file mode 100644 index 0000000000..ea2ec2a908 --- /dev/null +++ b/arch/x86/lib/acpigen.c @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Google LLC + */ + +#include <common.h> +#include <acpi/acpigen.h> +#include <acpi/acpi_table.h> +#include <asm/acpigen.h> + +void acpigen_write_empty_pct(struct acpi_ctx *ctx) +{ + /* + * Name (_PCT, Package (0x02) + * { + * ResourceTemplate () + * { + * Register (FFixedHW, + * 0x00, // Bit Width + * 0x00, // Bit Offset + * 0x0000000000000000, // Address + * ,) + * }, + * + * ResourceTemplate () + * { + * Register (FFixedHW, + * 0x00, // Bit Width + * 0x00, // Bit Offset + * 0x0000000000000000, // Address + * ,) + * } + * }) + */ + static char stream[] = { + /* 00000030 "0._PCT.," */ + 0x08, 0x5f, 0x50, 0x43, 0x54, 0x12, 0x2c, + /* 00000038 "........" */ + 0x02, 0x11, 0x14, 0x0a, 0x11, 0x82, 0x0c, 0x00, + /* 00000040 "........" */ + 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000048 "....y..." */ + 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, + /* 00000050 "........" */ + 0x0a, 0x11, 0x82, 0x0c, 0x00, 0x7f, 0x00, 0x00, + /* 00000058 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x79, 0x00 + }; + acpigen_emit_stream(ctx, stream, ARRAY_SIZE(stream)); +} + +void acpigen_write_empty_ptc(struct acpi_ctx *ctx) +{ + /* + * Name (_PTC, Package (0x02) + * { + * ResourceTemplate () + * { + * Register (FFixedHW, + * 0x00, // Bit Width + * 0x00, // Bit Offset + * 0x0000000000000000, // Address + * ,) + * }, + * + * ResourceTemplate () + * { + * Register (FFixedHW, + * 0x00, // Bit Width + * 0x00, // Bit Offset + * 0x0000000000000000, // Address + * ,) + * } + * }) + */ + struct acpi_gen_regaddr addr = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + .bit_width = 0, + .bit_offset = 0, + .access_size = 0, + .addrl = 0, + .addrh = 0, + }; + + acpigen_write_name(ctx, "_PTC"); + acpigen_write_package(ctx, 2); + + /* ControlRegister */ + acpigen_write_register_resource(ctx, &addr); + + /* StatusRegister */ + acpigen_write_register_resource(ctx, &addr); + + acpigen_pop_len(ctx); +} diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 1198a52eca..da6b8ce1ec 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -136,7 +136,7 @@ static int boot_prep_linux(bootm_headers_t *images) printf("Setup at %#08lx\n", images->ep); ret = setup_zimage((void *)images->ep, cmd_line_dest, 0, images->rd_start, - images->rd_end - images->rd_start); + images->rd_end - images->rd_start, 0); if (ret) { printf("## Setting up boot parameters failed ...\n"); diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index ea52954725..4061fa244c 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -60,6 +60,22 @@ void board_final_init(void) debug("OK\n"); } +void board_final_cleanup(void) +{ + u32 status; + + /* TODO(sjg@chromium.org): This causes Linux to crash */ + return; + + /* call into FspNotify */ + debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): "); + status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE); + if (status) + debug("fail, error code %x\n", status); + else + debug("OK\n"); +} + int fsp_save_s3_stack(void) { struct udevice *dev; diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index faa819fab4..a76497d4e0 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -12,6 +12,7 @@ #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/post.h> +#include <dm/ofnode.h> DECLARE_GLOBAL_DATA_PTR; @@ -92,6 +93,8 @@ unsigned int install_e820_map(unsigned int max_entries, unsigned int num_entries = 0; const struct hob_header *hdr; struct hob_res_desc *res_desc; + const fdt64_t *prop; + int size; hdr = gd->arch.hob_list; @@ -133,6 +136,20 @@ unsigned int install_e820_map(unsigned int max_entries, num_entries++; } + prop = ofnode_read_chosen_prop("e820-entries", &size); + if (prop) { + int count = size / (sizeof(u64) * 3); + int i; + + if (num_entries + count >= max_entries) + return -ENOSPC; + for (i = 0; i < count; i++, num_entries++, prop += 3) { + entries[num_entries].addr = fdt64_to_cpu(prop[0]); + entries[num_entries].size = fdt64_to_cpu(prop[1]); + entries[num_entries].type = fdt64_to_cpu(prop[2]); + } + } + return num_entries; } diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index e8c1e07af1..858d7942fe 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -3,14 +3,19 @@ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> */ +#define LOG_CATEGORY UCLASS_VIDEO + #include <common.h> #include <dm.h> #include <init.h> #include <log.h> #include <vbe.h> #include <video.h> +#include <acpi/acpi_table.h> #include <asm/fsp/fsp_support.h> +#include <asm/intel_opregion.h> #include <asm/mtrr.h> +#include <dm/acpi.h> DECLARE_GLOBAL_DATA_PTR; @@ -127,6 +132,32 @@ static int fsp_video_bind(struct udevice *dev) return 0; } +#ifdef CONFIG_INTEL_GMA_ACPI +static int fsp_video_acpi_write_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct igd_opregion *opregion; + int ret; + + printf("ACPI: * IGD OpRegion\n"); + opregion = (struct igd_opregion *)ctx->current; + + ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion); + if (ret) + return ret; + + acpi_inc_align(ctx, sizeof(struct igd_opregion)); + + return 0; +} +#endif + +struct acpi_ops fsp_video_acpi_ops = { +#ifdef CONFIG_INTEL_GMA_ACPI + .write_tables = fsp_video_acpi_write_tables, +#endif +}; + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -139,6 +170,7 @@ U_BOOT_DRIVER(fsp_video) = { .bind = fsp_video_bind, .probe = fsp_video_probe, .flags = DM_FLAG_PRE_RELOC, + ACPI_OPS_PTR(&fsp_video_acpi_ops) }; static struct pci_device_id fsp_video_supported[] = { diff --git a/arch/x86/lib/fsp2/fsp_silicon_init.c b/arch/x86/lib/fsp2/fsp_silicon_init.c index 0f221a864f..ead3493de8 100644 --- a/arch/x86/lib/fsp2/fsp_silicon_init.c +++ b/arch/x86/lib/fsp2/fsp_silicon_init.c @@ -26,8 +26,10 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash) struct binman_entry entry; struct udevice *dev; ulong rom_offset = 0; + u32 init_addr; int ret; + log_debug("Locating FSP\n"); ret = fsp_locate_fsp(FSP_S, &entry, use_spi_flash, &dev, &hdr, &rom_offset); if (ret) @@ -44,7 +46,7 @@ int fsp_silicon_init(bool s3wake, bool use_spi_flash) ret = fsps_update_config(dev, rom_offset, &upd); if (ret) return log_msg_ret("Could not setup config", ret); - log_debug("Silicon init..."); + log_debug("Silicon init @ %x...", init_addr); bootstage_start(BOOTSTAGE_ID_ACCUM_FSP_S, "fsp-s"); func = (fsp_silicon_init_func)(hdr->img_base + hdr->fsp_silicon_init); ret = func(&upd); diff --git a/arch/x86/lib/fsp2/fsp_support.c b/arch/x86/lib/fsp2/fsp_support.c index 3f2ca840dc..f220ef498b 100644 --- a/arch/x86/lib/fsp2/fsp_support.c +++ b/arch/x86/lib/fsp2/fsp_support.c @@ -35,7 +35,8 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, * * You are in a maze of twisty little headers all alike. */ - debug("offset=%x buf=%x\n", (uint)offset, (uint)buf); + log_debug("offset=%x buf=%x, use_spi_flash=%d\n", (uint)offset, + (uint)buf, use_spi_flash); if (use_spi_flash) { ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); if (ret) @@ -52,16 +53,16 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, fv = ptr; /* Check the FV signature, _FVH */ - debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign); + log_debug("offset=%x sign=%x\n", (uint)offset, (uint)fv->sign); if (fv->sign != EFI_FVH_SIGNATURE) return log_msg_ret("Base FV signature", -EINVAL); /* Go to the end of the FV header and align the address */ - debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off); + log_debug("fv->ext_hdr_off = %x\n", fv->ext_hdr_off); ptr += fv->ext_hdr_off; exhdr = ptr; ptr += ALIGN(exhdr->ext_hdr_size, 8); - debug("ptr=%x\n", ptr - (void *)buf); + log_debug("ptr=%x\n", ptr - (void *)buf); /* Check the FFS GUID */ file_hdr = ptr; @@ -71,7 +72,7 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, ptr = file_hdr + 1; raw = ptr; - debug("raw->type = %x\n", raw->type); + log_debug("raw->type = %x\n", raw->type); if (raw->type != EFI_SECTION_RAW) return log_msg_ret("Section type not RAW", -ENOEXEC); @@ -80,13 +81,18 @@ int fsp_get_header(ulong offset, ulong size, bool use_spi_flash, fsp = ptr; /* Check the FSPH header */ - debug("fsp %x\n", (uint)fsp); + log_debug("fsp %x, fsp-buf=%x, si=%x\n", (uint)fsp, ptr - (void *)buf, + (void *)&fsp->fsp_silicon_init - (void *)buf); if (fsp->sign != EFI_FSPH_SIGNATURE) return log_msg_ret("Base FSPH signature", -EACCES); base = (void *)fsp->img_base; - debug("Image base %x\n", (uint)base); - debug("Image addr %x\n", (uint)fsp->fsp_mem_init); + log_debug("image base %x\n", (uint)base); + if (fsp->fsp_mem_init) + log_debug("mem_init offset %x\n", (uint)fsp->fsp_mem_init); + else if (fsp->fsp_silicon_init) + log_debug("silicon_init offset %x\n", + (uint)fsp->fsp_silicon_init); if (use_spi_flash) { ret = spi_flash_read_dm(dev, offset, size, base); if (ret) diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index d2b6002008..a00964cc8d 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -45,6 +45,42 @@ #define COMMAND_LINE_SIZE 2048 +/** + * struct zboot_state - Current state of the boot + * + * @bzimage_addr: Address of the bzImage to boot + * @bzimage_size: Size of the bzImage, or 0 to detect this + * @initrd_addr: Address of the initial ramdisk, or 0 if none + * @initrd_size: Size of the initial ramdisk, or 0 if none + * @load_address: Address where the bzImage is moved before booting, either + * BZIMAGE_LOAD_ADDR or ZIMAGE_LOAD_ADDR + * @base_ptr: Pointer to the boot parameters, typically at address + * DEFAULT_SETUP_BASE + * @cmdline: Address of 'override' command line, or 0 to use the one in the + * setup block + */ +struct zboot_state { + ulong bzimage_addr; + ulong bzimage_size; + ulong initrd_addr; + ulong initrd_size; + ulong load_address; + struct boot_params *base_ptr; + ulong cmdline; +} state; + +enum { + ZBOOT_STATE_START = BIT(0), + ZBOOT_STATE_LOAD = BIT(1), + ZBOOT_STATE_SETUP = BIT(2), + ZBOOT_STATE_INFO = BIT(3), + ZBOOT_STATE_GO = BIT(4), + + /* This one doesn't execute automatically, so stop the count before 5 */ + ZBOOT_STATE_DUMP = BIT(5), + ZBOOT_STATE_COUNT = 5, +}; + static void build_command_line(char *command_line, int auto_boot) { char *env_command_line; @@ -85,21 +121,23 @@ static int kernel_magic_ok(struct setup_header *hdr) } } -static int get_boot_protocol(struct setup_header *hdr) +static int get_boot_protocol(struct setup_header *hdr, bool verbose) { if (hdr->header == KERNEL_V2_MAGIC) { - printf("Magic signature found\n"); + if (verbose) + printf("Magic signature found\n"); return hdr->version; } else { /* Very old kernel */ - printf("Magic signature not found\n"); + if (verbose) + printf("Magic signature not found\n"); return 0x0100; } } static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob) { - int bootproto = get_boot_protocol(hdr); + int bootproto = get_boot_protocol(hdr, false); struct setup_data *sd; int size; @@ -129,10 +167,24 @@ static int setup_device_tree(struct setup_header *hdr, const void *fdt_blob) return 0; } +static const char *get_kernel_version(struct boot_params *params, + void *kernel_base) +{ + struct setup_header *hdr = ¶ms->hdr; + int bootproto; + + bootproto = get_boot_protocol(hdr, false); + if (bootproto < 0x0200 || hdr->setup_sects < 15) + return NULL; + + return kernel_base + hdr->kernel_version + 0x200; +} + struct boot_params *load_zimage(char *image, unsigned long kernel_size, ulong *load_addressp) { struct boot_params *setup_base; + const char *version; int setup_size; int bootproto; int big_image; @@ -160,21 +212,16 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, printf("Error: Setup is too large (%d bytes)\n", setup_size); /* determine boot protocol version */ - bootproto = get_boot_protocol(hdr); + bootproto = get_boot_protocol(hdr, true); printf("Using boot protocol version %x.%02x\n", (bootproto & 0xff00) >> 8, bootproto & 0xff); - if (bootproto >= 0x0200) { - if (hdr->setup_sects >= 15) { - printf("Linux kernel version %s\n", - (char *)params + - hdr->kernel_version + 0x200); - } else { - printf("Setup Sectors < 15 - " - "Cannot print kernel version.\n"); - } - } + version = get_kernel_version(params, image); + if (version) + printf("Linux kernel version %s\n", version); + else + printf("Setup Sectors < 15 - Cannot print kernel version\n"); /* Determine image type */ big_image = (bootproto >= 0x0200) && @@ -240,10 +287,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, } int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, - unsigned long initrd_addr, unsigned long initrd_size) + ulong initrd_addr, ulong initrd_size, ulong cmdline_force) { struct setup_header *hdr = &setup_base->hdr; - int bootproto = get_boot_protocol(hdr); + int bootproto = get_boot_protocol(hdr, false); setup_base->e820_entries = install_e820_map( ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map); @@ -253,8 +300,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, setup_base->screen_info.cl_offset = COMMAND_LINE_OFFSET; } if (bootproto >= 0x0200) { - hdr->type_of_loader = 8; - + hdr->type_of_loader = 0x80; /* U-Boot version 0 */ if (initrd_addr) { printf("Initial RAM disk at linear address " "0x%08lx, size %ld bytes\n", @@ -282,40 +328,33 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, } /* build command line at COMMAND_LINE_OFFSET */ - build_command_line(cmd_line, auto_boot); + if (cmdline_force) + strcpy(cmd_line, (char *)cmdline_force); + else + build_command_line(cmd_line, auto_boot); } -#ifdef CONFIG_INTEL_MID - if (bootproto >= 0x0207) + if (IS_ENABLED(CONFIG_INTEL_MID) && bootproto >= 0x0207) hdr->hardware_subarch = X86_SUBARCH_INTEL_MID; -#endif -#ifdef CONFIG_GENERATE_ACPI_TABLE - setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr(); -#endif + if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) + setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr(); setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0)); setup_video(&setup_base->screen_info); -#ifdef CONFIG_EFI_STUB - setup_efi_info(&setup_base->efi_info); -#endif + if (IS_ENABLED(CONFIG_EFI_STUB)) + setup_efi_info(&setup_base->efi_info); return 0; } -int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int do_zboot_start(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) { - struct boot_params *base_ptr; - void *bzImage_addr = NULL; - ulong load_address; - char *s; - ulong bzImage_size = 0; - ulong initrd_addr = 0; - ulong initrd_size = 0; - - disable_interrupts(); + const char *s; + memset(&state, '\0', sizeof(state)); if (argc >= 2) { /* argv[1] holds the address of the bzImage */ s = argv[1]; @@ -324,39 +363,361 @@ int do_zboot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } if (s) - bzImage_addr = (void *)simple_strtoul(s, NULL, 16); + state.bzimage_addr = simple_strtoul(s, NULL, 16); if (argc >= 3) { /* argv[2] holds the size of the bzImage */ - bzImage_size = simple_strtoul(argv[2], NULL, 16); + state.bzimage_size = simple_strtoul(argv[2], NULL, 16); } if (argc >= 4) - initrd_addr = simple_strtoul(argv[3], NULL, 16); + state.initrd_addr = simple_strtoul(argv[3], NULL, 16); if (argc >= 5) - initrd_size = simple_strtoul(argv[4], NULL, 16); + state.initrd_size = simple_strtoul(argv[4], NULL, 16); + if (argc >= 6) { + /* + * When the base_ptr is passed in, we assume that the image is + * already loaded at the address given by argv[1] and therefore + * the original bzImage is somewhere else, or not accessible. + * In any case, we don't need access to the bzImage since all + * the processing is assumed to be done. + * + * So set the base_ptr to the given address, use this arg as the + * load address and set bzimage_addr to 0 so we know that it + * cannot be proceesed (or processed again). + */ + state.base_ptr = (void *)simple_strtoul(argv[5], NULL, 16); + state.load_address = state.bzimage_addr; + state.bzimage_addr = 0; + } + if (argc >= 7) + state.cmdline = simple_strtoul(argv[6], NULL, 16); + + return 0; +} + +static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct boot_params *base_ptr; + + if (state.base_ptr) { + struct boot_params *from = (struct boot_params *)state.base_ptr; + + base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE; + printf("Building boot_params at 0x%8.8lx\n", (ulong)base_ptr); + memset(base_ptr, '\0', sizeof(*base_ptr)); + base_ptr->hdr = from->hdr; + } else { + base_ptr = load_zimage((void *)state.bzimage_addr, state.bzimage_size, + &state.load_address); + if (!base_ptr) { + puts("## Kernel loading failed ...\n"); + return CMD_RET_FAILURE; + } + } + state.base_ptr = base_ptr; + if (env_set_hex("zbootbase", (ulong)base_ptr) || + env_set_hex("zbootaddr", state.load_address)) + return CMD_RET_FAILURE; - /* Lets look for */ - base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address); + return 0; +} + +static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct boot_params *base_ptr = state.base_ptr; + int ret; if (!base_ptr) { - puts("## Kernel loading failed ...\n"); - return -1; + printf("base is not set: use 'zboot load' first\n"); + return CMD_RET_FAILURE; } - if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, - 0, initrd_addr, initrd_size)) { + ret = setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, + 0, state.initrd_addr, state.initrd_size, + state.cmdline); + if (ret) { puts("Setting up boot parameters failed ...\n"); - return -1; + return CMD_RET_FAILURE; } + return 0; +} + +static int do_zboot_info(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + printf("Kernel loaded at %08lx, setup_base=%p\n", + state.load_address, state.base_ptr); + + return 0; +} + +static int do_zboot_go(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret; + + disable_interrupts(); + /* we assume that the kernel is in place */ - return boot_linux_kernel((ulong)base_ptr, load_address, false); + ret = boot_linux_kernel((ulong)state.base_ptr, state.load_address, + false); + printf("Kernel returned! (err=%d)\n", ret); + + return CMD_RET_FAILURE; +} + +static void print_num(const char *name, ulong value) +{ + printf("%-20s: %lx\n", name, value); +} + +static void print_num64(const char *name, u64 value) +{ + printf("%-20s: %llx\n", name, value); +} + +static const char *const e820_type_name[E820_COUNT] = { + [E820_RAM] = "RAM", + [E820_RESERVED] = "Reserved", + [E820_ACPI] = "ACPI", + [E820_NVS] = "ACPI NVS", + [E820_UNUSABLE] = "Unusable", +}; + +static const char *const bootloader_id[] = { + "LILO", + "Loadlin", + "bootsect-loader", + "Syslinux", + "Etherboot/gPXE/iPXE", + "ELILO", + "undefined", + "GRUB", + "U-Boot", + "Xen", + "Gujin", + "Qemu", + "Arcturus Networks uCbootloader", + "kexec-tools", + "Extended", + "Special", + "Reserved", + "Minimal Linux Bootloader", + "OVMF UEFI virtualization stack", +}; + +struct flag_info { + uint bit; + const char *name; +}; + +static struct flag_info load_flags[] = { + { LOADED_HIGH, "loaded-high" }, + { QUIET_FLAG, "quiet" }, + { KEEP_SEGMENTS, "keep-segments" }, + { CAN_USE_HEAP, "can-use-heap" }, +}; + +static struct flag_info xload_flags[] = { + { XLF_KERNEL_64, "64-bit-entry" }, + { XLF_CAN_BE_LOADED_ABOVE_4G, "can-load-above-4gb" }, + { XLF_EFI_HANDOVER_32, "32-efi-handoff" }, + { XLF_EFI_HANDOVER_64, "64-efi-handoff" }, + { XLF_EFI_KEXEC, "kexec-efi-runtime" }, +}; + +static void print_flags(struct flag_info *flags, int count, uint value) +{ + int i; + + printf("%-20s:", ""); + for (i = 0; i < count; i++) { + uint mask = flags[i].bit; + + if (value & mask) + printf(" %s", flags[i].name); + } + printf("\n"); +} + +static void show_loader(struct setup_header *hdr) +{ + bool version_valid = false; + int type, version; + const char *name; + + type = hdr->type_of_loader >> 4; + version = hdr->type_of_loader & 0xf; + if (type == 0xe) + type = 0x10 + hdr->ext_loader_type; + version |= hdr->ext_loader_ver << 4; + if (!hdr->type_of_loader) { + name = "pre-2.00 bootloader"; + } else if (hdr->type_of_loader == 0xff) { + name = "unknown"; + } else if (type < ARRAY_SIZE(bootloader_id)) { + name = bootloader_id[type]; + version_valid = true; + } else { + name = "undefined"; + } + printf("%20s %s", "", name); + if (version_valid) + printf(", version %x", version); + printf("\n"); +} + +int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct boot_params *base_ptr = state.base_ptr; + struct setup_header *hdr; + const char *version; + int i; + + if (argc > 1) + base_ptr = (void *)simple_strtoul(argv[1], NULL, 16); + if (!base_ptr) { + printf("No zboot setup_base\n"); + return CMD_RET_FAILURE; + } + printf("Setup located at %p:\n\n", base_ptr); + print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr); + + printf("E820: %d entries\n", base_ptr->e820_entries); + if (base_ptr->e820_entries) { + printf("%18s %16s %s\n", "Addr", "Size", "Type"); + for (i = 0; i < base_ptr->e820_entries; i++) { + struct e820_entry *entry = &base_ptr->e820_map[i]; + + printf("%12llx %10llx %s\n", entry->addr, entry->size, + entry->type < E820_COUNT ? + e820_type_name[entry->type] : + simple_itoa(entry->type)); + } + } + + hdr = &base_ptr->hdr; + print_num("Setup sectors", hdr->setup_sects); + print_num("Root flags", hdr->root_flags); + print_num("Sys size", hdr->syssize); + print_num("RAM size", hdr->ram_size); + print_num("Video mode", hdr->vid_mode); + print_num("Root dev", hdr->root_dev); + print_num("Boot flag", hdr->boot_flag); + print_num("Jump", hdr->jump); + print_num("Header", hdr->header); + if (hdr->header == KERNEL_V2_MAGIC) + printf("%-20s %s\n", "", "Kernel V2"); + else + printf("%-20s %s\n", "", "Ancient kernel, using version 100"); + print_num("Version", hdr->version); + print_num("Real mode switch", hdr->realmode_swtch); + print_num("Start sys", hdr->start_sys); + print_num("Kernel version", hdr->kernel_version); + version = get_kernel_version(base_ptr, (void *)state.bzimage_addr); + if (version) + printf(" @%p: %s\n", version, version); + print_num("Type of loader", hdr->type_of_loader); + show_loader(hdr); + print_num("Load flags", hdr->loadflags); + print_flags(load_flags, ARRAY_SIZE(load_flags), hdr->loadflags); + print_num("Setup move size", hdr->setup_move_size); + print_num("Code32 start", hdr->code32_start); + print_num("Ramdisk image", hdr->ramdisk_image); + print_num("Ramdisk size", hdr->ramdisk_size); + print_num("Bootsect kludge", hdr->bootsect_kludge); + print_num("Heap end ptr", hdr->heap_end_ptr); + print_num("Ext loader ver", hdr->ext_loader_ver); + print_num("Ext loader type", hdr->ext_loader_type); + print_num("Command line ptr", hdr->cmd_line_ptr); + if (hdr->cmd_line_ptr) { + printf(" "); + /* Use puts() to avoid limits from CONFIG_SYS_PBSIZE */ + puts((char *)(ulong)hdr->cmd_line_ptr); + printf("\n"); + } + print_num("Initrd addr max", hdr->initrd_addr_max); + print_num("Kernel alignment", hdr->kernel_alignment); + print_num("Relocatable kernel", hdr->relocatable_kernel); + print_num("Min alignment", hdr->min_alignment); + if (hdr->min_alignment) + printf("%-20s: %x\n", "", 1 << hdr->min_alignment); + print_num("Xload flags", hdr->xloadflags); + print_flags(xload_flags, ARRAY_SIZE(xload_flags), hdr->xloadflags); + print_num("Cmdline size", hdr->cmdline_size); + print_num("Hardware subarch", hdr->hardware_subarch); + print_num64("HW subarch data", hdr->hardware_subarch_data); + print_num("Payload offset", hdr->payload_offset); + print_num("Payload length", hdr->payload_length); + print_num64("Setup data", hdr->setup_data); + print_num64("Pref address", hdr->pref_address); + print_num("Init size", hdr->init_size); + print_num("Handover offset", hdr->handover_offset); + if (get_boot_protocol(hdr, false) >= 0x215) + print_num("Kernel info offset", hdr->kernel_info_offset); + + return 0; +} + +/* Note: This defines the complete_zboot() function */ +U_BOOT_SUBCMDS(zboot, + U_BOOT_CMD_MKENT(start, 8, 1, do_zboot_start, "", ""), + U_BOOT_CMD_MKENT(load, 1, 1, do_zboot_load, "", ""), + U_BOOT_CMD_MKENT(setup, 1, 1, do_zboot_setup, "", ""), + U_BOOT_CMD_MKENT(info, 1, 1, do_zboot_info, "", ""), + U_BOOT_CMD_MKENT(go, 1, 1, do_zboot_go, "", ""), + U_BOOT_CMD_MKENT(dump, 2, 1, do_zboot_dump, "", ""), +) + +int do_zboot_states(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int state_mask) +{ + int i; + + for (i = 0; i < ZBOOT_STATE_COUNT; i++) { + struct cmd_tbl *cmd = &zboot_subcmds[i]; + int mask = 1 << i; + int ret; + + if (mask & state_mask) { + ret = cmd->cmd(cmd, flag, argc, argv); + if (ret) + return ret; + } + } + + return 0; +} + +int do_zboot_parent(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], int *repeatable) +{ + /* determine if we have a sub command */ + if (argc > 1) { + char *endp; + + simple_strtoul(argv[1], &endp, 16); + /* + * endp pointing to nul means that argv[1] was just a valid + * number, so pass it along to the normal processing + */ + if (*endp) + return do_zboot(cmdtp, flag, argc, argv, repeatable); + } + + do_zboot_states(cmdtp, flag, argc, argv, ZBOOT_STATE_START | + ZBOOT_STATE_LOAD | ZBOOT_STATE_SETUP | + ZBOOT_STATE_INFO | ZBOOT_STATE_GO); + + return CMD_RET_FAILURE; } -U_BOOT_CMD( - zboot, 5, 0, do_zboot, - "Boot bzImage", - "[addr] [size] [initrd addr] [initrd size]\n" +U_BOOT_CMDREP_COMPLETE( + zboot, 8, do_zboot_parent, "Boot bzImage", + "[addr] [size] [initrd addr] [initrd size] [setup] [cmdline]\n" " addr - The optional starting address of the bzimage.\n" " If not set it defaults to the environment\n" " variable \"fileaddr\".\n" @@ -364,4 +725,17 @@ U_BOOT_CMD( " zero.\n" " initrd addr - The address of the initrd image to use, if any.\n" " initrd size - The size of the initrd image to use, if any.\n" + " setup - The address of the kernel setup region, if this\n" + " is not at addr\n" + " cmdline - The address of the kernel command line, to\n" + " override U-Boot's normal cmdline generation\n" + "\n" + "Sub-commands to do part of the zboot sequence:\n" + "\tstart [addr [arg ...]] - specify arguments\n" + "\tload - load OS image\n" + "\tsetup - set up table\n" + "\tinfo - show summary info\n" + "\tgo - start OS\n" + "\tdump [addr] - dump info (optional address of boot params)", + complete_zboot ); diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile index ceee59b9bd..c59df7d372 100644 --- a/arch/xtensa/lib/Makefile +++ b/arch/xtensa/lib/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o -obj-y += cache.o misc.o relocate.o time.o bdinfo.o +obj-y += cache.o misc.o relocate.o time.o diff --git a/arch/xtensa/lib/bdinfo.c b/arch/xtensa/lib/bdinfo.c deleted file mode 100644 index 4ec8529521..0000000000 --- a/arch/xtensa/lib/bdinfo.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * XTENSA-specific information for the 'bd' command - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include <common.h> -#include <init.h> - -DECLARE_GLOBAL_DATA_PTR; - -int arch_setup_bdinfo(void) -{ - struct bd_info *bd = gd->bd; - - bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE); - bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; - - return 0; -} diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 458eaf95c0..0e564507f9 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -41,15 +41,14 @@ static struct bp_tag *setup_last_tag(struct bp_tag *params) static struct bp_tag *setup_memory_tag(struct bp_tag *params) { - struct bd_info *bd = gd->bd; struct meminfo *mem; params->id = BP_TAG_MEMORY; params->size = sizeof(struct meminfo); mem = (struct meminfo *)params->data; mem->type = MEMORY_TYPE_CONVENTIONAL; - mem->start = bd->bi_memstart; - mem->end = bd->bi_memstart + bd->bi_memsize; + mem->start = PHYSADDR(gd->ram_base); + mem->end = PHYSADDR(gd->ram_base + gd->ram_size); printf(" MEMORY: tag:0x%04x, type:0X%lx, start:0X%lx, end:0X%lx\n", BP_TAG_MEMORY, mem->type, mem->start, mem->end); |