diff options
Diffstat (limited to 'board/freescale/ls1046aqds/ls1046aqds.c')
| -rw-r--r-- | board/freescale/ls1046aqds/ls1046aqds.c | 128 |
1 files changed, 64 insertions, 64 deletions
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index dfdc9f06ab..3d0881643c 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -41,55 +41,55 @@ DECLARE_GLOBAL_DATA_PTR; struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; @@ -97,54 +97,54 @@ struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = { { "nand", - CONFIG_SYS_NAND_CSPR, - CONFIG_SYS_NAND_CSPR_EXT, - CONFIG_SYS_NAND_AMASK, - CONFIG_SYS_NAND_CSOR, + CFG_SYS_NAND_CSPR, + CFG_SYS_NAND_CSPR_EXT, + CFG_SYS_NAND_AMASK, + CFG_SYS_NAND_CSOR, { - CONFIG_SYS_NAND_FTIM0, - CONFIG_SYS_NAND_FTIM1, - CONFIG_SYS_NAND_FTIM2, - CONFIG_SYS_NAND_FTIM3 + CFG_SYS_NAND_FTIM0, + CFG_SYS_NAND_FTIM1, + CFG_SYS_NAND_FTIM2, + CFG_SYS_NAND_FTIM3 }, }, { "nor0", - CONFIG_SYS_NOR0_CSPR, - CONFIG_SYS_NOR0_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR0_CSPR, + CFG_SYS_NOR0_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "nor1", - CONFIG_SYS_NOR1_CSPR, - CONFIG_SYS_NOR1_CSPR_EXT, - CONFIG_SYS_NOR_AMASK, - CONFIG_SYS_NOR_CSOR, + CFG_SYS_NOR1_CSPR, + CFG_SYS_NOR1_CSPR_EXT, + CFG_SYS_NOR_AMASK, + CFG_SYS_NOR_CSOR, { - CONFIG_SYS_NOR_FTIM0, - CONFIG_SYS_NOR_FTIM1, - CONFIG_SYS_NOR_FTIM2, - CONFIG_SYS_NOR_FTIM3 + CFG_SYS_NOR_FTIM0, + CFG_SYS_NOR_FTIM1, + CFG_SYS_NOR_FTIM2, + CFG_SYS_NOR_FTIM3 }, }, { "fpga", - CONFIG_SYS_FPGA_CSPR, - CONFIG_SYS_FPGA_CSPR_EXT, - CONFIG_SYS_FPGA_AMASK, - CONFIG_SYS_FPGA_CSOR, + CFG_SYS_FPGA_CSPR, + CFG_SYS_FPGA_CSPR_EXT, + CFG_SYS_FPGA_AMASK, + CFG_SYS_FPGA_CSOR, { - CONFIG_SYS_FPGA_FTIM0, - CONFIG_SYS_FPGA_FTIM1, - CONFIG_SYS_FPGA_FTIM2, - CONFIG_SYS_FPGA_FTIM3 + CFG_SYS_FPGA_FTIM0, + CFG_SYS_FPGA_FTIM1, + CFG_SYS_FPGA_FTIM2, + CFG_SYS_FPGA_FTIM3 }, } }; |