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-rw-r--r--board/kontron/sl28/sl28.c68
1 files changed, 68 insertions, 0 deletions
diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c
new file mode 100644
index 0000000000..b18127c4d1
--- /dev/null
+++ b/board/kontron/sl28/sl28.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <fsl_ddr.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <env_internal.h>
+#include <asm/arch-fsl-layerscape/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <i2c.h>
+#include <asm/arch/soc.h>
+#include <fsl_immap.h>
+#include <netdev.h>
+
+#include <fdtdec.h>
+#include <miiphy.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ if (CONFIG_IS_ENABLED(FSL_CAAM))
+ sec_init();
+
+ return 0;
+}
+
+int board_eth_init(struct bd_info *bis)
+{
+ return pci_eth_init(bis);
+}
+
+int checkboard(void)
+{
+ printf("EL: %d\n", current_el());
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+ print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+ print_ddr_info(0);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+ int nbanks = CONFIG_NR_DRAM_BANKS;
+ int i;
+
+ ft_cpu_setup(blob, bd);
+
+ /* fixup DT for the two GPP DDR banks */
+ for (i = 0; i < nbanks; i++) {
+ base[i] = gd->bd->bi_dram[i].start;
+ size[i] = gd->bd->bi_dram[i].size;
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, nbanks);
+
+ fdt_fixup_icid(blob);
+
+ return 0;
+}