4 files changed, 82 insertions, 0 deletions
diff --git a/board/beacon/beacon-rzg2m/Kconfig b/board/beacon/beacon-rzg2m/Kconfig
new file mode 100644
index 0000000000..c03857cf2f
--- /dev/null
+++ b/board/beacon/beacon-rzg2m/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BEACON_RZG2M
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "beacon-rzg2m"
+
+config SYS_VENDOR
+	default "beacon"
+
+config SYS_CONFIG_NAME
+	default "beacon-rzg2m"
+
+endif
diff --git a/board/beacon/beacon-rzg2m/MAINTAINERS b/board/beacon/beacon-rzg2m/MAINTAINERS
new file mode 100644
index 0000000000..3383a68936
--- /dev/null
+++ b/board/beacon/beacon-rzg2m/MAINTAINERS
@@ -0,0 +1,6 @@
+BEACON_RZG2M BOARD
+M:	Adam Ford <aford173@gmail.com>
+S:	Maintained
+F:	board/beacon/beacon-rzg2m/
+F:	include/configs/beacon-rzg2m.h
+F:	configs/r8a774a1_beacon_defconfig
diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile
new file mode 100644
index 0000000000..439f3199aa
--- /dev/null
+++ b/board/beacon/beacon-rzg2m/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/hihope-rzg2m/Makefile
+#
+# Copyright (C) 2019 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= beacon-rzg2m.o
diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c
new file mode 100644
index 0000000000..86a24dd065
--- /dev/null
+++ b/board/beacon/beacon-rzg2m/beacon-rzg2m.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Compass Electronics Group, LLC
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/rcar-mstp.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void)
+{
+}
+
+/* Kconfig forces this on, so just return 0 */
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	if (fdtdec_setup_mem_size_base() != 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	fdtdec_setup_memory_banksize();
+
+	return 0;
+}
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CODE	0xA5A5000F
+
+void reset_cpu(ulong addr)
+{
+	writel(RST_CODE, RST_CA57RESCNT);
+}