diff options
Diffstat (limited to 'board')
84 files changed, 2921 insertions, 1686 deletions
diff --git a/board/Seagate/dockstar/MAINTAINERS b/board/Seagate/dockstar/MAINTAINERS index f259e58ae6..0f6243e257 100644 --- a/board/Seagate/dockstar/MAINTAINERS +++ b/board/Seagate/dockstar/MAINTAINERS @@ -1,5 +1,5 @@ DOCKSTAR BOARD -M: Eric Cooper <ecc@cmu.edu> +M: Tony Dinh <mibodhi@gmail.com> S: Maintained F: board/Seagate/dockstar/ F: include/configs/dockstar.h diff --git a/board/Seagate/goflexhome/MAINTAINERS b/board/Seagate/goflexhome/MAINTAINERS index 6d6a1ff4e3..a71b4ba1fe 100644 --- a/board/Seagate/goflexhome/MAINTAINERS +++ b/board/Seagate/goflexhome/MAINTAINERS @@ -1,5 +1,5 @@ GOFLEXHOME BOARD -M: Suriyan Ramasami <suriyan.r@gmail.com> +M: Tony Dinh <mibodhi@gmail.com> S: Maintained F: board/Seagate/goflexhome/ F: include/configs/goflexhome.h diff --git a/board/Seagate/goflexhome/goflexhome.c b/board/Seagate/goflexhome/goflexhome.c index af8cab7bdc..52be64fb8c 100644 --- a/board/Seagate/goflexhome/goflexhome.c +++ b/board/Seagate/goflexhome/goflexhome.c @@ -1,5 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 + * Tony Dinh <mibodhi@gmail.com> + * Suriyan Ramasami <suriyan.r@gmail.com> + * * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com> * * Based on dockstar.c originally written by @@ -107,36 +111,65 @@ int board_init(void) return 0; } +static int fdt_get_phy_addr(const char *path) +{ + const void *fdt = gd->fdt_blob; + const u32 *reg; + const u32 *val; + int node, phandle, addr; + + /* Find the node by its full path */ + node = fdt_path_offset(fdt, path); + if (node >= 0) { + /* Look up phy-handle */ + val = fdt_getprop(fdt, node, "phy-handle", NULL); + if (val) { + phandle = fdt32_to_cpu(*val); + if (!phandle) + return -1; + /* Follow it to its node */ + node = fdt_node_offset_by_phandle(fdt, phandle); + if (node) { + /* Look up reg */ + reg = fdt_getprop(fdt, node, "reg", NULL); + if (reg) { + addr = fdt32_to_cpu(*reg); + return addr; + } + } + } + } + return -1; +} + #ifdef CONFIG_RESET_PHY_R /* Configure and enable MV88E1116 PHY */ void reset_phy(void) { u16 reg; - u16 devadr; - char *name = "egiga0"; + int phyaddr; + char *name = "ethernet-controller@72000"; + char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; if (miiphy_set_current_dev(name)) return; - /* command to read PHY dev address */ - if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { - printf("Err..%s could not read PHY dev address\n", - __func__); + phyaddr = fdt_get_phy_addr(eth0_path); + if (phyaddr < 0) return; - } /* * Enable RGMII delay on Tx and Rx for CPU port * Ref: sec 4.7.2 of chip datasheet */ - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, ®); reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); + miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); /* reset the phy */ - miiphy_reset(name, devadr); + miiphy_reset(name, phyaddr); printf("88E1116 Initialized on %s\n", name); } diff --git a/board/amlogic/odroid-n2/odroid-n2.c b/board/amlogic/odroid-n2/odroid-n2.c index c37ea65417..2135457edd 100644 --- a/board/amlogic/odroid-n2/odroid-n2.c +++ b/board/amlogic/odroid-n2/odroid-n2.c @@ -48,7 +48,7 @@ static struct meson_odroid_boards { /* OdroidN2 rev 2019,2,7 */ { MESON_SOC_ID_G12B, 330 * 4, 350 * 4, "n2" }, /* OdroidN2plus rev 2019,11,20 */ - { MESON_SOC_ID_G12B, 410 * 4, 430 * 4, "n2_plus" }, + { MESON_SOC_ID_G12B, 410 * 4, 430 * 4, "n2-plus" }, /* OdroidC4 rev 2020,01,29 */ { MESON_SOC_ID_SM1, 80 * 4, 100 * 4, "c4" }, /* OdroidHC4 rev 2019,12,10 */ diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index a7dc5c6aeb..a8f8c78558 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -123,10 +123,3 @@ int board_eth_init(struct bd_info *bis) return rc; } - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - printf("DEBUG: PCI Init TODO *****\n"); -} -#endif diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 0818048ba6..a7de82d3bf 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -64,5 +64,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply VIRTIO_PCI imply VIRTIO_NET imply VIRTIO_BLK + imply MTD_NOR_FLASH + imply CFI_FLASH endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 116c1e71cc..3a171688c3 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -63,7 +63,6 @@ obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o -obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index be97a28ed2..dc2d62850d 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -9,68 +9,9 @@ #include "cadmus.h" #if defined(CONFIG_OF_BOARD_SETUP) -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) -static void cds_pci_fixup(void *blob) -{ - int node; - const char *path; - int len, slot, i; - u32 *map = NULL, *piccells = NULL; - int off, cells; - - node = fdt_path_offset(blob, "/aliases"); - if (node >= 0) { - path = fdt_getprop(blob, node, "pci0", NULL); - if (path) { - node = fdt_path_offset(blob, path); - if (node >= 0) { - map = fdt_getprop_w(blob, node, "interrupt-map", &len); - } - /* Each item in "interrupt-map" property is translated with - * following cells: - * PCI #address-cells, PCI #interrupt-cells, - * PIC address, PIC #address-cells, PIC #interrupt-cells. - */ - cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1); - cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1); - off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells))); - if (off <= 0) - return; - cells += 1; - piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL); - if (piccells == NULL) - return; - cells += *piccells; - piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL); - if (piccells == NULL) - return; - cells += *piccells; - } - } - - if (map) { - len /= sizeof(u32); - - slot = get_pci_slot(); - - for (i=0;i<len;i+=cells) { - /* We rotate the interrupt pins so that the mapping - * changes depending on the slot the carrier card is in. - */ - map[3] = ((map[3] + slot - 2) % 4) + 1; - map+=cells; - } - } -} -#endif - int ft_board_setup(void *blob, struct bd_info *bd) { ft_cpu_setup(blob, bd); -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) - ft_pci_setup(blob, bd); - cds_pci_fixup(blob); -#endif return 0; } diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 066aa9a7c3..c90afe2e21 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include <common.h> @@ -498,8 +499,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) return ret; ret = algo->hash_init(algo, &ctx); - if (ret) + if (ret) { + if (ctx) + free(ctx); return ret; + } /* Update hash for ESBC key */ #ifdef CONFIG_KEY_REVOCATION @@ -518,8 +522,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img) /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) + if (ret) { + if (ctx) + free(ctx); return ret; + } for (i = 0; i < SHA256_BYTES; i++) img->img_key_hash[i] = hash_val[i]; @@ -547,14 +554,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) ret = algo->hash_init(algo, &ctx); /* Copy hash at destination buffer */ - if (ret) + if (ret) { + free(ctx); return ret; + } /* Update hash for CSF Header */ ret = algo->hash_update(algo, ctx, (u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0); - if (ret) + if (ret) { + free(ctx); return ret; + } /* Update the hash with that of srk table if srk flag is 1 * If IE Table is selected, key is not added in the hash @@ -581,22 +592,29 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img) key_hash = 1; } #endif - if (ret) + if (ret) { + free(ctx); return ret; - if (!key_hash) + } + if (!key_hash) { + free(ctx); return ERROR_KEY_TABLE_NOT_FOUND; + } /* Update hash for actual Image */ ret = algo->hash_update(algo, ctx, (u8 *)(*(img->img_addr_ptr)), img->img_size, 1); - if (ret) + if (ret) { + free(ctx); return ret; + } /* Copy hash at destination buffer */ ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size); - if (ret) + if (ret) { + free(ctx); return ret; - + } return 0; } diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c deleted file mode 100644 index bb3cdac841..0000000000 --- a/board/freescale/common/idt8t49n222a_serdes_clk.c +++ /dev/null @@ -1,208 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Author: Shaveta Leekha <shaveta@freescale.com> - */ - -#include "idt8t49n222a_serdes_clk.h" -#include <log.h> -#include <linux/delay.h> - -#define DEVICE_ID_REG 0x00 - -static int check_pll_status(u8 idt_addr) -{ - u8 val = 0; - int ret; - - ret = i2c_read(idt_addr, 0x17, 1, &val, 1); - if (ret < 0) { - printf("IDT:0x%x could not read status register from device.\n", - idt_addr); - return ret; - } - - if (val & 0x04) { - debug("idt8t49n222a PLL is LOCKED: %x\n", val); - } else { - printf("idt8t49n222a PLL is not LOCKED: %x\n", val); - return -1; - } - - return 0; -} - -int set_serdes_refclk(u8 idt_addr, u8 serdes_num, - enum serdes_refclk refclk1, - enum serdes_refclk refclk2, u8 feedback) -{ - u8 dev_id = 0; - int i, ret; - - debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n", - idt_addr); - - ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1); - if (ret < 0) { - debug("IDT:0x%x could not read DEV_ID from device.\n", - idt_addr); - return ret; - } - - if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) { - debug("IDT: device at address 0x%x is not idt8t49n222a.\n", - idt_addr); - } - - if (serdes_num != 1 && serdes_num != 2) { - debug("serdes_num should be 1 for SerDes1 and" - " 2 for SerDes2.\n"); - return -1; - } - - if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88) - || (refclk1 != SERDES_REFCLK_122_88 - && refclk2 == SERDES_REFCLK_122_88)) { - debug("Only one refclk at 122.88MHz is not supported." - " Please set both refclk1 & refclk2 to 122.88MHz" - " or both not to 122.88MHz.\n"); - return -1; - } - - if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88 - && refclk1 != SERDES_REFCLK_125 - && refclk1 != SERDES_REFCLK_156_25) { - debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz" - " or 156.25MHz.\n"); - return -1; - } - - if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88 - && refclk2 != SERDES_REFCLK_125 - && refclk2 != SERDES_REFCLK_156_25) { - debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz" - " or 156.25MHz.\n"); - return -1; - } - - if (feedback != 0 && feedback != 1) { - debug("valid values for feedback are 0(default) or 1.\n"); - return -1; - } - - /* Configuring IDT for output refclks as - * Refclk1 = 122.88MHz Refclk2 = 122.88MHz - */ - if (refclk1 == SERDES_REFCLK_122_88 && - refclk2 == SERDES_REFCLK_122_88) { - printf("Setting refclk1:122.88 and refclk2:122.88\n"); - for (i = 0; i < NUM_IDT_REGS; i++) - i2c_reg_write(idt_addr, idt_conf_122_88[i][0], - idt_conf_122_88[i][1]); - - if (feedback) { - for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++) - i2c_reg_write(idt_addr, - idt_conf_122_88_feedback[i][0], - idt_conf_122_88_feedback[i][1]); - } - } - - if (refclk1 != SERDES_REFCLK_122_88 && - refclk2 != SERDES_REFCLK_122_88) { - for (i = 0; i < NUM_IDT_REGS; i++) - i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0], - idt_conf_not_122_88[i][1]); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 100MHz Refclk2 = 125MHz - */ - if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) { - printf("Setting refclk1:100 and refclk2:125\n"); - i2c_reg_write(idt_addr, 0x11, 0x10); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 125MHz Refclk2 = 125MHz - */ - if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) { - printf("Setting refclk1:125 and refclk2:125\n"); - i2c_reg_write(idt_addr, 0x10, 0x10); - i2c_reg_write(idt_addr, 0x11, 0x10); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 125MHz Refclk2 = 100MHz - */ - if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) { - printf("Setting refclk1:125 and refclk2:100\n"); - i2c_reg_write(idt_addr, 0x10, 0x10); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 156.25MHz Refclk2 = 156.25MHz - */ - if (refclk1 == SERDES_REFCLK_156_25 && - refclk2 == SERDES_REFCLK_156_25) { - printf("Setting refclk1:156.25 and refclk2:156.25\n"); - for (i = 0; i < NUM_IDT_REGS_156_25; i++) - i2c_reg_write(idt_addr, idt_conf_156_25[i][0], - idt_conf_156_25[i][1]); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 100MHz Refclk2 = 156.25MHz - */ - if (refclk1 == SERDES_REFCLK_100 && - refclk2 == SERDES_REFCLK_156_25) { - printf("Setting refclk1:100 and refclk2:156.25\n"); - for (i = 0; i < NUM_IDT_REGS_156_25; i++) - i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0], - idt_conf_100_156_25[i][1]); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 125MHz Refclk2 = 156.25MHz - */ - if (refclk1 == SERDES_REFCLK_125 && - refclk2 == SERDES_REFCLK_156_25) { - printf("Setting refclk1:125 and refclk2:156.25\n"); - for (i = 0; i < NUM_IDT_REGS_156_25; i++) - i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0], - idt_conf_125_156_25[i][1]); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 156.25MHz Refclk2 = 100MHz - */ - if (refclk1 == SERDES_REFCLK_156_25 && - refclk2 == SERDES_REFCLK_100) { - printf("Setting refclk1:156.25 and refclk2:100\n"); - for (i = 0; i < NUM_IDT_REGS_156_25; i++) - i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0], - idt_conf_156_25_100[i][1]); - } - - /* Configuring IDT for output refclks as - * Refclk1 = 156.25MHz Refclk2 = 125MHz - */ - if (refclk1 == SERDES_REFCLK_156_25 && - refclk2 == SERDES_REFCLK_125) { - printf("Setting refclk1:156.25 and refclk2:125\n"); - for (i = 0; i < NUM_IDT_REGS_156_25; i++) - i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0], - idt_conf_156_25_125[i][1]); - } - - /* waiting for maximum of 1 second if PLL doesn'r get locked - * initially. then check the status again. - */ - if (check_pll_status(idt_addr)) { - mdelay(1000); - if (check_pll_status(idt_addr)) - return -1; - } - - return 0; -} diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h deleted file mode 100644 index b1528e3266..0000000000 --- a/board/freescale/common/idt8t49n222a_serdes_clk.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * Author: Shaveta Leekha <shaveta@freescale.com> - */ - -#ifndef __IDT8T49N222A_SERDES_CLK_H_ -#define __IDT8T49N222A_SERDES_CLK_H_ 1 - -#include <common.h> -#include <i2c.h> -#include "qixis.h" -#include "../b4860qds/b4860qds_qixis.h" -#include <errno.h> - -#define NUM_IDT_REGS 23 -#define NUM_IDT_REGS_FEEDBACK 12 -#define NUM_IDT_REGS_156_25 11 - -/* CLK */ -enum serdes_refclk { - SERDES_REFCLK_100, /* refclk 100Mhz */ - SERDES_REFCLK_122_88, /* refclk 122.88Mhz */ - SERDES_REFCLK_125, /* refclk 125Mhz */ - SERDES_REFCLK_156_25, /* refclk 156.25Mhz */ - SERDES_REFCLK_NONE = -1, -}; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 = 122.88MHz Refclk2 = 122.88MHz - */ -static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00}, - {0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00}, - {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, - {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, - {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12}, - {0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, - {0x16, 0xA0} }; - - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz - */ -static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00}, - {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00}, - {0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00}, - {0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00}, - {0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14}, - {0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08}, - {0x16, 0xA0} }; - -/* Reconfiguration values for some of IDT registers for - * Output Refclks: - * Refclk1 = 122.88MHz Refclk2 = 122.88MHz - * and with feedback as 1 - */ -static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7}, - {0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07}, - {0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B}, - {0x14, 0x00}, {0x15, 0xE8} }; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 : 156.25MHz Refclk2 : 156.25MHz - */ -static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, - {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, - {0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, - {0x15, 0xE8} }; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 : 100MHz Refclk2 : 156.25MHz - */ -static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, - {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, - {0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, - {0x15, 0xE8} }; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 : 125MHz Refclk2 : 156.25MHz - */ -static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03}, - {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, - {0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C}, - {0x15, 0xE8} }; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 : 156.25MHz Refclk2 : 100MHz - */ -static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03}, - {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, - {0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C}, - {0x15, 0xE8} }; - -/* configuration values for IDT registers for Output Refclks: - * Refclk1 : 156.25MHz Refclk2 : 125MHz - */ -static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03}, - {0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20}, - {0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C}, - {0x15, 0xE8} }; - -int set_serdes_refclk(u8 idt_addr, u8 serdes_num, - enum serdes_refclk refclk1, - enum serdes_refclk refclk2, u8 feedback); - -#endif /*__IDT8T49N222A_SERDES_CLK_H_ */ diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile index 29c9d544ae..ce156018a0 100644 --- a/board/freescale/common/p_corenet/Makefile +++ b/board/freescale/common/p_corenet/Makefile @@ -4,5 +4,4 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += law.o -obj-$(CONFIG_PCI) += pci.o obj-y += tlb.o diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c deleted file mode 100644 index 636334863e..0000000000 --- a/board/freescale/common/p_corenet/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/imx8ulp_evk/Kconfig b/board/freescale/imx8ulp_evk/Kconfig new file mode 100644 index 0000000000..1e461ee1da --- /dev/null +++ b/board/freescale/imx8ulp_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8ULP_EVK + +config SYS_BOARD + default "imx8ulp_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8ulp_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8ulp_evk/MAINTAINERS b/board/freescale/imx8ulp_evk/MAINTAINERS new file mode 100644 index 0000000000..267b7b0caa --- /dev/null +++ b/board/freescale/imx8ulp_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX8ULP EVK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/imx8ulp_evk/ +F: include/configs/imx8ulp_evk.h +F: configs/imx8ulp_evk_defconfig diff --git a/board/freescale/imx8ulp_evk/Makefile b/board/freescale/imx8ulp_evk/Makefile new file mode 100644 index 0000000000..b2e72b4e85 --- /dev/null +++ b/board/freescale/imx8ulp_evk/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += imx8ulp_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o ddr_init.o lpddr4_timing.o +endif diff --git a/board/freescale/imx8ulp_evk/ddr_init.c b/board/freescale/imx8ulp_evk/ddr_init.c new file mode 100644 index 0000000000..f4238d29b3 --- /dev/null +++ b/board/freescale/imx8ulp_evk/ddr_init.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx-regs.h> + +#define DENALI_CTL_00 (DDR_CTL_BASE_ADDR) +#define CTL_START 0x1 + +#define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3) +#define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197) +#define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250) +#define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251) +#define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266) +#define DFI_INIT_COMPLETE 0x2 + +#define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614) +#define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615) + +#define DENALI_PI_00 (DDR_PI_BASE_ADDR) +#define PI_START 0x1 + +#define DENALI_PI_04 (DDR_PI_BASE_ADDR + 4 * 4) +#define DENALI_PI_11 (DDR_PI_BASE_ADDR + 4 * 11) +#define DENALI_PI_12 (DDR_PI_BASE_ADDR + 4 * 12) +#define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23) +#define DENALI_CTL_25 (DDR_CTL_BASE_ADDR + 4 * 25) + +#define DENALI_PHY_1624 (DDR_PHY_BASE_ADDR + 4 * 1624) +#define DENALI_PHY_1537 (DDR_PHY_BASE_ADDR + 4 * 1537) +#define PHY_FREQ_SEL_MULTICAST_EN(X) ((X) << 8) +#define PHY_FREQ_SEL_INDEX(X) ((X) << 16) + +#define DENALI_PHY_1547 (DDR_PHY_BASE_ADDR + 4 * 1547) +#define DENALI_PHY_1555 (DDR_PHY_BASE_ADDR + 4 * 1555) +#define DENALI_PHY_1564 (DDR_PHY_BASE_ADDR + 4 * 1564) +#define DENALI_PHY_1565 (DDR_PHY_BASE_ADDR + 4 * 1565) + +int ddr_calibration(unsigned int fsp_table[3]) +{ + u32 reg_val; + u32 int_status_init, phy_freq_req, phy_freq_type; + u32 lock_0, lock_1, lock_2; + u32 freq_chg_pt, freq_chg_cnt; + + reg_val = readl(DENALI_CTL_250); + if (((reg_val >> 16) & 0x3) == 1) + freq_chg_cnt = 2; + else + freq_chg_cnt = 3; + + reg_val = readl(DENALI_PI_12); + if (reg_val == 0x3) { + freq_chg_pt = 1; + } else if (reg_val == 0x7) { + freq_chg_pt = 2; + } else { + printf("frequency map(0x%x) is wrong, please check!\r\n", reg_val); + return -1; + } + + debug("%s\n", __func__); + + /* Assert PI_START parameter and then assert START parameter in Controller. */ + reg_val = readl(DENALI_PI_00) | PI_START; + writel(reg_val, DENALI_PI_00); + + reg_val = readl(DENALI_CTL_00) | CTL_START; + writel(reg_val, DENALI_CTL_00); + + /* Poll for init_done_bit in Controller interrupt status register (INT_STATUS_INIT) */ + do { + if (!freq_chg_cnt) { + int_status_init = (readl(DENALI_CTL_266) >> 8) & 0xff; + /* DDR subsystem is ready for traffic. */ + if (int_status_init & DFI_INIT_COMPLETE) { + printf("complete\n"); + break; + } + } + + /* + * During leveling, PHY will request for freq change and SoC clock + * logic should provide requested frequency, Polling SIM LPDDR_CTRL2 + * Bit phy_freq_chg_req until be 1'b1 + */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + phy_freq_req = (reg_val >> 7) & 0x1; + + if (phy_freq_req) { + phy_freq_type = reg_val & 0x1F; + if (!phy_freq_type) { + printf("Poll for freq_chg_req on SIM register and change to F0 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + } else if (phy_freq_type == 0x01) { + printf("Poll for freq_chg_req on SIM register and change to F1 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 1) + freq_chg_cnt--; + } else if (phy_freq_type == 0x02) { + printf("Poll for freq_chg_req on SIM register and change to F2 frequency.\n"); + set_ddr_clk(fsp_table[phy_freq_type] >> 1); + + /* Write 1'b1 at LPDDR_CTRL2 bit phy_freq_cfg_ack */ + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + writel(reg_val | (0x1 << 6), AVD_SIM_LPDDR_CTRL2); + if (freq_chg_pt == 2) + freq_chg_cnt--; + } + reg_val = readl(AVD_SIM_LPDDR_CTRL2); + } + } while (1); + + /* Check PLL lock status */ + lock_0 = readl(DENALI_PHY_1564) & 0xffff; + lock_1 = (readl(DENALI_PHY_1564) >> 16) & 0xffff; + lock_2 = readl(DENALI_PHY_1565) & 0xffff; + + if ((lock_0 & 0x3) != 0x3 || (lock_1 & 0x3) != 0x3 || (lock_2 & 0x3) != 0x3) { + printf("De-Skew PLL failed to lock\n"); + printf("lock_0=0x%x, lock_1=0x%x, lock_2=0x%x\n", lock_0, lock_1, lock_2); + return -1; + } + + printf("De-Skew PLL is locked and ready\n"); + return 0; +} + +int ddr_init(struct dram_timing_info2 *dram_timing) +{ + int i; + + debug("%s\n", __func__); + + set_ddr_clk(dram_timing->fsp_table[0] >> 1); /* Set to boot freq */ + + /* Initialize CTL registers */ + for (i = 0; i < dram_timing->ctl_cfg_num; i++) + writel(dram_timing->ctl_cfg[i].val, (ulong)dram_timing->ctl_cfg[i].reg); + + /* Initialize PI registers */ + for (i = 0; i < dram_timing->pi_cfg_num; i++) + writel(dram_timing->pi_cfg[i].val, (ulong)dram_timing->pi_cfg[i].reg); + + /* Write PHY regiters for all 3 frequency points (48Mhz/384Mhz/528Mhz): f1_index=0 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f1_cfg_num; i++) + writel(dram_timing->phy_f1_cfg[i].val, (ulong)dram_timing->phy_f1_cfg[i].reg); + + /* Write PHY regiters for freqency point 2 (528Mhz): f2_index=1 */ + writel(PHY_FREQ_SEL_MULTICAST_EN(0) | PHY_FREQ_SEL_INDEX(1), DENALI_PHY_1537); + for (i = 0; i < dram_timing->phy_f2_cfg_num; i++) + writel(dram_timing->phy_f2_cfg[i].val, (ulong)dram_timing->phy_f2_cfg[i].reg); + + /* Re-enable MULTICAST mode */ + writel(PHY_FREQ_SEL_MULTICAST_EN(1) | PHY_FREQ_SEL_INDEX(0), DENALI_PHY_1537); + + return ddr_calibration(dram_timing->fsp_table); +} + +void enable_bypass_mode(void) +{ + u32 reg_val; + + /* PI_INIT_LVL_EN=0x0 (DENALI_PI_04) */ + reg_val = readl(DENALI_PI_04) & ~0x1; + writel(reg_val, DENALI_PI_04); + + /* PI_FREQ_MAP=0x1 (DENALI_PI_12) */ + writel(0x1, DENALI_PI_12); + + /* PI_INIT_WORK_FREQ=0x0 (DENALI_PI_11) */ + reg_val = readl(DENALI_PI_11) & ~(0x1f << 8); + writel(reg_val, DENALI_PI_11); + + /* DFIBUS_FREQ_INIT=0x0 (DENALI_CTL_23) */ + reg_val = readl(DENALI_CTL_23) & ~(0x3 << 24); + writel(reg_val, DENALI_CTL_23); + + /* PHY_LP4_BOOT_DISABLE=0x0 (DENALI_PHY_1547) */ + reg_val = readl(DENALI_PHY_1547) & ~(0x1 << 8); + writel(reg_val, DENALI_PHY_1547); + + /* PHY_PLL_BYPASS=0x1 (DENALI_PHY_1624) */ + reg_val = readl(DENALI_PHY_1624) | 0x1; + writel(reg_val, DENALI_PHY_1624); + + /* PHY_LP4_BOOT_PLL_BYPASS to 0x1 (DENALI_PHY_1555) */ + reg_val = readl(DENALI_PHY_1555) | 0x1; + writel(reg_val, DENALI_PHY_1555); + + /* FREQ_CHANGE_TYPE_F0 = 0x0/FREQ_CHANGE_TYPE_F1 = 0x1/FREQ_CHANGE_TYPE_F2 = 0x2 */ + reg_val = 0x020100; + writel(reg_val, DENALI_CTL_25); +} diff --git a/board/freescale/imx8ulp_evk/imx8ulp_evk.c b/board/freescale/imx8ulp_evk/imx8ulp_evk.c new file mode 100644 index 0000000000..3ff4d43c99 --- /dev/null +++ b/board/freescale/imx8ulp_evk/imx8ulp_evk.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include <common.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/imx8ulp-pins.h> +#include <asm/arch/clock.h> +#include <asm/arch/pcc.h> +#include <asm/arch/sys_proto.h> +#include <miiphy.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if IS_ENABLED(CONFIG_FEC_MXC) +#define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE) +static iomux_cfg_t const enet_clk_pads[] = { + IMX8ULP_PAD_PTE19__ENET0_REFCLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + IMX8ULP_PAD_PTF10__ENET0_1588_CLKIN | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), +}; + +static int setup_fec(void) +{ + /* + * Since ref clock and timestamp clock are from external, + * set the iomux prior the clock enablement + */ + imx8ulp_iomux_setup_multiple_pads(enet_clk_pads, ARRAY_SIZE(enet_clk_pads)); + + /* Select enet time stamp clock: 001 - External Timestamp Clock */ + cgc1_enet_stamp_sel(1); + + /* enable FEC PCC */ + pcc_clock_enable(4, ENET_PCC4_SLOT, true); + pcc_reset_peripheral(4, ENET_PCC4_SLOT, false); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_late_init(void) +{ + return 0; +} diff --git a/board/freescale/imx8ulp_evk/lpddr4_timing.c b/board/freescale/imx8ulp_evk/lpddr4_timing.c new file mode 100644 index 0000000000..4546e92b01 --- /dev/null +++ b/board/freescale/imx8ulp_evk/lpddr4_timing.c @@ -0,0 +1,1158 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 NXP + * + * Generated code from MX8M_DDR_tool + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +/** CTL settings **/ +struct dram_cfg_param ddr_ctl_cfg[] = { + { 0x2e060000, 0xb00 }, /* 0 */ + { 0x2e060028, 0x258100 }, /* 10 */ + { 0x2e06002c, 0x17702 }, /* 11 */ + { 0x2e060030, 0x5 }, /* 12 */ + { 0x2e060034, 0x61 }, /* 13 */ + { 0x2e060038, 0xce3f }, /* 14 */ + { 0x2e06003c, 0x80e70 }, /* 15 */ + { 0x2e060040, 0x5 }, /* 16 */ + { 0x2e060044, 0x210 }, /* 17 */ + { 0x2e060048, 0x19c7d }, /* 18 */ + { 0x2e06004c, 0x101cdf }, /* 19 */ + { 0x2e060050, 0x5 }, /* 20 */ + { 0x2e060054, 0x420 }, /* 21 */ + { 0x2e060058, 0x1010000 }, /* 22 */ + { 0x2e06005c, 0x2011001 }, /* 23 */ + { 0x2e060060, 0x2010000 }, /* 24 */ + { 0x2e060064, 0x102 }, /* 25 */ + { 0x2e060068, 0xa }, /* 26 */ + { 0x2e06006c, 0x19 }, /* 27 */ + { 0x2e060078, 0x2020200 }, /* 30 */ + { 0x2e06007c, 0x160b }, /* 31 */ + { 0x2e060090, 0x10 }, /* 36 */ + { 0x2e0600a4, 0x40c040c }, /* 41 */ + { 0x2e0600a8, 0x8040614 }, /* 42 */ + { 0x2e0600ac, 0x604 }, /* 43 */ + { 0x2e0600b0, 0x3090003 }, /* 44 */ + { 0x2e0600b4, 0x40002 }, /* 45 */ + { 0x2e0600b8, 0xc0011 }, /* 46 */ + { 0x2e0600bc, 0xb0509 }, /* 47 */ + { 0x2e0600c0, 0x2106 }, /* 48 */ + { 0x2e0600c4, 0xa090017 }, /* 49 */ + { 0x2e0600c8, 0x8200016 }, /* 50 */ + { 0x2e0600cc, 0xa0a }, /* 51 */ + { 0x2e0600d0, 0x4000694 }, /* 52 */ + { 0x2e0600d4, 0xa0a0804 }, /* 53 */ + { 0x2e0600d8, 0x4002432 }, /* 54 */ + { 0x2e0600dc, 0xa0a0804 }, /* 55 */ + { 0x2e0600e0, 0x4004864 }, /* 56 */ + { 0x2e0600e4, 0x2030404 }, /* 57 */ + { 0x2e0600e8, 0x5040400 }, /* 58 */ + { 0x2e0600ec, 0x80b0a06 }, /* 59 */ + { 0x2e0600f0, 0x7010100 }, /* 60 */ + { 0x2e0600f4, 0x4150b }, /* 61 */ + { 0x2e0600fc, 0x1010000 }, /* 63 */ + { 0x2e060100, 0x1000000 }, /* 64 */ + { 0x2e060104, 0xe0403 }, /* 65 */ + { 0x2e060108, 0xb3 }, /* 66 */ + { 0x2e06010c, 0x4a }, /* 67 */ + { 0x2e060110, 0x3fd }, /* 68 */ + { 0x2e060114, 0x94 }, /* 69 */ + { 0x2e060118, 0x803 }, /* 70 */ + { 0x2e06011c, 0x5 }, /* 71 */ + { 0x2e060120, 0x70000 }, /* 72 */ + { 0x2e060124, 0x25000f }, /* 73 */ + { 0x2e060128, 0x4a0078 }, /* 74 */ + { 0x2e06012c, 0x4000f9 }, /* 75 */ + { 0x2e060130, 0x120103 }, /* 76 */ + { 0x2e060134, 0x50005 }, /* 77 */ + { 0x2e060138, 0x8070005 }, /* 78 */ + { 0x2e06013c, 0x505010d }, /* 79 */ + { 0x2e060140, 0x101030a }, /* 80 */ + { 0x2e060144, 0x30a0505 }, /* 81 */ + { 0x2e060148, 0x5050101 }, /* 82 */ + { 0x2e06014c, 0x1030a }, /* 83 */ + { 0x2e060150, 0xe000e }, /* 84 */ + { 0x2e060154, 0x4c004c }, /* 85 */ + { 0x2e060158, 0x980098 }, /* 86 */ + { 0x2e06015c, 0x3050505 }, /* 87 */ + { 0x2e060160, 0x3010403 }, /* 88 */ + { 0x2e060164, 0x4050505 }, /* 89 */ + { 0x2e060168, 0x3010403 }, /* 90 */ + { 0x2e06016c, 0x8050505 }, /* 91 */ + { 0x2e060170, 0x3010403 }, /* 92 */ + { 0x2e060174, 0x3010000 }, /* 93 */ + { 0x2e060178, 0x10000 }, /* 94 */ + { 0x2e060180, 0x1000000 }, /* 96 */ + { 0x2e060184, 0x80104002 }, /* 97 */ + { 0x2e060188, 0x40003 }, /* 98 */ + { 0x2e06018c, 0x40005 }, /* 99 */ + { 0x2e060190, 0x30000 }, /* 100 */ + { 0x2e060194, 0x50004 }, /* 101 */ + { 0x2e060198, 0x4 }, /* 102 */ + { 0x2e06019c, 0x40003 }, /* 103 */ + { 0x2e0601a0, 0x40005 }, /* 104 */ + { 0x2e0601a8, 0x2cc0 }, /* 106 */ + { 0x2e0601ac, 0x2cc0 }, /* 107 */ + { 0x2e0601b0, 0x2cc0 }, /* 108 */ + { 0x2e0601b4, 0x2cc0 }, /* 109 */ + { 0x2e0601b8, 0x2cc0 }, /* 110 */ + { 0x2e0601c0, 0x4e5 }, /* 112 */ + { 0x2e0601c4, 0xff40 }, /* 113 */ + { 0x2e0601c8, 0xff40 }, /* 114 */ + { 0x2e0601cc, 0xff40 }, /* 115 */ + { 0x2e0601d0, 0xff40 }, /* 116 */ + { 0x2e0601d4, 0xff40 }, /* 117 */ + { 0x2e0601dc, 0x1beb }, /* 119 */ + { 0x2e0601e0, 0x200c0 }, /* 120 */ + { 0x2e0601e4, 0x200c0 }, /* 121 */ + { 0x2e0601e8, 0x200c0 }, /* 122 */ + { 0x2e0601ec, 0x200c0 }, /* 123 */ + { 0x2e0601f0, 0x200c0 }, /* 124 */ + { 0x2e0601f8, 0x3815 }, /* 126 */ + { 0x2e06021c, 0x5000000 }, /* 135 */ + { 0x2e060220, 0x5030503 }, /* 136 */ + { 0x2e060224, 0x3 }, /* 137 */ + { 0x2e060228, 0x7010a09 }, /* 138 */ + { 0x2e06022c, 0xe0a09 }, /* 139 */ + { 0x2e060230, 0x10a0900 }, /* 140 */ + { 0x2e060234, 0xe0a0907 }, /* 141 */ + { 0x2e060238, 0xa090000 }, /* 142 */ + { 0x2e06023c, 0xa090701 }, /* 143 */ + { 0x2e060240, 0x101000e }, /* 144 */ + { 0x2e060244, 0x40003 }, /* 145 */ + { 0x2e060248, 0x7 }, /* 146 */ + { 0x2e060264, 0x4040100 }, /* 153 */ + { 0x2e060268, 0x1000000 }, /* 154 */ + { 0x2e06026c, 0x100000c0 }, /* 155 */ + { 0x2e060270, 0x100000c0 }, /* 156 */ + { 0x2e060274, 0x100000c0 }, /* 157 */ + { 0x2e06027c, 0x1600 }, /* 159 */ + { 0x2e060284, 0x1 }, /* 161 */ + { 0x2e060288, 0x2 }, /* 162 */ + { 0x2e06028c, 0x100e }, /* 163 */ + { 0x2e0602a4, 0xa0000 }, /* 169 */ + { 0x2e0602a8, 0xd0005 }, /* 170 */ + { 0x2e0602ac, 0x404 }, /* 171 */ + { 0x2e0602b0, 0xd }, /* 172 */ + { 0x2e0602b4, 0x1b0035 }, /* 173 */ + { 0x2e0602b8, 0x4040042 }, /* 174 */ + { 0x2e0602bc, 0x42 }, /* 175 */ + { 0x2e0602c0, 0x35006a }, /* 176 */ + { 0x2e0602c4, 0x4040084 }, /* 177 */ + { 0x2e0602c8, 0x84 }, /* 178 */ + { 0x2e0602d8, 0x40004 }, /* 182 */ + { 0x2e0602dc, 0x30000914 }, /* 183 */ + { 0x2e0602e0, 0x3030 }, /* 184 */ + { 0x2e0602e4, 0x44440000 }, /* 185 */ + { 0x2e0602e8, 0x19191944 }, /* 186 */ + { 0x2e0602ec, 0x19191908 }, /* 187 */ + { 0x2e0602f0, 0x4000000 }, /* 188 */ + { 0x2e0602f4, 0x40404 }, /* 189 */ + { 0x2e0602f8, 0x9140004 }, /* 190 */ + { 0x2e0602fc, 0x30303000 }, /* 191 */ + { 0x2e060304, 0x19444444 }, /* 193 */ + { 0x2e060308, 0x19081919 }, /* 194 */ + { 0x2e06030c, 0x1919 }, /* 195 */ + { 0x2e060310, 0x4040400 }, /* 196 */ + { 0x2e060314, 0x1010120 }, /* 197 */ + { 0x2e060318, 0x1000100 }, /* 198 */ + { 0x2e06031c, 0x1 }, /* 199 */ + { 0x2e060324, 0x1000000 }, /* 201 */ + { 0x2e060328, 0x1 }, /* 202 */ + { 0x2e060354, 0x11000000 }, /* 213 */ + { 0x2e060358, 0x40c1815 }, /* 214 */ + { 0x2e060390, 0x30000 }, /* 228 */ + { 0x2e060394, 0x1000200 }, /* 229 */ + { 0x2e060398, 0x310040 }, /* 230 */ + { 0x2e06039c, 0x20002 }, /* 231 */ + { 0x2e0603a0, 0x400100 }, /* 232 */ + { 0x2e0603a4, 0x80108 }, /* 233 */ + { 0x2e0603a8, 0x1000200 }, /* 234 */ + { 0x2e0603ac, 0x2100040 }, /* 235 */ + { 0x2e0603b0, 0x10 }, /* 236 */ + { 0x2e0603b4, 0xe0003 }, /* 237 */ + { 0x2e0603b8, 0x100001b }, /* 238 */ + { 0x2e0603d8, 0xffff0b00 }, /* 246 */ + { 0x2e0603dc, 0x1010001 }, /* 247 */ + { 0x2e0603e0, 0x1010101 }, /* 248 */ + { 0x2e0603e4, 0x10b0101 }, /* 249 */ + { 0x2e0603e8, 0x10000 }, /* 250 */ + { 0x2e0603ec, 0x4010101 }, /* 251 */ + { 0x2e0603f0, 0x1010000 }, /* 252 */ + { 0x2e0603f4, 0x4 }, /* 253 */ + { 0x2e0603fc, 0x3030101 }, /* 255 */ + { 0x2e060400, 0x103 }, /* 256 */ + { 0x2e0604a4, 0x2020101 }, /* 297 */ + { 0x2e0604a8, 0x10100 }, /* 298 */ + { 0x2e0604ac, 0x1000101 }, /* 299 */ + { 0x2e0604b0, 0x1010101 }, /* 300 */ + { 0x2e0604b4, 0x4030300 }, /* 301 */ + { 0x2e0604b8, 0x8080505 }, /* 302 */ + { 0x2e0604bc, 0x8020808 }, /* 303 */ + { 0x2e0604c0, 0x8020e00 }, /* 304 */ + { 0x2e0604c4, 0xa020e00 }, /* 305 */ + { 0x2e0604c8, 0x8000f00 }, /* 306 */ + { 0x2e0604cc, 0xa08 }, /* 307 */ + { 0x2e0604d0, 0x1010101 }, /* 308 */ + { 0x2e0604d4, 0x102 }, /* 309 */ + { 0x2e0604d8, 0x404 }, /* 310 */ + { 0x2e0604dc, 0x40400 }, /* 311 */ + { 0x2e0604e0, 0x4040000 }, /* 312 */ + { 0x2e0604e4, 0x4000000 }, /* 313 */ + { 0x2e0604e8, 0x10004 }, /* 314 */ + { 0x2e0604f0, 0xfffff }, /* 316 */ + { 0x2e0604f8, 0xfffff }, /* 318 */ + { 0x2e060500, 0xfffff }, /* 320 */ + { 0x2e060508, 0xfffff }, /* 322 */ + { 0x2e060510, 0xfffff }, /* 324 */ + { 0x2e060518, 0xfffff }, /* 326 */ + { 0x2e060520, 0xfffff }, /* 328 */ + { 0x2e060528, 0xfffff }, /* 330 */ + { 0x2e060530, 0xfffff }, /* 332 */ + { 0x2e060538, 0xfffff }, /* 334 */ + { 0x2e060540, 0xfffff }, /* 336 */ + { 0x2e060548, 0xfffff }, /* 338 */ + { 0x2e060550, 0xfffff }, /* 340 */ + { 0x2e060558, 0xfffff }, /* 342 */ + { 0x2e060560, 0xfffff }, /* 344 */ + { 0x2e060568, 0xfffff }, /* 346 */ + { 0x2e060570, 0xfffff }, /* 348 */ + { 0x2e060578, 0xfffff }, /* 350 */ + { 0x2e060580, 0xfffff }, /* 352 */ + { 0x2e060588, 0xfffff }, /* 354 */ + { 0x2e060590, 0xfffff }, /* 356 */ + { 0x2e060598, 0xfffff }, /* 358 */ + { 0x2e0605a0, 0xfffff }, /* 360 */ + { 0x2e0605a8, 0xfffff }, /* 362 */ + { 0x2e0605b0, 0xfffff }, /* 364 */ + { 0x2e0605b8, 0xfffff }, /* 366 */ + { 0x2e0605c0, 0xfffff }, /* 368 */ + { 0x2e0605c8, 0xfffff }, /* 370 */ + { 0x2e0605d0, 0xfffff }, /* 372 */ + { 0x2e0605d8, 0xfffff }, /* 374 */ + { 0x2e0605e0, 0xfffff }, /* 376 */ + { 0x2e0605e8, 0xfffff }, /* 378 */ + { 0x2e0605f0, 0xfffff }, /* 380 */ + { 0x2e0605f8, 0xfffff }, /* 382 */ + { 0x2e060600, 0xfffff }, /* 384 */ + { 0x2e060608, 0xfffff }, /* 386 */ + { 0x2e060610, 0xfffff }, /* 388 */ + { 0x2e060618, 0xfffff }, /* 390 */ + { 0x2e060620, 0xfffff }, /* 392 */ + { 0x2e060628, 0xfffff }, /* 394 */ + { 0x2e060630, 0xfffff }, /* 396 */ + { 0x2e060638, 0xfffff }, /* 398 */ + { 0x2e060640, 0xfffff }, /* 400 */ + { 0x2e060648, 0xfffff }, /* 402 */ + { 0x2e060650, 0xfffff }, /* 404 */ + { 0x2e060658, 0xfffff }, /* 406 */ + { 0x2e060660, 0xfffff }, /* 408 */ + { 0x2e060668, 0xfffff }, /* 410 */ + { 0x2e060670, 0xfffff }, /* 412 */ + { 0x2e060678, 0xfffff }, /* 414 */ + { 0x2e060680, 0xfffff }, /* 416 */ + { 0x2e060688, 0xfffff }, /* 418 */ + { 0x2e060690, 0xfffff }, /* 420 */ + { 0x2e060698, 0xfffff }, /* 422 */ + { 0x2e0606a0, 0xfffff }, /* 424 */ + { 0x2e0606a8, 0xfffff }, /* 426 */ + { 0x2e0606b0, 0xfffff }, /* 428 */ + { 0x2e0606b8, 0xfffff }, /* 430 */ + { 0x2e0606c0, 0xfffff }, /* 432 */ + { 0x2e0606c8, 0xfffff }, /* 434 */ + { 0x2e0606d0, 0xfffff }, /* 436 */ + { 0x2e0606d8, 0xfffff }, /* 438 */ + { 0x2e0606e0, 0xfffff }, /* 440 */ + { 0x2e0606e8, 0x30fffff }, /* 442 */ + { 0x2e0606ec, 0xffffffff }, /* 443 */ + { 0x2e0606f0, 0x30f0f }, /* 444 */ + { 0x2e0606f4, 0xffffffff }, /* 445 */ + { 0x2e0606f8, 0x30f0f }, /* 446 */ + { 0x2e0606fc, 0xffffffff }, /* 447 */ + { 0x2e060700, 0x30f0f }, /* 448 */ + { 0x2e060704, 0xffffffff }, /* 449 */ + { 0x2e060708, 0x30f0f }, /* 450 */ + { 0x2e06070c, 0xffffffff }, /* 451 */ + { 0x2e060710, 0x30f0f }, /* 452 */ + { 0x2e060714, 0xffffffff }, /* 453 */ + { 0x2e060718, 0x30f0f }, /* 454 */ + { 0x2e06071c, 0xffffffff }, /* 455 */ + { 0x2e060720, 0x30f0f }, /* 456 */ + { 0x2e060724, 0xffffffff }, /* 457 */ + { 0x2e060728, 0x30f0f }, /* 458 */ + { 0x2e06072c, 0xffffffff }, /* 459 */ + { 0x2e060730, 0x30f0f }, /* 460 */ + { 0x2e060734, 0xffffffff }, /* 461 */ + { 0x2e060738, 0x30f0f }, /* 462 */ + { 0x2e06073c, 0xffffffff }, /* 463 */ + { 0x2e060740, 0x30f0f }, /* 464 */ + { 0x2e060744, 0xffffffff }, /* 465 */ + { 0x2e060748, 0x30f0f }, /* 466 */ + { 0x2e06074c, 0xffffffff }, /* 467 */ + { 0x2e060750, 0x30f0f }, /* 468 */ + { 0x2e060754, 0xffffffff }, /* 469 */ + { 0x2e060758, 0x30f0f }, /* 470 */ + { 0x2e06075c, 0xffffffff }, /* 471 */ + { 0x2e060760, 0x30f0f }, /* 472 */ + { 0x2e060764, 0xffffffff }, /* 473 */ + { 0x2e060768, 0x30f0f }, /* 474 */ + { 0x2e06076c, 0xffffffff }, /* 475 */ + { 0x2e060770, 0x30f0f }, /* 476 */ + { 0x2e060774, 0xffffffff }, /* 477 */ + { 0x2e060778, 0x30f0f }, /* 478 */ + { 0x2e06077c, 0xffffffff }, /* 479 */ + { 0x2e060780, 0x30f0f }, /* 480 */ + { 0x2e060784, 0xffffffff }, /* 481 */ + { 0x2e060788, 0x30f0f }, /* 482 */ + { 0x2e06078c, 0xffffffff }, /* 483 */ + { 0x2e060790, 0x30f0f }, /* 484 */ + { 0x2e060794, 0xffffffff }, /* 485 */ + { 0x2e060798, 0x30f0f }, /* 486 */ + { 0x2e06079c, 0xffffffff }, /* 487 */ + { 0x2e0607a0, 0x30f0f }, /* 488 */ + { 0x2e0607a4, 0xffffffff }, /* 489 */ + { 0x2e0607a8, 0x30f0f }, /* 490 */ + { 0x2e0607ac, 0xffffffff }, /* 491 */ + { 0x2e0607b0, 0x30f0f }, /* 492 */ + { 0x2e0607b4, 0xffffffff }, /* 493 */ + { 0x2e0607b8, 0x30f0f }, /* 494 */ + { 0x2e0607bc, 0xffffffff }, /* 495 */ + { 0x2e0607c0, 0x30f0f }, /* 496 */ + { 0x2e0607c4, 0xffffffff }, /* 497 */ + { 0x2e0607c8, 0x30f0f }, /* 498 */ + { 0x2e0607cc, 0xffffffff }, /* 499 */ + { 0x2e0607d0, 0x30f0f }, /* 500 */ + { 0x2e0607d4, 0xffffffff }, /* 501 */ + { 0x2e0607d8, 0x30f0f }, /* 502 */ + { 0x2e0607dc, 0xffffffff }, /* 503 */ + { 0x2e0607e0, 0x30f0f }, /* 504 */ + { 0x2e0607e4, 0xffffffff }, /* 505 */ + { 0x2e0607e8, 0x30f0f }, /* 506 */ + { 0x2e0607ec, 0xffffffff }, /* 507 */ + { 0x2e0607f0, 0x30f0f }, /* 508 */ + { 0x2e0607f4, 0xffffffff }, /* 509 */ + { 0x2e0607f8, 0x30f0f }, /* 510 */ + { 0x2e0607fc, 0xffffffff }, /* 511 */ + { 0x2e060800, 0x30f0f }, /* 512 */ + { 0x2e060804, 0xffffffff }, /* 513 */ + { 0x2e060808, 0x30f0f }, /* 514 */ + { 0x2e06080c, 0xffffffff }, /* 515 */ + { 0x2e060810, 0x30f0f }, /* 516 */ + { 0x2e060814, 0xffffffff }, /* 517 */ + { 0x2e060818, 0x30f0f }, /* 518 */ + { 0x2e06081c, 0xffffffff }, /* 519 */ + { 0x2e060820, 0x30f0f }, /* 520 */ + { 0x2e060824, 0xffffffff }, /* 521 */ + { 0x2e060828, 0x30f0f }, /* 522 */ + { 0x2e06082c, 0xffffffff }, /* 523 */ + { 0x2e060830, 0x30f0f }, /* 524 */ + { 0x2e060834, 0xffffffff }, /* 525 */ + { 0x2e060838, 0x30f0f }, /* 526 */ + { 0x2e06083c, 0xffffffff }, /* 527 */ + { 0x2e060840, 0x30f0f }, /* 528 */ + { 0x2e060844, 0xffffffff }, /* 529 */ + { 0x2e060848, 0x30f0f }, /* 530 */ + { 0x2e06084c, 0xffffffff }, /* 531 */ + { 0x2e060850, 0x30f0f }, /* 532 */ + { 0x2e060854, 0xffffffff }, /* 533 */ + { 0x2e060858, 0x30f0f }, /* 534 */ + { 0x2e06085c, 0xffffffff }, /* 535 */ + { 0x2e060860, 0x30f0f }, /* 536 */ + { 0x2e060864, 0xffffffff }, /* 537 */ + { 0x2e060868, 0x30f0f }, /* 538 */ + { 0x2e06086c, 0xffffffff }, /* 539 */ + { 0x2e060870, 0x30f0f }, /* 540 */ + { 0x2e060874, 0xffffffff }, /* 541 */ + { 0x2e060878, 0x30f0f }, /* 542 */ + { 0x2e06087c, 0xffffffff }, /* 543 */ + { 0x2e060880, 0x30f0f }, /* 544 */ + { 0x2e060884, 0xffffffff }, /* 545 */ + { 0x2e060888, 0x30f0f }, /* 546 */ + { 0x2e06088c, 0xffffffff }, /* 547 */ + { 0x2e060890, 0x30f0f }, /* 548 */ + { 0x2e060894, 0xffffffff }, /* 549 */ + { 0x2e060898, 0x30f0f }, /* 550 */ + { 0x2e06089c, 0xffffffff }, /* 551 */ + { 0x2e0608a0, 0x30f0f }, /* 552 */ + { 0x2e0608a4, 0xffffffff }, /* 553 */ + { 0x2e0608a8, 0x30f0f }, /* 554 */ + { 0x2e0608ac, 0xffffffff }, /* 555 */ + { 0x2e0608b0, 0x30f0f }, /* 556 */ + { 0x2e0608b4, 0xffffffff }, /* 557 */ + { 0x2e0608b8, 0x30f0f }, /* 558 */ + { 0x2e0608bc, 0xffffffff }, /* 559 */ + { 0x2e0608c0, 0x30f0f }, /* 560 */ + { 0x2e0608c4, 0xffffffff }, /* 561 */ + { 0x2e0608c8, 0x30f0f }, /* 562 */ + { 0x2e0608cc, 0xffffffff }, /* 563 */ + { 0x2e0608d0, 0x30f0f }, /* 564 */ + { 0x2e0608d4, 0xffffffff }, /* 565 */ + { 0x2e0608d8, 0x30f0f }, /* 566 */ + { 0x2e0608dc, 0xffffffff }, /* 567 */ + { 0x2e0608e0, 0x30f0f }, /* 568 */ + { 0x2e0608e4, 0xffffffff }, /* 569 */ + { 0x2e0608e8, 0x32070f0f }, /* 570 */ + { 0x2e0608ec, 0x1320001 }, /* 571 */ + { 0x2e0608f0, 0x13200 }, /* 572 */ + { 0x2e0608f4, 0x132 }, /* 573 */ + { 0x2e0608fc, 0x1d1b0000 }, /* 575 */ + { 0x2e060900, 0x21 }, /* 576 */ + { 0x2e060904, 0xa }, /* 577 */ + { 0x2e060908, 0x166 }, /* 578 */ + { 0x2e06090c, 0x200 }, /* 579 */ + { 0x2e060910, 0x200 }, /* 580 */ + { 0x2e060914, 0x200 }, /* 581 */ + { 0x2e060918, 0x200 }, /* 582 */ + { 0x2e06091c, 0x432 }, /* 583 */ + { 0x2e060920, 0xdfc }, /* 584 */ + { 0x2e060924, 0x204 }, /* 585 */ + { 0x2e060928, 0x7fa }, /* 586 */ + { 0x2e06092c, 0x200 }, /* 587 */ + { 0x2e060930, 0x200 }, /* 588 */ + { 0x2e060934, 0x200 }, /* 589 */ + { 0x2e060938, 0x200 }, /* 590 */ + { 0x2e06093c, 0x17ee }, /* 591 */ + { 0x2e060940, 0x4fc4 }, /* 592 */ + { 0x2e060944, 0x204 }, /* 593 */ + { 0x2e060948, 0x1006 }, /* 594 */ + { 0x2e06094c, 0x200 }, /* 595 */ + { 0x2e060950, 0x200 }, /* 596 */ + { 0x2e060954, 0x200 }, /* 597 */ + { 0x2e060958, 0x200 }, /* 598 */ + { 0x2e06095c, 0x3012 }, /* 599 */ + { 0x2e060960, 0xa03c }, /* 600 */ + { 0x2e060964, 0x2020406 }, /* 601 */ + { 0x2e060968, 0x2030202 }, /* 602 */ + { 0x2e06096c, 0x1000202 }, /* 603 */ + { 0x2e060970, 0x3040100 }, /* 604 */ + { 0x2e060974, 0x10105 }, /* 605 */ + { 0x2e060978, 0x10101 }, /* 606 */ + { 0x2e06097c, 0x10101 }, /* 607 */ + { 0x2e060980, 0x10001 }, /* 608 */ + { 0x2e060984, 0x101 }, /* 609 */ + { 0x2e060988, 0x2000201 }, /* 610 */ + { 0x2e06098c, 0x2010000 }, /* 611 */ + { 0x2e060990, 0x6000200 }, /* 612 */ + { 0x2e060994, 0x3000a06 }, /* 613 */ + { 0x2e060998, 0x2000c06 }, /* 614 */ +}; + +/** PI settings **/ +struct dram_cfg_param ddr_pi_cfg[] = { + { 0x2e062000, 0xb00 }, /* 0 */ + { 0x2e062004, 0xbeedb66f }, /* 1 */ + { 0x2e062008, 0xabef6bd }, /* 2 */ + { 0x2e06200c, 0x1001387 }, /* 3 */ + { 0x2e062010, 0x1 }, /* 4 */ + { 0x2e062014, 0x10064 }, /* 5 */ + { 0x2e06202c, 0x201 }, /* 11 */ + { 0x2e062030, 0x7 }, /* 12 */ + { 0x2e062034, 0x50001 }, /* 13 */ + { 0x2e062038, 0x3030800 }, /* 14 */ + { 0x2e06203c, 0x1 }, /* 15 */ + { 0x2e062040, 0x5 }, /* 16 */ + { 0x2e062064, 0x1000000 }, /* 25 */ + { 0x2e062068, 0xa000001 }, /* 26 */ + { 0x2e06206c, 0x28 }, /* 27 */ + { 0x2e062070, 0x1 }, /* 28 */ + { 0x2e062074, 0x320005 }, /* 29 */ + { 0x2e062080, 0x10102 }, /* 32 */ + { 0x2e062084, 0x1 }, /* 33 */ + { 0x2e062088, 0xaa }, /* 34 */ + { 0x2e06208c, 0x55 }, /* 35 */ + { 0x2e062090, 0xb5 }, /* 36 */ + { 0x2e062094, 0x4a }, /* 37 */ + { 0x2e062098, 0x56 }, /* 38 */ + { 0x2e06209c, 0xa9 }, /* 39 */ + { 0x2e0620a0, 0xa9 }, /* 40 */ + { 0x2e0620a4, 0xb5 }, /* 41 */ + { 0x2e0620a8, 0x10000 }, /* 42 */ + { 0x2e0620ac, 0x100 }, /* 43 */ + { 0x2e0620b0, 0x5050000 }, /* 44 */ + { 0x2e0620b4, 0x13 }, /* 45 */ + { 0x2e0620b8, 0x7d0 }, /* 46 */ + { 0x2e0620bc, 0x300 }, /* 47 */ + { 0x2e0620c8, 0x1000000 }, /* 50 */ + { 0x2e0620cc, 0x10101 }, /* 51 */ + { 0x2e0620d8, 0x10003 }, /* 54 */ + { 0x2e0620dc, 0x170500 }, /* 55 */ + { 0x2e0620ec, 0xa140a01 }, /* 59 */ + { 0x2e0620f0, 0x204010a }, /* 60 */ + { 0x2e0620f4, 0x21010 }, /* 61 */ + { 0x2e0620f8, 0x40401 }, /* 62 */ + { 0x2e0620fc, 0x10e0005 }, /* 63 */ + { 0x2e062100, 0x5000001 }, /* 64 */ + { 0x2e062104, 0x204 }, /* 65 */ + { 0x2e062108, 0x34 }, /* 66 */ + { 0x2e062114, 0x1000000 }, /* 69 */ + { 0x2e062118, 0x1000000 }, /* 70 */ + { 0x2e06211c, 0x80200 }, /* 71 */ + { 0x2e062120, 0x2000200 }, /* 72 */ + { 0x2e062124, 0x1000100 }, /* 73 */ + { 0x2e062128, 0x1000000 }, /* 74 */ + { 0x2e06212c, 0x2000200 }, /* 75 */ + { 0x2e062130, 0x200 }, /* 76 */ + { 0x2e062164, 0x400 }, /* 89 */ + { 0x2e062168, 0x2010000 }, /* 90 */ + { 0x2e06216c, 0x80103 }, /* 91 */ + { 0x2e062174, 0x10008 }, /* 93 */ + { 0x2e06217c, 0xaa00 }, /* 95 */ + { 0x2e062188, 0x10000 }, /* 98 */ + { 0x2e0621ec, 0x8 }, /* 123 */ + { 0x2e062218, 0xf0000 }, /* 134 */ + { 0x2e06221c, 0xa }, /* 135 */ + { 0x2e062220, 0x19 }, /* 136 */ + { 0x2e062224, 0x100 }, /* 137 */ + { 0x2e062228, 0x100 }, /* 138 */ + { 0x2e062238, 0x1000000 }, /* 142 */ + { 0x2e06223c, 0x10003 }, /* 143 */ + { 0x2e062240, 0x2000101 }, /* 144 */ + { 0x2e062244, 0x1030001 }, /* 145 */ + { 0x2e062248, 0x10400 }, /* 146 */ + { 0x2e06224c, 0x6000105 }, /* 147 */ + { 0x2e062250, 0x1070001 }, /* 148 */ + { 0x2e062260, 0x10001 }, /* 152 */ + { 0x2e062274, 0x401 }, /* 157 */ + { 0x2e06227c, 0x10000 }, /* 159 */ + { 0x2e062284, 0x6010000 }, /* 161 */ + { 0x2e062288, 0xb }, /* 162 */ + { 0x2e06228c, 0x34 }, /* 163 */ + { 0x2e062290, 0x36 }, /* 164 */ + { 0x2e062294, 0x2003c }, /* 165 */ + { 0x2e062298, 0x2000200 }, /* 166 */ + { 0x2e06229c, 0xc040c04 }, /* 167 */ + { 0x2e0622a0, 0xe1406 }, /* 168 */ + { 0x2e0622a4, 0xb3 }, /* 169 */ + { 0x2e0622a8, 0x4a }, /* 170 */ + { 0x2e0622ac, 0x3fd }, /* 171 */ + { 0x2e0622b0, 0x94 }, /* 172 */ + { 0x2e0622b4, 0x4000803 }, /* 173 */ + { 0x2e0622b8, 0x1010404 }, /* 174 */ + { 0x2e0622bc, 0x1501 }, /* 175 */ + { 0x2e0622c0, 0x1a0018 }, /* 176 */ + { 0x2e0622c4, 0x1000100 }, /* 177 */ + { 0x2e0622c8, 0x100 }, /* 178 */ + { 0x2e0622d0, 0x5040303 }, /* 180 */ + { 0x2e0622d4, 0x1010805 }, /* 181 */ + { 0x2e0622d8, 0x1010101 }, /* 182 */ + { 0x2e0622e8, 0x2060404 }, /* 186 */ + { 0x2e0622ec, 0x2020402 }, /* 187 */ + { 0x2e0622f0, 0x3102 }, /* 188 */ + { 0x2e0622f4, 0x340009 }, /* 189 */ + { 0x2e0622f8, 0x36000c }, /* 190 */ + { 0x2e0622fc, 0x101000e }, /* 191 */ + { 0x2e062300, 0xd0101 }, /* 192 */ + { 0x2e062304, 0x1004201 }, /* 193 */ + { 0x2e062308, 0x1000084 }, /* 194 */ + { 0x2e06230c, 0xe000e }, /* 195 */ + { 0x2e062310, 0x430100 }, /* 196 */ + { 0x2e062314, 0x1000043 }, /* 197 */ + { 0x2e062318, 0x850085 }, /* 198 */ + { 0x2e06231c, 0x220f220f }, /* 199 */ + { 0x2e062320, 0x101220f }, /* 200 */ + { 0x2e062324, 0xa070601 }, /* 201 */ + { 0x2e062328, 0xa07060d }, /* 202 */ + { 0x2e06232c, 0xa07070d }, /* 203 */ + { 0x2e062330, 0xc00d }, /* 204 */ + { 0x2e062334, 0xc01000 }, /* 205 */ + { 0x2e062338, 0xc01000 }, /* 206 */ + { 0x2e06233c, 0x21000 }, /* 207 */ + { 0x2e062340, 0x11000d }, /* 208 */ + { 0x2e062344, 0x140042 }, /* 209 */ + { 0x2e062348, 0x190084 }, /* 210 */ + { 0x2e06234c, 0x220f0056 }, /* 211 */ + { 0x2e062350, 0x101 }, /* 212 */ + { 0x2e062354, 0x560019 }, /* 213 */ + { 0x2e062358, 0x101220f }, /* 214 */ + { 0x2e06235c, 0x1b00 }, /* 215 */ + { 0x2e062360, 0x220f0056 }, /* 216 */ + { 0x2e062364, 0x8000101 }, /* 217 */ + { 0x2e062368, 0x4090403 }, /* 218 */ + { 0x2e06236c, 0x5eb }, /* 219 */ + { 0x2e062370, 0x20010003 }, /* 220 */ + { 0x2e062374, 0x80a0a03 }, /* 221 */ + { 0x2e062378, 0x6090506 }, /* 222 */ + { 0x2e06237c, 0x2093 }, /* 223 */ + { 0x2e062380, 0x2001000c }, /* 224 */ + { 0x2e062384, 0x80a0a04 }, /* 225 */ + { 0x2e062388, 0xb090a0c }, /* 226 */ + { 0x2e06238c, 0x4126 }, /* 227 */ + { 0x2e062390, 0x20020017 }, /* 228 */ + { 0x2e062394, 0xa0a08 }, /* 229 */ + { 0x2e062398, 0x166 }, /* 230 */ + { 0x2e06239c, 0xdfc }, /* 231 */ + { 0x2e0623a0, 0x7fa }, /* 232 */ + { 0x2e0623a4, 0x4fc4 }, /* 233 */ + { 0x2e0623a8, 0x1006 }, /* 234 */ + { 0x2e0623ac, 0xa03c }, /* 235 */ + { 0x2e0623b0, 0x4c000e }, /* 236 */ + { 0x2e0623b4, 0x3030098 }, /* 237 */ + { 0x2e0623b8, 0x258103 }, /* 238 */ + { 0x2e0623bc, 0x17702 }, /* 239 */ + { 0x2e0623c0, 0x5 }, /* 240 */ + { 0x2e0623c4, 0x61 }, /* 241 */ + { 0x2e0623c8, 0xe }, /* 242 */ + { 0x2e0623cc, 0xce3f }, /* 243 */ + { 0x2e0623d0, 0x80e70 }, /* 244 */ + { 0x2e0623d4, 0x5 }, /* 245 */ + { 0x2e0623d8, 0x210 }, /* 246 */ + { 0x2e0623dc, 0x4c }, /* 247 */ + { 0x2e0623e0, 0x19c7d }, /* 248 */ + { 0x2e0623e4, 0x101cdf }, /* 249 */ + { 0x2e0623e8, 0x5 }, /* 250 */ + { 0x2e0623ec, 0x420 }, /* 251 */ + { 0x2e0623f0, 0x1000098 }, /* 252 */ + { 0x2e0623f4, 0x310040 }, /* 253 */ + { 0x2e0623f8, 0x10002 }, /* 254 */ + { 0x2e0623fc, 0x1080040 }, /* 255 */ + { 0x2e062400, 0x10008 }, /* 256 */ + { 0x2e062404, 0x2100040 }, /* 257 */ + { 0x2e062408, 0x310 }, /* 258 */ + { 0x2e06240c, 0x1b000e }, /* 259 */ + { 0x2e062410, 0x1010101 }, /* 260 */ + { 0x2e062414, 0x2020101 }, /* 261 */ + { 0x2e062418, 0x8080404 }, /* 262 */ + { 0x2e06241c, 0x5508 }, /* 263 */ + { 0x2e062420, 0x83c5a00 }, /* 264 */ + { 0x2e062424, 0x55 }, /* 265 */ + { 0x2e062428, 0x55083c5a }, /* 266 */ + { 0x2e06242c, 0x5a000000 }, /* 267 */ + { 0x2e062430, 0x55083c }, /* 268 */ + { 0x2e062434, 0x3c5a0000 }, /* 269 */ + { 0x2e062438, 0xf0e0d0c }, /* 270 */ + { 0x2e06243c, 0xb0a0908 }, /* 271 */ + { 0x2e062440, 0x7060504 }, /* 272 */ + { 0x2e062444, 0x3020100 }, /* 273 */ + { 0x2e06244c, 0x2020101 }, /* 275 */ + { 0x2e062450, 0x8080404 }, /* 276 */ + { 0x2e062454, 0x44300004 }, /* 277 */ + { 0x2e062458, 0x4041919 }, /* 278 */ + { 0x2e06245c, 0x19443000 }, /* 279 */ + { 0x2e062460, 0x9140419 }, /* 280 */ + { 0x2e062464, 0x19194430 }, /* 281 */ + { 0x2e062468, 0x30000404 }, /* 282 */ + { 0x2e06246c, 0x4191944 }, /* 283 */ + { 0x2e062470, 0x44300004 }, /* 284 */ + { 0x2e062474, 0x14041919 }, /* 285 */ + { 0x2e062478, 0x19443009 }, /* 286 */ + { 0x2e06247c, 0x40419 }, /* 287 */ + { 0x2e062480, 0x19194430 }, /* 288 */ + { 0x2e062484, 0x30000404 }, /* 289 */ + { 0x2e062488, 0x4191944 }, /* 290 */ + { 0x2e06248c, 0x44300914 }, /* 291 */ + { 0x2e062490, 0x44041919 }, /* 292 */ + { 0x2e062494, 0x19443000 }, /* 293 */ + { 0x2e062498, 0x40419 }, /* 294 */ + { 0x2e06249c, 0x19194430 }, /* 295 */ + { 0x2e0624a0, 0x30091404 }, /* 296 */ + { 0x2e0624a4, 0x4191944 }, /* 297 */ +}; + +/** PHY_F1 settings **/ +struct dram_cfg_param ddr_phy_f1_cfg[] = { + { 0x2e064000, 0x4f0 }, /* 0 */ + { 0x2e064008, 0x1030200 }, /* 2 */ + { 0x2e064014, 0x3000000 }, /* 5 */ + { 0x2e064018, 0x1000001 }, /* 6 */ + { 0x2e06401c, 0x3000400 }, /* 7 */ + { 0x2e064020, 0x1 }, /* 8 */ + { 0x2e064024, 0x1 }, /* 9 */ + { 0x2e064030, 0x10000 }, /* 12 */ + { 0x2e064038, 0xc00004 }, /* 14 */ + { 0x2e06403c, 0xcc0008 }, /* 15 */ + { 0x2e064040, 0x660601 }, /* 16 */ + { 0x2e064044, 0x3 }, /* 17 */ + { 0x2e06404c, 0x1 }, /* 19 */ + { 0x2e064050, 0xaaaa }, /* 20 */ + { 0x2e064054, 0x5555 }, /* 21 */ + { 0x2e064058, 0xb5b5 }, /* 22 */ + { 0x2e06405c, 0x4a4a }, /* 23 */ + { 0x2e064060, 0x5656 }, /* 24 */ + { 0x2e064064, 0xa9a9 }, /* 25 */ + { 0x2e064068, 0xb7b7 }, /* 26 */ + { 0x2e06406c, 0x4848 }, /* 27 */ + { 0x2e064078, 0x8000000 }, /* 30 */ + { 0x2e06407c, 0x4010008 }, /* 31 */ + { 0x2e064080, 0x408 }, /* 32 */ + { 0x2e064084, 0x3102000 }, /* 33 */ + { 0x2e064088, 0xc0020 }, /* 34 */ + { 0x2e06408c, 0x10000 }, /* 35 */ + { 0x2e064090, 0x55555555 }, /* 36 */ + { 0x2e064094, 0xaaaaaaaa }, /* 37 */ + { 0x2e064098, 0x55555555 }, /* 38 */ + { 0x2e06409c, 0xaaaaaaaa }, /* 39 */ + { 0x2e0640a0, 0x5555 }, /* 40 */ + { 0x2e0640a4, 0x1000100 }, /* 41 */ + { 0x2e0640a8, 0x800180 }, /* 42 */ + { 0x2e0640ac, 0x1 }, /* 43 */ + { 0x2e064100, 0x4 }, /* 64 */ + { 0x2e06411c, 0x41f07ff }, /* 71 */ + { 0x2e064120, 0x1 }, /* 72 */ + { 0x2e064124, 0x1cc0800 }, /* 73 */ + { 0x2e064128, 0x3003cc08 }, /* 74 */ + { 0x2e06412c, 0x2000014e }, /* 75 */ + { 0x2e064130, 0x7ff0200 }, /* 76 */ + { 0x2e064134, 0x301 }, /* 77 */ + { 0x2e064140, 0x30000 }, /* 80 */ + { 0x2e064154, 0x2000000 }, /* 85 */ + { 0x2e064158, 0x51515042 }, /* 86 */ + { 0x2e06415c, 0x31c06000 }, /* 87 */ + { 0x2e064160, 0x9bf000a }, /* 88 */ + { 0x2e064164, 0xc0c000 }, /* 89 */ + { 0x2e064168, 0x1000000 }, /* 90 */ + { 0x2e06416c, 0x10001000 }, /* 91 */ + { 0x2e064170, 0xc043242 }, /* 92 */ + { 0x2e064174, 0xf0c1201 }, /* 93 */ + { 0x2e064178, 0x1000140 }, /* 94 */ + { 0x2e06417c, 0xc000120 }, /* 95 */ + { 0x2e064180, 0x143 }, /* 96 */ + { 0x2e064184, 0x1000203 }, /* 97 */ + { 0x2e064188, 0x56417032 }, /* 98 */ + { 0x2e06418c, 0x8 }, /* 99 */ + { 0x2e064190, 0x2c302c3 }, /* 100 */ + { 0x2e064194, 0x2c302c3 }, /* 101 */ + { 0x2e064198, 0x2c302c3 }, /* 102 */ + { 0x2e06419c, 0x2c302c3 }, /* 103 */ + { 0x2e0641a0, 0x2c3 }, /* 104 */ + { 0x2e0641a4, 0x8000 }, /* 105 */ + { 0x2e0641a8, 0x800080 }, /* 106 */ + { 0x2e0641ac, 0x800080 }, /* 107 */ + { 0x2e0641b0, 0x800080 }, /* 108 */ + { 0x2e0641b4, 0x800080 }, /* 109 */ + { 0x2e0641b8, 0x800080 }, /* 110 */ + { 0x2e0641bc, 0x800080 }, /* 111 */ + { 0x2e0641c0, 0x800080 }, /* 112 */ + { 0x2e0641c4, 0x800080 }, /* 113 */ + { 0x2e0641c8, 0x6b0080 }, /* 114 */ + { 0x2e0641cc, 0x1a00001 }, /* 115 */ + { 0x2e0641d4, 0x10000 }, /* 117 */ + { 0x2e0641d8, 0x80200 }, /* 118 */ + { 0x2e064400, 0x4f0 }, /* 256 */ + { 0x2e064408, 0x1030200 }, /* 258 */ + { 0x2e064414, 0x3000000 }, /* 261 */ + { 0x2e064418, 0x1000001 }, /* 262 */ + { 0x2e06441c, 0x3000400 }, /* 263 */ + { 0x2e064420, 0x1 }, /* 264 */ + { 0x2e064424, 0x1 }, /* 265 */ + { 0x2e064430, 0x10000 }, /* 268 */ + { 0x2e064438, 0xc00004 }, /* 270 */ + { 0x2e06443c, 0xcc0008 }, /* 271 */ + { 0x2e064440, 0x660601 }, /* 272 */ + { 0x2e064444, 0x3 }, /* 273 */ + { 0x2e06444c, 0x1 }, /* 275 */ + { 0x2e064450, 0xaaaa }, /* 276 */ + { 0x2e064454, 0x5555 }, /* 277 */ + { 0x2e064458, 0xb5b5 }, /* 278 */ + { 0x2e06445c, 0x4a4a }, /* 279 */ + { 0x2e064460, 0x5656 }, /* 280 */ + { 0x2e064464, 0xa9a9 }, /* 281 */ + { 0x2e064468, 0xb7b7 }, /* 282 */ + { 0x2e06446c, 0x4848 }, /* 283 */ + { 0x2e064478, 0x8000000 }, /* 286 */ + { 0x2e06447c, 0x4010008 }, /* 287 */ + { 0x2e064480, 0x408 }, /* 288 */ + { 0x2e064484, 0x3102000 }, /* 289 */ + { 0x2e064488, 0xc0020 }, /* 290 */ + { 0x2e06448c, 0x10000 }, /* 291 */ + { 0x2e064490, 0x55555555 }, /* 292 */ + { 0x2e064494, 0xaaaaaaaa }, /* 293 */ + { 0x2e064498, 0x55555555 }, /* 294 */ + { 0x2e06449c, 0xaaaaaaaa }, /* 295 */ + { 0x2e0644a0, 0x5555 }, /* 296 */ + { 0x2e0644a4, 0x1000100 }, /* 297 */ + { 0x2e0644a8, 0x800180 }, /* 298 */ + { 0x2e064500, 0x4 }, /* 320 */ + { 0x2e06451c, 0x41f07ff }, /* 327 */ + { 0x2e064520, 0x1 }, /* 328 */ + { 0x2e064524, 0x1cc0800 }, /* 329 */ + { 0x2e064528, 0x3003cc08 }, /* 330 */ + { 0x2e06452c, 0x2000014e }, /* 331 */ + { 0x2e064530, 0x7ff0200 }, /* 332 */ + { 0x2e064534, 0x301 }, /* 333 */ + { 0x2e064540, 0x30000 }, /* 336 */ + { 0x2e064554, 0x2000000 }, /* 341 */ + { 0x2e064558, 0x51515042 }, /* 342 */ + { 0x2e06455c, 0x31c06000 }, /* 343 */ + { 0x2e064560, 0x9bf000a }, /* 344 */ + { 0x2e064564, 0xc0c000 }, /* 345 */ + { 0x2e064568, 0x1000000 }, /* 346 */ + { 0x2e06456c, 0x10001000 }, /* 347 */ + { 0x2e064570, 0xc043242 }, /* 348 */ + { 0x2e064574, 0xf0c1201 }, /* 349 */ + { 0x2e064578, 0x1000140 }, /* 350 */ + { 0x2e06457c, 0xc000120 }, /* 351 */ + { 0x2e064580, 0x143 }, /* 352 */ + { 0x2e064584, 0x1000203 }, /* 353 */ + { 0x2e064588, 0x30217465 }, /* 354 */ + { 0x2e06458c, 0x8 }, /* 355 */ + { 0x2e064590, 0x2c302c3 }, /* 356 */ + { 0x2e064594, 0x2c302c3 }, /* 357 */ + { 0x2e064598, 0x2c302c3 }, /* 358 */ + { 0x2e06459c, 0x2c302c3 }, /* 359 */ + { 0x2e0645a0, 0x2c3 }, /* 360 */ + { 0x2e0645a4, 0x8000 }, /* 361 */ + { 0x2e0645a8, 0x800080 }, /* 362 */ + { 0x2e0645ac, 0x800080 }, /* 363 */ + { 0x2e0645b0, 0x800080 }, /* 364 */ + { 0x2e0645b4, 0x800080 }, /* 365 */ + { 0x2e0645b8, 0x800080 }, /* 366 */ + { 0x2e0645bc, 0x800080 }, /* 367 */ + { 0x2e0645c0, 0x800080 }, /* 368 */ + { 0x2e0645c4, 0x800080 }, /* 369 */ + { 0x2e0645c8, 0x6b0080 }, /* 370 */ + { 0x2e0645cc, 0x1a00001 }, /* 371 */ + { 0x2e0645d4, 0x10000 }, /* 373 */ + { 0x2e0645d8, 0x80200 }, /* 374 */ + { 0x2e064800, 0x4f0 }, /* 512 */ + { 0x2e064808, 0x1030200 }, /* 514 */ + { 0x2e064814, 0x3000000 }, /* 517 */ + { 0x2e064818, 0x1000001 }, /* 518 */ + { 0x2e06481c, 0x3000400 }, /* 519 */ + { 0x2e064820, 0x1 }, /* 520 */ + { 0x2e064824, 0x1 }, /* 521 */ + { 0x2e064830, 0x10000 }, /* 524 */ + { 0x2e064838, 0xc00004 }, /* 526 */ + { 0x2e06483c, 0xcc0008 }, /* 527 */ + { 0x2e064840, 0x660601 }, /* 528 */ + { 0x2e064844, 0x3 }, /* 529 */ + { 0x2e06484c, 0x1 }, /* 531 */ + { 0x2e064850, 0xaaaa }, /* 532 */ + { 0x2e064854, 0x5555 }, /* 533 */ + { 0x2e064858, 0xb5b5 }, /* 534 */ + { 0x2e06485c, 0x4a4a }, /* 535 */ + { 0x2e064860, 0x5656 }, /* 536 */ + { 0x2e064864, 0xa9a9 }, /* 537 */ + { 0x2e064868, 0xb7b7 }, /* 538 */ + { 0x2e06486c, 0x4848 }, /* 539 */ + { 0x2e064878, 0x8000000 }, /* 542 */ + { 0x2e06487c, 0x4010008 }, /* 543 */ + { 0x2e064880, 0x408 }, /* 544 */ + { 0x2e064884, 0x3102000 }, /* 545 */ + { 0x2e064888, 0xc0020 }, /* 546 */ + { 0x2e06488c, 0x10000 }, /* 547 */ + { 0x2e064890, 0x55555555 }, /* 548 */ + { 0x2e064894, 0xaaaaaaaa }, /* 549 */ + { 0x2e064898, 0x55555555 }, /* 550 */ + { 0x2e06489c, 0xaaaaaaaa }, /* 551 */ + { 0x2e0648a0, 0x5555 }, /* 552 */ + { 0x2e0648a4, 0x1000100 }, /* 553 */ + { 0x2e0648a8, 0x800180 }, /* 554 */ + { 0x2e0648ac, 0x1 }, /* 555 */ + { 0x2e064900, 0x4 }, /* 576 */ + { 0x2e06491c, 0x41f07ff }, /* 583 */ + { 0x2e064920, 0x1 }, /* 584 */ + { 0x2e064924, 0x1cc0800 }, /* 585 */ + { 0x2e064928, 0x3003cc08 }, /* 586 */ + { 0x2e06492c, 0x2000014e }, /* 587 */ + { 0x2e064930, 0x7ff0200 }, /* 588 */ + { 0x2e064934, 0x301 }, /* 589 */ + { 0x2e064940, 0x30000 }, /* 592 */ + { 0x2e064954, 0x2000000 }, /* 597 */ + { 0x2e064958, 0x51515042 }, /* 598 */ + { 0x2e06495c, 0x31c06000 }, /* 599 */ + { 0x2e064960, 0x9bf000a }, /* 600 */ + { 0x2e064964, 0xc0c000 }, /* 601 */ + { 0x2e064968, 0x1000000 }, /* 602 */ + { 0x2e06496c, 0x10001000 }, /* 603 */ + { 0x2e064970, 0xc043242 }, /* 604 */ + { 0x2e064974, 0xf0c1201 }, /* 605 */ + { 0x2e064978, 0x1000140 }, /* 606 */ + { 0x2e06497c, 0xc000120 }, /* 607 */ + { 0x2e064980, 0x143 }, /* 608 */ + { 0x2e064984, 0x1000203 }, /* 609 */ + { 0x2e064988, 0x75436012 }, /* 610 */ + { 0x2e06498c, 0x8 }, /* 611 */ + { 0x2e064990, 0x2c302c3 }, /* 612 */ + { 0x2e064994, 0x2c302c3 }, /* 613 */ + { 0x2e064998, 0x2c302c3 }, /* 614 */ + { 0x2e06499c, 0x2c302c3 }, /* 615 */ + { 0x2e0649a0, 0x2c3 }, /* 616 */ + { 0x2e0649a4, 0x8000 }, /* 617 */ + { 0x2e0649a8, 0x800080 }, /* 618 */ + { 0x2e0649ac, 0x800080 }, /* 619 */ + { 0x2e0649b0, 0x800080 }, /* 620 */ + { 0x2e0649b4, 0x800080 }, /* 621 */ + { 0x2e0649b8, 0x800080 }, /* 622 */ + { 0x2e0649bc, 0x800080 }, /* 623 */ + { 0x2e0649c0, 0x800080 }, /* 624 */ + { 0x2e0649c4, 0x800080 }, /* 625 */ + { 0x2e0649c8, 0x6b0080 }, /* 626 */ + { 0x2e0649cc, 0x1a00001 }, /* 627 */ + { 0x2e0649d4, 0x10000 }, /* 629 */ + { 0x2e0649d8, 0x80200 }, /* 630 */ + { 0x2e064c00, 0x4f0 }, /* 768 */ + { 0x2e064c08, 0x1030200 }, /* 770 */ + { 0x2e064c14, 0x3000000 }, /* 773 */ + { 0x2e064c18, 0x1000001 }, /* 774 */ + { 0x2e064c1c, 0x3000400 }, /* 775 */ + { 0x2e064c20, 0x1 }, /* 776 */ + { 0x2e064c24, 0x1 }, /* 777 */ + { 0x2e064c30, 0x10000 }, /* 780 */ + { 0x2e064c38, 0xc00004 }, /* 782 */ + { 0x2e064c3c, 0xcc0008 }, /* 783 */ + { 0x2e064c40, 0x660601 }, /* 784 */ + { 0x2e064c44, 0x3 }, /* 785 */ + { 0x2e064c4c, 0x1 }, /* 787 */ + { 0x2e064c50, 0xaaaa }, /* 788 */ + { 0x2e064c54, 0x5555 }, /* 789 */ + { 0x2e064c58, 0xb5b5 }, /* 790 */ + { 0x2e064c5c, 0x4a4a }, /* 791 */ + { 0x2e064c60, 0x5656 }, /* 792 */ + { 0x2e064c64, 0xa9a9 }, /* 793 */ + { 0x2e064c68, 0xb7b7 }, /* 794 */ + { 0x2e064c6c, 0x4848 }, /* 795 */ + { 0x2e064c78, 0x8000000 }, /* 798 */ + { 0x2e064c7c, 0x4010008 }, /* 799 */ + { 0x2e064c80, 0x408 }, /* 800 */ + { 0x2e064c84, 0x3102000 }, /* 801 */ + { 0x2e064c88, 0xc0020 }, /* 802 */ + { 0x2e064c8c, 0x10000 }, /* 803 */ + { 0x2e064c90, 0x55555555 }, /* 804 */ + { 0x2e064c94, 0xaaaaaaaa }, /* 805 */ + { 0x2e064c98, 0x55555555 }, /* 806 */ + { 0x2e064c9c, 0xaaaaaaaa }, /* 807 */ + { 0x2e064ca0, 0x5555 }, /* 808 */ + { 0x2e064ca4, 0x1000100 }, /* 809 */ + { 0x2e064ca8, 0x800180 }, /* 810 */ + { 0x2e064d00, 0x4 }, /* 832 */ + { 0x2e064d1c, 0x41f07ff }, /* 839 */ + { 0x2e064d20, 0x1 }, /* 840 */ + { 0x2e064d24, 0x1cc0800 }, /* 841 */ + { 0x2e064d28, 0x3003cc08 }, /* 842 */ + { 0x2e064d2c, 0x2000014e }, /* 843 */ + { 0x2e064d30, 0x7ff0200 }, /* 844 */ + { 0x2e064d34, 0x301 }, /* 845 */ + { 0x2e064d40, 0x30000 }, /* 848 */ + { 0x2e064d54, 0x2000000 }, /* 853 */ + { 0x2e064d58, 0x51515042 }, /* 854 */ + { 0x2e064d5c, 0x31c06000 }, /* 855 */ + { 0x2e064d60, 0x9bf000a }, /* 856 */ + { 0x2e064d64, 0xc0c000 }, /* 857 */ + { 0x2e064d68, 0x1000000 }, /* 858 */ + { 0x2e064d6c, 0x10001000 }, /* 859 */ + { 0x2e064d70, 0xc043242 }, /* 860 */ + { 0x2e064d74, 0xf0c1201 }, /* 861 */ + { 0x2e064d78, 0x1000140 }, /* 862 */ + { 0x2e064d7c, 0xc000120 }, /* 863 */ + { 0x2e064d80, 0x143 }, /* 864 */ + { 0x2e064d84, 0x1000203 }, /* 865 */ + { 0x2e064d88, 0x32017465 }, /* 866 */ + { 0x2e064d8c, 0x8 }, /* 867 */ + { 0x2e064d90, 0x2c302c3 }, /* 868 */ + { 0x2e064d94, 0x2c302c3 }, /* 869 */ + { 0x2e064d98, 0x2c302c3 }, /* 870 */ + { 0x2e064d9c, 0x2c302c3 }, /* 871 */ + { 0x2e064da0, 0x2c3 }, /* 872 */ + { 0x2e064da4, 0x8000 }, /* 873 */ + { 0x2e064da8, 0x800080 }, /* 874 */ + { 0x2e064dac, 0x800080 }, /* 875 */ + { 0x2e064db0, 0x800080 }, /* 876 */ + { 0x2e064db4, 0x800080 }, /* 877 */ + { 0x2e064db8, 0x800080 }, /* 878 */ + { 0x2e064dbc, 0x800080 }, /* 879 */ + { 0x2e064dc0, 0x800080 }, /* 880 */ + { 0x2e064dc4, 0x800080 }, /* 881 */ + { 0x2e064dc8, 0x6b0080 }, /* 882 */ + { 0x2e064dcc, 0x1a00001 }, /* 883 */ + { 0x2e064dd4, 0x10000 }, /* 885 */ + { 0x2e064dd8, 0x80200 }, /* 886 */ + { 0x2e065014, 0x100 }, /* 1029 */ + { 0x2e065018, 0x201 }, /* 1030 */ + { 0x2e06502c, 0x400000 }, /* 1035 */ + { 0x2e065030, 0x80 }, /* 1036 */ + { 0x2e065034, 0xdcba98 }, /* 1037 */ + { 0x2e065038, 0x3000000 }, /* 1038 */ + { 0x2e06504c, 0x2a }, /* 1043 */ + { 0x2e065050, 0x15 }, /* 1044 */ + { 0x2e065054, 0x15 }, /* 1045 */ + { 0x2e065058, 0x2a }, /* 1046 */ + { 0x2e06505c, 0x33 }, /* 1047 */ + { 0x2e065060, 0xc }, /* 1048 */ + { 0x2e065064, 0xc }, /* 1049 */ + { 0x2e065068, 0x33 }, /* 1050 */ + { 0x2e06506c, 0x543210 }, /* 1051 */ + { 0x2e065070, 0x3f0000 }, /* 1052 */ + { 0x2e065074, 0xf013f }, /* 1053 */ + { 0x2e065078, 0xf }, /* 1054 */ + { 0x2e06507c, 0x3cc }, /* 1055 */ + { 0x2e065080, 0x30000 }, /* 1056 */ + { 0x2e065084, 0x300 }, /* 1057 */ + { 0x2e065088, 0x300 }, /* 1058 */ + { 0x2e06508c, 0x300 }, /* 1059 */ + { 0x2e065090, 0x300 }, /* 1060 */ + { 0x2e065094, 0x300 }, /* 1061 */ + { 0x2e065098, 0x42080010 }, /* 1062 */ + { 0x2e06509c, 0x332 }, /* 1063 */ + { 0x2e0650a0, 0x2 }, /* 1064 */ + { 0x2e065414, 0x100 }, /* 1285 */ + { 0x2e065418, 0x201 }, /* 1286 */ + { 0x2e06542c, 0x400000 }, /* 1291 */ + { 0x2e065430, 0x80 }, /* 1292 */ + { 0x2e065434, 0xdcba98 }, /* 1293 */ + { 0x2e065438, 0x3000000 }, /* 1294 */ + { 0x2e06544c, 0x2a }, /* 1299 */ + { 0x2e065450, 0x15 }, /* 1300 */ + { 0x2e065454, 0x15 }, /* 1301 */ + { 0x2e065458, 0x2a }, /* 1302 */ + { 0x2e06545c, 0x33 }, /* 1303 */ + { 0x2e065460, 0xc }, /* 1304 */ + { 0x2e065464, 0xc }, /* 1305 */ + { 0x2e065468, 0x33 }, /* 1306 */ + { 0x2e06546c, 0x543210 }, /* 1307 */ + { 0x2e065470, 0x3f0000 }, /* 1308 */ + { 0x2e065474, 0xf013f }, /* 1309 */ + { 0x2e065478, 0xf }, /* 1310 */ + { 0x2e06547c, 0x3cc }, /* 1311 */ + { 0x2e065480, 0x30000 }, /* 1312 */ + { 0x2e065484, 0x300 }, /* 1313 */ + { 0x2e065488, 0x300 }, /* 1314 */ + { 0x2e06548c, 0x300 }, /* 1315 */ + { 0x2e065490, 0x300 }, /* 1316 */ + { 0x2e065494, 0x300 }, /* 1317 */ + { 0x2e065498, 0x42080010 }, /* 1318 */ + { 0x2e06549c, 0x332 }, /* 1319 */ + { 0x2e0654a0, 0x2 }, /* 1320 */ + { 0x2e065804, 0x100 }, /* 1537 */ + { 0x2e065814, 0x50000 }, /* 1541 */ + { 0x2e065818, 0x4000100 }, /* 1542 */ + { 0x2e06581c, 0x55 }, /* 1543 */ + { 0x2e06582c, 0xf0001 }, /* 1547 */ + { 0x2e065830, 0x280040 }, /* 1548 */ + { 0x2e065834, 0x5002 }, /* 1549 */ + { 0x2e065838, 0x10101 }, /* 1550 */ + { 0x2e065840, 0x90e0000 }, /* 1552 */ + { 0x2e065844, 0x101010f }, /* 1553 */ + { 0x2e065848, 0x10f0004 }, /* 1554 */ + { 0x2e065854, 0x64 }, /* 1557 */ + { 0x2e06585c, 0x1000000 }, /* 1559 */ + { 0x2e065860, 0x8040201 }, /* 1560 */ + { 0x2e065864, 0x2010201 }, /* 1561 */ + { 0x2e065868, 0xf0f0f }, /* 1562 */ + { 0x2e06586c, 0x241b42 }, /* 1563 */ + { 0x2e065874, 0x1020000 }, /* 1565 */ + { 0x2e065878, 0x701 }, /* 1566 */ + { 0x2e06587c, 0x54 }, /* 1567 */ + { 0x2e065880, 0x4102000 }, /* 1568 */ + { 0x2e065884, 0x24410 }, /* 1569 */ + { 0x2e065888, 0x4410 }, /* 1570 */ + { 0x2e06588c, 0x4410 }, /* 1571 */ + { 0x2e065890, 0x4410 }, /* 1572 */ + { 0x2e065894, 0x4410 }, /* 1573 */ + { 0x2e065898, 0x4410 }, /* 1574 */ + { 0x2e06589c, 0x4410 }, /* 1575 */ + { 0x2e0658a0, 0x4410 }, /* 1576 */ + { 0x2e0658a4, 0x4410 }, /* 1577 */ + { 0x2e0658b0, 0x60000 }, /* 1580 */ + { 0x2e0658b8, 0x96 }, /* 1582 */ + { 0x2e0658bc, 0x10000 }, /* 1583 */ + { 0x2e0658c0, 0x8 }, /* 1584 */ + { 0x2e0658d8, 0x3000000 }, /* 1590 */ + { 0x2e0658e8, 0x4102006 }, /* 1594 */ + { 0x2e0658ec, 0x41020 }, /* 1595 */ + { 0x2e0658f0, 0x1c98c98 }, /* 1596 */ + { 0x2e0658f4, 0x3f400000 }, /* 1597 */ + { 0x2e0658f8, 0x3f3f1f3f }, /* 1598 */ + { 0x2e0658fc, 0x1f }, /* 1599 */ + { 0x2e06590c, 0x1 }, /* 1603 */ + { 0x2e06591c, 0x1 }, /* 1607 */ + { 0x2e065920, 0x76543210 }, /* 1608 */ + { 0x2e065924, 0x10198 }, /* 1609 */ + { 0x2e065934, 0x40700 }, /* 1613 */ + { 0x2e06594c, 0x2 }, /* 1619 */ + { 0x2e065958, 0xf3c3 }, /* 1622 */ + { 0x2e065964, 0x11542 }, /* 1625 */ + { 0x2e065968, 0x30209bf }, /* 1626 */ + { 0x2e06596c, 0x30000 }, /* 1627 */ + { 0x2e065970, 0x3000300 }, /* 1628 */ + { 0x2e065974, 0x3000300 }, /* 1629 */ + { 0x2e065978, 0x3000300 }, /* 1630 */ + { 0x2e06597c, 0x3000300 }, /* 1631 */ + { 0x2e065980, 0x300 }, /* 1632 */ + { 0x2e065984, 0x300 }, /* 1633 */ + { 0x2e065988, 0x300 }, /* 1634 */ + { 0x2e06598c, 0x4bf77 }, /* 1635 */ + { 0x2e065990, 0x77 }, /* 1636 */ + { 0x2e065994, 0x27f }, /* 1637 */ + { 0x2e06599c, 0x27f }, /* 1639 */ + { 0x2e0659a4, 0x27f00 }, /* 1641 */ + { 0x2e0659a8, 0x1980000 }, /* 1642 */ + { 0x2e0659ac, 0x27fcc }, /* 1643 */ + { 0x2e0659b4, 0x27f00 }, /* 1645 */ + { 0x2e0659b8, 0x1980000 }, /* 1646 */ + { 0x2e0659bc, 0x27f00 }, /* 1647 */ + { 0x2e0659c0, 0x1980000 }, /* 1648 */ + { 0x2e0659c4, 0x27f00 }, /* 1649 */ + { 0x2e0659c8, 0x1980000 }, /* 1650 */ + { 0x2e0659cc, 0x27f00 }, /* 1651 */ + { 0x2e0659d0, 0x1980000 }, /* 1652 */ + { 0x2e0659d4, 0x20040003 }, /* 1653 */ +}; + +/** PHY_F2 settings **/ +struct dram_cfg_param ddr_phy_f2_cfg[] = { + { 0x2e064168, 0x3020000 }, /* 90 */ + { 0x2e064170, 0xc043e42 }, /* 92 */ + { 0x2e064174, 0xf0c1701 }, /* 93 */ + { 0x2e064180, 0x187 }, /* 96 */ + { 0x2e064184, 0x3010203 }, /* 97 */ + { 0x2e064190, 0x3070307 }, /* 100 */ + { 0x2e064194, 0x3070307 }, /* 101 */ + { 0x2e064198, 0x3070307 }, /* 102 */ + { 0x2e06419c, 0x3070307 }, /* 103 */ + { 0x2e0641a0, 0x307 }, /* 104 */ + { 0x2e0641c8, 0x1bd0080 }, /* 114 */ + { 0x2e064568, 0x3020000 }, /* 346 */ + { 0x2e064570, 0xc043e42 }, /* 348 */ + { 0x2e064574, 0xf0c1701 }, /* 349 */ + { 0x2e064580, 0x187 }, /* 352 */ + { 0x2e064584, 0x3010203 }, /* 353 */ + { 0x2e064590, 0x3070307 }, /* 356 */ + { 0x2e064594, 0x3070307 }, /* 357 */ + { 0x2e064598, 0x3070307 }, /* 358 */ + { 0x2e06459c, 0x3070307 }, /* 359 */ + { 0x2e0645a0, 0x307 }, /* 360 */ + { 0x2e0645c8, 0x1bd0080 }, /* 370 */ + { 0x2e064968, 0x3020000 }, /* 602 */ + { 0x2e064970, 0xc043e42 }, /* 604 */ + { 0x2e064974, 0xf0c1701 }, /* 605 */ + { 0x2e064980, 0x187 }, /* 608 */ + { 0x2e064984, 0x3010203 }, /* 609 */ + { 0x2e064990, 0x3070307 }, /* 612 */ + { 0x2e064994, 0x3070307 }, /* 613 */ + { 0x2e064998, 0x3070307 }, /* 614 */ + { 0x2e06499c, 0x3070307 }, /* 615 */ + { 0x2e0649a0, 0x307 }, /* 616 */ + { 0x2e0649c8, 0x1bd0080 }, /* 626 */ + { 0x2e064d68, 0x3020000 }, /* 858 */ + { 0x2e064d70, 0xc043e42 }, /* 860 */ + { 0x2e064d74, 0xf0c1701 }, /* 861 */ + { 0x2e064d80, 0x187 }, /* 864 */ + { 0x2e064d84, 0x3010203 }, /* 865 */ + { 0x2e064d90, 0x3070307 }, /* 868 */ + { 0x2e064d94, 0x3070307 }, /* 869 */ + { 0x2e064d98, 0x3070307 }, /* 870 */ + { 0x2e064d9c, 0x3070307 }, /* 871 */ + { 0x2e064da0, 0x307 }, /* 872 */ + { 0x2e064dc8, 0x1bd0080 }, /* 882 */ + { 0x2e06509c, 0x33e }, /* 1063 */ + { 0x2e06549c, 0x33e }, /* 1319 */ + { 0x2e065878, 0x10703 }, /* 1566 */ + { 0x2e065964, 0x1342 }, /* 1625 */ +}; + +/* ddr timing config params */ +struct dram_timing_info2 dram_timing = { + .ctl_cfg = ddr_ctl_cfg, + .ctl_cfg_num = ARRAY_SIZE(ddr_ctl_cfg), + .pi_cfg = ddr_pi_cfg, + .pi_cfg_num = ARRAY_SIZE(ddr_pi_cfg), + .phy_f1_cfg = ddr_phy_f1_cfg, + .phy_f1_cfg_num = ARRAY_SIZE(ddr_phy_f1_cfg), + .phy_f2_cfg = ddr_phy_f2_cfg, + .phy_f2_cfg_num = ARRAY_SIZE(ddr_phy_f2_cfg), + .fsp_table = { 96, 528, 1056 }, +}; diff --git a/board/freescale/imx8ulp_evk/spl.c b/board/freescale/imx8ulp_evk/spl.c new file mode 100644 index 0000000000..faece336ef --- /dev/null +++ b/board/freescale/imx8ulp_evk/spl.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include <common.h> +#include <init.h> +#include <spl.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx8ulp-pins.h> +#include <dm/uclass.h> +#include <dm/device.h> +#include <dm/uclass-internal.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <asm/arch/ddr.h> +#include <asm/arch/rdc.h> +#include <asm/arch/upower.h> + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + init_clk_ddr(); + ddr_init(&dram_timing); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +int power_init_board(void) +{ + u32 pmic_reg; + + /* PMIC set bucks1-4 to PWM mode */ + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + upower_pmic_i2c_write(0x10, 0x3d); + upower_pmic_i2c_write(0x14, 0x7d); + upower_pmic_i2c_write(0x21, 0x7d); + upower_pmic_i2c_write(0x2e, 0x3d); + + upower_pmic_i2c_read(0x10, &pmic_reg); + upower_pmic_i2c_read(0x14, &pmic_reg); + upower_pmic_i2c_read(0x21, &pmic_reg); + upower_pmic_i2c_read(0x2e, &pmic_reg); + + /* Set buck3 to 1.1v OD */ + upower_pmic_i2c_write(0x22, 0x28); + return 0; +} + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + preloader_console_init(); + + puts("Normal Boot\n"); + + /* After AP set iomuxc0, the i2c can't work, Need M33 to set it now */ + + upower_init(); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + /* This must place after upower init, so access to MDA and MRC are valid */ + /* Init XRDC MDA */ + xrdc_init_mda(); + + /* Init XRDC MRC for VIDEO, DSP domains */ + xrdc_init_mrc(); +} + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 6504cf768f..e8722f20c1 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -33,6 +33,9 @@ #endif #include "../common/vid.h" +#define CORTINA_FW_ADDR_IFCNOR 0x580980000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000 +#define CORTINA_FW_ADDR_QSPI 0x980000 #define PIN_MUX_SEL_SDHC 0x00 #define PIN_MUX_SEL_DSPI 0x0a @@ -235,6 +238,41 @@ int config_board_mux(int ctrl_type) return 0; } +ulong *cs4340_get_fw_addr(void) +{ +#ifdef CONFIG_TFABOOT + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 svr = gur_in32(&gur->svr); +#endif + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_TFABOOT + /* LS2088A TFA boot */ + if (SVR_SOC_VER(svr) == SVR_LS2088A) { + enum boot_src src = get_boot_src(); + u8 sw; + + switch (src) { + case BOOT_SOURCE_IFC_NOR: + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & 0x0f); + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + break; + case BOOT_SOURCE_QSPI_NOR: + /* Only one bank in QSPI */ + cortina_fw_addr = CORTINA_FW_ADDR_QSPI; + break; + default: + printf("WARNING: Boot source not found\n"); + } + } +#endif + return (ulong *)cortina_fw_addr; +} + int board_init(void) { #ifdef CONFIG_FSL_MC_ENET diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index 3ddbe71775..8c76c46d42 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -115,77 +115,4 @@ void pib_init(void) i2c_set_bus_num(orig_i2c_bus); } -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; -#ifndef CONFIG_MPC83XX_PCI2 - struct pci_region *reg[] = { pci1_regions }; -#else - struct pci_region *reg[] = { pci1_regions, pci2_regions }; -#endif - - /* initialize the PCA9555PW IO expander on the PIB board */ - pib_init(); - - /* Enable all 8 PCI_CLK_OUTPUTS */ - clk->occr = 0xff000000; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - - udelay(2000); - -#ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg); -#else - mpc83xx_pci_init(2, reg); -#endif -} - -#else -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; - struct pci_region *reg[] = { pci1_regions }; - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; - - pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - - mpc83xx_pci_init(1, reg); - - /* Configure PCI Inbound Translation Windows (3 1MB windows) */ - pci_ctrl->pitar0 = 0x0; - pci_ctrl->pibar0 = 0x0; - pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_1M; - - pci_ctrl->pitar1 = 0x0; - pci_ctrl->pibar1 = 0x0; - pci_ctrl->piebar1 = 0x0; - pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_1M; - - pci_ctrl->pitar2 = 0x0; - pci_ctrl->pibar2 = 0x0; - pci_ctrl->piebar2 = 0x0; - pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | - PIWAR_WTT_SNOOP | PIWAR_IWS_1M; - - /* Unlock the configuration bit */ - mpc83xx_pcislave_unlock(0); - printf("PCI: Agent mode enabled\n"); -} #endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile index c683b017b5..4661e4cf23 100644 --- a/board/freescale/mpc837xerdb/Makefile +++ b/board/freescale/mpc837xerdb/Makefile @@ -4,4 +4,3 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-y += mpc837xerdb.o -obj-$(CONFIG_PCI) += pci.o diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c deleted file mode 100644 index dccf8c5551..0000000000 --- a/board/freescale/mpc837xerdb/pci.c +++ /dev/null @@ -1,109 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <init.h> -#include <mpc83xx.h> -#include <pci.h> -#include <asm/io.h> -#include <linux/delay.h> - -static struct pci_region pci_regions[] = { - { - bus_start: CONFIG_SYS_PCI_MEM_BASE, - phys_start: CONFIG_SYS_PCI_MEM_PHYS, - size: CONFIG_SYS_PCI_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CONFIG_SYS_PCI_MMIO_BASE, - phys_start: CONFIG_SYS_PCI_MMIO_PHYS, - size: CONFIG_SYS_PCI_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CONFIG_SYS_PCI_IO_BASE, - phys_start: CONFIG_SYS_PCI_IO_PHYS, - size: CONFIG_SYS_PCI_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -static struct pci_region pcie_regions_0[] = { - { - .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, - .size = CONFIG_SYS_PCIE1_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE1_IO_BASE, - .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, - .size = CONFIG_SYS_PCIE1_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -static struct pci_region pcie_regions_1[] = { - { - .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, - .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, - .size = CONFIG_SYS_PCIE2_MEM_SIZE, - .flags = PCI_REGION_MEM, - }, - { - .bus_start = CONFIG_SYS_PCIE2_IO_BASE, - .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, - .size = CONFIG_SYS_PCIE2_IO_SIZE, - .flags = PCI_REGION_IO, - }, -}; - -void pci_init_board(void) -{ - volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile sysconf83xx_t *sysconf = &immr->sysconf; - volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; - volatile law83xx_t *pci_law = immr->sysconf.pcilaw; - volatile law83xx_t *pcie_law = sysconf->pcielaw; - struct pci_region *reg[] = { pci_regions }; - struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - u32 spridr = in_be32(&immr->sysconf.spridr); - - /* Enable all 5 PCI_CLK_OUTPUTS */ - clk->occr |= 0xf8000000; - udelay(2000); - - /* Configure PCI Local Access Windows */ - pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; - - pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - mpc83xx_pci_init(1, reg); - - /* There is no PEX in MPC8379 parts. */ - if (PARTID_NO_E(spridr) == SPR_8379) - return; - - /* Configure the clock for PCIE controller */ - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, - SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); - - /* Deassert the resets in the control register */ - out_be32(&sysconf->pecr1, 0xE0008000); - out_be32(&sysconf->pecr2, 0xE0008000); - udelay(2000); - - /* Configure PCI Express Local Access Windows */ - out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); - out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - - out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); - out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - - mpc83xx_pcie_init(2, pcie_reg); -} diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index a1a9742bfa..cfb5b0b38b 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -168,113 +168,6 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ } -#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_mpc85xxcds_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller pci1_hose; -#endif /* CONFIG_PCI */ - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - struct fsl_pci_info pci_info; - u32 devdisr, pordevsr, io_sel; - u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; - int first_free_busno = 0; - char buf[32]; - - devdisr = in_be32(&gur->devdisr); - pordevsr = in_be32(&gur->pordevsr); - porpllsr = in_be32(&gur->porpllsr); - io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; - - debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); - -#ifdef CONFIG_PCI1 - pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ - pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ - pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; - pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", - (pci_32) ? 32 : 64, - strmhz(buf, pci_speed), - pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter", - pci_info.regs); - - pci1_hose.config_table = pci_mpc85xxcds_config_table; - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - -#ifdef CONFIG_PCIX_CHECK - if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) { - /* PCI-X init */ - if (CONFIG_SYS_CLK_FREQ < 66000000) - printf("PCI-X will only work at 66 MHz\n"); - - reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ - | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; - pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); - } -#endif - } else { - printf("PCI1: disabled\n"); - } - - puts("\n"); -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ -#endif - -#ifdef CONFIG_PCI2 -{ - uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */ - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - if (pci_dual) { - printf("PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf("PCI2: disabled\n"); - } -} -#else - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */ -#endif /* CONFIG_PCI2 */ - - fsl_pcie_init_board(first_free_busno); -} -#endif - void configure_rgmii(void) { unsigned short temp; @@ -354,10 +247,3 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); } - -#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI) -void ft_pci_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/mx28evk/MAINTAINERS b/board/freescale/mx28evk/MAINTAINERS index 597118d3f6..c565010ccf 100644 --- a/board/freescale/mx28evk/MAINTAINERS +++ b/board/freescale/mx28evk/MAINTAINERS @@ -2,6 +2,7 @@ MX28EVK BOARD M: Fabio Estevam <festevam@gmail.com> S: Maintained F: board/freescale/mx28evk/ +F: arch/arm/dts/imx28-evk.dts F: include/configs/mx28evk.h F: configs/mx28evk_defconfig F: configs/mx28evk_auart_console_defconfig diff --git a/board/freescale/mx28evk/mx28evk.c b/board/freescale/mx28evk/mx28evk.c index 21c9cb1128..88c3bf3608 100644 --- a/board/freescale/mx28evk/mx28evk.c +++ b/board/freescale/mx28evk/mx28evk.c @@ -72,80 +72,3 @@ int board_init(void) return 0; } - -#ifdef CONFIG_CMD_MMC -static int mx28evk_mmc_wp(int id) -{ - if (id != 0) { - printf("MXS MMC: Invalid card selected (card id = %d)\n", id); - return 1; - } - - return gpio_get_value(MX28_PAD_SSP1_SCK__GPIO_2_12); -} - -int board_mmc_init(struct bd_info *bis) -{ - /* Configure WP as input */ - gpio_direction_input(MX28_PAD_SSP1_SCK__GPIO_2_12); - - /* Configure MMC0 Power Enable */ - gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); - - return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL); -} -#endif - -#ifdef CONFIG_CMD_NET - -int board_eth_init(struct bd_info *bis) -{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - struct eth_device *dev; - int ret; - - ret = cpu_eth_init(bis); - if (ret) - return ret; - - /* MX28EVK uses ENET_CLK PAD to drive FEC clock */ - writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, - &clkctrl_regs->hw_clkctrl_enet); - - /* Power-on FECs */ - gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0); - - /* Reset FEC PHYs */ - gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); - udelay(200); - gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); - - ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC0\n"); - return ret; - } - - ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE); - if (ret) { - puts("FEC MXS: Unable to init FEC1\n"); - return ret; - } - - dev = eth_get_dev_by_name("FEC0"); - if (!dev) { - puts("FEC MXS: Unable to get FEC0 device entry\n"); - return -EINVAL; - } - - dev = eth_get_dev_by_name("FEC1"); - if (!dev) { - puts("FEC MXS: Unable to get FEC1 device entry\n"); - return -EINVAL; - } - - return ret; -} - -#endif diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index 90436337df..84fc891b67 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -129,13 +129,6 @@ int board_early_init_r(void) return 0; } -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif /* ifdef CONFIG_PCI */ - int config_board_mux(int ctrl_type) { ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -617,10 +610,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) base = env_get_bootm_low(); size = env_get_bootm_size(); -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) - FT_FSL_PCI_SETUP; -#endif - fdt_fixup_memory(blob, (u64)base, (u64)size); #if defined(CONFIG_HAS_FSL_DR_USB) diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index cf4d9c11b8..19ece12296 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -239,13 +239,6 @@ int checkboard(void) return 0; } -#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -363,10 +356,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_memory(blob, (u64)base, (u64)size); -#if !defined(CONFIG_DM_PCI) - FT_FSL_PCI_SETUP; -#endif - #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", sizeof("okay"), 0); diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index ddeb44f36e..e597486c94 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -10,7 +10,6 @@ else obj-y += t102xrdb.o obj-$(CONFIG_TARGET_T1024RDB) += cpld.o obj-y += eth_t102xrdb.o -obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o obj-y += law.o diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c deleted file mode 100644 index 45ab9223ae..0000000000 --- a/board/freescale/t102xrdb/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile index 31abbd9aca..d67e9412ec 100644 --- a/board/freescale/t104xrdb/Makefile +++ b/board/freescale/t104xrdb/Makefile @@ -8,7 +8,6 @@ else obj-y += t104xrdb.o obj-y += cpld.o obj-y += eth.o -obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_FSL_DIU_FB)+= diu.o endif obj-y += ddr.o diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c deleted file mode 100644 index 1fd2402700..0000000000 --- a/board/freescale/t104xrdb/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 55b1e7390a..de8613058d 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o -obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c deleted file mode 100644 index a03b11ccb5..0000000000 --- a/board/freescale/t208xqds/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2013 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 25ea66a024..7af3cd0ac4 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o -obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o diff --git a/board/freescale/t208xrdb/cpld.h b/board/freescale/t208xrdb/cpld.h index a623b1811f..3139c2b85f 100644 --- a/board/freescale/t208xrdb/cpld.h +++ b/board/freescale/t208xrdb/cpld.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor + * Copyright 2021 NXP */ /* @@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value); /* RSTCON Register */ #define CPLD_RSTCON_EDC_RST 0x04 + +/* MISCCSR Register */ +#define CPLD_MISC_POR_EN 0x30 diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c deleted file mode 100644 index 45ab9223ae..0000000000 --- a/board/freescale/t208xrdb/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2007-2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index 1f0cdee0b8..73ebb4a55b 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -128,6 +128,13 @@ int misc_init_r(void) reg |= CPLD_RSTCON_EDC_RST; CPLD_WRITE(reset_ctl, reg); + /* Enable POR for boards revisions D and up */ + if (get_hw_revision() >= 'D') { + reg = CPLD_READ(misc_csr); + reg |= CPLD_MISC_POR_EN; + CPLD_WRITE(misc_csr, reg); + } + return 0; } @@ -158,3 +165,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 reg; + + reg = CPLD_READ(flash_csr); + if (!(reg & CPLD_BOOT_SEL)) { + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT); + if (reg == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (reg == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; + } +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h index edbc860c9d..26998898e8 100644 --- a/board/freescale/t208xrdb/t208xrdb.h +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -7,6 +7,9 @@ #ifndef __CORENET_DS_H__ #define __CORENET_DS_H__ +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000 + void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); void fdt_fixup_board_fman_ethernet(void *blob); diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index f1fd623339..3106848639 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -10,7 +10,6 @@ else obj-$(CONFIG_TARGET_T4240RDB) += t4240rdb.o obj-y += cpld.o obj-y += eth.o -obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c deleted file mode 100644 index c2bc05164d..0000000000 --- a/board/freescale/t4rdb/pci.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#include <common.h> -#include <command.h> -#include <init.h> -#include <pci.h> -#include <asm/fsl_pci.h> -#include <linux/libfdt.h> -#include <fdt_support.h> -#include <asm/fsl_serdes.h> - -#if !defined(CONFIG_DM_PCI) -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} - -void pci_of_setup(void *blob, struct bd_info *bd) -{ - FT_FSL_PCI_SETUP; -} -#endif diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c index 6ab35ca918..20ce7523e5 100644 --- a/board/freescale/t4rdb/t4240rdb.c +++ b/board/freescale/t4rdb/t4240rdb.c @@ -151,3 +151,22 @@ void board_detail(void) break; } } + +ulong *cs4340_get_fw_addr(void) +{ + ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; + +#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR + u8 sw; + + sw = CPLD_READ(vbank); + sw = sw & CPLD_BANK_SEL_MASK; + + if (sw == 0) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR; + else if (sw == 4) + cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK; +#endif + + return (ulong *)cortina_fw_addr; +} diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h index 3f1fa7bbd2..06779f552f 100644 --- a/board/freescale/t4rdb/t4rdb.h +++ b/board/freescale/t4rdb/t4rdb.h @@ -11,6 +11,9 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM2_DTSEC 4 +#define CORTINA_FW_ADDR_IFCNOR 0xefe00000 +#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000 + void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 4a15837473..2be921f47a 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -19,6 +19,7 @@ #include <power/pmic.h> #include <power/ltc3676_pmic.h> #include <power/pfuze100_pmic.h> +#include <power/mp5416.h> #include "common.h" @@ -178,21 +179,12 @@ void setup_ventana_i2c(int i2c) * Baseboard specific GPIO */ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* GPS_SHDN */ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; @@ -204,28 +196,14 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* GPS_SHDN */ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), /* USBOTG_SEL */ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* PCI_RST# (GW522x) */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ @@ -239,16 +217,6 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ @@ -257,14 +225,14 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), /* GPS_SHDN */ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), + /* J6_PWREN */ + IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG), + /* PCIEGBE_EN */ + IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { @@ -274,16 +242,6 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), /* MIPI_DIO */ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), /* RS485_EN */ @@ -294,23 +252,17 @@ static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), + /* J7_PWREN */ + IOMUX_PADS(PAD_EIM_DA15__GPIO3_IO15 | DIO_PAD_CFG), + /* PCIEGBE_EN */ + IOMUX_PADS(PAD_EIM_DA14__GPIO3_IO14 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw551x_gpio_pads[] = { - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLED# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; @@ -320,16 +272,6 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = { IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* USBOTG_SEL */ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* MX6_DIO[4:9] */ IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), @@ -348,14 +290,6 @@ static iomux_v3_cfg_t const gw552x_gpio_pads[] = { static iomux_v3_cfg_t const gw553x_gpio_pads[] = { /* SD3_VSELECT */ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), - /* VID_PWR */ - IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; @@ -363,45 +297,23 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = { static iomux_v3_cfg_t const gw560x_gpio_pads[] = { /* RS232_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), /* DIOI2C_DIS# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* VID_EN */ - IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG), /* RS485_EN */ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), - /* USBH2_PEN (OTG) */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* 12V0_PWR_EN */ IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw5901_gpio_pads[] = { - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* ETH1_EN */ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), - /* CAN_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), /* PMIC reset */ IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG), /* COM_CFGA/B/C/D */ @@ -418,24 +330,14 @@ static iomux_v3_cfg_t const gw5901_gpio_pads[] = { }; static iomux_v3_cfg_t const gw5902_gpio_pads[] = { - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), - /* CAN1_STBY */ - IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), - /* CAN2_STBY */ - IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG), /* UART1_EN# */ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), /* 5V_UVLO */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), /* ETI_IRQ# */ IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG), /* DIO_IRQ# */ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* USBOTG_PEN */ - IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), }; static iomux_v3_cfg_t const gw5903_gpio_pads[] = { @@ -449,8 +351,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = { IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG), /* USBH1_PEN (EHCI) */ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), - /* USBH2_PEN (OTG) */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* USBDPC_PEN */ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), /* TOUCH_RST */ @@ -459,8 +359,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), /* UART1_TEN# */ IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* LVDS_BKLEN # */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), /* RGMII_PDWN# */ @@ -472,14 +370,6 @@ static iomux_v3_cfg_t const gw5903_gpio_pads[] = { }; static iomux_v3_cfg_t const gw5904_gpio_pads[] = { - /* USB_HUBRST# */ - IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), - /* PANLEDG# */ - IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), - /* PANLEDR# */ - IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), /* IOEXP_PWREN# */ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), /* IOEXP_IRQ# */ @@ -511,28 +401,18 @@ static iomux_v3_cfg_t const gw5904_gpio_pads[] = { static iomux_v3_cfg_t const gw5905_gpio_pads[] = { /* EMMY_PDN# */ IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG), - /* MX6_LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), /* MIPI_RST */ IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), /* MIPI_PWDN */ IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), /* USBEHCI_SEL */ IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), - /* PCI_RST# */ - IOMUX_PADS(PAD_GPIO_16__GPIO7_IO11 | DIO_PAD_CFG), /* LVDS_BKLEN # */ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), /* PCIESKT_WDIS# */ IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG), /* SPK_SHDN# */ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), - /* LOCLED# */ - IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), - /* FLASH LED1 */ - IOMUX_PADS(PAD_DISP0_DAT11__GPIO5_IO05 | DIO_PAD_CFG), - /* FLASH LED2 */ - IOMUX_PADS(PAD_DISP0_DAT12__GPIO5_IO06 | DIO_PAD_CFG), /* DECT_RST# */ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG), /* USBH1_PEN (EHCI) */ @@ -549,6 +429,28 @@ static iomux_v3_cfg_t const gw5905_gpio_pads[] = { IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), }; +static iomux_v3_cfg_t const gw5910_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), + /* RF_RESET# */ + IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), + /* RF_BOOT */ + IOMUX_PADS(PAD_GPIO_8__GPIO1_IO08 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), +}; + +static iomux_v3_cfg_t const gw5912_gpio_pads[] = { + /* SD3_VSELECT */ + IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), + /* PCIESKT_WDIS# */ + IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), +}; + /* Digital I/O */ struct dio_cfg gw51xx_dio[] = { { @@ -949,6 +851,51 @@ struct dio_cfg gw5906_dio[] = { }, }; +struct dio_cfg gw5913_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, + { + { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15) }, + IMX_GPIO_NR(1, 15), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14) }, + IMX_GPIO_NR(1, 14), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05) }, + IMX_GPIO_NR(4, 5), + { 0, 0 }, + 0 + }, +}; + /* * Board Specific GPIO */ @@ -959,18 +906,13 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, .dio_cfg = gw54xx_dio, .dio_num = ARRAY_SIZE(gw54xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .mezz_pwren = IMX_GPIO_NR(4, 7), .mezz_irq = IMX_GPIO_NR(4, 9), .rs485en = IMX_GPIO_NR(3, 24), .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), .mmc_cd = IMX_GPIO_NR(7, 0), + .wdis = -1, }, /* GW51xx */ @@ -979,17 +921,10 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, .dio_cfg = gw51xx_dio, .dio_num = ARRAY_SIZE(gw51xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 2), - .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), - .nand = true, }, /* GW52xx */ @@ -998,23 +933,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, .dio_cfg = gw52xx_dio, .dio_num = ARRAY_SIZE(gw52xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), .usb_sel = IMX_GPIO_NR(1, 2), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, }, /* GW53xx */ @@ -1023,22 +950,14 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, .dio_cfg = gw53xx_dio, .dio_num = ARRAY_SIZE(gw53xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, }, /* GW54xx */ @@ -1047,16 +966,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, .dio_cfg = gw54xx_dio, .dio_num = ARRAY_SIZE(gw54xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .rs485en = IMX_GPIO_NR(7, 1), - .vidin_en = IMX_GPIO_NR(3, 31), .dioi2c_en = IMX_GPIO_NR(4, 5), .pcie_sson = IMX_GPIO_NR(1, 20), .wdis = IMX_GPIO_NR(5, 17), @@ -1064,7 +976,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .rs232_en = GP_RS232_EN, .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, }, /* GW551x */ @@ -1073,12 +984,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, .dio_cfg = gw551x_dio, .dio_num = ARRAY_SIZE(gw551x_dio), - .leds = { - IMX_GPIO_NR(4, 7), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .wdis = IMX_GPIO_NR(7, 12), - .nand = true, }, /* GW552x */ @@ -1087,16 +993,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, .dio_cfg = gw552x_dio, .dio_num = ARRAY_SIZE(gw552x_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, - .nand = true, }, /* GW553x */ @@ -1105,16 +1004,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, .dio_cfg = gw553x_dio, .dio_num = ARRAY_SIZE(gw553x_dio), - .leds = { - IMX_GPIO_NR(4, 10), - IMX_GPIO_NR(4, 11), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), - .vidin_en = IMX_GPIO_NR(5, 20), .wdis = IMX_GPIO_NR(7, 12), .vsel_pin = IMX_GPIO_NR(6, 14), .mmc_cd = IMX_GPIO_NR(7, 0), - .nand = true, }, /* GW560x */ @@ -1123,16 +1015,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2, .dio_cfg = gw560x_dio, .dio_num = ARRAY_SIZE(gw560x_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(4, 31), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .rs232_en = GP_RS232_EN, - .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), .mmc_cd = IMX_GPIO_NR(7, 0), }, @@ -1142,11 +1027,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .gpio_pads = gw5901_gpio_pads, .num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2, .dio_cfg = gw5901_dio, - .leds = { - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), - .nand = true, + .wdis = -1, }, /* GW5902 */ @@ -1154,12 +1035,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .gpio_pads = gw5902_gpio_pads, .num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2, .dio_cfg = gw5902_dio, - .leds = { - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .rs232_en = GP_RS232_EN, - .nand = true, + .wdis = -1, }, /* GW5903 */ @@ -1168,10 +1045,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2, .dio_cfg = gw5903_dio, .dio_num = ARRAY_SIZE(gw5903_dio), - .leds = { - IMX_GPIO_NR(6, 14), - }, .mmc_cd = IMX_GPIO_NR(6, 11), + .wdis = -1, }, /* GW5904 */ @@ -1180,24 +1055,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, .dio_cfg = gw5904_dio, .dio_num = ARRAY_SIZE(gw5904_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), + .wdis = -1, }, /* GW5905 */ { .gpio_pads = gw5905_gpio_pads, .num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2, - .leds = { - IMX_GPIO_NR(6, 14), - }, - .pcie_rst = IMX_GPIO_NR(7, 11), .wdis = IMX_GPIO_NR(7, 13), }, @@ -1207,16 +1073,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, .dio_cfg = gw5906_dio, .dio_num = ARRAY_SIZE(gw5906_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .usb_sel = IMX_GPIO_NR(1, 7), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, - .nand = true, }, /* GW5907 */ @@ -1225,13 +1084,7 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, .dio_cfg = gw51xx_dio, .dio_num = ARRAY_SIZE(gw51xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 10), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .wdis = IMX_GPIO_NR(7, 12), - .nand = true, }, /* GW5908 */ @@ -1240,16 +1093,9 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, .dio_cfg = gw53xx_dio, .dio_num = ARRAY_SIZE(gw53xx_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 29), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), .gps_shdn = IMX_GPIO_NR(1, 27), - .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, .rs232_en = GP_RS232_EN, @@ -1261,14 +1107,42 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, .dio_cfg = gw5904_dio, .dio_num = ARRAY_SIZE(gw5904_dio), - .leds = { - IMX_GPIO_NR(4, 6), - IMX_GPIO_NR(4, 7), - IMX_GPIO_NR(4, 15), - }, - .pcie_rst = IMX_GPIO_NR(1, 0), .mezz_pwren = IMX_GPIO_NR(2, 19), .mezz_irq = IMX_GPIO_NR(2, 18), + .wdis = -1, + }, + + /* GW5910 */ + { + .gpio_pads = gw5910_gpio_pads, + .num_pads = ARRAY_SIZE(gw5910_gpio_pads) / 2, + .dio_cfg = gw52xx_dio, + .dio_num = ARRAY_SIZE(gw52xx_dio), + .wdis = IMX_GPIO_NR(7, 12), + .rs232_en = GP_RS232_EN, + .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), + }, + + /* GW5912 */ + { + .gpio_pads = gw5912_gpio_pads, + .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2, + .dio_cfg = gw54xx_dio, + .dio_num = ARRAY_SIZE(gw54xx_dio), + .wdis = IMX_GPIO_NR(1, 0), + .rs232_en = GP_RS232_EN, + .vsel_pin = IMX_GPIO_NR(6, 14), + .mmc_cd = IMX_GPIO_NR(7, 0), + }, + + /* GW5913 */ + { + .gpio_pads = gw5912_gpio_pads, + .num_pads = ARRAY_SIZE(gw5912_gpio_pads) / 2, + .dio_cfg = gw5913_dio, + .dio_num = ARRAY_SIZE(gw5913_dio), + .wdis = IMX_GPIO_NR(1, 0), }, }; @@ -1280,8 +1154,6 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { gpio_direction_input(gpio); void setup_iomux_gpio(int board, struct ventana_board_info *info) { - int i; - if (board >= GW_UNKNOWN) return; @@ -1295,24 +1167,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_direction_output(gpio_cfg[board].rs232_en, 0); } - /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ - if (board == GW52xx && info->model[4] == '2') - gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); - - /* assert PCI_RST# */ - gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); - gpio_direction_output(gpio_cfg[board].pcie_rst, 0); - - /* turn off (active-high) user LED's */ - for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { - char name[16]; - if (gpio_cfg[board].leds[i]) { - sprintf(name, "led_user%d", i); - gpio_request(gpio_cfg[board].leds[i], name); - gpio_direction_output(gpio_cfg[board].leds[i], 1); - } - } - /* MSATA Enable - default to PCI */ if (gpio_cfg[board].msata_en) { gpio_request(gpio_cfg[board].msata_en, "msata_en"); @@ -1341,12 +1195,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_direction_output(gpio_cfg[board].gps_shdn, 1); } - /* Analog video codec power enable */ - if (gpio_cfg[board].vidin_en) { - gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); - gpio_direction_output(gpio_cfg[board].vidin_en, 1); - } - /* DIOI2C_DIS# */ if (gpio_cfg[board].dioi2c_en) { gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); @@ -1366,7 +1214,7 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) } /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ - if (gpio_cfg[board].wdis) { + if (gpio_cfg[board].wdis != -1) { gpio_request(gpio_cfg[board].wdis, "wlan_dis"); gpio_direction_output(gpio_cfg[board].wdis, 1); } @@ -1386,16 +1234,23 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) /* Anything else board specific */ switch(board) { + case GW53xx: + gpio_request(IMX_GPIO_NR(3, 15), "j6_pwren"); + gpio_direction_output(IMX_GPIO_NR(3, 15), 1); + gpio_request(IMX_GPIO_NR(3, 14), "gbe_en"); + gpio_direction_output(IMX_GPIO_NR(3, 14), 1); + break; + case GW54xx: + gpio_request(IMX_GPIO_NR(3, 15), "j7_pwren"); + gpio_direction_output(IMX_GPIO_NR(3, 15), 1); + gpio_request(IMX_GPIO_NR(3, 14), "gbe_en"); + gpio_direction_output(IMX_GPIO_NR(3, 14), 1); + break; case GW560x: gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); gpio_direction_output(IMX_GPIO_NR(4, 26), 1); break; - case GW5901: - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0); - break; case GW5902: - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0); - SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0); SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1); break; case GW5903: @@ -1453,6 +1308,11 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) */ SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1); break; + case GW5910: + /* CC1352 */ + SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "rf_reset#", 1); + SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 8), "rf_boot", 1); + break; } } @@ -1695,6 +1555,170 @@ void setup_pmic(void) pmic_reg_write(p, LTC3676_BUCK3, 0xc0); pmic_reg_write(p, LTC3676_BUCK4, 0xc0); } + + /* configure MP5416 PMIC */ + else if (!i2c_probe(0x69)) { + puts("PMIC: MP5416\n"); + switch (board) { + case GW5910: + /* SW1: VDD_ARM 1.2V -> (1.275 to 1.475) */ + reg = MP5416_VSET_EN | MP5416_VSET_SW1_SVAL(1475000); + i2c_write(0x69, MP5416_VSET_SW1, 1, (uint8_t *)®, 1); + /* SW4: VDD_SOC 1.2V -> (1.350 to 1.475) */ + reg = MP5416_VSET_EN | MP5416_VSET_SW4_SVAL(1475000); + i2c_write(0x69, MP5416_VSET_SW4, 1, (uint8_t *)®, 1); + break; + } + } +} + +#include <fdt_support.h> +#define WDOG1_ADDR 0x20bc000 +#define WDOG2_ADDR 0x20c0000 +#define GPIO3_ADDR 0x20a4000 +#define USDHC3_ADDR 0x2198000 + +static void ft_board_wdog_fixup(void *blob, phys_addr_t addr) +{ + int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr); + + if (off) { + fdt_delprop(blob, off, "ext-reset-output"); + fdt_delprop(blob, off, "fsl,ext-reset-output"); + } +} + +void ft_early_fixup(void *blob, int board_type) +{ + struct ventana_board_info *info = &ventana_info; + char rev = 0; + int i; + + /* determine board revision */ + for (i = sizeof(ventana_info.model) - 1; i > 0; i--) { + if (ventana_info.model[i] >= 'A') { + rev = ventana_info.model[i]; + break; + } + } + + /* + * Board model specific fixups + */ + switch (board_type) { + case GW51xx: + /* + * disable wdog node for GW51xx-A/B to work around + * errata causing wdog timer to be unreliable. + */ + if (rev >= 'A' && rev < 'C') { + i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", + WDOG1_ADDR); + if (i) + fdt_status_disabled(blob, i); + } + + /* GW51xx-E adds WDOG1_B external reset */ + if (rev < 'E') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + break; + + case GW52xx: + /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ + if (info->model[4] == '2') { + u32 handle = 0; + u32 *range = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx6q-pcie"); + if (i) + range = (u32 *)fdt_getprop(blob, i, + "reset-gpio", NULL); + + if (range) { + i = fdt_node_offset_by_compat_reg(blob, + "fsl,imx6q-gpio", GPIO3_ADDR); + if (i) + handle = fdt_get_phandle(blob, i); + if (handle) { + range[0] = cpu_to_fdt32(handle); + range[1] = cpu_to_fdt32(23); + } + } + + /* these have broken usd_vsel */ + if (strstr((const char *)info->model, "SP318-B") || + strstr((const char *)info->model, "SP331-B")) + gpio_cfg[board_type].usd_vsel = 0; + + /* GW522x-B adds WDOG1_B external reset */ + if (rev < 'B') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + } + + /* GW520x-E adds WDOG1_B external reset */ + else if (info->model[4] == '0' && rev < 'E') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + break; + + case GW53xx: + /* GW53xx-E adds WDOG1_B external reset */ + if (rev < 'E') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + + /* GW53xx-G has an adv7280 instead of an adv7180 */ + else if (rev > 'F') { + i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180"); + if (i) { + fdt_setprop_string(blob, i, "compatible", "adi,adv7280"); + fdt_setprop_empty(blob, i, "adv,force-bt656-4"); + } + } + break; + + case GW54xx: + /* + * disable serial2 node for GW54xx for compatibility with older + * 3.10.x kernel that improperly had this node enabled in the DT + */ + fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED, + 0); + + /* GW54xx-E adds WDOG2_B external reset */ + if (rev < 'E') + ft_board_wdog_fixup(blob, WDOG2_ADDR); + + /* GW54xx-G has an adv7280 instead of an adv7180 */ + else if (rev > 'F') { + i = fdt_node_offset_by_compatible(blob, -1, "adi,adv7180"); + if (i) { + fdt_setprop_string(blob, i, "compatible", "adi,adv7280"); + fdt_setprop_empty(blob, i, "adv,force-bt656-4"); + } + } + break; + + case GW551x: + /* GW551x-C adds WDOG1_B external reset */ + if (rev < 'C') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + break; + case GW5901: + case GW5902: + /* GW5901/GW5901 revB adds WDOG1_B as an external reset */ + if (rev < 'B') + ft_board_wdog_fixup(blob, WDOG1_ADDR); + break; + } + + /* remove no-1-8-v if UHS-I support is present */ + if (gpio_cfg[board_type].usd_vsel) { + debug("Enabling UHS-I support\n"); + i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc", + USDHC3_ADDR); + if (i) + fdt_delprop(blob, i, "no-1-8-v"); + } } #ifdef CONFIG_FSL_ESDHC_IMX @@ -1711,6 +1735,8 @@ int board_mmc_init(struct bd_info *bis) case GW53xx: case GW54xx: case GW553x: + case GW5910: + case GW5912: /* usdhc3: 4bit microSD */ SETUP_IOMUX_PADS(usdhc3_pads); usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index 813f7d9f56..edfb065f6a 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -61,13 +61,10 @@ struct ventana { struct dio_cfg *dio_cfg; int dio_num; /* various gpios (0 if non-existent) */ - int leds[3]; - int pcie_rst; int mezz_pwren; int mezz_irq; int rs485en; int gps_shdn; - int vidin_en; int dioi2c_en; int pcie_sson; int usb_sel; @@ -78,7 +75,6 @@ struct ventana { int mmc_cd; /* various features */ bool usd_vsel; - bool nand; }; extern struct ventana gpio_cfg[GW_UNKNOWN]; @@ -93,5 +89,7 @@ void setup_pmic(void); void setup_iomux_gpio(int board, struct ventana_board_info *); /* late setup of GPIO (configuration per baseboard and env) */ void setup_board_gpio(int board, struct ventana_board_info *); +/* early model/revision ft fixups */ +void ft_early_fixup(void *fdt, int board_type); #endif /* #ifndef _GWVENTANA_COMMON_H_ */ diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c index b9862c7dfc..d21aa3c38f 100644 --- a/board/gateworks/gw_ventana/eeprom.c +++ b/board/gateworks/gw_ventana/eeprom.c @@ -124,6 +124,12 @@ read_eeprom(int bus, struct ventana_board_info *info) type = GW5908; else if (info->model[4] == '0' && info->model[5] == '9') type = GW5909; + else if (info->model[4] == '1' && info->model[5] == '0') + type = GW5910; + else if (info->model[4] == '1' && info->model[5] == '2') + type = GW5912; + else if (info->model[4] == '1' && info->model[5] == '3') + type = GW5913; break; default: printf("EEPROM: Unknown model in EEPROM: %s\n", info->model); diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c index 59fd1b6939..324e5dbed2 100644 --- a/board/gateworks/gw_ventana/gsc.c +++ b/board/gateworks/gw_ventana/gsc.c @@ -15,10 +15,13 @@ #include <linux/ctype.h> #include <asm/arch/sys_proto.h> +#include <asm/global_data.h> #include "ventana_eeprom.h" #include "gsc.h" +DECLARE_GLOBAL_DATA_PTR; + /* * The Gateworks System Controller will fail to ACK a master transaction if * it is busy, which can occur during its 1HZ timer tick while reading ADC's. @@ -65,24 +68,116 @@ int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) return ret; } -static void read_hwmon(const char *name, uint reg, uint size) +int gsc_get_board_temp(void) { - unsigned char buf[3]; - uint ui; + const void *fdt = gd->fdt_blob; + int node, reg, mode, val; + const char *label; + u8 buf[2]; + int ret; - printf("%-8s:", name); - memset(buf, 0, sizeof(buf)); - if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) { - puts("fRD\n"); - } else { - ui = buf[0] | (buf[1]<<8) | (buf[2]<<16); - if (size == 2 && ui > 0x8000) - ui -= 0xffff; - if (ui == 0xffffff) - puts("invalid\n"); - else - printf("%d\n", ui); + node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc"); + if (node <= 0) + return node; + i2c_set_bus_num(0); + + /* iterate over hwmon nodes */ + node = fdt_first_subnode(fdt, node); + while (node > 0) { + reg = fdtdec_get_int(fdt, node, "reg", -1); + mode = fdtdec_get_int(fdt, node, "gw,mode", -1); + label = fdt_stringlist_get(fdt, node, "label", 0, NULL); + + if ((reg == -1) || (mode == -1) || !label) { + printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL)); + continue; + } + + if ((mode != 0) || strcmp(label, "temp")) + continue; + + memset(buf, 0, sizeof(buf)); + ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf)); + val = buf[0] | buf[1] << 8; + if (val >= 0) { + if (val > 0x8000) + val -= 0xffff; + return val; + } + node = fdt_next_subnode(fdt, node); } + + return 0; +} + +/* display hardware monitor ADC channels */ +int gsc_hwmon(void) +{ + const void *fdt = gd->fdt_blob; + int node, reg, mode, len, val, offset; + const char *label; + u8 buf[2]; + int ret; + + node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc"); + if (node <= 0) + return node; + i2c_set_bus_num(0); + + /* iterate over hwmon nodes */ + node = fdt_first_subnode(fdt, node); + while (node > 0) { + reg = fdtdec_get_int(fdt, node, "reg", -1); + mode = fdtdec_get_int(fdt, node, "gw,mode", -1); + offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0); + label = fdt_stringlist_get(fdt, node, "label", 0, NULL); + + if ((reg == -1) || (mode == -1) || !label) + printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL)); + + memset(buf, 0, sizeof(buf)); + ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf)); + val = buf[0] | buf[1] << 8; + if (val >= 0) { + const u32 *div; + int r[2]; + + switch (mode) { + case 0: /* temperature (C*10) */ + if (val > 0x8000) + val -= 0xffff; + printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10)); + break; + case 1: /* prescaled voltage */ + if (val != 0xffff) + printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); + break; + case 2: /* scaled based on ref volt and resolution */ + val *= 2500; + val /= 1 << 12; + + /* apply pre-scaler voltage divider */ + div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len); + if (div && (len == sizeof(uint32_t) * 2)) { + r[0] = fdt32_to_cpu(div[0]); + r[1] = fdt32_to_cpu(div[1]); + if (r[0] && r[1]) { + val *= (r[0] + r[1]); + val /= r[1]; + } + } + + /* adjust by offset */ + val += (offset / 1000); + + printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); + break; + } + } + node = fdt_next_subnode(fdt, node); + } + + return 0; } int gsc_info(int verbose) @@ -103,54 +198,13 @@ int gsc_info(int verbose) gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &buf[GSC_SC_STATUS], 1); } - if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) { - int ui = buf[0] | buf[1]<<8; - if (ui > 0x8000) - ui -= 0xffff; - printf(" board temp at %dC", ui / 10); - } + printf(" board temp at %dC", gsc_get_board_temp() / 10); puts("\n"); if (!verbose) return CMD_RET_SUCCESS; - read_hwmon("Temp", GSC_HWMON_TEMP, 2); - read_hwmon("VIN", GSC_HWMON_VIN, 3); - read_hwmon("VBATT", GSC_HWMON_VBATT, 3); - read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3); - read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3); - read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3); - read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3); - read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3); - read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3); - if (strncasecmp((const char*) ventana_info.model, "GW553", 5)) - read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3); - read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3); - read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3); - switch (ventana_info.model[3]) { - case '1': /* GW51xx */ - read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - break; - case '2': /* GW52xx */ - break; - case '3': /* GW53xx */ - read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '4': /* GW54xx */ - read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */ - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '5': /* GW55xx */ - break; - case '6': /* GW560x */ - read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); - read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3); - break; - case '9': /* GW590x */ - read_hwmon("AMONBMON", GSC_HWMON_VDD_IO3, 3); - read_hwmon("BAT_VOLT", GSC_HWMON_VDD_EXT, 3); - read_hwmon("BAT_TEMP", GSC_HWMON_VDD_IO4, 2); - } + gsc_hwmon(); + return 0; } diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 912075db88..79629828d0 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -372,18 +372,6 @@ int power_init_board(void) return 0; } -int imx6_pcie_toggle_reset(struct gpio_desc *gpio, bool active_high) -{ - if (board_type < GW_UNKNOWN) { - uint pin = gpio_cfg[board_type].pcie_rst; - gpio_request(pin, "pci_rst#"); - gpio_direction_output(pin, 0); - mdelay(50); - gpio_direction_output(pin, 1); - } - return 0; -} - /* * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its * GPIO's as PERST# signals for its downstream ports - configure the GPIO's @@ -967,16 +955,6 @@ void ft_board_pci_fixup(void *blob, struct bd_info *bd) } #endif /* if defined(CONFIG_CMD_PCI) */ -void ft_board_wdog_fixup(void *blob, phys_addr_t addr) -{ - int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr); - - if (off) { - fdt_delprop(blob, off, "ext-reset-output"); - fdt_delprop(blob, off, "fsl,ext-reset-output"); - } -} - /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -986,16 +964,12 @@ void ft_board_wdog_fixup(void *blob, phys_addr_t addr) * - board (full model from EEPROM) * - peripherals removed from DTB if not loaded on board (per EEPROM config) */ -#define WDOG1_ADDR 0x20bc000 -#define WDOG2_ADDR 0x20c0000 -#define GPIO3_ADDR 0x20a4000 -#define USDHC3_ADDR 0x2198000 #define PWM0_ADDR 0x2080000 int ft_board_setup(void *blob, struct bd_info *bd) { struct ventana_board_info *info = &ventana_info; struct ventana_eeprom_config *cfg; - static const struct node_info nodes[] = { + static const struct node_info nand_nodes[] = { { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */ { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ }; @@ -1017,11 +991,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } - if (test_bit(EECONFIG_NAND, info->config)) { - /* Update partition nodes using info from mtdparts env var */ - puts(" Updating MTD partitions...\n"); - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); - } + /* Update MTD partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nand_nodes, ARRAY_SIZE(nand_nodes)); /* Update display timings from display env var */ if (display) { @@ -1043,139 +1015,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) /* set desired digital video capture format */ ft_sethdmiinfmt(blob, env_get("hdmiinfmt")); - /* - * Board model specific fixups - */ - switch (board_type) { - case GW51xx: - /* - * disable wdog node for GW51xx-A/B to work around - * errata causing wdog timer to be unreliable. - */ - if (rev >= 'A' && rev < 'C') { - i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", - WDOG1_ADDR); - if (i) - fdt_status_disabled(blob, i); - } - - /* GW51xx-E adds WDOG1_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW52xx: - /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ - if (info->model[4] == '2') { - u32 handle = 0; - u32 *range = NULL; - - i = fdt_node_offset_by_compatible(blob, -1, - "fsl,imx6q-pcie"); - if (i) - range = (u32 *)fdt_getprop(blob, i, - "reset-gpio", NULL); - - if (range) { - i = fdt_node_offset_by_compat_reg(blob, - "fsl,imx6q-gpio", GPIO3_ADDR); - if (i) - handle = fdt_get_phandle(blob, i); - if (handle) { - range[0] = cpu_to_fdt32(handle); - range[1] = cpu_to_fdt32(23); - } - } - - /* these have broken usd_vsel */ - if (strstr((const char *)info->model, "SP318-B") || - strstr((const char *)info->model, "SP331-B")) - gpio_cfg[board_type].usd_vsel = 0; - - /* GW522x-B adds WDOG1_B external reset */ - if (rev < 'B') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - } - - /* GW520x-E adds WDOG1_B external reset */ - else if (info->model[4] == '0' && rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW53xx: - /* GW53xx-E adds WDOG1_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - - case GW54xx: - /* - * disable serial2 node for GW54xx for compatibility with older - * 3.10.x kernel that improperly had this node enabled in the DT - */ - fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED, - 0); - - /* GW54xx-E adds WDOG2_B external reset */ - if (rev < 'E') - ft_board_wdog_fixup(blob, WDOG2_ADDR); - break; - - case GW551x: - /* - * isolate CSI0_DATA_EN for GW551x-A to work around errata - * causing non functional digital video in (it is not hooked up) - */ - if (rev == 'A') { - u32 *range = NULL; - int len; - const u32 *handle = NULL; - - i = fdt_node_offset_by_compatible(blob, -1, - "fsl,imx-tda1997x-video"); - if (i) - handle = fdt_getprop(blob, i, "pinctrl-0", - NULL); - if (handle) - i = fdt_node_offset_by_phandle(blob, - fdt32_to_cpu(*handle)); - if (i) - range = (u32 *)fdt_getprop(blob, i, "fsl,pins", - &len); - if (range) { - len /= sizeof(u32); - for (i = 0; i < len; i += 6) { - u32 mux_reg = fdt32_to_cpu(range[i+0]); - u32 conf_reg = fdt32_to_cpu(range[i+1]); - /* mux PAD_CSI0_DATA_EN to GPIO */ - if (is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x260 && - conf_reg == 0x630) - range[i+3] = cpu_to_fdt32(0x5); - else if (!is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x08c && - conf_reg == 0x3a0) - range[i+3] = cpu_to_fdt32(0x5); - } - fdt_setprop_inplace(blob, i, "fsl,pins", range, - len); - } - - /* set BT656 video format */ - ft_sethdmiinfmt(blob, "yuv422bt656"); - } - - /* GW551x-C adds WDOG1_B external reset */ - if (rev < 'C') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - case GW5901: - case GW5902: - /* GW5901/GW5901 revB adds WDOG1_B as an external reset */ - if (rev < 'B') - ft_board_wdog_fixup(blob, WDOG1_ADDR); - break; - } + /* early board/revision ft fixups */ + ft_early_fixup(blob, board_type); /* Configure DIO */ for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { @@ -1201,15 +1042,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) } } - /* remove no-1-8-v if UHS-I support is present */ - if (gpio_cfg[board_type].usd_vsel) { - debug("Enabling UHS-I support\n"); - i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc", - USDHC3_ADDR); - if (i) - fdt_delprop(blob, i, "no-1-8-v"); - } - #if defined(CONFIG_CMD_PCI) if (!env_get("nopcifixup")) ft_board_pci_fixup(blob, bd); diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index a4f64395a1..5a69aff671 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -729,10 +729,10 @@ void board_boot_order(u32 *spl_boot_list) /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */ /* its our chance to print info about boot device */ +static int board_type; void spl_board_init(void) { u32 boot_device; - int board_type; /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */ boot_device = spl_boot_device(); @@ -785,3 +785,8 @@ int spl_start_uboot(void) return ret; } #endif + +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + ft_early_fixup(spl_image->fdt_addr, board_type); +} diff --git a/board/gateworks/gw_ventana/ventana_eeprom.h b/board/gateworks/gw_ventana/ventana_eeprom.h index 4fa085b320..2d5c27261e 100644 --- a/board/gateworks/gw_ventana/ventana_eeprom.h +++ b/board/gateworks/gw_ventana/ventana_eeprom.h @@ -121,6 +121,9 @@ enum { GW5907, GW5908, GW5909, + GW5910, + GW5912, + GW5913, GW_UNKNOWN, GW_BADCRC, }; diff --git a/board/gateworks/venice/gsc.c b/board/gateworks/venice/gsc.c index 271bc8c229..7d6acd7b4a 100644 --- a/board/gateworks/venice/gsc.c +++ b/board/gateworks/venice/gsc.c @@ -18,6 +18,7 @@ DECLARE_GLOBAL_DATA_PTR; struct venice_board_info som_info; struct venice_board_info base_info; char venice_model[32]; +uint32_t venice_serial; /* return a mac address from EEPROM info */ int gsc_getmac(int index, uint8_t *address) @@ -123,13 +124,13 @@ enum { GSC_SC_RST_CAUSE_MAX = 10, }; +#include <dm/device.h> static struct udevice *gsc_get_dev(int busno, int slave) { - static const char * const i2c[] = { "i2c@30a20000", "i2c@30a30000" }; struct udevice *dev, *bus; int ret; - ret = uclass_get_device_by_name(UCLASS_I2C, i2c[busno - 1], &bus); + ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); if (ret) { printf("GSC : failed I2C%d probe: %d\n", busno, ret); return NULL; @@ -246,7 +247,7 @@ int gsc_hwmon(void) return node; /* probe device */ - dev = gsc_get_dev(1, GSC_HWMON_ADDR); + dev = gsc_get_dev(GSC_BUSNO, GSC_HWMON_ADDR); if (!dev) { puts("ERROR: Failed to probe GSC HWMON\n"); return -ENODEV; @@ -451,33 +452,22 @@ const char *gsc_get_dtb_name(int level, char *buf, int sz) static int gsc_read(void) { + char rev_pcb; + int rev_bom; int ret; - ret = gsc_read_eeprom(1, GSC_EEPROM_ADDR, 1, &som_info); + ret = gsc_read_eeprom(GSC_BUSNO, GSC_EEPROM_ADDR, 1, &som_info); if (ret) { memset(&som_info, 0, sizeof(som_info)); return ret; } /* read optional baseboard EEPROM */ - return gsc_read_eeprom(2, 0x52, 2, &base_info); -} + gsc_read_eeprom(BASEBOARD_EEPROM_BUSNO, BASEBOARD_EEPROM_ADDR, + 2, &base_info); -static int gsc_info(int verbose) -{ - struct udevice *dev; - unsigned char buf[16]; - char rev_pcb; - int rev_bom; - - if (!base_info.model[0]) { - strcpy(venice_model, som_info.model); - printf("Model : %s\n", som_info.model); - printf("Serial : %d\n", som_info.serial); - printf("MFGDate : %02x-%02x-%02x%02x\n", - som_info.mfgdate[0], som_info.mfgdate[1], - som_info.mfgdate[2], som_info.mfgdate[3]); - } else { + /* create model strings */ + if (base_info.model[0]) { sprintf(venice_model, "GW%c%c%c%c-%c%c-", som_info.model[2], /* family */ base_info.model[3], /* baseboard */ @@ -498,27 +488,38 @@ static int gsc_info(int verbose) sprintf(venice_model + strlen(venice_model), "%c%d", rev_pcb, rev_bom); else sprintf(venice_model + strlen(venice_model), "%c", rev_pcb); + } else { + strcpy(venice_model, som_info.model); + } + venice_serial = som_info.serial; - if (verbose > 1) { - printf("SOM : %s %d %02x-%02x-%02x%02x\n", - som_info.model, som_info.serial, - som_info.mfgdate[0], som_info.mfgdate[1], - som_info.mfgdate[2], som_info.mfgdate[3]); - printf("BASE : %s %d %02x-%02x-%02x%02x\n", - base_info.model, base_info.serial, - base_info.mfgdate[0], base_info.mfgdate[1], - base_info.mfgdate[2], base_info.mfgdate[3]); - } - printf("Model : %s\n", venice_model); - printf("Serial : %d\n", som_info.serial); - printf("MFGDate : %02x-%02x-%02x%02x\n", + return 0; +} + +static int gsc_info(int verbose) +{ + struct udevice *dev; + unsigned char buf[16]; + + printf("Model : %s\n", venice_model); + printf("Serial : %d\n", som_info.serial); + printf("MFGDate : %02x-%02x-%02x%02x\n", + som_info.mfgdate[0], som_info.mfgdate[1], + som_info.mfgdate[2], som_info.mfgdate[3]); + if (base_info.model[0] && verbose > 1) { + printf("SOM : %s %d %02x-%02x-%02x%02x\n", + som_info.model, som_info.serial, som_info.mfgdate[0], som_info.mfgdate[1], som_info.mfgdate[2], som_info.mfgdate[3]); + printf("BASE : %s %d %02x-%02x-%02x%02x\n", + base_info.model, base_info.serial, + base_info.mfgdate[0], base_info.mfgdate[1], + base_info.mfgdate[2], base_info.mfgdate[3]); } /* Display RTC */ puts("RTC : "); - dev = gsc_get_dev(1, GSC_RTC_ADDR); + dev = gsc_get_dev(GSC_BUSNO, GSC_RTC_ADDR); if (!dev) { puts("Failed to probe GSC RTC\n"); } else { @@ -542,7 +543,7 @@ int gsc_init(int quiet) */ while (1) { /* probe device */ - dev = gsc_get_dev(1, GSC_SC_ADDR); + dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); if (dev) break; mdelay(1); @@ -575,6 +576,11 @@ const char *gsc_get_model(void) return venice_model; } +uint32_t gsc_get_serial(void) +{ + return venice_serial; +} + #if !(IS_ENABLED(CONFIG_SPL_BUILD)) static int gsc_sleep(unsigned long secs) { @@ -583,7 +589,7 @@ static int gsc_sleep(unsigned long secs) int ret; /* probe device */ - dev = gsc_get_dev(1, GSC_SC_ADDR); + dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); if (!dev) return -ENODEV; @@ -631,7 +637,7 @@ static int gsc_boot_wd_disable(void) int ret; /* probe device */ - dev = gsc_get_dev(1, GSC_SC_ADDR); + dev = gsc_get_dev(GSC_BUSNO, GSC_SC_ADDR); if (!dev) return -ENODEV; diff --git a/board/gateworks/venice/gsc.h b/board/gateworks/venice/gsc.h index 27b02117bb..b391b2e326 100644 --- a/board/gateworks/venice/gsc.h +++ b/board/gateworks/venice/gsc.h @@ -6,11 +6,16 @@ #ifndef _GSC_H_ #define _GSC_H_ +/* I2C bus numbers */ +#define GSC_BUSNO 0 +#define BASEBOARD_EEPROM_BUSNO 1 + /* I2C slave addresses */ #define GSC_SC_ADDR 0x20 #define GSC_RTC_ADDR 0x68 #define GSC_HWMON_ADDR 0x29 #define GSC_EEPROM_ADDR 0x51 +#define BASEBOARD_EEPROM_ADDR 0x52 struct venice_board_info { u8 mac[6]; /* 0x00: MAC base */ @@ -35,5 +40,6 @@ int gsc_hwmon(void); const char *gsc_get_model(void); const char *gsc_get_dtb_name(int level, char *buf, int len); int gsc_getmac(int index, uint8_t *enetaddr); +uint32_t gsc_get_serial(void); #endif diff --git a/board/gateworks/venice/imx8mm_venice.c b/board/gateworks/venice/imx8mm_venice.c index 2657bd675f..2a97d55d32 100644 --- a/board/gateworks/venice/imx8mm_venice.c +++ b/board/gateworks/venice/imx8mm_venice.c @@ -13,6 +13,7 @@ #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <asm/unaligned.h> #include "gsc.h" @@ -20,20 +21,19 @@ DECLARE_GLOBAL_DATA_PTR; int board_phys_sdram_size(phys_size_t *size) { - int ddr_size = readl(M4_BOOTROM_BASE_ADDR); - - if (ddr_size == 0x4) { - *size = 0x100000000; - } else if (ddr_size == 0x3) { - *size = 0xc0000000; - } else if (ddr_size == 0x2) { - *size = 0x80000000; - } else if (ddr_size == 0x1) { - *size = 0x40000000; - } else { - printf("Unknown DDR type!!!\n"); - *size = 0x40000000; - } + const fdt64_t *val; + int offset; + int len; + + /* get size from dt which SPL updated per EEPROM config */ + offset = fdt_path_offset(gd->fdt_blob, "/memory"); + if (offset < 0) + return -EINVAL; + + val = fdt_getprop(gd->fdt_blob, offset, "reg", &len); + if (len < sizeof(*val) * 2) + return -EINVAL; + *size = get_unaligned_be64(&val[1]); return 0; } @@ -113,6 +113,10 @@ int board_late_init(void) led_default_state(); + /* Set board serial/model */ + env_set_ulong("serial#", gsc_get_serial()); + env_set("model", gsc_get_model()); + /* Set fdt_file vars */ i = 0; do { @@ -148,3 +152,11 @@ int board_mmc_get_env_dev(int devno) { return devno; } + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* set board model dt prop */ + fdt_setprop_string(blob, 0, "board", gsc_get_model()); + + return 0; +} diff --git a/board/gateworks/venice/lpddr4_timing.c b/board/gateworks/venice/lpddr4_timing.c index 47e93e1236..f362d9741c 100644 --- a/board/gateworks/venice/lpddr4_timing.c +++ b/board/gateworks/venice/lpddr4_timing.c @@ -2503,3 +2503,519 @@ struct dram_timing_info dram_timing_4gb = { .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), .fsp_table = { 3000, 400, 100, }, }; + +static struct dram_cfg_param lpddr4_ddrc_cfg_2gb[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x3a980 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg_2gb[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x5 }, + { 0x130a3, 0x2 }, + { 0x130a4, 0x3 }, + { 0x130a5, 0x4 }, + { 0x130a6, 0x7 }, + { 0x130a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, +}; + +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp2_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg_2gb[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg_2gb[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg_2gb), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg_2gb), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp2_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg_2gb), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg_2gb, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg_2gb), + }, +}; + +/* lpddr4 timing config params */ +struct dram_timing_info dram_timing_2gb = { + .ddrc_cfg = lpddr4_ddrc_cfg_2gb, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg_2gb), + .ddrphy_cfg = lpddr4_ddrphy_cfg_2gb, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg_2gb), + .fsp_msg = lpddr4_dram_fsp_msg_2gb, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg_2gb), + .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/gateworks/venice/lpddr4_timing.h b/board/gateworks/venice/lpddr4_timing.h index 94445f86a4..b73d067f7d 100644 --- a/board/gateworks/venice/lpddr4_timing.h +++ b/board/gateworks/venice/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1gb; +extern struct dram_timing_info dram_timing_2gb; extern struct dram_timing_info dram_timing_4gb; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 8c357757c1..b819c6846d 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -44,6 +44,9 @@ static void spl_dram_init(int size) case 1: dram_timing = &dram_timing_1gb; break; + case 2: + dram_timing = &dram_timing_2gb; + break; case 4: dram_timing = &dram_timing_4gb; break; @@ -116,7 +119,7 @@ static int power_init_board(void) if ((!strncmp(model, "GW71", 4)) || (!strncmp(model, "GW72", 4)) || (!strncmp(model, "GW73", 4))) { - ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a20000", &bus); + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C1 probe: %d\n", ret); return ret; @@ -133,8 +136,12 @@ static int power_init_board(void) BIT(7) | MP5416_VSET_SW3_SVAL(920000)); } - else if (!strncmp(model, "GW7901", 6)) { - ret = uclass_get_device_by_name(UCLASS_I2C, "i2c@30a30000", &bus); + else if ((!strncmp(model, "GW7901", 6)) || + (!strncmp(model, "GW7902", 6))) { + if (!strncmp(model, "GW7901", 6)) + ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + else + ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); if (ret) { printf("PMIC : failed I2C2 probe: %d\n", ret); return ret; diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 9af1f92e5d..d2e2e4ae20 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -196,7 +196,6 @@ int board_fix_fdt(void *rw_fdt_blob) } #endif -#if IS_ENABLED(CONFIG_DM_PCI) int board_early_init_r(void) { struct udevice *dev; @@ -243,69 +242,3 @@ int board_early_init_r(void) return 0; } -#else -void pci_init_board(void) -{ - pci_dev_t bdf; - u32 val32; - u8 val8; - - switch (malta_sys_con()) { - case SYSCON_GT64120: - gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - 0x10000000, 0x10000000, 128 * 1024 * 1024, - 0x00000000, 0x00000000, 0x20000); - break; - - default: - case SYSCON_MSC01: - msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), - 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, - MALTA_MSC01_PCIMEM_MAP, - CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), - MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, - 0x00000000, MALTA_MSC01_PCIIO_SIZE); - break; - } - - bdf = pci_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB_0, 0); - if (bdf == -1) - panic("Failed to find PIIX4 PCI bridge\n"); - - /* setup PCI interrupt routing */ - pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10); - pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10); - pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11); - pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11); - - /* mux SERIRQ onto SERIRQ pin */ - pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32); - val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ; - pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32); - - /* enable SERIRQ - Linux currently depends upon this */ - pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); - val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; - pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); - - bdf = pci_find_device(PCI_VENDOR_ID_INTEL, - PCI_DEVICE_ID_INTEL_82371AB, 0); - if (bdf == -1) - panic("Failed to find PIIX4 IDE controller\n"); - - /* enable bus master & IO access */ - val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; - pci_write_config_dword(bdf, PCI_COMMAND, val32); - - /* set latency */ - pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); - - /* enable IDE/ATA */ - pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, - PCI_CFG_PIIX4_IDETIM_IDE); - pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, - PCI_CFG_PIIX4_IDETIM_IDE); -} -#endif diff --git a/board/intel/n5x-socdk/MAINTAINERS b/board/intel/n5x-socdk/MAINTAINERS new file mode 100644 index 0000000000..ca063a9f3f --- /dev/null +++ b/board/intel/n5x-socdk/MAINTAINERS @@ -0,0 +1,9 @@ +SOCFPGA BOARD +M: Chee Tien Fong <tien.fong.chee@intel.com> +M: Lim Siew Chin <elly.siew.chin.lim@intel.com> +S: Maintained +F: board/intel/n5x-socdk/ +F: include/configs/socfpga_n5x_socdk.h +F: configs/socfpga_n5x_defconfig +F: configs/socfpga_n5x_atf_defconfig +F: configs/socfpga_n5x_vab_defconfig diff --git a/board/intel/n5x-socdk/Makefile b/board/intel/n5x-socdk/Makefile new file mode 100644 index 0000000000..accfdcddcb --- /dev/null +++ b/board/intel/n5x-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2020-2021 Intel Corporation <www.intel.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/n5x-socdk/socfpga.c b/board/intel/n5x-socdk/socfpga.c new file mode 100644 index 0000000000..985ba190d0 --- /dev/null +++ b/board/intel/n5x-socdk/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020-2021 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c index e930de31b2..2dd2c1534c 100644 --- a/board/renesas/condor/condor.c +++ b/board/renesas/condor/condor.c @@ -21,9 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 0aaae815c0..3d00652a8d 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -54,9 +54,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c index bb32e3d2c5..3417b50f3b 100644 --- a/board/renesas/eagle/eagle.c +++ b/board/renesas/eagle/eagle.c @@ -65,9 +65,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c index 9d4af8d3a6..9a70192596 100644 --- a/board/renesas/ebisu/ebisu.c +++ b/board/renesas/ebisu/ebisu.c @@ -32,9 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - return 0; } diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index 1802547bbf..d4752e5798 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -53,9 +53,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index ffc4eb9ff3..4626d223b0 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -51,9 +51,6 @@ int board_early_init_f(void) int board_init(void) { - /* adress of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; - /* USB1 pull-up */ setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); diff --git a/board/sifive/unleashed/Makefile b/board/sifive/unleashed/Makefile index 5821679dd9..98e9111cbc 100644 --- a/board/sifive/unleashed/Makefile +++ b/board/sifive/unleashed/Makefile @@ -2,8 +2,8 @@ # # Copyright (c) 2019 Western Digital Corporation or its affiliates. -obj-y += unleashed.o - ifdef CONFIG_SPL_BUILD obj-y += spl.o +else +obj-y += unleashed.o endif diff --git a/board/sifive/unleashed/unleashed.c b/board/sifive/unleashed/unleashed.c index a4e78220cb..fa65fcade0 100644 --- a/board/sifive/unleashed/unleashed.c +++ b/board/sifive/unleashed/unleashed.c @@ -16,6 +16,7 @@ #include <misc.h> #include <spl.h> #include <asm/arch/cache.h> +#include <asm/sections.h> /* * This define is a value used for error/unknown serial. @@ -113,6 +114,16 @@ int misc_init_r(void) #endif +void *board_fdt_blob_setup(void) +{ + if (IS_ENABLED(CONFIG_OF_SEPARATE)) { + if (gd->arch.firmware_fdt_addr) + return (ulong *)gd->arch.firmware_fdt_addr; + else + return (ulong *)&_end; + } +} + int board_init(void) { int ret; diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile index e00b330e8c..1345330089 100644 --- a/board/sifive/unmatched/Makefile +++ b/board/sifive/unmatched/Makefile @@ -2,9 +2,10 @@ # # Copyright (c) 2020-2021 SiFive, Inc -obj-y += unmatched.o obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +else +obj-y += unmatched.o endif diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 6d60559588..da23a6ce24 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -9,6 +9,17 @@ #include <common.h> #include <dm.h> #include <asm/arch/cache.h> +#include <asm/sections.h> + +void *board_fdt_blob_setup(void) +{ + if (IS_ENABLED(CONFIG_OF_SEPARATE)) { + if (gd->arch.firmware_fdt_addr) + return (ulong *)gd->arch.firmware_fdt_addr; + else + return (ulong *)&_end; + } +} int board_init(void) { diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 3444af6a8c..3ba2fbbd56 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -53,7 +53,7 @@ int checkboard (void) } putc('\n'); -#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI) +#if defined(CONFIG_PCI) /* Check the PCI_clk sel bit */ if (in_be32(&gur->porpllsr) & (1<<15)) { src = "SYSCLK"; @@ -130,9 +130,7 @@ int misc_init_r (void) &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); } -#if defined(CONFIG_DM_PCI) pci_init(); -#endif return 0; } diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index ddcf33a122..2f57118bb2 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -8,18 +8,22 @@ config CMD_STBOARD config MTDPARTS_NAND0_BOOT string "mtd boot partitions for nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" + default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \ + !TFABOOT + default "2m(fsbl),4m(fip1),4m(fip2)" depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP help This define the partitions of nand0 used to build mtparts dynamically for boot from nand0. Each partition need to be aligned with the device erase block size, 512KB is the max size for the NAND supported by stm32mp1 platform. + The fsbl partition support multiple copy of the same binary, one by + erase block. config MTDPARTS_NAND0_TEE string "mtd tee partitions for nand0" default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE help This define the tee partitions added in mtparts dynamically when tee is supported with boot from nand0. @@ -28,7 +32,9 @@ config MTDPARTS_NAND0_TEE config MTDPARTS_NOR0_BOOT string "mtd boot partitions for nor0" - default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" + default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if STM32MP15x_STM32IMAGE || \ + !TFABOOT + default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)" depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP help This define the partitions of nand0 used to build mtparts dynamically @@ -40,24 +46,27 @@ config MTDPARTS_NOR0_BOOT config MTDPARTS_NOR0_TEE string "mtd tee partitions for nor0" default "256k(teeh),512k(teed),256k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE help This define the tee partitions added in mtparts dynamically when tee is supported with boot from nor0. config MTDPARTS_SPINAND0_BOOT string "mtd boot partitions for spi-nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" + default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || !TFABOOT + default "2m(fsbl),4m(fip1),4m(fip2)" depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP help This define the partitions of nand0 used to build mtparts dynamically for boot from spi-nand0, 512KB is the max size for the NAND supported by stm32mp1 platform. + The fsbl partition support multiple copy of the same binary, one by + erase block. config MTDPARTS_SPINAND0_TEE string "mtd tee partitions for spi-nand0" default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP + depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE help This define the tee partitions added in mtparts dynamically when tee is supported with boot from spi-nand0, diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c index f074fc189d..8b636d62fa 100644 --- a/board/st/common/stm32mp_mtdparts.c +++ b/board/st/common/stm32mp_mtdparts.c @@ -11,7 +11,9 @@ #include <log.h> #include <mtd.h> #include <mtd_node.h> +#ifdef CONFIG_STM32MP15x_STM32IMAGE #include <tee.h> +#endif #include <asm/arch/stm32prog.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> @@ -31,7 +33,9 @@ static void board_set_mtdparts(const char *dev, char *mtdids, char *mtdparts, const char *boot, +#ifdef CONFIG_STM32MP15x_STM32IMAGE const char *tee, +#endif const char *user) { /* mtdids: "<dev>=<dev>, ...." */ @@ -55,10 +59,12 @@ static void board_set_mtdparts(const char *dev, strncat(mtdparts, ",", MTDPARTS_LEN); } +#ifdef CONFIG_STM32MP15x_STM32IMAGE if (tee) { strncat(mtdparts, tee, MTDPARTS_LEN); strncat(mtdparts, ",", MTDPARTS_LEN); } +#endif strncat(mtdparts, user, MTDPARTS_LEN); } @@ -70,7 +76,10 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) static char parts[3 * MTDPARTS_LEN + 1]; static char ids[MTDIDS_LEN + 1]; static bool mtd_initialized; - bool tee, nor, nand, spinand, serial; + bool nor, nand, spinand, serial; +#ifdef CONFIG_STM32MP15x_STM32IMAGE + bool tee = false; +#endif if (mtd_initialized) { *mtdids = ids; @@ -78,7 +87,6 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) return; } - tee = false; nor = false; nand = false; spinand = false; @@ -89,7 +97,9 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) case BOOT_SERIAL_USB: serial = true; if (CONFIG_IS_ENABLED(CMD_STM32PROG)) { +#ifdef CONFIG_STM32MP15x_STM32IMAGE tee = stm32prog_get_tee_partitions(); +#endif nor = stm32prog_get_fsbl_nor(); } nand = true; @@ -108,9 +118,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) break; } +#ifdef CONFIG_STM32MP15x_STM32IMAGE if (!serial && CONFIG_IS_ENABLED(OPTEE) && tee_find_device(NULL, NULL, NULL, NULL)) tee = true; +#endif memset(parts, 0, sizeof(parts)); memset(ids, 0, sizeof(ids)); @@ -125,10 +137,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) if (nand) { mtd = get_mtd_device_nm("nand0"); if (!IS_ERR_OR_NULL(mtd)) { - const char *mtd_tee = CONFIG_MTDPARTS_NAND0_TEE; board_set_mtdparts("nand0", ids, parts, CONFIG_MTDPARTS_NAND0_BOOT, - !nor && tee ? mtd_tee : NULL, +#ifdef CONFIG_STM32MP15x_STM32IMAGE + !nor && tee ? CONFIG_MTDPARTS_NAND0_TEE : NULL, +#endif "-(UBI)"); put_mtd_device(mtd); } @@ -137,10 +150,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) if (spinand) { mtd = get_mtd_device_nm("spi-nand0"); if (!IS_ERR_OR_NULL(mtd)) { - const char *mtd_tee = CONFIG_MTDPARTS_SPINAND0_TEE; board_set_mtdparts("spi-nand0", ids, parts, CONFIG_MTDPARTS_SPINAND0_BOOT, - !nor && tee ? mtd_tee : NULL, +#ifdef CONFIG_STM32MP15x_STM32IMAGE + !nor && tee ? CONFIG_MTDPARTS_SPINAND0_TEE : NULL, +#endif "-(UBI)"); put_mtd_device(mtd); } @@ -148,10 +162,11 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) if (nor) { if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { - const char *mtd_tee = CONFIG_MTDPARTS_NOR0_TEE; board_set_mtdparts("nor0", ids, parts, CONFIG_MTDPARTS_NOR0_BOOT, - tee ? mtd_tee : NULL, +#ifdef CONFIG_STM32MP15x_STM32IMAGE + tee ? CONFIG_MTDPARTS_NOR0_TEE : NULL, +#endif "-(nor_user)"); } } diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index fe8fc6f484..0e6d80fb45 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -5,6 +5,7 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-stm.git S: Maintained F: arch/arm/dts/stm32mp15* F: board/st/stm32mp1/ +F: configs/stm32mp15_defconfig F: configs/stm32mp15_basic_defconfig F: configs/stm32mp15_trusted_defconfig F: include/configs/stm32mp1.h diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 59fb6e548c..032f08d795 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -105,10 +105,14 @@ int checkboard(void) const char *fdt_compat; int fdt_compat_len; - if (IS_ENABLED(CONFIG_TFABOOT)) - mode = "trusted"; - else + if (IS_ENABLED(CONFIG_TFABOOT)) { + if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE)) + mode = "trusted - stm32image"; + else + mode = "trusted"; + } else { mode = "basic"; + } fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", &fdt_compat_len); diff --git a/board/toradex/apalis-tk1/apalis-tk1.c b/board/toradex/apalis-tk1/apalis-tk1.c index b97617cfca..2769b54601 100644 --- a/board/toradex/apalis-tk1/apalis-tk1.c +++ b/board/toradex/apalis-tk1/apalis-tk1.c @@ -38,8 +38,24 @@ int arch_misc_init(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == - NVBOOTTYPE_RECOVERY) - printf("USB recovery mode\n"); + NVBOOTTYPE_RECOVERY) { + printf("USB recovery mode, attempting to boot Toradex Easy " + "Installer\n"); + env_set("bootdelay", "-2"); + env_set("defargs", "pcie_aspm=off user_debug=30"); + env_set("fdt_high", ""); + env_set("initrd_high", ""); + + env_set("setup", "env set setupargs igb_mac=${ethaddr} " + "consoleblank=0 no_console_suspend=1 " + "console=${console},${baudrate}n8 ${memargs}"); + env_set("teziargs", "rootfstype=squashfs root=/dev/ram quiet " + "autoinstall"); + env_set("vidargs", "video=HDMI-A-1:640x480-16@60D"); + env_set("bootcmd", "run setup; env set bootargs ${defargs} " + "${setupargs} ${vidargs} ${teziargs}; bootm 0x80208000" + "#config@${soc}-${fdt_module}-${fdt_board}.dtb"); + } /* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */ gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication"); diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index c0e7754469..587d92a8e9 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -1081,6 +1081,16 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + if (!strcmp(name, "imx6-colibri")) + return 0; + + return -1; +} +#endif + void reset_cpu(void) { } diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 301b07d5b4..6822102d2c 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -355,12 +355,22 @@ int board_usb_phy_mode(int port) } } +#if defined(CONFIG_BOARD_LATE_INIT) int board_late_init(void) { #if defined(CONFIG_DM_VIDEO) setup_lcd(); #endif + +#if defined(CONFIG_CMD_USB_SDP) + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif return 0; } +#endif /* CONFIG_BOARD_LATE_INIT */ #endif diff --git a/board/toradex/colibri_vf/colibri_vf.c b/board/toradex/colibri_vf/colibri_vf.c index e9c5bc0632..c09591e543 100644 --- a/board/toradex/colibri_vf/colibri_vf.c +++ b/board/toradex/colibri_vf/colibri_vf.c @@ -433,7 +433,7 @@ int checkboard(void) #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { -#ifndef CONFIG_DM_VIDEO +#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO) int ret = 0; #endif #ifdef CONFIG_FDT_FIXUP_PARTITIONS diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig index 36068d2e3b..1f6a5e4db5 100644 --- a/board/toradex/common/Kconfig +++ b/board/toradex/common/Kconfig @@ -84,4 +84,14 @@ config TDX_CFG_BLOCK_EXTRA Enables fetching auxilary config blocks from carrier board/display adapter EEPROMs. +config TDX_CFG_BLOCK_USB_GADGET_PID + bool "Use config block product ID as USB product ID" + depends on USB_GADGET_DOWNLOAD + default y + help + Use the Toradex product ID learned from the config block as USB + product ID. An offset of 0x4000 is added to the product ID since + inside the Toradex vendor ID (0x1b67) the range starting from + offset 0x4000 is reserved for Colibri/Apalis modules. + endif diff --git a/board/toradex/common/tdx-common.c b/board/toradex/common/tdx-common.c index a3d287ed5e..061abf7537 100644 --- a/board/toradex/common/tdx-common.c +++ b/board/toradex/common/tdx-common.c @@ -147,7 +147,7 @@ int show_board_info(void) return 0; } -#ifdef CONFIG_USB_GADGET_DOWNLOAD +#ifdef CONFIG_TDX_CFG_BLOCK_USB_GADGET_PID int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { unsigned short usb_pid; diff --git a/board/warp/imximage.cfg b/board/warp/imximage.cfg index 619f6aa7b0..d952c6f2e9 100644 --- a/board/warp/imximage.cfg +++ b/board/warp/imximage.cfg @@ -24,7 +24,7 @@ BOOT_FROM sd /* * Secure boot support */ -#ifdef CONFIG__IMX_HAB +#ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c index 157aa32826..c1fce7d331 100644 --- a/board/xes/common/fsl_8xxx_pci.c +++ b/board/xes/common/fsl_8xxx_pci.c @@ -14,56 +14,6 @@ #include <linux/libfdt.h> #include <fdt_support.h> - -#ifdef CONFIG_PCI1 -static struct pci_controller pci1_hose; -#endif - -void pci_init_board(void) -{ - int first_free_busno = 0; - -#ifdef CONFIG_PCI1 - int pcie_ep; - struct fsl_pci_info pci_info; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - u32 devdisr = in_be32(&gur->devdisr); - uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD; - uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32; - uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB; - uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1; - uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000; - - if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { - SET_STD_PCI_INFO(pci_info, 1); - set_next_law(pci_info.mem_phys, - law_size_bits(pci_info.mem_size), pci_info.law); - set_next_law(pci_info.io_phys, - law_size_bits(pci_info.io_size), pci_info.law); - - pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs); - printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n", - pci_32 ? 32 : 64, - pcix ? "PCIX" : "PCI", - pci_spd_norm ? ">=" : "<=", - pcix ? freq * 2 : freq, - pcie_ep ? "agent" : "host", - pci_arb ? "arbiter" : "external-arbiter"); - - first_free_busno = fsl_pci_init_port(&pci_info, - &pci1_hose, first_free_busno); - } else { - printf("PCI1: disabled\n"); - } -#elif defined CONFIG_ARCH_MPC8548 - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - /* PCI1 not present on MPC8572 */ - setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); -#endif - - fsl_pcie_init_board(first_free_busno); -} - #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_pci_setup(void *blob, struct bd_info *bd) { |