diff options
Diffstat (limited to 'board')
-rw-r--r-- | board/renesas/draak/Kconfig | 15 | ||||
-rw-r--r-- | board/renesas/draak/MAINTAINERS | 6 | ||||
-rw-r--r-- | board/renesas/draak/Makefile | 9 | ||||
-rw-r--r-- | board/renesas/draak/draak.c | 133 | ||||
-rw-r--r-- | board/renesas/eagle/Kconfig | 15 | ||||
-rw-r--r-- | board/renesas/eagle/MAINTAINERS | 6 | ||||
-rw-r--r-- | board/renesas/eagle/Makefile | 9 | ||||
-rw-r--r-- | board/renesas/eagle/eagle.c | 110 | ||||
-rw-r--r-- | board/samsung/common/exynos5-dt-types.c | 27 | ||||
-rw-r--r-- | board/samsung/common/exynos5-dt.c | 4 |
10 files changed, 325 insertions, 9 deletions
diff --git a/board/renesas/draak/Kconfig b/board/renesas/draak/Kconfig new file mode 100644 index 0000000000..9106387bb9 --- /dev/null +++ b/board/renesas/draak/Kconfig @@ -0,0 +1,15 @@ +if TARGET_DRAAK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "draak" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "draak" + +endif diff --git a/board/renesas/draak/MAINTAINERS b/board/renesas/draak/MAINTAINERS new file mode 100644 index 0000000000..1dbcc2811c --- /dev/null +++ b/board/renesas/draak/MAINTAINERS @@ -0,0 +1,6 @@ +DRAAK BOARD +M: Marek Vasut <marek.vasut+renesas@gmail.com> +S: Maintained +F: board/renesas/draak/ +F: include/configs/draak.h +F: configs/r8a77995_draak_defconfig diff --git a/board/renesas/draak/Makefile b/board/renesas/draak/Makefile new file mode 100644 index 0000000000..604522ebb1 --- /dev/null +++ b/board/renesas/draak/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/draak/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := draak.o diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c new file mode 100644 index 0000000000..acdaaff72a --- /dev/null +++ b/board/renesas/draak/draak.c @@ -0,0 +1,133 @@ +/* + * board/renesas/draak/draak.c + * This file is Draak board support. + * + * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPCR 0xE6150904 +#define CPGWPR 0xE615090C + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + writel(0xA5A50000, CPGWPCR); + writel(0xFFFFFFFF, CPGWPR); +} + +#define GSX_MSTP112 BIT(12) /* 3DG */ +#define TMU0_MSTP125 BIT(25) /* secure */ +#define TMU1_MSTP124 BIT(24) /* non-secure */ +#define SCIF2_MSTP310 BIT(10) /* SCIF2 */ +#define DVFS_MSTP926 BIT(26) +#define HSUSB_MSTP704 BIT(4) /* HSUSB */ + +int board_early_init_f(void) +{ + /* TMU0,1 */ /* which use ? */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); + +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH) + /* DVFS for reset */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, DVFS_MSTP926); +#endif + return 0; +} + +/* SYSC */ +/* R/- 32 Power status register 2(3DG) */ +#define SYSC_PWRSR2 0xE6180100 +/* -/W 32 Power resume control register 2 (3DG) */ +#define SYSC_PWRONCR2 0xE618010C + +/* HSUSB block registers */ +#define HSUSB_REG_LPSTS 0xE6590102 +#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14) +#define HSUSB_REG_UGCTRL2 0xE6590184 +#define HSUSB_REG_UGCTRL2_USB0SEL 0x30 +#define HSUSB_REG_UGCTRL2_USB0SEL_EHCI 0x10 + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* USB1 pull-up */ + setbits_le32(PFC_PUEN6, PUEN_USB1_OVC | PUEN_USB1_PWEN); + + /* Configure the HSUSB block */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, HSUSB_MSTP704); + /* Choice USB0SEL */ + clrsetbits_le32(HSUSB_REG_UGCTRL2, HSUSB_REG_UGCTRL2_USB0SEL, + HSUSB_REG_UGCTRL2_USB0SEL_EHCI); + /* low power status */ + setbits_le16(HSUSB_REG_LPSTS, HSUSB_REG_LPSTS_SUSPM_NORMAL); + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig new file mode 100644 index 0000000000..1e0710e73e --- /dev/null +++ b/board/renesas/eagle/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EAGLE + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "eagle" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "eagle" + +endif diff --git a/board/renesas/eagle/MAINTAINERS b/board/renesas/eagle/MAINTAINERS new file mode 100644 index 0000000000..f387c13616 --- /dev/null +++ b/board/renesas/eagle/MAINTAINERS @@ -0,0 +1,6 @@ +EAGLE BOARD +M: Marek Vasut <marek.vasut+renesas@gmail.com> +S: Maintained +F: board/renesas/eagle/ +F: include/configs/eagle.h +F: configs/r8a77970_eagle_defconfig diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile new file mode 100644 index 0000000000..dffa295404 --- /dev/null +++ b/board/renesas/eagle/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/eagle/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := eagle.o diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c new file mode 100644 index 0000000000..6b918f42a1 --- /dev/null +++ b/board/renesas/eagle/eagle.c @@ -0,0 +1,110 @@ +/* + * board/renesas/eagle/eagle.c + * This file is Eagle board support. + * + * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <netdev.h> +#include <dm.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/sh_sdhi.h> +#include <i2c.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define CPGWPCR 0xE6150904 +#define CPGWPR 0xE615090C + +/* PLL */ +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_OFFSET 24 + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 0.8GHz */ + stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); +} + +#define TMU0_MSTP125 BIT(25) /* secure */ + +int board_early_init_f(void) +{ + writel(0xA5A5FFFF, CPGWPCR); + writel(0x5A5A0000, CPGWPR); + + /* TMU0 */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + return 0; +} + +int dram_init(void) +{ + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; + + return 0; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void reset_cpu(ulong addr) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 48fd1f7d96..03d3a3112a 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -25,17 +25,22 @@ static const struct udevice_id board_ids[] = { }; /** - * Odroix XU3/4 board revisions: + * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf): * Rev ADCmax Board * 0.1 0 XU3 0.1 - * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) - * 0.3 1408 XU4 0.1 - * Use +10 % for ADC value tolerance. + * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) + * 0.3 1280 XU4 0.1 + * 0.4 739 XU4 0.2 + * 0.5 1016 XU4+Air0.1 (Passive cooling) + * 0.6 1308 XU4S 0.1 (HC1) + * Use +1% for ADC value tolerance in the array below, the code loops until + * the measured ADC value is lower than then ADCmax from the array. */ struct odroid_rev_info odroid_info[] = { { EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" }, - { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" }, - { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" }, + { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" }, + { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" }, + { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" }, { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, }; @@ -61,7 +66,7 @@ static int odroid_get_board_type(void) goto rev_default; for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { - /* ADC tolerance: +20 % */ + /* ADC tolerance: +1% */ if (adcval < odroid_info[i].adc_val) return odroid_info[i].board_type; } @@ -132,6 +137,14 @@ bool board_is_odroidxu4(void) return false; } +bool board_is_odroidhc1(void) +{ + if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01) + return true; + + return false; +} + bool board_is_generic(void) { if (gd->board_type == EXYNOS5_BOARD_GENERIC) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 0d17f30712..a4eb351405 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -176,7 +176,7 @@ char *get_dfu_alt_system(char *interface, char *devstr) { char *info = "Not supported!"; - if (board_is_odroidxu4()) + if (board_is_odroidxu4() || board_is_odroidhc1()) return info; return env_get("dfu_alt_system"); @@ -189,7 +189,7 @@ char *get_dfu_alt_boot(char *interface, char *devstr) char *alt_boot; int dev_num; - if (board_is_odroidxu4()) + if (board_is_odroidxu4() || board_is_odroidhc1()) return info; dev_num = simple_strtoul(devstr, NULL, 10); |