diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/logicpd/omap3som/README | 43 | ||||
| -rw-r--r-- | board/logicpd/omap3som/omap3logic.c | 55 | ||||
| -rw-r--r-- | board/samsung/common/exynos5-dt-types.c | 27 | ||||
| -rw-r--r-- | board/samsung/common/exynos5-dt.c | 4 | ||||
| -rw-r--r-- | board/synopsys/hsdk/hsdk.c | 12 |
5 files changed, 131 insertions, 10 deletions
diff --git a/board/logicpd/omap3som/README b/board/logicpd/omap3som/README index 06b3998ac0..b77b3d63db 100644 --- a/board/logicpd/omap3som/README +++ b/board/logicpd/omap3som/README @@ -17,3 +17,46 @@ This step is optional, but should you want to change the default to the SOM-LV, make distclean make omap3_logic_defconfig +Falcon Mode: FAT SD cards +========================= + +In this case the additional file is written to the filesystem. In this +example we assume that the uImage and device tree to be used are already on +the FAT filesystem (only the uImage MUST be for this to function +afterwards) along with a Falcon Mode aware MLO and the FAT partition has +already been created and marked bootable: + +U-Boot # mmc rescan +# Load kernel and device tree into memory, perform export +U-Boot # fatload mmc 0 ${loadaddr} uImage +U-Boot # run loadfdt +U-Boot # setenv optargs quiet +U-Boot # run mmcargs +U-Boot # run common_bootargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} + +This will print a number of lines and then end with something like: + Loading Device Tree to 8dec9000, end 8dee0295 ... OK + +So then note the starting address and write the args to mmc/sd: + +U-Boot # fatwrite mmc 0:1 0x8dec9000 args 0x20000 + +The size of 0x20000 matches the CMD_SPL_WRITE_SIZE. + +Falcon Mode: NAND +================= + +In this case the additional data is written to another partition of the +NAND. In this example we assume that the uImage and device tree to be are +already located on the NAND somewhere (such as filesystem or mtd partition) +along with a Falcon Mode aware MLO written to the correct locations for +booting and mtdparts have been configured correctly for the board: + +U-Boot # nand read ${loadaddr} kernel +U-Boot # load nand rootfs ${fdtaddr} /boot/am335x-evm.dtb +U-Boot # run nandargs +U-Boot # run common_bootargs +U-Boot # spl export fdt ${loadaddr} - ${fdtaddr} +U-Boot # nand erase.part u-boot-spl-os +U-Boot # nand write ${fdtaddr} u-boot-spl-os diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index a55a520e63..b30fa24a32 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -114,6 +114,47 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; } + +#define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c) +#define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE + 0x84) +#define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE + 0x80) + +void spl_board_prepare_for_linux(void) +{ + /* The Micron NAND starts locked which + * prohibits mounting the NAND as RW + * The following commands are what unlocks + * the NAND to become RW Falcon Mode does not + * have as many smarts as U-Boot, but Logic PD + * only makes NAND with 512MB so these hard coded + * values should work for all current models + */ + + writeb(0x70, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x7a, GPMC_NAND_COMMAND_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_COMMAND_0); + + /* Begin address 0 */ + writeb(NAND_CMD_UNLOCK1, 0x6e00007c); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(0x00, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + + /* Ending address at the end of Flash */ + writeb(NAND_CMD_UNLOCK2, GPMC_NAND_COMMAND_0); + writeb(0xc0, GPMC_NAND_ADDRESS_0); + writeb(0xff, GPMC_NAND_ADDRESS_0); + writeb(0x03, GPMC_NAND_ADDRESS_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(0x79, GPMC_NAND_COMMAND_0); + writeb(-1, GPMC_NAND_DATA_0); + writeb(-1, GPMC_NAND_DATA_0); +} #endif #ifdef CONFIG_USB_MUSB_OMAP2PLUS @@ -207,6 +248,16 @@ int board_init(void) } #ifdef CONFIG_BOARD_LATE_INIT + +static void unlock_nand(void) +{ + int dev = nand_curr_device; + struct mtd_info *mtd; + + mtd = get_nand_dev_by_index(dev); + nand_unlock(mtd, 0, mtd->size, 0); +} + int board_late_init(void) { struct board_id *board; @@ -256,6 +307,10 @@ int board_late_init(void) /* restore hsusb0_data5 pin as hsusb0_data5 */ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); + +#ifdef CONFIG_CMD_NAND_LOCK_UNLOCK + unlock_nand(); +#endif return 0; } #endif diff --git a/board/samsung/common/exynos5-dt-types.c b/board/samsung/common/exynos5-dt-types.c index 48fd1f7d96..03d3a3112a 100644 --- a/board/samsung/common/exynos5-dt-types.c +++ b/board/samsung/common/exynos5-dt-types.c @@ -25,17 +25,22 @@ static const struct udevice_id board_ids[] = { }; /** - * Odroix XU3/4 board revisions: + * Odroix XU3/XU4/HC1 board revisions (from HC1_MAIN_REV0.1_20170630.pdf): * Rev ADCmax Board * 0.1 0 XU3 0.1 - * 0.2 410 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) - * 0.3 1408 XU4 0.1 - * Use +10 % for ADC value tolerance. + * 0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT (probe I2C0:0x40 / INA231) + * 0.3 1280 XU4 0.1 + * 0.4 739 XU4 0.2 + * 0.5 1016 XU4+Air0.1 (Passive cooling) + * 0.6 1308 XU4S 0.1 (HC1) + * Use +1% for ADC value tolerance in the array below, the code loops until + * the measured ADC value is lower than then ADCmax from the array. */ struct odroid_rev_info odroid_info[] = { { EXYNOS5_BOARD_ODROID_XU3_REV01, 1, 10, "xu3" }, - { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 410, "xu3" }, - { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1408, "xu4" }, + { EXYNOS5_BOARD_ODROID_XU3_REV02, 2, 375, "xu3" }, + { EXYNOS5_BOARD_ODROID_XU4_REV01, 1, 1293, "xu4" }, + { EXYNOS5_BOARD_ODROID_HC1_REV01, 1, 1321, "hc1" }, { EXYNOS5_BOARD_ODROID_UNKNOWN, 0, 4095, "unknown" }, }; @@ -61,7 +66,7 @@ static int odroid_get_board_type(void) goto rev_default; for (i = 0; i < ARRAY_SIZE(odroid_info); i++) { - /* ADC tolerance: +20 % */ + /* ADC tolerance: +1% */ if (adcval < odroid_info[i].adc_val) return odroid_info[i].board_type; } @@ -132,6 +137,14 @@ bool board_is_odroidxu4(void) return false; } +bool board_is_odroidhc1(void) +{ + if (gd->board_type == EXYNOS5_BOARD_ODROID_HC1_REV01) + return true; + + return false; +} + bool board_is_generic(void) { if (gd->board_type == EXYNOS5_BOARD_GENERIC) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 0d17f30712..a4eb351405 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -176,7 +176,7 @@ char *get_dfu_alt_system(char *interface, char *devstr) { char *info = "Not supported!"; - if (board_is_odroidxu4()) + if (board_is_odroidxu4() || board_is_odroidhc1()) return info; return env_get("dfu_alt_system"); @@ -189,7 +189,7 @@ char *get_dfu_alt_boot(char *interface, char *devstr) char *alt_boot; int dev_num; - if (board_is_odroidxu4()) + if (board_is_odroidxu4() || board_is_odroidhc1()) return info; dev_num = simple_strtoul(devstr, NULL, 10); diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 7b562556e6..7641978a7b 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -26,6 +26,10 @@ int board_early_init_f(void) return 0; } +#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000) +#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108) +#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30) + int board_mmc_init(bd_t *bis) { struct dwmci_host *host = NULL; @@ -36,12 +40,18 @@ int board_mmc_init(bd_t *bis) return 1; } + /* + * Switch SDIO external ciu clock divider from default div-by-8 to + * minimum possible div-by-2. + */ + writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *) SDIO_UHS_REG_EXT); + memset(host, 0, sizeof(struct dwmci_host)); host->name = "Synopsys Mobile storage"; host->ioaddr = (void *)ARC_DWMMC_BASE; host->buswidth = 4; host->dev_index = 0; - host->bus_hz = 100000000; + host->bus_hz = 50000000; add_dwmci(host, host->bus_hz / 2, 400000); |