diff options
Diffstat (limited to 'drivers/clk/renesas/r8a779a0-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a779a0-cpg-mssr.c | 20 |
1 files changed, 9 insertions, 11 deletions
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index a9c941b6db..6b7ec36ab0 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -232,11 +232,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { /* * CPG Clock Data */ - /* * MD EXTAL PLL1 PLL20 PLL30 PLL4 PLL5 OSC * 14 13 (MHz) 21 31 - * -------------------------------------------------------- + * ---------------------------------------------------------------- * 0 0 16.66 x 1 x128 x216 x128 x144 x192 /16 * 0 1 20 x 1 x106 x180 x106 x120 x160 /19 * 1 0 Prohibited setting @@ -244,13 +243,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { */ #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ (((md) & BIT(13)) >> 13)) - -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = { - /* EXTAL div PLL1 mult/div Not used OSC prediv PLL5 mult/div */ - { 1, 128, 1, 128, 1, 16, 192, 1, }, - { 1, 106, 1, 106, 1, 19, 160, 1, }, - { 0, 0, 0, 0, 0, 0, 0, 0, }, - { 2, 128, 1, 128, 1, 32, 192, 1, }, +static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = { + /* EXTAL div PLL1 mult/div PLL2 mult/div PLL3 mult/div PLL4 mult/div PLL5 mult/div PLL6 mult/div OSC prediv */ + { 1, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 16, }, + { 1, 106, 1, 0, 0, 0, 0, 120, 1, 160, 1, 0, 0, 19, }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, + { 2, 128, 1, 0, 0, 0, 0, 144, 1, 192, 1, 0, 0, 32, }, }; /* @@ -292,13 +290,13 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = { .mstp_table = r8a779a0_mstp_table, .mstp_table_size = ARRAY_SIZE(r8a779a0_mstp_table), .reset_node = "renesas,r8a779a0-rst", - .reset_modemr_offset = 0x00, + .reset_modemr_offset = CPG_RST_MODEMR0, .extalr_node = "extalr", .mod_clk_base = MOD_CLK_BASE, .clk_extal_id = CLK_EXTAL, .clk_extalr_id = CLK_EXTALR, .get_pll_config = r8a779a0_get_pll_config, - .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, + .reg_layout = CLK_REG_LAYOUT_RCAR_GEN4, }; static const struct udevice_id r8a779a0_cpg_ids[] = { |