diff options
Diffstat (limited to 'drivers/ddr/marvell/a38x/ddr3_training_ip.h')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_ip.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_ip.h b/drivers/ddr/marvell/a38x/ddr3_training_ip.h index 0102e69194..531103c1ab 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_ip.h +++ b/drivers/ddr/marvell/a38x/ddr3_training_ip.h @@ -10,11 +10,10 @@ #include "ddr_topology_def.h" #include "ddr_training_ip_db.h" -#define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29." - #define MAX_CS_NUM 4 #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM) -#define MAX_DQ_NUM 40 +#define TIP_ENG_LOCK 0x02000000 +#define TIP_TX_DLL_RANGE_MAX 64 #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2) #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1) @@ -38,11 +37,15 @@ #define READ_LEVELING_TF_MASK_BIT 0x00010000 #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000 #define DM_PBS_TX_MASK_BIT 0x00040000 +#define RL_DQS_BURST_MASK_BIT 0x00080000 #define CENTRALIZATION_RX_MASK_BIT 0x00100000 #define CENTRALIZATION_TX_MASK_BIT 0x00200000 #define TX_EMPHASIS_MASK_BIT 0x00400000 #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000 #define VREF_CALIBRATION_MASK_BIT 0x01000000 +#define WRITE_LEVELING_LF_MASK_BIT 0x02000000 + +/* DDR4 Specific Training Mask bits */ enum hws_result { TEST_FAILED = 0, @@ -79,6 +82,7 @@ enum auto_tune_stage { TX_EMPHASIS, LOAD_PATTERN_HIGH, PER_BIT_READ_LEVELING_TF, + WRITE_LEVELING_LF, MAX_STAGE_LIMIT }; @@ -110,7 +114,7 @@ struct pattern_info { /* CL value for each frequency */ struct cl_val_per_freq { - u8 cl_val[DDR_FREQ_LIMIT]; + u8 cl_val[DDR_FREQ_LAST]; }; struct cs_element { @@ -167,11 +171,14 @@ int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable); int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm); int hws_ddr3_tip_load_topology_map(u32 dev_num, - struct hws_topology_map *topology); + struct mv_ddr_topology_map *topology); int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type); int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info); +int hws_ddr3_tip_read_training_result(u32 dev_num, + enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]); int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode); u8 ddr3_tip_get_buf_min(u8 *buf_ptr); u8 ddr3_tip_get_buf_max(u8 *buf_ptr); - +uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void); +uint64_t mv_ddr_get_total_memory_size_in_bits(void); #endif /* _DDR3_TRAINING_IP_H_ */ |