summaryrefslogtreecommitdiff
path: root/drivers/pinctrl
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig20
-rw-r--r--drivers/pinctrl/Makefile1
-rw-r--r--drivers/pinctrl/aspeed/Makefile1
-rw-r--r--drivers/pinctrl/aspeed/pinctrl_ast2600.c459
-rw-r--r--drivers/pinctrl/pinctrl-apple.c207
5 files changed, 688 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 30eaa376c8..03946245c7 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -145,6 +145,17 @@ config SPL_PINCONF_RECURSIVE
if PINCTRL || SPL_PINCTRL
+config PINCTRL_APPLE
+ bool "Apple pinctrl driver"
+ depends on DM && PINCTRL_GENERIC && ARCH_APPLE
+ default y
+ help
+ Support pin multiplexing on Apple SoCs.
+
+ The driver is controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
+
config PINCTRL_AR933X
bool "QCA/Athores ar933x pin control driver"
depends on DM && SOC_AR933X
@@ -291,6 +302,15 @@ config ASPEED_AST2500_PINCTRL
uses Generic Pinctrl framework and is compatible with the Linux
driver, i.e. it uses the same device tree configuration.
+config ASPEED_AST2600_PINCTRL
+ bool "Aspeed AST2600 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2600
+ default y
+ help
+ Support pin multiplexing control on Aspeed ast2600 SoC. The driver
+ uses Generic Pinctrl framework and is compatible with the Linux
+ driver, i.e. it uses the same device tree configuration.
+
config PINCTRL_K210
bool "Kendryte K210 Fully-Programmable Input/Output Array driver"
depends on DM && PINCTRL_GENERIC
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 05b71f2f13..fd736a7f64 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -3,6 +3,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
obj-y += nxp/
diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile
index 2e6ed604c8..a3e01ed1ca 100644
--- a/drivers/pinctrl/aspeed/Makefile
+++ b/drivers/pinctrl/aspeed/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ASPEED_AST2500_PINCTRL) += pinctrl_ast2500.o
+obj-$(CONFIG_ASPEED_AST2600_PINCTRL) += pinctrl_ast2600.o
diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
new file mode 100644
index 0000000000..12cba83f6c
--- /dev/null
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c
@@ -0,0 +1,459 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/pinctrl.h>
+#include <asm/arch/scu_ast2600.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+/*
+ * This driver works with very simple configuration that has the same name
+ * for group and function. This way it is compatible with the Linux Kernel
+ * driver.
+ */
+struct aspeed_sig_desc {
+ u32 offset;
+ u32 reg_set;
+ int clr;
+};
+
+struct aspeed_group_config {
+ char *group_name;
+ int ndescs;
+ struct aspeed_sig_desc *descs;
+};
+
+struct ast2600_pinctrl_priv {
+ struct ast2600_scu *scu;
+};
+
+static int ast2600_pinctrl_probe(struct udevice *dev)
+{
+ struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
+ struct udevice *clk_dev;
+ int ret = 0;
+
+ /* find SCU base address from clock device */
+ uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(aspeed_ast2600_scu), &clk_dev);
+
+ if (ret)
+ return ret;
+
+ priv->scu = dev_read_addr_ptr(clk_dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
+
+ return 0;
+}
+
+static struct aspeed_sig_desc i2c1_link[] = {
+ { 0x418, GENMASK(9, 8), 1 },
+ { 0x4B8, GENMASK(9, 8), 0 },
+};
+
+static struct aspeed_sig_desc i2c2_link[] = {
+ { 0x418, GENMASK(11, 10), 1 },
+ { 0x4B8, GENMASK(11, 10), 0 },
+};
+
+static struct aspeed_sig_desc i2c3_link[] = {
+ { 0x418, GENMASK(13, 12), 1 },
+ { 0x4B8, GENMASK(13, 12), 0 },
+};
+
+static struct aspeed_sig_desc i2c4_link[] = {
+ { 0x418, GENMASK(15, 14), 1 },
+ { 0x4B8, GENMASK(15, 14), 0 },
+};
+
+static struct aspeed_sig_desc i2c5_link[] = {
+ { 0x418, GENMASK(17, 16), 0 },
+};
+
+static struct aspeed_sig_desc i2c6_link[] = {
+ { 0x418, GENMASK(19, 18), 0 },
+};
+
+static struct aspeed_sig_desc i2c7_link[] = {
+ { 0x418, GENMASK(21, 20), 0 },
+};
+
+static struct aspeed_sig_desc i2c8_link[] = {
+ { 0x418, GENMASK(23, 22), 0 },
+};
+
+static struct aspeed_sig_desc i2c9_link[] = {
+ { 0x418, GENMASK(25, 24), 0 },
+};
+
+static struct aspeed_sig_desc i2c10_link[] = {
+ { 0x418, GENMASK(27, 26), 0 },
+};
+
+static struct aspeed_sig_desc i2c11_link[] = {
+ { 0x410, GENMASK(1, 0), 1 },
+ { 0x4B0, GENMASK(1, 0), 0 },
+};
+
+static struct aspeed_sig_desc i2c12_link[] = {
+ { 0x410, GENMASK(3, 2), 1 },
+ { 0x4B0, GENMASK(3, 2), 0 },
+};
+
+static struct aspeed_sig_desc i2c13_link[] = {
+ { 0x410, GENMASK(5, 4), 1 },
+ { 0x4B0, GENMASK(5, 4), 0 },
+};
+
+static struct aspeed_sig_desc i2c14_link[] = {
+ { 0x410, GENMASK(7, 6), 1 },
+ { 0x4B0, GENMASK(7, 6), 0 },
+};
+
+static struct aspeed_sig_desc i2c15_link[] = {
+ { 0x414, GENMASK(29, 28), 1 },
+ { 0x4B4, GENMASK(29, 28), 0 },
+};
+
+static struct aspeed_sig_desc i2c16_link[] = {
+ { 0x414, GENMASK(31, 30), 1 },
+ { 0x4B4, GENMASK(31, 30), 0 },
+};
+
+static struct aspeed_sig_desc mac1_link[] = {
+ { 0x410, BIT(4), 0 },
+ { 0x470, BIT(4), 1 },
+};
+
+static struct aspeed_sig_desc mac2_link[] = {
+ { 0x410, BIT(5), 0 },
+ { 0x470, BIT(5), 1 },
+};
+
+static struct aspeed_sig_desc mac3_link[] = {
+ { 0x410, BIT(6), 0 },
+ { 0x470, BIT(6), 1 },
+};
+
+static struct aspeed_sig_desc mac4_link[] = {
+ { 0x410, BIT(7), 0 },
+ { 0x470, BIT(7), 1 },
+};
+
+static struct aspeed_sig_desc rgmii1[] = {
+ { 0x500, BIT(6), 0 },
+ { 0x400, GENMASK(11, 0), 0 },
+};
+
+static struct aspeed_sig_desc rgmii2[] = {
+ { 0x500, BIT(7), 0 },
+ { 0x400, GENMASK(23, 12), 0 },
+};
+
+static struct aspeed_sig_desc rgmii3[] = {
+ { 0x510, BIT(0), 0 },
+ { 0x410, GENMASK(27, 16), 0 },
+};
+
+static struct aspeed_sig_desc rgmii4[] = {
+ { 0x510, BIT(1), 0 },
+ { 0x410, GENMASK(31, 28), 1 },
+ { 0x4b0, GENMASK(31, 28), 0 },
+ { 0x474, GENMASK(7, 0), 1 },
+ { 0x414, GENMASK(7, 0), 1 },
+ { 0x4b4, GENMASK(7, 0), 0 },
+};
+
+static struct aspeed_sig_desc rmii1[] = {
+ { 0x504, BIT(6), 0 },
+ { 0x400, GENMASK(3, 0), 0 },
+ { 0x400, GENMASK(11, 6), 0 },
+};
+
+static struct aspeed_sig_desc rmii2[] = {
+ { 0x504, BIT(7), 0 },
+ { 0x400, GENMASK(15, 12), 0 },
+ { 0x400, GENMASK(23, 18), 0 },
+};
+
+static struct aspeed_sig_desc rmii3[] = {
+ { 0x514, BIT(0), 0 },
+ { 0x410, GENMASK(27, 22), 0 },
+ { 0x410, GENMASK(19, 16), 0 },
+};
+
+static struct aspeed_sig_desc rmii4[] = {
+ { 0x514, BIT(1), 0 },
+ { 0x410, GENMASK(7, 2), 1 },
+ { 0x410, GENMASK(31, 28), 1 },
+ { 0x414, GENMASK(7, 2), 1 },
+ { 0x4B0, GENMASK(31, 28), 0 },
+ { 0x4B4, GENMASK(7, 2), 0 },
+};
+
+static struct aspeed_sig_desc rmii1_rclk_oe[] = {
+ { 0x340, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc rmii2_rclk_oe[] = {
+ { 0x340, BIT(30), 0 },
+};
+
+static struct aspeed_sig_desc rmii3_rclk_oe[] = {
+ { 0x350, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc rmii4_rclk_oe[] = {
+ { 0x350, BIT(30), 0 },
+};
+
+static struct aspeed_sig_desc mdio1_link[] = {
+ { 0x430, BIT(17) | BIT(16), 0 },
+};
+
+static struct aspeed_sig_desc mdio2_link[] = {
+ { 0x470, BIT(13) | BIT(12), 1 },
+ { 0x410, BIT(13) | BIT(12), 0 },
+};
+
+static struct aspeed_sig_desc mdio3_link[] = {
+ { 0x470, BIT(1) | BIT(0), 1 },
+ { 0x410, BIT(1) | BIT(0), 0 },
+};
+
+static struct aspeed_sig_desc mdio4_link[] = {
+ { 0x470, BIT(3) | BIT(2), 1 },
+ { 0x410, BIT(3) | BIT(2), 0 },
+};
+
+static struct aspeed_sig_desc sdio2_link[] = {
+ { 0x414, GENMASK(23, 16), 1 },
+ { 0x4B4, GENMASK(23, 16), 0 },
+ { 0x450, BIT(1), 0 },
+};
+
+static struct aspeed_sig_desc sdio1_link[] = {
+ { 0x414, GENMASK(15, 8), 0 },
+};
+
+/* when sdio1 8bits, sdio2 can't use */
+static struct aspeed_sig_desc sdio1_8bit_link[] = {
+ { 0x414, GENMASK(15, 8), 0 },
+ { 0x4b4, GENMASK(21, 18), 0 },
+ { 0x450, BIT(3), 0 },
+ { 0x450, BIT(1), 1 },
+};
+
+static struct aspeed_sig_desc emmc_link[] = {
+ { 0x400, GENMASK(31, 24), 0 },
+};
+
+static struct aspeed_sig_desc emmcg8_link[] = {
+ { 0x400, GENMASK(31, 24), 0 },
+ { 0x404, GENMASK(3, 0), 0 },
+/* set SCU504 to clear the strap bits in SCU500 */
+ { 0x504, BIT(3), 0 },
+ { 0x504, BIT(5), 0 },
+};
+
+static struct aspeed_sig_desc fmcquad_link[] = {
+ { 0x438, GENMASK(5, 4), 0 },
+};
+
+static struct aspeed_sig_desc spi1_link[] = {
+ { 0x438, GENMASK(13, 11), 0 },
+};
+
+static struct aspeed_sig_desc spi1abr_link[] = {
+ { 0x438, BIT(9), 0 },
+};
+
+static struct aspeed_sig_desc spi1cs1_link[] = {
+ { 0x438, BIT(8), 0 },
+};
+
+static struct aspeed_sig_desc spi1wp_link[] = {
+ { 0x438, BIT(10), 0 },
+};
+
+static struct aspeed_sig_desc spi1quad_link[] = {
+ { 0x438, GENMASK(15, 14), 0 },
+};
+
+static struct aspeed_sig_desc spi2_link[] = {
+ { 0x434, GENMASK(29, 27) | BIT(24), 0 },
+};
+
+static struct aspeed_sig_desc spi2cs1_link[] = {
+ { 0x434, BIT(25), 0 },
+};
+
+static struct aspeed_sig_desc spi2cs2_link[] = {
+ { 0x434, BIT(26), 0 },
+};
+
+static struct aspeed_sig_desc spi2quad_link[] = {
+ { 0x434, GENMASK(31, 30), 0 },
+};
+
+static struct aspeed_sig_desc fsi1[] = {
+ { 0xd48, GENMASK(21, 20), 0 },
+};
+
+static struct aspeed_sig_desc fsi2[] = {
+ { 0xd48, GENMASK(23, 22), 0 },
+};
+
+static struct aspeed_sig_desc usb2ad_link[] = {
+ { 0x440, BIT(24), 0 },
+ { 0x440, BIT(25), 1 },
+};
+
+static struct aspeed_sig_desc usb2ah_link[] = {
+ { 0x440, BIT(24), 1 },
+ { 0x440, BIT(25), 0 },
+};
+
+static struct aspeed_sig_desc usb2bh_link[] = {
+ { 0x440, BIT(28), 1 },
+ { 0x440, BIT(29), 0 },
+};
+
+static struct aspeed_sig_desc pcie0rc_link[] = {
+ { 0x40, BIT(21), 0 },
+};
+
+static struct aspeed_sig_desc pcie1rc_link[] = {
+ { 0x40, BIT(19), 0 }, /* SSPRST# output enable */
+ { 0x500, BIT(24), 0 }, /* dedicate rc reset */
+};
+
+static const struct aspeed_group_config ast2600_groups[] = {
+ { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link },
+ { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link },
+ { "MAC3LINK", ARRAY_SIZE(mac3_link), mac3_link },
+ { "MAC4LINK", ARRAY_SIZE(mac4_link), mac4_link },
+ { "RGMII1", ARRAY_SIZE(rgmii1), rgmii1 },
+ { "RGMII2", ARRAY_SIZE(rgmii2), rgmii2 },
+ { "RGMII3", ARRAY_SIZE(rgmii3), rgmii3 },
+ { "RGMII4", ARRAY_SIZE(rgmii4), rgmii4 },
+ { "RMII1", ARRAY_SIZE(rmii1), rmii1 },
+ { "RMII2", ARRAY_SIZE(rmii2), rmii2 },
+ { "RMII3", ARRAY_SIZE(rmii3), rmii3 },
+ { "RMII4", ARRAY_SIZE(rmii4), rmii4 },
+ { "RMII1RCLK", ARRAY_SIZE(rmii1_rclk_oe), rmii1_rclk_oe },
+ { "RMII2RCLK", ARRAY_SIZE(rmii2_rclk_oe), rmii2_rclk_oe },
+ { "RMII3RCLK", ARRAY_SIZE(rmii3_rclk_oe), rmii3_rclk_oe },
+ { "RMII4RCLK", ARRAY_SIZE(rmii4_rclk_oe), rmii4_rclk_oe },
+ { "MDIO1", ARRAY_SIZE(mdio1_link), mdio1_link },
+ { "MDIO2", ARRAY_SIZE(mdio2_link), mdio2_link },
+ { "MDIO3", ARRAY_SIZE(mdio3_link), mdio3_link },
+ { "MDIO4", ARRAY_SIZE(mdio4_link), mdio4_link },
+ { "SD1", ARRAY_SIZE(sdio1_link), sdio1_link },
+ { "SD1_8bits", ARRAY_SIZE(sdio1_8bit_link), sdio1_8bit_link },
+ { "SD2", ARRAY_SIZE(sdio2_link), sdio2_link },
+ { "EMMC", ARRAY_SIZE(emmc_link), emmc_link },
+ { "EMMCG8", ARRAY_SIZE(emmcg8_link), emmcg8_link },
+ { "FMCQUAD", ARRAY_SIZE(fmcquad_link), fmcquad_link },
+ { "SPI1", ARRAY_SIZE(spi1_link), spi1_link },
+ { "SPI1ABR", ARRAY_SIZE(spi1abr_link), spi1abr_link },
+ { "SPI1CS1", ARRAY_SIZE(spi1cs1_link), spi1cs1_link },
+ { "SPI1WP", ARRAY_SIZE(spi1wp_link), spi1wp_link },
+ { "SPI1QUAD", ARRAY_SIZE(spi1quad_link), spi1quad_link },
+ { "SPI2", ARRAY_SIZE(spi2_link), spi2_link },
+ { "SPI2CS1", ARRAY_SIZE(spi2cs1_link), spi2cs1_link },
+ { "SPI2CS2", ARRAY_SIZE(spi2cs2_link), spi2cs2_link },
+ { "SPI2QUAD", ARRAY_SIZE(spi2quad_link), spi2quad_link },
+ { "I2C1", ARRAY_SIZE(i2c1_link), i2c1_link },
+ { "I2C2", ARRAY_SIZE(i2c2_link), i2c2_link },
+ { "I2C3", ARRAY_SIZE(i2c3_link), i2c3_link },
+ { "I2C4", ARRAY_SIZE(i2c4_link), i2c4_link },
+ { "I2C5", ARRAY_SIZE(i2c5_link), i2c5_link },
+ { "I2C6", ARRAY_SIZE(i2c6_link), i2c6_link },
+ { "I2C7", ARRAY_SIZE(i2c7_link), i2c7_link },
+ { "I2C8", ARRAY_SIZE(i2c8_link), i2c8_link },
+ { "I2C9", ARRAY_SIZE(i2c9_link), i2c9_link },
+ { "I2C10", ARRAY_SIZE(i2c10_link), i2c10_link },
+ { "I2C11", ARRAY_SIZE(i2c11_link), i2c11_link },
+ { "I2C12", ARRAY_SIZE(i2c12_link), i2c12_link },
+ { "I2C13", ARRAY_SIZE(i2c13_link), i2c13_link },
+ { "I2C14", ARRAY_SIZE(i2c14_link), i2c14_link },
+ { "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link },
+ { "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link },
+ { "FSI1", ARRAY_SIZE(fsi1), fsi1 },
+ { "FSI2", ARRAY_SIZE(fsi2), fsi2 },
+ { "USB2AD", ARRAY_SIZE(usb2ad_link), usb2ad_link },
+ { "USB2AH", ARRAY_SIZE(usb2ah_link), usb2ah_link },
+ { "USB2BH", ARRAY_SIZE(usb2bh_link), usb2bh_link },
+ { "PCIE0RC", ARRAY_SIZE(pcie0rc_link), pcie0rc_link },
+ { "PCIE1RC", ARRAY_SIZE(pcie1rc_link), pcie1rc_link },
+};
+
+static int ast2600_pinctrl_get_groups_count(struct udevice *dev)
+{
+ debug("PINCTRL: get_(functions/groups)_count\n");
+
+ return ARRAY_SIZE(ast2600_groups);
+}
+
+static const char *ast2600_pinctrl_get_group_name(struct udevice *dev,
+ unsigned selector)
+{
+ debug("PINCTRL: get_(function/group)_name %u\n", selector);
+
+ return ast2600_groups[selector].group_name;
+}
+
+static int ast2600_pinctrl_group_set(struct udevice *dev, unsigned selector, unsigned func_selector)
+{
+ struct ast2600_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct aspeed_group_config *config;
+ const struct aspeed_sig_desc *descs;
+ u32 ctrl_reg = (u32)priv->scu;
+ u32 i;
+
+ debug("PINCTRL: group_set <%u, %u>\n", selector, func_selector);
+ if (selector >= ARRAY_SIZE(ast2600_groups))
+ return -EINVAL;
+
+ config = &ast2600_groups[selector];
+ for (i = 0; i < config->ndescs; i++) {
+ descs = &config->descs[i];
+ if (descs->clr)
+ clrbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set);
+ else
+ setbits_le32((u32)ctrl_reg + descs->offset, descs->reg_set);
+ }
+
+ return 0;
+}
+
+static struct pinctrl_ops ast2600_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_groups_count = ast2600_pinctrl_get_groups_count,
+ .get_group_name = ast2600_pinctrl_get_group_name,
+ .get_functions_count = ast2600_pinctrl_get_groups_count,
+ .get_function_name = ast2600_pinctrl_get_group_name,
+ .pinmux_group_set = ast2600_pinctrl_group_set,
+};
+
+static const struct udevice_id ast2600_pinctrl_ids[] = {
+ { .compatible = "aspeed,g6-pinctrl" },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_aspeed) = {
+ .name = "aspeed_ast2600_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = ast2600_pinctrl_ids,
+ .priv_auto = sizeof(struct ast2600_pinctrl_priv),
+ .ops = &ast2600_pinctrl_ops,
+ .probe = ast2600_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/pinctrl-apple.c b/drivers/pinctrl/pinctrl-apple.c
new file mode 100644
index 0000000000..62476358c3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-apple.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Mark Kettenis <kettenis@openbsd.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/pinctrl/apple.h>
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <linux/bitfield.h>
+
+struct apple_pinctrl_priv {
+ void *base;
+ int pin_count;
+};
+
+#define REG_GPIO(x) (4 * (x))
+#define REG_GPIO_DATA BIT(0)
+#define REG_GPIO_MODE GENMASK(3, 1)
+#define REG_GPIO_OUT 1
+#define REG_GPIO_PERIPH GENMASK(6, 5)
+#define REG_GPIO_INPUT_ENABLE BIT(9)
+
+static void apple_pinctrl_config_pin(struct apple_pinctrl_priv *priv,
+ unsigned pin, u32 clr, u32 set)
+{
+ unsigned reg = REG_GPIO(pin);
+ u32 old, new;
+
+ old = readl(priv->base + REG_GPIO(pin));
+ new = (old & ~clr) | set;
+ writel(new, priv->base + reg);
+}
+
+static int apple_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ return !!(readl(priv->base + REG_GPIO(offset)) & REG_GPIO_DATA);
+}
+
+static int apple_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ apple_pinctrl_config_pin(priv, offset, REG_GPIO_DATA,
+ value ? REG_GPIO_DATA : 0);
+ return 0;
+}
+
+static int apple_gpio_get_direction(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ u32 reg = readl(priv->base + REG_GPIO(offset));
+
+ if (FIELD_GET(REG_GPIO_MODE, reg) == REG_GPIO_OUT)
+ return GPIOF_OUTPUT;
+ else
+ return GPIOF_INPUT;
+}
+
+static int apple_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ apple_pinctrl_config_pin(priv, offset,
+ REG_GPIO_PERIPH | REG_GPIO_MODE,
+ REG_GPIO_INPUT_ENABLE);
+ return 0;
+}
+
+static int apple_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ u32 set = (value ? REG_GPIO_DATA : 0);
+
+ apple_pinctrl_config_pin(priv, offset, REG_GPIO_DATA |
+ REG_GPIO_PERIPH | REG_GPIO_MODE,
+ set | FIELD_PREP(REG_GPIO_MODE, REG_GPIO_OUT));
+ return 0;
+}
+
+static int apple_gpio_probe(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev->parent);
+ struct gpio_dev_priv *uc_priv;
+
+ uc_priv = dev_get_uclass_priv(dev);
+ uc_priv->bank_name = "gpio";
+ uc_priv->gpio_count = priv->pin_count;
+
+ return 0;
+}
+
+static struct dm_gpio_ops apple_gpio_ops = {
+ .get_value = apple_gpio_get_value,
+ .set_value = apple_gpio_set_value,
+ .get_function = apple_gpio_get_direction,
+ .direction_input = apple_gpio_direction_input,
+ .direction_output = apple_gpio_direction_output,
+};
+
+static struct driver apple_gpio_driver = {
+ .name = "apple_gpio",
+ .id = UCLASS_GPIO,
+ .probe = apple_gpio_probe,
+ .ops = &apple_gpio_ops,
+};
+
+static int apple_pinctrl_get_pins_count(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ return priv->pin_count;
+}
+
+static const char *apple_pinctrl_get_pin_name(struct udevice *dev,
+ unsigned selector)
+{
+ static char pin_name[PINNAME_SIZE];
+
+ snprintf(pin_name, PINNAME_SIZE, "pin%d", selector);
+ return pin_name;
+}
+
+static int apple_pinctrl_get_pin_muxing(struct udevice *dev, unsigned selector,
+ char *buf, int size)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + REG_GPIO(selector)) & REG_GPIO_PERIPH)
+ strncpy(buf, "periph", size);
+ else
+ strncpy(buf, "gpio", size);
+ return 0;
+}
+
+static int apple_pinctrl_pinmux_set(struct udevice *dev, unsigned pin_selector,
+ unsigned func_selector)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+
+ apple_pinctrl_config_pin(priv, pin_selector,
+ REG_GPIO_DATA | REG_GPIO_MODE,
+ FIELD_PREP(REG_GPIO_PERIPH, func_selector) |
+ REG_GPIO_INPUT_ENABLE);
+ return 0;
+}
+
+static int apple_pinctrl_pinmux_property_set(struct udevice *dev,
+ u32 pinmux_group)
+{
+ unsigned pin_selector = APPLE_PIN(pinmux_group);
+ unsigned func_selector = APPLE_FUNC(pinmux_group);
+ int ret;
+
+ ret = apple_pinctrl_pinmux_set(dev, pin_selector, func_selector);
+ return ret ? ret : pin_selector;
+}
+
+static int apple_pinctrl_probe(struct udevice *dev)
+{
+ struct apple_pinctrl_priv *priv = dev_get_priv(dev);
+ struct ofnode_phandle_args args;
+ struct udevice *child;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -EINVAL;
+
+ if (!dev_read_phandle_with_args(dev, "gpio-ranges",
+ NULL, 3, 0, &args))
+ priv->pin_count = args.args[2];
+
+ device_bind(dev, &apple_gpio_driver, "apple_gpio", NULL,
+ dev_ofnode(dev), &child);
+
+ return 0;
+}
+
+static struct pinctrl_ops apple_pinctrl_ops = {
+ .set_state = pinctrl_generic_set_state,
+ .get_pins_count = apple_pinctrl_get_pins_count,
+ .get_pin_name = apple_pinctrl_get_pin_name,
+ .pinmux_set = apple_pinctrl_pinmux_set,
+ .pinmux_property_set = apple_pinctrl_pinmux_property_set,
+ .get_pin_muxing = apple_pinctrl_get_pin_muxing,
+};
+
+static const struct udevice_id apple_pinctrl_ids[] = {
+ { .compatible = "apple,pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_apple) = {
+ .name = "apple_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = apple_pinctrl_ids,
+ .priv_auto = sizeof(struct apple_pinctrl_priv),
+ .ops = &apple_pinctrl_ops,
+ .probe = apple_pinctrl_probe,
+};
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-05 09:40:40 +0300