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path: root/drivers/pwm/tegra_pwm.c
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Diffstat (limited to 'drivers/pwm/tegra_pwm.c')
-rw-r--r--drivers/pwm/tegra_pwm.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/pwm/tegra_pwm.c b/drivers/pwm/tegra_pwm.c
index 36c35c608b..95fc26458b 100644
--- a/drivers/pwm/tegra_pwm.c
+++ b/drivers/pwm/tegra_pwm.c
@@ -20,19 +20,21 @@ static int tegra_pwm_set_config(struct udevice *dev, uint channel,
{
struct tegra_pwm_priv *priv = dev_get_priv(dev);
struct pwm_ctlr *regs = priv->regs;
+ const u32 pwm_max_freq = dev_get_driver_data(dev);
uint pulse_width;
u32 reg;
if (channel >= 4)
return -EINVAL;
debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
- /* We ignore the period here and just use 32KHz */
- clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
+
+ clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_PERIPH, pwm_max_freq);
pulse_width = duty_ns * 255 / period_ns;
reg = pulse_width << PWM_WIDTH_SHIFT;
reg |= 1 << PWM_DIVIDER_SHIFT;
+ reg |= PWM_ENABLE_MASK;
writel(reg, &regs[channel].control);
debug("%s: pulse_width=%u\n", __func__, pulse_width);
@@ -68,8 +70,8 @@ static const struct pwm_ops tegra_pwm_ops = {
};
static const struct udevice_id tegra_pwm_ids[] = {
- { .compatible = "nvidia,tegra124-pwm" },
- { .compatible = "nvidia,tegra20-pwm" },
+ { .compatible = "nvidia,tegra20-pwm", .data = 48 * 1000000 },
+ { .compatible = "nvidia,tegra114-pwm", .data = 408 * 1000000 },
{ }
};