diff options
Diffstat (limited to 'drivers/ram/rockchip')
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3288.c | 10 | ||||
| -rw-r--r-- | drivers/ram/rockchip/sdram_rk3399.c | 10 |
2 files changed, 10 insertions, 10 deletions
diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index 3eb14cdb32..9f6f555147 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -17,7 +17,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3288.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/ddr_rk3288.h> #include <asm/arch-rockchip/grf_rk3288.h> #include <asm/arch-rockchip/pmu_rk3288.h> @@ -37,7 +37,7 @@ struct dram_info { struct chan_info chan[2]; struct ram_info info; struct clk ddr_clk; - struct rk3288_cru *cru; + struct rockchip_cru *cru; struct rk3288_grf *grf; struct rk3288_sgrf *sgrf; struct rk3288_pmu *pmu; @@ -93,7 +93,7 @@ static void copy_to_reg(u32 *dest, const u32 *src, u32 n) } } -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) +static void ddr_reset(struct rockchip_cru *cru, u32 ch, u32 ctl, u32 phy) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; u32 ctl_psrstn_shift = 3 + 5 * ch; @@ -110,7 +110,7 @@ static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) phy << phy_srstn_shift); } -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) +static void ddr_phy_ctl_reset(struct rockchip_cru *cru, u32 ch, u32 n) { u32 phy_ctl_srstn_shift = 4 + 5 * ch; @@ -118,7 +118,7 @@ static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); } -static void phy_pctrl_reset(struct rk3288_cru *cru, +static void phy_pctrl_reset(struct rockchip_cru *cru, struct rk3288_ddr_publ *publ, int channel) { diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index 9c276e13b2..d69ef01d08 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -14,7 +14,7 @@ #include <syscon.h> #include <asm/io.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> +#include <asm/arch-rockchip/cru.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/pmu_rk3399.h> #include <asm/arch-rockchip/hardware.h> @@ -66,7 +66,7 @@ struct dram_info { u32 pwrup_srefresh_exit[2]; struct chan_info chan[2]; struct clk ddr_clk; - struct rk3399_cru *cru; + struct rockchip_cru *cru; struct rk3399_grf_regs *grf; struct rk3399_pmu_regs *pmu; struct rk3399_pmucru *pmucru; @@ -228,7 +228,7 @@ static void *get_ddrc0_con(struct dram_info *dram, u8 channel) return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; } -static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, +static void rkclk_ddr_reset(struct rockchip_cru *cru, u32 channel, u32 ctl, u32 phy) { channel &= 0x1; @@ -239,7 +239,7 @@ static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, &cru->softrst_con[4]); } -static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel) +static void phy_pctrl_reset(struct rockchip_cru *cru, u32 channel) { rkclk_ddr_reset(cru, channel, 1, 1); udelay(10); @@ -2943,7 +2943,7 @@ static int sdram_init(struct dram_info *dram, for (channel = 0; channel < 2; channel++) { const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_cru *cru = dram->cru; + struct rockchip_cru *cru = dram->cru; struct rk3399_ddr_publ_regs *publ = chan->publ; phy_pctrl_reset(cru, channel); |