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path: root/drivers/ram/stm32mp1/stm32mp1_tuning.c
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Diffstat (limited to 'drivers/ram/stm32mp1/stm32mp1_tuning.c')
-rw-r--r--drivers/ram/stm32mp1/stm32mp1_tuning.c124
1 files changed, 63 insertions, 61 deletions
diff --git a/drivers/ram/stm32mp1/stm32mp1_tuning.c b/drivers/ram/stm32mp1/stm32mp1_tuning.c
index a8d6892bb0..c8cd7c3cea 100644
--- a/drivers/ram/stm32mp1/stm32mp1_tuning.c
+++ b/drivers/ram/stm32mp1/stm32mp1_tuning.c
@@ -2,6 +2,9 @@
/*
* Copyright (C) 2019, STMicroelectronics - All Rights Reserved
*/
+
+#define LOG_CATEGORY UCLASS_RAM
+
#include <common.h>
#include <console.h>
#include <clk.h>
@@ -227,8 +230,7 @@ static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
& DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
- pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
- __func__, addr, readl(addr), index);
+ log_debug("[%x]: %x => DQ unit index = %x\n", addr, readl(addr), index);
return index;
}
@@ -470,13 +472,13 @@ static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
for (bit_i = 0; bit_i < 8; bit_i++) {
set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
index = DQ_unit_index(phy, byte, bit_i);
- pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
- byte, bit_i, deskew_delay[byte][bit_i],
- index, index - 3);
+ log_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
+ byte, bit_i, deskew_delay[byte][bit_i],
+ index, index - 3);
printf("Byte %d, bit %d, DQ delay = %d",
byte, bit_i, deskew_delay[byte][bit_i]);
if (deskew_non_converge[byte][bit_i] == 1)
- pr_debug(" - not converged : still more skew");
+ log_debug(" - not converged : still more skew");
printf("\n");
}
}
@@ -536,7 +538,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/* Config the BIST block */
config_BIST(ctl, phy);
- pr_debug("BIST Config done.\n");
+ log_debug("BIST Config done.\n");
/* Train each byte */
for (datx8 = 0; datx8 < nb_bytes; datx8++) {
@@ -545,9 +547,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("\n======================\n");
- pr_debug("Start deskew byte %d .\n", datx8);
- pr_debug("======================\n");
+ log_debug("\n======================\n");
+ log_debug("Start deskew byte %d .\n", datx8);
+ log_debug("======================\n");
/* Enable Byte (DXNGCR, bit DXEN) */
setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
@@ -584,7 +586,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* Else, look for Pass init condition
*/
if (!success) {
- pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
+ log_debug("Fail at init condtion. Let's look for a good init condition.\n");
success = 0; /* init */
/* Make sure we start with a PASS condition before
* looking for a fail condition.
@@ -592,7 +594,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
/* escape if we find a PASS */
- pr_debug("increase Phase idx\n");
+ log_debug("increase Phase idx\n");
while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
DQS_phase_delay(phy, datx8, phase_idx);
BIST_test(phy, datx8, &result);
@@ -618,7 +620,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* we have hold violation, lets try reduce DQS_unit
* Delay
*/
- pr_debug("Still fail. Try decrease DQS Unit delay\n");
+ log_debug("Still fail. Try decrease DQS Unit delay\n");
phase_idx = 0;
dqs_unit_delay_index = 0;
@@ -665,9 +667,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
return TEST_FAILED;
}
- pr_debug("there is a pass region for phase idx %d\n",
- phase_idx);
- pr_debug("Step1: Find the first failing condition\n");
+ log_debug("there is a pass region for phase idx %d\n",
+ phase_idx);
+ log_debug("Step1: Find the first failing condition\n");
/* Look for the first failing condition by PHASE stepping.
* This part of the algo can finish without converging.
*/
@@ -692,9 +694,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* stepping (minimal delay)
*/
if (!success) {
- pr_debug("Fail region (PHASE) found phase idx %d\n",
- phase_idx);
- pr_debug("Let's look for first success by DQS Unit steps\n");
+ log_debug("Fail region (PHASE) found phase idx %d\n",
+ phase_idx);
+ log_debug("Let's look for first success by DQS Unit steps\n");
/* This part, the algo always converge */
phase_idx--;
@@ -721,7 +723,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
/*+1 to get back to current condition */
last_right_ok.unit = dqs_unit_delay_index + 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Found %d\n", dqs_unit_delay_index);
+ log_debug("Found %d\n", dqs_unit_delay_index);
} else {
/* the last OK condition is then with the
* previous phase_idx.
@@ -735,8 +737,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
last_right_ok.unit = 1;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Not Found : try previous phase %d\n",
- phase_idx - 1);
+ log_debug("Not Found : try previous phase %d\n",
+ phase_idx - 1);
DQS_phase_delay(phy, datx8, phase_idx - 1);
dqs_unit_delay_index = 0;
@@ -749,8 +751,8 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
BIST_test(phy, datx8, &result);
success = result.test_result;
dqs_unit_delay_index++;
- pr_debug("dqs_unit_delay_index = %d, result = %d\n",
- dqs_unit_delay_index, success);
+ log_debug("dqs_unit_delay_index = %d, result = %d\n",
+ dqs_unit_delay_index, success);
}
if (!success) {
@@ -758,7 +760,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index - 1;
} else {
last_right_ok.unit = 0;
- pr_debug("ERROR: failed region not FOUND");
+ log_debug("ERROR: failed region not FOUND");
}
}
} else {
@@ -775,7 +777,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
last_right_ok.phase = MAX_DQS_PHASE_IDX;
last_right_ok.unit = MAX_DQS_UNIT_IDX;
last_right_ok.bits_delay = 0xFFFFFFFF;
- pr_debug("Can't find the a fail condition\n");
+ log_debug("Can't find the a fail condition\n");
}
/* step 2:
@@ -787,9 +789,9 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
*/
printf("Byte %d, DQS unit = %d, phase = %d\n",
datx8, last_right_ok.unit, last_right_ok.phase);
- pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
- last_right_ok.unit, last_right_ok.phase,
- last_right_ok.bits_delay);
+ log_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
+ last_right_ok.unit, last_right_ok.phase,
+ last_right_ok.bits_delay);
/* Restore the last_right_ok condtion. */
DQS_unit_delay(phy, datx8, last_right_ok.unit);
@@ -812,7 +814,7 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
datx8 + 1, nb_bytes, error);
return error;
}
- pr_debug("deskewing bit %d:\n", bit_i);
+ log_debug("deskewing bit %d:\n", bit_i);
success = 1; /* init */
/* Set all DQDLYn to maximum value.
* Only bit_i will be down-delayed
@@ -855,10 +857,10 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* at one bit.
*/
fail_found = 1;
- pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
- bit_i, bit_i_delay_index + 1,
- datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
+ bit_i, bit_i_delay_index + 1,
+ datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
} else {
/* if we can find a success condition by
* back-delaying this bit, just set the delay
@@ -870,20 +872,20 @@ static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
* in the report.
*/
deskew_non_converge[datx8][bit_i] = 1;
- pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
- bit_i, datx8, bit_i,
- deskew_delay[datx8][bit_i]);
+ log_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
+ bit_i, datx8, bit_i,
+ deskew_delay[datx8][bit_i]);
}
}
- pr_debug("**********byte %d tuning complete************\n",
- datx8);
+ log_debug("**********byte %d tuning complete************\n",
+ datx8);
/* If we can't find any failure by back delaying DQ lines,
* hold the default values
*/
if (!fail_found) {
for (bit_i = 0; bit_i < 8; bit_i++)
deskew_delay[datx8][bit_i] = 0;
- pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
+ log_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
}
apply_deskew_results(phy, datx8, deskew_delay,
@@ -986,7 +988,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
dqs_unit_delay_index_pass = dqs_unit_delay_index;
success = 0;
- pr_debug("STEP0: Find Init delay\n");
+ log_debug("STEP0: Find Init delay\n");
/* STEP0: Find Init delay: a delay that put the system
* in a "Pass" condition then (TODO) update
* dqs_unit_delay_index_pass & phase_idx_pass
@@ -1035,7 +1037,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
+ log_debug("STEP1: Find LEFT PHASE DQS Bound\n");
/* STEP1: Find LEFT PHASE DQS Bound */
while ((phase_idx >= 0) &&
(phase_idx <= MAX_DQS_PHASE_IDX) &&
@@ -1069,7 +1071,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP2: Find UNIT left bound\n");
+ log_debug("STEP2: Find UNIT left bound\n");
/* STEP2: Find UNIT left bound */
while ((dqs_unit_delay_index >= 0) &&
!left_unit_bound_found) {
@@ -1097,7 +1099,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP3: Find PHase right bound\n");
+ log_debug("STEP3: Find PHase right bound\n");
/* STEP3: Find PHase right bound, start with "pass"
* condition
*/
@@ -1135,7 +1137,7 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
byte + 1, nb_bytes, error);
return TEST_FAILED;
}
- pr_debug("STEP4: Find UNIT right bound\n");
+ log_debug("STEP4: Find UNIT right bound\n");
/* STEP4: Find UNIT right bound */
while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
!right_unit_bound_found) {
@@ -1174,12 +1176,12 @@ static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
eye_training_val[byte][1]++;
- pr_debug("** found phase : %d - %d & unit %d - %d\n",
- right_bound.phase, left_bound.phase,
- right_bound.unit, left_bound.unit);
- pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
- eye_training_val[byte][0],
- eye_training_val[byte][1]);
+ log_debug("** found phase : %d - %d & unit %d - %d\n",
+ right_bound.phase, left_bound.phase,
+ right_bound.unit, left_bound.unit);
+ log_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
+ eye_training_val[byte][0],
+ eye_training_val[byte][1]);
} else {
/* PPPPPPPPPP, we're already good.
* Set nominal values.
@@ -1280,11 +1282,11 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
* or pppppff or ffppppp
*/
if (left_bound_found || right_bound_found) {
- pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
- left_bound_found,
- right_bound_idx[0], left_bound_idx[0],
- right_bound_found,
- right_bound_idx[1], left_bound_idx[1]);
+ log_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
+ left_bound_found,
+ right_bound_idx[0], left_bound_idx[0],
+ right_bound_found,
+ right_bound_idx[1], left_bound_idx[1]);
dqs_gate_values[byte][0] =
(right_bound_idx[0] + left_bound_idx[0]) / 2;
dqs_gate_values[byte][1] =
@@ -1319,14 +1321,14 @@ static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
left_bound_idx[0];
}
}
- pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
- dqs_gate_values[byte][0],
- dqs_gate_values[byte][1]);
- pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
+ log_debug("*******calculating mid region: system latency: %d phase: %d********\n",
+ dqs_gate_values[byte][0],
+ dqs_gate_values[byte][1]);
+ log_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
}
} else {
/* if intermitant, restore defaut values */
- pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
+ log_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
dqs_gate_values[byte][0] = 0;
dqs_gate_values[byte][1] = 2;
}
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-07 02:26:16 +0300