diff options
Diffstat (limited to 'drivers')
189 files changed, 1943 insertions, 3316 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index fd218c9056..4cbc40787d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,9 +1,12 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/ obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/ obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk/ obj-$(CONFIG_$(SPL_TPL_)DM) += core/ +obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/ +obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/ obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/ obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/ obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/ @@ -12,48 +15,40 @@ obj-$(CONFIG_$(SPL_TPL_)FIRMWARE) +=firmware/ obj-$(CONFIG_$(SPL_TPL_)I2C) += i2c/ obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/ obj-$(CONFIG_$(SPL_TPL_)LED) += led/ -obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/ +obj-$(CONFIG_$(SPL_TPL_)MMC) += mmc/ obj-y += mtd/ obj-$(CONFIG_$(SPL_)MULTIPLEXER) += mux/ -obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/ +obj-$(CONFIG_$(SPL_TPL_)ETH) += net/ +obj-$(CONFIG_$(SPL_TPL_)PCH) += pch/ obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/ obj-$(CONFIG_$(SPL_TPL_)PHY) += phy/ obj-$(CONFIG_$(SPL_TPL_)PINCTRL) += pinctrl/ +obj-$(CONFIG_$(SPL_TPL_)POWER) += power/ obj-$(CONFIG_$(SPL_TPL_)RAM) += ram/ -obj-$(CONFIG_$(SPL_TPL_)RTC_SUPPORT) += rtc/ -obj-$(CONFIG_$(SPL_TPL_)SERIAL_SUPPORT) += serial/ -obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/ +obj-$(CONFIG_$(SPL_TPL_)RTC) += rtc/ +obj-$(CONFIG_$(SPL_TPL_)SERIAL) += serial/ +obj-$(CONFIG_$(SPL_TPL_)SPI) += spi/ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/ obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/ -obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/ obj-$(CONFIG_SPL_CPU) += cpu/ obj-$(CONFIG_SPL_CRYPTO) += crypto/ -obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ +obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ -obj-$(CONFIG_SPL_POWER) += power/ power/pmic/ -obj-$(CONFIG_SPL_POWER) += power/regulator/ -obj-$(CONFIG_SPL_POWER_DOMAIN) += power/domain/ obj-$(CONFIG_SPL_DM_RESET) += reset/ -obj-$(CONFIG_SPL_DMA) += dma/ -obj-$(CONFIG_SPL_ETH) += net/ -obj-$(CONFIG_SPL_ETH) += net/phy/ -obj-$(CONFIG_SPL_USB_ETHER) += net/phy/ obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ @@ -61,7 +56,7 @@ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ obj-$(CONFIG_SPL_WATCHDOG) += watchdog/ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ -obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ +obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ @@ -70,8 +65,7 @@ endif ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/ -obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ +obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/ endif @@ -83,7 +77,6 @@ obj-y += bus/ obj-$(CONFIG_DM_DEMO) += demo/ obj-$(CONFIG_BIOSEMU) += bios_emulator/ obj-y += block/ -obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 6f0b772383..5639536811 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -36,10 +36,17 @@ menu "SATA/SCSI device support" config AHCI_PCI bool "Support for PCI-based AHCI controller" + depends on PCI depends on DM_SCSI help Enables support for the PCI-based AHCI controller. +config SPL_AHCI_PCI + bool "Support for PCI-based AHCI controller for SPL" + depends on SPL + depends on SPL_PCI + depends on SPL_SATA_SUPPORT && DM_SCSI + config SATA_CEVA bool "Ceva Sata controller" depends on AHCI diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 4811b2f82c..cd88131dcd 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_DWC_AHCI) += dwc_ahci.o obj-$(CONFIG_AHCI) += ahci-uclass.o -obj-$(CONFIG_AHCI_PCI) += ahci-pci.o +obj-$(CONFIG_$(SPL_)AHCI_PCI) += ahci-pci.o obj-$(CONFIG_SCSI_AHCI) += ahci.o obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o obj-$(CONFIG_FSL_SATA) += fsl_sata.o diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 4023332dd9..56a4eec05a 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -52,14 +52,12 @@ config BLOCK_CACHE config SPL_BLOCK_CACHE bool "Use block device cache in SPL" depends on SPL_BLK - default n help This option enables the disk-block cache in SPL config TPL_BLOCK_CACHE bool "Use block device cache in TPL" depends on TPL_BLK - default n help This option enables the disk-block cache in TPL diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c index 5d93e6a7e5..aec0bca7b3 100644 --- a/drivers/clk/at91/clk-master.c +++ b/drivers/clk/at91/clk-master.c @@ -12,13 +12,15 @@ #include <asm/processor.h> #include <clk-uclass.h> #include <common.h> +#include <div64.h> #include <dm.h> #include <linux/clk-provider.h> #include <linux/clk/at91_pmc.h> #include "pmc.h" -#define UBOOT_DM_CLK_AT91_MASTER "at91-master-clk" +#define UBOOT_DM_CLK_AT91_MASTER_PRES "at91-master-clk-pres" +#define UBOOT_DM_CLK_AT91_MASTER_DIV "at91-master-clk-div" #define UBOOT_DM_CLK_AT91_SAMA7G5_MASTER "at91-sama7g5-master-clk" #define MASTER_PRES_MASK 0x7 @@ -73,7 +75,7 @@ static int clk_master_enable(struct clk *clk) return 0; } -static ulong clk_master_get_rate(struct clk *clk) +static ulong clk_master_pres_get_rate(struct clk *clk) { struct clk_master *master = to_clk_master(clk); const struct clk_master_layout *layout = master->layout; @@ -81,7 +83,7 @@ static ulong clk_master_get_rate(struct clk *clk) master->characteristics; ulong rate = clk_get_parent_rate(clk); unsigned int mckr; - u8 pres, div; + u8 pres; if (!rate) return 0; @@ -90,29 +92,21 @@ static ulong clk_master_get_rate(struct clk *clk) mckr &= layout->mask; pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; - div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) - rate /= 3; + pres = 3; else - rate >>= pres; - - rate /= characteristics->divisors[div]; - - if (rate < characteristics->output.min) - pr_warn("master clk is underclocked"); - else if (rate > characteristics->output.max) - pr_warn("master clk is overclocked"); + pres = (1 << pres); - return rate; + return DIV_ROUND_CLOSEST_ULL(rate, pres); } -static const struct clk_ops master_ops = { +static const struct clk_ops master_pres_ops = { .enable = clk_master_enable, - .get_rate = clk_master_get_rate, + .get_rate = clk_master_pres_get_rate, }; -struct clk *at91_clk_register_master(void __iomem *base, +struct clk *at91_clk_register_master_pres(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, @@ -140,7 +134,7 @@ struct clk *at91_clk_register_master(void __iomem *base, pmc_read(master->base, master->layout->offset, &val); clk = &master->clk; clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; - ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER, name, + ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_PRES, name, parent_names[val & AT91_PMC_CSS]); if (ret) { kfree(master); @@ -150,10 +144,81 @@ struct clk *at91_clk_register_master(void __iomem *base, return clk; } -U_BOOT_DRIVER(at91_master_clk) = { - .name = UBOOT_DM_CLK_AT91_MASTER, +U_BOOT_DRIVER(at91_master_pres_clk) = { + .name = UBOOT_DM_CLK_AT91_MASTER_PRES, + .id = UCLASS_CLK, + .ops = &master_pres_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +static ulong clk_master_div_get_rate(struct clk *clk) +{ + struct clk_master *master = to_clk_master(clk); + const struct clk_master_layout *layout = master->layout; + const struct clk_master_characteristics *characteristics = + master->characteristics; + ulong rate = clk_get_parent_rate(clk); + unsigned int mckr; + u8 div; + + if (!rate) + return 0; + + pmc_read(master->base, master->layout->offset, &mckr); + mckr &= layout->mask; + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; + + rate = DIV_ROUND_CLOSEST_ULL(rate, characteristics->divisors[div]); + if (rate < characteristics->output.min) + pr_warn("master clk is underclocked"); + else if (rate > characteristics->output.max) + pr_warn("master clk is overclocked"); + + return rate; +} + +static const struct clk_ops master_div_ops = { + .enable = clk_master_enable, + .get_rate = clk_master_div_get_rate, +}; + +struct clk *at91_clk_register_master_div(void __iomem *base, + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics) +{ + struct clk_master *master; + struct clk *clk; + int ret; + + if (!base || !name || !parent_name || !layout || !characteristics) + return ERR_PTR(-EINVAL); + + master = kzalloc(sizeof(*master), GFP_KERNEL); + if (!master) + return ERR_PTR(-ENOMEM); + + master->layout = layout; + master->characteristics = characteristics; + master->base = base; + master->num_parents = 1; + + clk = &master->clk; + clk->flags = CLK_GET_RATE_NOCACHE | CLK_IS_CRITICAL; + ret = clk_register(clk, UBOOT_DM_CLK_AT91_MASTER_DIV, name, + parent_name); + if (ret) { + kfree(master); + clk = ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(at91_master_div_clk) = { + .name = UBOOT_DM_CLK_AT91_MASTER_DIV, .id = UCLASS_CLK, - .ops = &master_ops, + .ops = &master_div_ops, .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index f07f535e49..2b4dd9a3d9 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -97,12 +97,17 @@ sam9x60_clk_register_frac_pll(void __iomem *base, const char *name, const struct clk_pll_characteristics *characteristics, const struct clk_pll_layout *layout, bool critical); struct clk * -at91_clk_register_master(void __iomem *base, const char *name, +at91_clk_register_master_pres(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const struct clk_master_layout *layout, const struct clk_master_characteristics *characteristics, const u32 *mux_table); struct clk * +at91_clk_register_master_div(void __iomem *base, + const char *name, const char *parent_name, + const struct clk_master_layout *layout, + const struct clk_master_characteristics *characteristics); +struct clk * at91_clk_sama7g5_register_master(void __iomem *base, const char *name, const char * const *parent_names, int num_parents, const u32 *mux_table, const u32 *clk_mux_table, diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c index 9e9a643d62..4d00ee2ddc 100644 --- a/drivers/clk/at91/sam9x60.c +++ b/drivers/clk/at91/sam9x60.c @@ -31,7 +31,7 @@ * @ID_PLL_A_FRAC: APLL fractional clock identifier * @ID_PLL_A_DIV: APLL divider clock identifier - * @ID_MCK: MCK clock identifier + * @ID_MCK_DIV: MCK DIV clock identifier * @ID_UTMI: UTMI clock identifier @@ -43,6 +43,8 @@ * @ID_DDR: DDR system clock identifier * @ID_QSPI: QSPI system clock identifier * + * @ID_MCK_PRES: MCK PRES clock identifier + * * Note: if changing the values of this enums please sync them with * device tree */ @@ -60,7 +62,7 @@ enum pmc_clk_ids { ID_PLL_A_FRAC = 9, ID_PLL_A_DIV = 10, - ID_MCK = 11, + ID_MCK_DIV = 11, ID_UTMI = 12, @@ -73,6 +75,8 @@ enum pmc_clk_ids { ID_DDR = 17, ID_QSPI = 18, + ID_MCK_PRES = 19, + ID_MAX, }; @@ -93,7 +97,8 @@ static const char *clk_names[] = { [ID_MAINCK] = "mainck", [ID_PLL_U_DIV] = "upll_divpmcck", [ID_PLL_A_DIV] = "plla_divpmcck", - [ID_MCK] = "mck", + [ID_MCK_PRES] = "mck_pres", + [ID_MCK_DIV] = "mck_div", }; /* Fractional PLL output range. */ @@ -260,10 +265,10 @@ static const struct { u8 id; u8 cid; } sam9x60_systemck[] = { - { .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, }, + { .n = "ddrck", .p = "mck_pres", .id = 2, .cid = ID_DDR, }, { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, }, { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, }, - { .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, }, + { .n = "qspick", .p = "mck_pres", .id = 19, .cid = ID_QSPI, }, }; /** @@ -508,7 +513,7 @@ static int sam9x60_clk_probe(struct udevice *dev) clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c); } - /* Register MCK clock. */ + /* Register MCK pres clock. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_MAINCK]; p[2] = clk_names[ID_PLL_A_DIV]; @@ -519,25 +524,36 @@ static int sam9x60_clk_probe(struct udevice *dev) cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4, fail); - c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout, - &mck_characteristics, tmpclkmux); + c = at91_clk_register_master_pres(base, clk_names[ID_MCK_PRES], p, 4, + &mck_layout, &mck_characteristics, + tmpclkmux); + if (IS_ERR(c)) { + ret = PTR_ERR(c); + goto fail; + } + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_PRES), c); + + /* Register MCK div clock. */ + c = at91_clk_register_master_div(base, clk_names[ID_MCK_DIV], + clk_names[ID_MCK_PRES], + &mck_layout, &mck_characteristics); if (IS_ERR(c)) { ret = PTR_ERR(c); goto fail; } - clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV), c); /* Register programmable clocks. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK]; + p[3] = clk_names[ID_MCK_DIV]; p[4] = clk_names[ID_PLL_A_DIV]; p[5] = clk_names[ID_PLL_U_DIV]; cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) { @@ -572,7 +588,7 @@ static int sam9x60_clk_probe(struct udevice *dev) for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) { c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout, sam9x60_periphck[i].n, - clk_names[ID_MCK], + clk_names[ID_MCK_DIV], sam9x60_periphck[i].id, &r); if (IS_ERR(c)) { @@ -587,7 +603,7 @@ static int sam9x60_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK]; + p[3] = clk_names[ID_MCK_DIV]; p[4] = clk_names[ID_PLL_A_DIV]; p[5] = clk_names[ID_PLL_U_DIV]; m[0] = 0; @@ -599,7 +615,7 @@ static int sam9x60_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV); for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) { diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c index c0d9271966..d1ec3c82b5 100644 --- a/drivers/clk/at91/sama7g5.c +++ b/drivers/clk/at91/sama7g5.c @@ -44,7 +44,8 @@ * @ID_PLL_ETH_FRAC: Ethernet PLL fractional clock identifier * @ID_PLL_ETH_DIV: Ethernet PLL divider clock identifier - * @ID_MCK0: MCK0 clock identifier + * @ID_MCK0_PRES: MCK0 PRES clock identifier + * @ID_MCK0_DIV: MCK0 DIV clock identifier * @ID_MCK1: MCK1 clock identifier * @ID_MCK2: MCK2 clock identifier * @ID_MCK3: MCK3 clock identifier @@ -95,7 +96,7 @@ enum pmc_clk_ids { ID_PLL_ETH_FRAC = 20, ID_PLL_ETH_DIV = 21, - ID_MCK0 = 22, + ID_MCK0_DIV = 22, ID_MCK1 = 23, ID_MCK2 = 24, ID_MCK3 = 25, @@ -121,6 +122,8 @@ enum pmc_clk_ids { ID_PCK6 = 42, ID_PCK7 = 43, + ID_MCK0_PRES = 44, + ID_MAX, }; @@ -147,7 +150,8 @@ static const char *clk_names[] = { [ID_PLL_AUDIO_DIVPMC] = "audiopll_divpmcck", [ID_PLL_AUDIO_DIVIO] = "audiopll_diviock", [ID_PLL_ETH_DIV] = "ethpll_divpmcck", - [ID_MCK0] = "mck0", + [ID_MCK0_DIV] = "mck0_div", + [ID_MCK0_PRES] = "mck0_pres", }; /* Fractional PLL output range. */ @@ -504,7 +508,7 @@ static const struct { struct clk_range r; u8 id; } sama7g5_periphck[] = { - { .n = "pioA_clk", .p = "mck0", .id = 11, }, + { .n = "pioA_clk", .p = "mck0_div", .id = 11, }, { .n = "sfr_clk", .p = "mck1", .id = 19, }, { .n = "hsmc_clk", .p = "mck1", .id = 21, }, { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, @@ -514,7 +518,7 @@ static const struct { { .n = "aes_clk", .p = "mck1", .id = 27, }, { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, - { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, + { .n = "cpkcc_clk", .p = "mck0_div", .id = 32, }, { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, }, { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, }, { .n = "eic_clk", .p = "mck1", .id = 37, }, @@ -1210,7 +1214,7 @@ static int sama7g5_clk_probe(struct udevice *dev) sama7g5_plls[i].c)); } - /* Register MCK0 clock. */ + /* Register MCK0_PRES clock. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_MAINCK]; p[2] = clk_names[ID_PLL_CPU_DIV]; @@ -1221,15 +1225,19 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2, fail); - clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0), - at91_clk_register_master(base, clk_names[ID_MCK0], p, + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_PRES), + at91_clk_register_master_pres(base, clk_names[ID_MCK0_PRES], p, 4, &mck0_layout, &mck0_characteristics, tmpclkmux)); + clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV), + at91_clk_register_master_div(base, clk_names[ID_MCK0_DIV], + clk_names[ID_MCK0_PRES], &mck0_layout, &mck0_characteristics)); + /* Register MCK1-4 clocks. */ p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; m[0] = 0; m[1] = 1; m[2] = 2; @@ -1237,7 +1245,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { for (j = 0; j < sama7g5_mckx[i].ep_count; j++) { p[4 + j] = sama7g5_mckx[i].ep[j]; @@ -1267,7 +1275,7 @@ static int sama7g5_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; p[4] = clk_names[ID_PLL_SYS_DIV]; p[5] = clk_names[ID_PLL_DDR_DIV]; p[6] = clk_names[ID_PLL_IMG_DIV]; @@ -1277,7 +1285,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_SYS_DIV); cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_DDR_DIV); cm[6] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_IMG_DIV); @@ -1315,7 +1323,7 @@ static int sama7g5_clk_probe(struct udevice *dev) p[0] = clk_names[ID_MD_SLCK]; p[1] = clk_names[ID_TD_SLCK]; p[2] = clk_names[ID_MAINCK]; - p[3] = clk_names[ID_MCK0]; + p[3] = clk_names[ID_MCK0_DIV]; m[0] = 0; m[1] = 1; m[2] = 2; @@ -1323,7 +1331,7 @@ static int sama7g5_clk_probe(struct udevice *dev) cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK); cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK); cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK); - cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0); + cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK0_DIV); for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { for (j = 0; j < sama7g5_gck[i].ep_count; j++) { p[4 + j] = sama7g5_gck[i].ep[j]; diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index cea38a4c6e..493018b33e 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -35,10 +35,9 @@ struct clk *dev_get_clk_ptr(struct udevice *dev) return (struct clk *)dev_get_uclass_priv(dev); } -#if CONFIG_IS_ENABLED(OF_CONTROL) -# if CONFIG_IS_ENABLED(OF_PLATDATA) -int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, - struct clk *clk) +#if CONFIG_IS_ENABLED(OF_PLATDATA) +int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, + struct clk *clk) { int ret; @@ -49,7 +48,9 @@ int clk_get_by_driver_info(struct udevice *dev, struct phandle_1_arg *cells, return 0; } -# else +#endif + +#if CONFIG_IS_ENABLED(OF_REAL) static int clk_of_xlate_default(struct clk *clk, struct ofnode_phandle_args *args) { @@ -412,7 +413,7 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } -# endif /* OF_PLATDATA */ +#endif /* OF_REAL */ int clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) { @@ -465,8 +466,6 @@ int clk_release_all(struct clk *clk, int count) return 0; } -#endif /* OF_CONTROL */ - int clk_request(struct udevice *dev, struct clk *clk) { const struct clk_ops *ops; diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c index e51f94a937..41b0d9c060 100644 --- a/drivers/clk/clk_fixed_factor.c +++ b/drivers/clk/clk_fixed_factor.c @@ -40,17 +40,17 @@ const struct clk_ops clk_fixed_factor_ops = { static int clk_fixed_factor_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - int err; - struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + int err; + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); - err = clk_get_by_index(dev, 0, &ff->parent); - if (err) - return err; + err = clk_get_by_index(dev, 0, &ff->parent); + if (err) + return err; - ff->div = dev_read_u32_default(dev, "clock-div", 1); - ff->mult = dev_read_u32_default(dev, "clock-mult", 1); -#endif + ff->div = dev_read_u32_default(dev, "clock-div", 1); + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); + } return 0; } diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 325a9b2dcf..e0dc4ab85f 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -32,9 +32,10 @@ void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev, struct clk_fixed_rate *plat) { struct clk *clk = &plat->clk; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0); -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) + plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", + 0); + /* Make fixed rate clock accessible from higher level struct clk */ /* FIXME: This is not allowed */ dev_set_uclass_priv(dev, clk); diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index a49b6f19f4..617ce0dce5 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -1367,7 +1367,7 @@ static ulong px30_clk_set_rate(struct clk *clk, ulong rate) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int px30_gmac_set_parent(struct clk *clk, struct clk *parent) { struct px30_clk_priv *priv = dev_get_priv(clk->dev); @@ -1418,7 +1418,7 @@ static int px30_clk_enable(struct clk *clk) static struct clk_ops px30_clk_ops = { .get_rate = px30_clk_get_rate, .set_rate = px30_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = px30_clk_set_parent, #endif .enable = px30_clk_enable, diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 1b62d8d289..038cb55965 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -540,11 +540,11 @@ static struct clk_ops rk3188_clk_ops = { static int rk3188_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3188_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3188_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 221a5bd400..3b29992c3e 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -950,18 +950,18 @@ static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3288_clk_ops = { .get_rate = rk3288_clk_get_rate, .set_rate = rk3288_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3288_clk_set_parent, #endif }; static int rk3288_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3288_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3288_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index 5248e59685..2876643e6b 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -939,7 +939,7 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent) { struct rk3308_clk_priv *priv = dev_get_priv(clk->dev); @@ -976,7 +976,7 @@ static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3308_clk_ops = { .get_rate = rk3308_clk_get_rate, .set_rate = rk3308_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3308_clk_set_parent, #endif }; diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 780b49ccd8..39caf23c31 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -158,7 +158,7 @@ static void rkclk_init(struct rk3368_cru *cru) } #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) static ulong rk3368_mmc_get_clk(struct rk3368_cru *cru, uint clk_id) { u32 div, con, con_id, rate; @@ -470,7 +470,7 @@ static ulong rk3368_clk_get_rate(struct clk *clk) case SCLK_SPI0 ... SCLK_SPI2: rate = rk3368_spi_get_clk(priv->cru, clk->id); break; -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: rate = rk3368_mmc_get_clk(priv->cru, clk->id); @@ -501,7 +501,7 @@ static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate) ret = rk3368_ddr_set_clk(priv->cru, rate); break; #endif -#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC_SUPPORT) +#if !IS_ENABLED(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(MMC) case HCLK_SDMMC: case HCLK_EMMC: ret = rk3368_mmc_set_clk(clk, rate); @@ -574,7 +574,7 @@ static int __maybe_unused rk3368_clk_set_parent(struct clk *clk, struct clk *par static struct clk_ops rk3368_clk_ops = { .get_rate = rk3368_clk_get_rate, .set_rate = rk3368_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3368_clk_set_parent, #endif }; @@ -596,11 +596,11 @@ static int rk3368_clk_probe(struct udevice *dev) static int rk3368_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3368_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3368_clk_priv *priv = dev_get_priv(dev); - priv->cru = dev_read_addr_ptr(dev); -#endif + priv->cru = dev_read_addr_ptr(dev); + } return 0; } diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index f8cbda4455..7d31a9f22a 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1289,7 +1289,7 @@ static int rk3399_clk_disable(struct clk *clk) static struct clk_ops rk3399_clk_ops = { .get_rate = rk3399_clk_get_rate, .set_rate = rk3399_clk_set_rate, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .set_parent = rk3399_clk_set_parent, #endif .enable = rk3399_clk_enable, @@ -1402,11 +1402,12 @@ static int rk3399_clk_probe(struct udevice *dev) static int rk3399_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3399_clk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3399_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + } - priv->cru = dev_read_addr_ptr(dev); -#endif return 0; } @@ -1614,11 +1615,12 @@ static int rk3399_pmuclk_probe(struct udevice *dev) static int rk3399_pmuclk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = dev_read_addr_ptr(dev); + } - priv->pmucru = dev_read_addr_ptr(dev); -#endif return 0; } diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 9ae188c1df..8f7703c8b5 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -80,7 +80,6 @@ config DM_DEVICE_REMOVE config SPL_DM_DEVICE_REMOVE bool "Support device removal in SPL" depends on SPL_DM - default n help We can save some code space by dropping support for removing a device. This is not normally required in SPL, so by default this @@ -107,7 +106,6 @@ config DM_SEQ_ALIAS config SPL_DM_SEQ_ALIAS bool "Support numbered aliases in device tree in SPL" depends on SPL_DM - default n help Most boards will have a '/aliases' node containing the path to numbered devices (e.g. serial0 = &serial0). This feature can be @@ -132,7 +130,6 @@ config TPL_DM_INLINE_OFNODE config DM_DMA bool "Support per-device DMA constraints" depends on DM - default n help Enable this to extract per-device DMA constraints, only supported on device-tree systems for now. This is needed in order translate @@ -274,7 +271,6 @@ config OF_TRANSLATE config SPL_OF_TRANSLATE bool "Translate addresses using fdt_translate_address in SPL" depends on SPL_DM && SPL_OF_CONTROL - default n help If this option is enabled, the reg property will be translated using the fdt_translate_address() function. This is necessary diff --git a/drivers/core/device.c b/drivers/core/device.c index 29668f6fb3..42ba2dce46 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -670,7 +670,7 @@ static int device_get_device_tail(struct udevice *dev, int ret, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * device_find_by_ofnode() - Return device associated with given ofnode * @@ -1074,7 +1074,7 @@ void dev_set_uclass_plat(struct udevice *dev, void *uclass_plat) dev->uclass_plat_ = uclass_plat; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) bool device_is_compatible(const struct udevice *dev, const char *compat) { return ofnode_device_is_compatible(dev_ofnode(dev), compat); diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c index 4ffbd6b2eb..6dfda20772 100644 --- a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { diff --git a/drivers/core/lists.c b/drivers/core/lists.c index e214306b90..350b9d3268 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -154,7 +154,7 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name, return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * driver_check_compatible() - Check if a driver matches a compatible string * diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 701b23e2c9..08705ef8d9 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -1103,3 +1103,36 @@ int ofnode_set_enabled(ofnode node, bool value) else return ofnode_write_string(node, "status", "disabled"); } + +bool ofnode_conf_read_bool(const char *prop_name) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return false; + + return ofnode_read_bool(node, prop_name); +} + +int ofnode_conf_read_int(const char *prop_name, int default_val) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return default_val; + + return ofnode_read_u32_default(node, prop_name, default_val); +} + +const char *ofnode_conf_read_str(const char *prop_name) +{ + ofnode node; + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) + return NULL; + + return ofnode_read_string(node, prop_name); +} diff --git a/drivers/core/root.c b/drivers/core/root.c index 78eee082c9..fecdcb5b30 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -245,7 +245,7 @@ int dm_scan_plat(bool pre_reloc_only) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * dm_scan_fdt_node() - Scan the device tree and bind drivers for a node * @@ -372,7 +372,7 @@ static int dm_scan(bool pre_reloc_only) return ret; } - if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (CONFIG_IS_ENABLED(OF_REAL)) { ret = dm_extended_scan(pre_reloc_only); if (ret) { debug("dm_extended_scan() failed: %d\n", ret); diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index abc55c2171..6022e7514e 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -65,7 +65,7 @@ UCLASS_DRIVER(simple_bus) = { .per_device_plat_auto = sizeof(struct simple_bus_plat), }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id generic_simple_bus_ids[] = { { .compatible = "simple-bus" }, { .compatible = "simple-mfd" }, diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index cb33facc71..25fdb66eaa 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -186,7 +186,7 @@ static const struct udevice_id generic_syscon_ids[] = { U_BOOT_DRIVER(generic_syscon) = { .name = "syscon", .id = UCLASS_SYSCON, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .of_match = generic_syscon_ids, diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 3146dfd032..c5a50952fd 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -397,7 +397,7 @@ done: return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int uclass_find_device_by_phandle(enum uclass_id id, struct udevice *parent, const char *name, struct udevice **devp) { diff --git a/drivers/core/util.c b/drivers/core/util.c index 5be4ee79de..aa60fdd15b 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -22,7 +22,7 @@ int list_count_items(struct list_head *head) return count; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int pci_get_devfn(struct udevice *dev) { struct fdt_pci_addr addr; diff --git a/drivers/cpu/at91_cpu.c b/drivers/cpu/at91_cpu.c index 9ef1b3102c..34a3f61c7e 100644 --- a/drivers/cpu/at91_cpu.c +++ b/drivers/cpu/at91_cpu.c @@ -70,6 +70,7 @@ static const struct cpu_ops at91_cpu_ops = { static const struct udevice_id at91_cpu_ids[] = { { .compatible = "arm,cortex-a7" }, + { .compatible = "arm,arm926ej-s" }, { /* Sentinel. */ } }; diff --git a/drivers/cpu/cpu_sandbox.c b/drivers/cpu/cpu_sandbox.c index fe6772ba5a..2e871fe313 100644 --- a/drivers/cpu/cpu_sandbox.c +++ b/drivers/cpu/cpu_sandbox.c @@ -38,7 +38,7 @@ static int cpu_sandbox_get_vendor(const struct udevice *dev, char *buf, return 0; } -static const char *cpu_current = "cpu-test1"; +static const char *cpu_current = "cpu@1"; void cpu_sandbox_set_current(const char *name) { diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 1ea116be75..0082177c21 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -1,5 +1,7 @@ menu "Hardware crypto devices" +source drivers/crypto/hash/Kconfig + source drivers/crypto/fsl/Kconfig endmenu diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca..4a12b56be6 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o obj-y += rsa_mod_exp/ obj-y += fsl/ +obj-y += hash/ diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig new file mode 100644 index 0000000000..cd29a5c6a4 --- /dev/null +++ b/drivers/crypto/hash/Kconfig @@ -0,0 +1,16 @@ +config DM_HASH + bool "Enable Driver Model for Hash" + depends on DM + help + If you want to use driver model for Hash, say Y. + +config HASH_SOFTWARE + bool "Enable driver for Hash in software" + depends on DM_HASH + depends on MD5 + depends on SHA1 + depends on SHA256 + depends on SHA512_ALGO + help + Enable driver for hashing operations in software. Currently + it support multiple hash algorithm including CRC/MD5/SHA. diff --git a/drivers/crypto/hash/Makefile b/drivers/crypto/hash/Makefile new file mode 100644 index 0000000000..33d88161ed --- /dev/null +++ b/drivers/crypto/hash/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2021 ASPEED Technology Inc. + +obj-$(CONFIG_DM_HASH) += hash-uclass.o +obj-$(CONFIG_HASH_SOFTWARE) += hash_sw.o diff --git a/drivers/crypto/hash/hash-uclass.c b/drivers/crypto/hash/hash-uclass.c new file mode 100644 index 0000000000..446eb9e56a --- /dev/null +++ b/drivers/crypto/hash/hash-uclass.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> + */ + +#define LOG_CATEGORY UCLASS_HASH + +#include <common.h> +#include <dm.h> +#include <asm/global_data.h> +#include <u-boot/hash.h> +#include <errno.h> +#include <fdtdec.h> +#include <malloc.h> +#include <asm/io.h> +#include <linux/list.h> + +struct hash_info { + char *name; + uint32_t digest_size; +}; + +static const struct hash_info hash_info[HASH_ALGO_NUM] = { + [HASH_ALGO_CRC16_CCITT] = { "crc16-ccitt", 2 }, + [HASH_ALGO_CRC32] = { "crc32", 4 }, + [HASH_ALGO_MD5] = { "md5", 16 }, + [HASH_ALGO_SHA1] = { "sha1", 20 }, + [HASH_ALGO_SHA256] = { "sha256", 32 }, + [HASH_ALGO_SHA384] = { "sha384", 48 }, + [HASH_ALGO_SHA512] = { "sha512", 64}, +}; + +enum HASH_ALGO hash_algo_lookup_by_name(const char *name) +{ + int i; + + if (!name) + return HASH_ALGO_INVALID; + + for (i = 0; i < HASH_ALGO_NUM; ++i) + if (!strcmp(name, hash_info[i].name)) + return i; + + return HASH_ALGO_INVALID; +} + +ssize_t hash_algo_digest_size(enum HASH_ALGO algo) +{ + if (algo >= HASH_ALGO_NUM) + return -EINVAL; + + return hash_info[algo].digest_size; +} + +const char *hash_algo_name(enum HASH_ALGO algo) +{ + if (algo >= HASH_ALGO_NUM) + return NULL; + + return hash_info[algo].name; +} + +int hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_digest) + return -ENOSYS; + + return ops->hash_digest(dev, algo, ibuf, ilen, obuf); +} + +int hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_digest_wd) + return -ENOSYS; + + return ops->hash_digest_wd(dev, algo, ibuf, ilen, obuf, chunk_sz); +} + +int hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_init) + return -ENOSYS; + + return ops->hash_init(dev, algo, ctxp); +} + +int hash_update(struct udevice *dev, void *ctx, const void *ibuf, const uint32_t ilen) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_update) + return -ENOSYS; + + return ops->hash_update(dev, ctx, ibuf, ilen); +} + +int hash_finish(struct udevice *dev, void *ctx, void *obuf) +{ + struct hash_ops *ops = (struct hash_ops *)device_get_ops(dev); + + if (!ops->hash_finish) + return -ENOSYS; + + return ops->hash_finish(dev, ctx, obuf); +} + +UCLASS_DRIVER(hash) = { + .id = UCLASS_HASH, + .name = "hash", +}; diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c new file mode 100644 index 0000000000..fea9d12609 --- /dev/null +++ b/drivers/crypto/hash/hash_sw.c @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 ASPEED Technology Inc. + * Author: ChiaWei Wang <chiawei_wang@aspeedtech.com> + */ +#include <config.h> +#include <common.h> +#include <dm.h> +#include <log.h> +#include <malloc.h> +#include <watchdog.h> +#include <u-boot/hash.h> +#include <u-boot/crc.h> +#include <u-boot/md5.h> +#include <u-boot/sha1.h> +#include <u-boot/sha256.h> +#include <u-boot/sha512.h> + +/* CRC16-CCITT */ +static void hash_init_crc16_ccitt(void *ctx) +{ + *((uint16_t *)ctx) = 0; +} + +static void hash_update_crc16_ccitt(void *ctx, const void *ibuf, uint32_t ilen) +{ + *((uint16_t *)ctx) = crc16_ccitt(*((uint16_t *)ctx), ibuf, ilen); +} + +static void hash_finish_crc16_ccitt(void *ctx, void *obuf) +{ + *((uint16_t *)obuf) = *((uint16_t *)ctx); +} + +/* CRC32 */ +static void hash_init_crc32(void *ctx) +{ + *((uint32_t *)ctx) = 0; +} + +static void hash_update_crc32(void *ctx, const void *ibuf, uint32_t ilen) +{ + *((uint32_t *)ctx) = crc32(*((uint32_t *)ctx), ibuf, ilen); +} + +static void hash_finish_crc32(void *ctx, void *obuf) +{ + *((uint32_t *)obuf) = *((uint32_t *)ctx); +} + +/* MD5 */ +static void hash_init_md5(void *ctx) +{ + MD5Init((struct MD5Context *)ctx); +} + +static void hash_update_md5(void *ctx, const void *ibuf, uint32_t ilen) +{ + MD5Update((struct MD5Context *)ctx, ibuf, ilen); +} + +static void hash_finish_md5(void *ctx, void *obuf) +{ + MD5Final(obuf, (struct MD5Context *)ctx); +} + +/* SHA1 */ +static void hash_init_sha1(void *ctx) +{ + sha1_starts((sha1_context *)ctx); +} + +static void hash_update_sha1(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha1_update((sha1_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha1(void *ctx, void *obuf) +{ + sha1_finish((sha1_context *)ctx, obuf); +} + +/* SHA256 */ +static void hash_init_sha256(void *ctx) +{ + sha256_starts((sha256_context *)ctx); +} + +static void hash_update_sha256(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha256_update((sha256_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha256(void *ctx, void *obuf) +{ + sha256_finish((sha256_context *)ctx, obuf); +} + +/* SHA384 */ +static void hash_init_sha384(void *ctx) +{ + sha384_starts((sha512_context *)ctx); +} + +static void hash_update_sha384(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha384_update((sha512_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha384(void *ctx, void *obuf) +{ + sha384_finish((sha512_context *)ctx, obuf); +} + +/* SHA512 */ +static void hash_init_sha512(void *ctx) +{ + sha512_starts((sha512_context *)ctx); +} + +static void hash_update_sha512(void *ctx, const void *ibuf, uint32_t ilen) +{ + sha512_update((sha512_context *)ctx, ibuf, ilen); +} + +static void hash_finish_sha512(void *ctx, void *obuf) +{ + sha512_finish((sha512_context *)ctx, obuf); +} + +struct sw_hash_ctx { + enum HASH_ALGO algo; + uint8_t algo_ctx[]; +}; + +struct sw_hash_impl { + void (*init)(void *ctx); + void (*update)(void *ctx, const void *ibuf, uint32_t ilen); + void (*finish)(void *ctx, void *obuf); + uint32_t ctx_alloc_sz; +}; + +static struct sw_hash_impl sw_hash_impl[HASH_ALGO_NUM] = { + [HASH_ALGO_CRC16_CCITT] = { + .init = hash_init_crc16_ccitt, + .update = hash_update_crc16_ccitt, + .finish = hash_finish_crc16_ccitt, + .ctx_alloc_sz = sizeof(uint16_t), + }, + + [HASH_ALGO_CRC32] = { + .init = hash_init_crc32, + .update = hash_update_crc32, + .finish = hash_finish_crc32, + .ctx_alloc_sz = sizeof(uint32_t), + }, + + [HASH_ALGO_MD5] = { + .init = hash_init_md5, + .update = hash_update_md5, + .finish = hash_finish_md5, + .ctx_alloc_sz = sizeof(struct MD5Context), + }, + + [HASH_ALGO_SHA1] = { + .init = hash_init_sha1, + .update = hash_update_sha1, + .finish = hash_finish_sha1, + .ctx_alloc_sz = sizeof(sha1_context), + }, + + [HASH_ALGO_SHA256] = { + .init = hash_init_sha256, + .update = hash_update_sha256, + .finish = hash_finish_sha256, + .ctx_alloc_sz = sizeof(sha256_context), + }, + + [HASH_ALGO_SHA384] = { + .init = hash_init_sha384, + .update = hash_update_sha384, + .finish = hash_finish_sha384, + .ctx_alloc_sz = sizeof(sha512_context), + }, + + [HASH_ALGO_SHA512] = { + .init = hash_init_sha512, + .update = hash_update_sha512, + .finish = hash_finish_sha512, + .ctx_alloc_sz = sizeof(sha512_context), + }, +}; + +static int sw_hash_init(struct udevice *dev, enum HASH_ALGO algo, void **ctxp) +{ + struct sw_hash_ctx *hash_ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[algo]; + + hash_ctx = malloc(sizeof(hash_ctx->algo) + hash_impl->ctx_alloc_sz); + if (!hash_ctx) + return -ENOMEM; + + hash_ctx->algo = algo; + + hash_impl->init(hash_ctx->algo_ctx); + + *ctxp = hash_ctx; + + return 0; +} + +static int sw_hash_update(struct udevice *dev, void *ctx, const void *ibuf, uint32_t ilen) +{ + struct sw_hash_ctx *hash_ctx = ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; + + hash_impl->update(hash_ctx->algo_ctx, ibuf, ilen); + + return 0; +} + +static int sw_hash_finish(struct udevice *dev, void *ctx, void *obuf) +{ + struct sw_hash_ctx *hash_ctx = ctx; + struct sw_hash_impl *hash_impl = &sw_hash_impl[hash_ctx->algo]; + + hash_impl->finish(hash_ctx->algo_ctx, obuf); + + free(ctx); + + return 0; +} + +static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf, uint32_t chunk_sz) +{ + int rc; + void *ctx; + const void *cur, *end; + uint32_t chunk; + + rc = sw_hash_init(dev, algo, &ctx); + if (rc) + return rc; + + if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { + cur = ibuf; + end = ibuf + ilen; + + while (cur < end) { + chunk = end - cur; + if (chunk > chunk_sz) + chunk = chunk_sz; + + rc = sw_hash_update(dev, ctx, cur, chunk); + if (rc) + return rc; + + cur += chunk; + WATCHDOG_RESET(); + } + } else { + rc = sw_hash_update(dev, ctx, ibuf, ilen); + if (rc) + return rc; + } + + rc = sw_hash_finish(dev, ctx, obuf); + if (rc) + return rc; + + return 0; +} + +static int sw_hash_digest(struct udevice *dev, enum HASH_ALGO algo, + const void *ibuf, const uint32_t ilen, + void *obuf) +{ + /* re-use the watchdog version with input length as the chunk_sz */ + return sw_hash_digest_wd(dev, algo, ibuf, ilen, obuf, ilen); +} + +static const struct hash_ops hash_ops_sw = { + .hash_init = sw_hash_init, + .hash_update = sw_hash_update, + .hash_finish = sw_hash_finish, + .hash_digest_wd = sw_hash_digest_wd, + .hash_digest = sw_hash_digest, +}; + +U_BOOT_DRIVER(hash_sw) = { + .name = "hash_sw", + .id = UCLASS_HASH, + .ops = &hash_ops_sw, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRVINFO(hash_sw) = { + .name = "hash_sw", +}; diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig index d4b393d25e..eec9d480b0 100644 --- a/drivers/ddr/Kconfig +++ b/drivers/ddr/Kconfig @@ -1,2 +1,34 @@ +choice + prompt "Method to determine DDR clock frequency" + default STATIC_DDR_CLK_FREQ + depends on ARCH_P1010 || ARCH_P1020 || ARCH_P2020 || ARCH_T1024 \ + || ARCH_T1042 || ARCH_T2080 || ARCH_T4240 || ARCH_LS1021A \ + || FSL_LSCH2 || FSL_LSCH3 || TARGET_KMCENT2 + help + The DDR clock frequency can either be defined statically now at + build time, or can be determined at run-time via the + get_board_ddr_clk function. + +config DYNAMIC_DDR_CLK_FREQ + bool "Run-time DDR clock frequency" + +config STATIC_DDR_CLK_FREQ + bool "Build-time static DDR clock frequency" + +endchoice + +config DDR_CLK_FREQ + int "DDR clock frequency in Hz" + depends on STATIC_DDR_CLK_FREQ + default 100000000 + help + The DDR clock frequency, specified in Hz. + +config DDR_SPD + bool "JEDEC Serial Presence Detect (SPD) support" + help + For memory controllers that can utilize it, add enable support for + using the JEDEC SDP standard. + source "drivers/ddr/altera/Kconfig" source "drivers/ddr/imx/Kconfig" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 8246f62798..fe3d6fc970 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -10,6 +10,8 @@ config SYS_FSL_MMDC help Select Freescale Multi Mode DDR controller (MMDC). +if SYS_FSL_DDR || SYS_FSL_MMDC + config SYS_FSL_DDR_BE bool help @@ -116,28 +118,51 @@ choice config SYS_FSL_DDR4 bool "Freescale DDR4 controller" depends on SYS_FSL_HAS_DDR4 + imply DDR_SPD select SYS_FSL_DDRC_GEN4 config SYS_FSL_DDR3 bool "Freescale DDR3 controller" depends on SYS_FSL_HAS_DDR3 + imply DDR_SPD select SYS_FSL_DDRC_GEN3 if PPC select SYS_FSL_DDRC_ARM_GEN3 if ARM config SYS_FSL_DDR2 bool "Freescale DDR2 controller" depends on SYS_FSL_HAS_DDR2 + imply DDR_SPD select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) config SYS_FSL_DDR1 bool "Freescale DDR1 controller" depends on SYS_FSL_HAS_DDR1 + imply DDR_SPD select SYS_FSL_DDRC_GEN1 endchoice endmenu +config FSL_DMA + def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER + +config DDR_ECC + bool "ECC DDR memory support" + +config DDR_ECC_CMD + bool "Access the ECC features of the memory controller" + depends on DDR_ECC && MPC83xx + default y + +config ECC_INIT_VIA_DDRCONTROLLER + bool "DDR Memory controller initializes memory." + help + Use the DDR controller to auto initialize memory. If not enabled, + the DMA controller is responsible for doing this. + +endif + config SYS_FSL_ERRATUM_A008378 bool diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index 270691e9bc..970651f870 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -19,10 +19,10 @@ #define FAR_END_DIMM_ADDR 0x50 #define MAX_DIMM_ADDR 0x60 -#ifndef CONFIG_DDR_FIXED_SIZE +#ifndef CONFIG_SYS_SDRAM_SIZE #define SDRAM_CS_SIZE 0xFFFFFFF #else -#define SDRAM_CS_SIZE (CONFIG_DDR_FIXED_SIZE - 1) +#define SDRAM_CS_SIZE ((CONFIG_SYS_SDRAM_SIZE >> 10) - 1) #endif #define SDRAM_CS_BASE 0x0 #define SDRAM_DIMM_SIZE 0x80000000 diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index 10d064d0a3..437a02efba 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -16,11 +16,7 @@ * Level 3: Provides the windows margin of each DQ as a results of DQS * centeralization */ -#ifdef CONFIG_DDR_LOG_LEVEL #define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL -#else -#define DDR3_LOG_LEVEL 0 -#endif #define DDR3_PBS 1 diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index b50547476c..48e41bc262 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -16,7 +16,6 @@ config DFU_OVER_TFTP if DFU config DFU_WRITE_ALT bool - default n config DFU_TFTP bool "DFU via TFTP" diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 1993c1d31d..9cacea88d0 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -35,19 +35,40 @@ config BCM6348_IUDMA This driver support data transfer from devices to memory and from memory to devices. +config DMA_LPC32XX + bool "LPC32XX DMA driver" + select DMA_LEGACY + help + Enable some legacy DMA code for lpc32xx. It provides some direct + functions likes lpc32xx_dma_wait_status() which can be called from + other code. + + This should be converted to use driver model and UCLASS_DMA. + config TI_EDMA3 bool "TI EDMA3 driver" + select DMA_LEGACY help Enable the TI EDMA3 driver for DRA7xx and AM43xx evms. This driver support data transfer between memory regions. +config TI_KSNAV + bool "TI Keystone Navigator DMA driver" + depends on ARCH_KEYSTONE + default y + select DMA_LEGACY + help + Enable the Keystone Navigator driver for Keystone 2 platforms. + config APBH_DMA bool "Support APBH DMA" depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M + select DMA_LEGACY help Enable APBH DMA driver. + if APBH_DMA config APBH_DMA_BURST bool "Enable DMA BURST" @@ -57,6 +78,15 @@ config APBH_DMA_BURST8 endif +config DMA_LEGACY + bool "Legacy DMA support" + default y if FSLDMAFEC + help + Enable legacy DMA support. This does not use driver model and should + be migrated to the new API. + + It is required for some PowerPC boards. + source "drivers/dma/ti/Kconfig" endmenu # menu "DMA Support" diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index b7eddf0f04..1864b5d88b 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -130,11 +130,9 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { /* * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER - * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA */ #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \ - !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \ - (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA))) + !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))) void dma_meminit(uint val, uint size) { uint *p = 0; diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index 443e4b2366..9a5ba79f3f 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -11,20 +11,20 @@ #include <linux/delay.h> struct qm_config qm_memmap = { - .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE, - .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE, - .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS, - .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE, - .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE, - .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE, - .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE, - .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE, - .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE, - .region_num = CONFIG_KSNAV_QM_REGION_NUM, - .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE, - .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE, - .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE, - .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM, + .stat_cfg = KS2_QM_QUEUE_STATUS_BASE, + .queue = (void *)KS2_QM_MANAGER_QUEUES_BASE, + .mngr_vbusm = KS2_QM_BASE_ADDRESS, + .i_lram = KS2_QM_LINK_RAM_BASE, + .proxy = (void *)KS2_QM_MANAGER_Q_PROXY_BASE, + .status_ram = KS2_QM_STATUS_RAM_BASE, + .mngr_cfg = (void *)KS2_QM_CONF_BASE, + .intd_cfg = KS2_QM_INTD_CONF_BASE, + .desc_mem = (void *)KS2_QM_DESC_SETUP_BASE, + .region_num = KS2_QM_REGION_NUM, + .pdsp_cmd = KS2_QM_PDSP1_CMD_BASE, + .pdsp_ctl = KS2_QM_PDSP1_CTRL_BASE, + .pdsp_iram = KS2_QM_PDSP1_IRAM_BASE, + .qpool_num = KS2_QM_QPOOL_NUM, }; /* @@ -252,7 +252,7 @@ int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers) writel(0, &pktdma->global->emulation_control); /* Set QM base address, only for K2x devices */ - writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); + writel(KS2_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); /* Enable all channels. The current state isn't important */ for (j = 0; j < pktdma->tx_ch_num; j++) { diff --git a/drivers/dma/keystone_nav_cfg.c b/drivers/dma/keystone_nav_cfg.c index 9a64801cf9..301419b6fd 100644 --- a/drivers/dma/keystone_nav_cfg.c +++ b/drivers/dma/keystone_nav_cfg.c @@ -8,19 +8,17 @@ #include <asm/ti-common/keystone_nav.h> -#ifdef CONFIG_KSNAV_PKTDMA_NETCP /* NETCP Pktdma */ struct pktdma_cfg netcp_pktdma = { - .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, - .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, - .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, - .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, - .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, - .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, - .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, - .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, - .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, - .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, - .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, + .global = (void *)KS2_NETCP_PDMA_CTRL_BASE, + .tx_ch = (void *)KS2_NETCP_PDMA_TX_BASE, + .tx_ch_num = KS2_NETCP_PDMA_TX_CH_NUM, + .rx_ch = (void *)KS2_NETCP_PDMA_RX_BASE, + .rx_ch_num = KS2_NETCP_PDMA_RX_CH_NUM, + .tx_sched = (u32 *)KS2_NETCP_PDMA_SCHED_BASE, + .rx_flows = (void *)KS2_NETCP_PDMA_RX_FLOW_BASE, + .rx_flow_num = KS2_NETCP_PDMA_RX_FLOW_NUM, + .rx_free_q = KS2_NETCP_PDMA_RX_FREE_QUEUE, + .rx_rcv_q = KS2_NETCP_PDMA_RX_RCV_QUEUE, + .tx_snd_q = KS2_NETCP_PDMA_TX_SND_QUEUE, }; -#endif diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index 9cbd5f334d..87c026e049 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -9,7 +9,6 @@ config TI_K3_NAVSS_UDMA select TI_K3_NAVSS_RINGACC select TI_K3_NAVSS_PSILCFG select TI_K3_PSIL - default n help Support for UDMA used in K3 devices. endif diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 2d1836a80e..d5e4a02098 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -74,7 +74,6 @@ config FASTBOOT_FLASH config FASTBOOT_UUU_SUPPORT bool "Enable FASTBOOT i.MX UUU special command" - default n help The fastboot protocol includes "UCmd" and "ACmd" command. Be aware that you provide full access to any U-Boot command, diff --git a/drivers/firmware/firmware-uclass.c b/drivers/firmware/firmware-uclass.c index bfaf283eed..e83a147a00 100644 --- a/drivers/firmware/firmware-uclass.c +++ b/drivers/firmware/firmware-uclass.c @@ -9,7 +9,7 @@ UCLASS_DRIVER(firmware) = { .id = UCLASS_FIRMWARE, .name = "firmware", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e37ac9f494..f0439e2417 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -2,7 +2,19 @@ # GPIO infrastructure and drivers # -menu "GPIO Support" +menuconfig GPIO + bool "GPIO support" + default y + help + Enable support for GPIOs (General-purpose Input/Output) in U-Boot. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of an U-Boot build. + +if GPIO config DM_GPIO bool "Enable Driver Model for GPIO drivers" @@ -39,7 +51,6 @@ config TPL_DM_GPIO config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO - default n help Enable gpio hog support The GPIO chip may contain GPIO hog definitions. GPIO hogging @@ -91,13 +102,11 @@ config CORTINA_GPIO config DWAPB_GPIO bool "DWAPB GPIO driver" depends on DM && DM_GPIO - default n help Support for the Designware APB GPIO driver. config AT91_GPIO bool "AT91 PIO GPIO driver" - default n help Say yes here to select AT91 PIO GPIO driver. AT91 PIO controller manages up to 32 fully programmable input/output @@ -110,7 +119,6 @@ config AT91_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" depends on DM_GPIO - default n help Say yes here to support the Atmel PIO4 driver. The PIO4 is new version of Atmel PIO controller, which manages @@ -150,13 +158,11 @@ config INTEL_ICH6_GPIO config IMX_RGPIO2P bool "i.MX7ULP RGPIO2P driver" depends on DM - default n help This driver supports i.MX7ULP Rapid GPIO2P controller. config IPROC_GPIO bool "Broadcom iProc GPIO driver(without pinconf)" - default n help The Broadcom iProc based SoCs- Cygnus, NS2, NS3, NSP and Stingray, use the same GPIO Controller IP hence this driver could be used @@ -168,14 +174,12 @@ config IPROC_GPIO config HSDK_CREG_GPIO bool "HSDK CREG GPIO griver" depends on DM_GPIO - default n help This driver supports CREG GPIOs on Synopsys HSDK SOC. config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM - default n help Support for the LPC32XX GPIO driver. @@ -203,7 +207,6 @@ config MSCC_SGPIO config MSM_GPIO bool "Qualcomm GPIO driver" depends on DM_GPIO - default n help Support GPIO controllers on Qualcomm Snapdragon family of SoCs. This controller have single bank (default name "soc"), every @@ -345,7 +348,6 @@ config GPIO_UNIPHIER config VYBRID_GPIO bool "Vybrid GPIO driver" depends on DM - default n help Say yes here to support Vybrid vf610 GPIOs. @@ -513,4 +515,4 @@ config NOMADIK_GPIO into a number of banks each with 32 GPIOs. The GPIOs for a device are defined in the device tree with one node for each bank. -endmenu +endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 58f4704f6b..18917488c2 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -33,7 +33,7 @@ obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o obj-$(CONFIG_S5P) += s5p_gpio.o -obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o +obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o @@ -62,7 +62,7 @@ obj-$(CONFIG_OCTEON_GPIO) += octeon_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o -obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o +obj-$(CONFIG_$(SPL_TPL_)PM8916_GPIO) += pm8916_gpio.o obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 8c77777dbe..bb2f23241e 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -7,6 +7,7 @@ #include <common.h> #include <dm.h> +#include <dt-structs.h> #include <log.h> #include <dm/devres.h> #include <dm/device_compat.h> @@ -231,7 +232,7 @@ static int gpio_find_and_xlate(struct gpio_desc *desc, return gpio_xlate_offs_flags(desc->dev, desc, args); } -#if defined(CONFIG_GPIO_HOG) +#if CONFIG_IS_ENABLED(GPIO_HOG) struct gpio_hog_priv { struct gpio_desc gpiod; @@ -1137,7 +1138,7 @@ err: return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int _gpio_request_by_name_nodev(ofnode node, const char *list_name, int index, struct gpio_desc *desc, int flags, bool add_index) @@ -1226,6 +1227,27 @@ int gpio_get_list_count(struct udevice *dev, const char *list_name) } #endif /* OF_PLATDATA */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) +int gpio_request_by_phandle(struct udevice *dev, + const struct phandle_2_arg *cells, + struct gpio_desc *desc, int flags) +{ + struct ofnode_phandle_args args; + struct udevice *gpio_dev; + const int index = 0; + int ret; + + ret = device_get_by_ofplat_idx(cells->idx, &gpio_dev); + if (ret) + return ret; + args.args[0] = cells->arg[0]; + args.args[1] = cells->arg[1]; + + return gpio_request_tail(ret, NULL, &args, NULL, index, desc, flags, + index > 0, gpio_dev); +} +#endif + int dm_gpio_free(struct udevice *dev, struct gpio_desc *desc) { /* For now, we don't do any checking of dev */ @@ -1430,7 +1452,7 @@ static int gpio_post_bind(struct udevice *dev) } #endif - if (IS_ENABLED(CONFIG_GPIO_HOG)) { + if (CONFIG_IS_ENABLED(OF_REAL) && IS_ENABLED(CONFIG_GPIO_HOG)) { dev_for_each_subnode(node, dev) { if (ofnode_read_bool(node, "gpio-hog")) { const char *name = ofnode_get_name(node); diff --git a/drivers/gpio/intel_gpio.c b/drivers/gpio/intel_gpio.c index f15ce7b59e..4a3ec6d635 100644 --- a/drivers/gpio/intel_gpio.c +++ b/drivers/gpio/intel_gpio.c @@ -204,7 +204,7 @@ static const struct dm_gpio_ops gpio_intel_ops = { #endif }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id intel_intel_gpio_ids[] = { { .compatible = "intel,gpio" }, { } diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index 7b9d88a8a7..1356f89ac2 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -262,7 +262,7 @@ static int mxs_gpio_probe(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxs_of_to_plat(struct udevice *dev) { struct mxs_gpio_plat *plat = dev_get_plat(dev); @@ -301,7 +301,7 @@ U_BOOT_DRIVER(fsl_imx23_gpio) = { .probe = mxs_gpio_probe, .priv_auto = sizeof(struct mxs_gpio_priv), .plat_auto = sizeof(struct mxs_gpio_plat), -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxs_gpio_ids, .of_to_plat = mxs_of_to_plat, #endif diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c index 316a28efa6..50c4f75ddf 100644 --- a/drivers/gpio/omap_gpio.c +++ b/drivers/gpio/omap_gpio.c @@ -336,7 +336,7 @@ static int omap_gpio_bind(struct udevice *dev) } #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id omap_gpio_ids[] = { { .compatible = "ti,omap3-gpio" }, { .compatible = "ti,omap4-gpio" }, @@ -362,7 +362,7 @@ U_BOOT_DRIVER(gpio_omap) = { .name = "gpio_omap", .id = UCLASS_GPIO, #if CONFIG_IS_ENABLED(OF_CONTROL) -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_gpio_ids, .of_to_plat = of_match_ptr(omap_gpio_of_to_plat), .plat_auto = sizeof(struct omap_gpio_plat), diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index d008fdd222..106b2a7b27 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -323,11 +323,13 @@ static const struct dm_gpio_ops gpio_sandbox_ops = { static int sandbox_gpio_of_to_plat(struct udevice *dev) { - struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); - uc_priv->gpio_count = dev_read_u32_default(dev, "sandbox,gpio-count", - 0); - uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); + uc_priv->gpio_count = + dev_read_u32_default(dev, "sandbox,gpio-count", 0); + uc_priv->bank_name = dev_read_string(dev, "gpio-bank-name"); + } return 0; } @@ -371,6 +373,8 @@ U_BOOT_DRIVER(sandbox_gpio) = { DM_DRIVER_ALIAS(sandbox_gpio, sandbox_gpio_alias) +#if CONFIG_IS_ENABLED(PINCTRL) + /* pincontrol: used only to check GPIO pin configuration (pinmux command) */ struct sb_pinctrl_priv { @@ -579,3 +583,5 @@ U_BOOT_DRIVER(sandbox_pinctrl_gpio) = { .priv_auto = sizeof(struct sb_pinctrl_priv), ACPI_OPS_PTR(&pinctrl_sandbox_acpi_ops) }; + +#endif /* PINCTRL */ diff --git a/drivers/gpio/sandbox_test.c b/drivers/gpio/sandbox_test.c new file mode 100644 index 0000000000..c76e199741 --- /dev/null +++ b/drivers/gpio/sandbox_test.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for testing GPIOs with of-platdata + * + * Copyright 2021 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <asm-generic/gpio.h> + +static const struct udevice_id sandbox_gpio_test_ids[] = { + { .compatible = "sandbox,gpio-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_gpio_test) = { + .name = "sandbox_gpio_test", + .id = UCLASS_MISC, + .of_match = sandbox_gpio_test_ids, +}; diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index 5d3af8a016..e00f104b9f 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -23,8 +23,8 @@ #include <dm/device-internal.h> #include <dt-bindings/gpio/gpio.h> -static const int CONFIG_SFIO = 0; -static const int CONFIG_GPIO = 1; +static const int CFG_SFIO = 0; +static const int CFG_GPIO = 1; static const int DIRECTION_INPUT = 0; static const int DIRECTION_OUTPUT = 1; @@ -54,7 +54,7 @@ static int get_config(unsigned gpio) debug("get_config: port = %d, bit = %d is %s\n", GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); - return type ? CONFIG_GPIO : CONFIG_SFIO; + return type ? CFG_GPIO : CFG_SFIO; } /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */ @@ -68,7 +68,7 @@ static void set_config(unsigned gpio, int type) GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO"); u = readl(&bank->gpio_config[GPIO_PORT(gpio)]); - if (type != CONFIG_SFIO) + if (type != CFG_SFIO) u |= 1 << GPIO_BIT(gpio); else u &= ~(1 << GPIO_BIT(gpio)); @@ -216,7 +216,7 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) set_direction(config[i].gpio, DIRECTION_OUTPUT); break; } - set_config(config[i].gpio, CONFIG_GPIO); + set_config(config[i].gpio, CFG_GPIO); } } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 63d03a3ceb..57cac4483f 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -47,6 +47,35 @@ config SPL_DM_I2C device (bus child) info is kept as parent platdata. The interface is defined in include/i2c.h. +config SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers" + depends on !DM_I2C + help + Enable the legacy I2C subsystem and drivers. While this is + deprecated in U-Boot itself, this can be useful in some situations + in SPL or TPL. + +config SPL_SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers in SPL" + depends on SUPPORT_SPL && !SPL_DM_I2C + help + Enable the legacy I2C subsystem and drivers in SPL. This is useful + in some size constrained situations. + +config TPL_SYS_I2C_LEGACY + bool "Enable legacy I2C subsystem and drivers in TPL" + depends on SUPPORT_TPL && !SPL_DM_I2C + help + Enable the legacy I2C subsystem and drivers in TPL. This is useful + in some size constrained situations. + +config SYS_I2C_EARLY_INIT + bool "Enable legacy I2C subsystem early in boot" + depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC + help + Add the function prototype for i2c_early_init_f which is called in + board_early_init_f. + config I2C_CROS_EC_TUNNEL tristate "Chrome OS EC tunnel I2C bus" depends on CROS_EC @@ -124,11 +153,36 @@ config SYS_I2C_IPROC config SYS_I2C_FSL bool "Freescale I2C bus driver" - depends on DM_I2C help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. +if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) +config SYS_FSL_I2C_OFFSET + hex "Offset from the IMMR of the address of the first I2C controller" + +config SYS_FSL_HAS_I2C2_OFFSET + bool "Support a second I2C controller" + +config SYS_FSL_I2C2_OFFSET + hex "Offset from the IMMR of the address of the second I2C controller" + depends on SYS_FSL_HAS_I2C2_OFFSET + +config SYS_FSL_HAS_I2C3_OFFSET + bool "Support a third I2C controller" + +config SYS_FSL_I2C3_OFFSET + hex "Offset from the IMMR of the address of the third I2C controller" + depends on SYS_FSL_HAS_I2C3_OFFSET + +config SYS_FSL_HAS_I2C4_OFFSET + bool "Support a fourth I2C controller" + +config SYS_FSL_I2C4_OFFSET + hex "Offset from the IMMR of the address of the fourth I2C controller" + depends on SYS_FSL_HAS_I2C4_OFFSET +endif + config SYS_I2C_CADENCE tristate "Cadence I2C Controller" depends on DM_I2C @@ -139,7 +193,6 @@ config SYS_I2C_CADENCE config SYS_I2C_CA tristate "Cortina-Access I2C Controller" depends on DM_I2C && CORTINA_PLATFORM - default n help Add support for the Cortina Access I2C host controller. Say yes here to select Cortina-Access I2C Host Controller. @@ -152,7 +205,6 @@ config SYS_I2C_DAVINCI config SYS_I2C_DW bool "Designware I2C Controller" - default n help Say yes here to select the Designware I2C Host Controller. This controller is used in various SoCs, e.g. the ST SPEAr, Altera @@ -205,10 +257,7 @@ config SYS_I2C_MXC channels and operating on standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. -# These settings are not used with DM_I2C, however SPL doesn't use -# DM_I2C even if DM_I2C is enabled, and so might use these settings even -# when main u-boot does not! -if SYS_I2C_MXC && (!DM_I2C || SPL) +if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_I2C_MXC_I2C1 bool "NXP MXC I2C1" help @@ -267,7 +316,7 @@ config SYS_MXC_I2C1_SPEED MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE - int "I2C1 Slave" + hex "I2C1 Slave" default 0 help MXC I2C1 Slave @@ -282,7 +331,7 @@ config SYS_MXC_I2C2_SPEED MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE - int "I2C2 Slave" + hex "I2C2 Slave" default 0 help MXC I2C2 Slave @@ -296,7 +345,7 @@ config SYS_MXC_I2C3_SPEED MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE - int "I2C3 Slave" + hex "I2C3 Slave" default 0 help MXC I2C3 Slave @@ -310,7 +359,7 @@ config SYS_MXC_I2C4_SPEED MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE - int "I2C4 Slave" + hex "I2C4 Slave" default 0 help MXC I2C4 Slave @@ -324,7 +373,7 @@ config SYS_MXC_I2C5_SPEED MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE - int "I2C5 Slave" + hex "I2C5 Slave" default 0 help MXC I2C5 Slave @@ -338,7 +387,7 @@ config SYS_MXC_I2C6_SPEED MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE - int "I2C6 Slave" + hex "I2C6 Slave" default 0 help MXC I2C6 Slave @@ -352,7 +401,7 @@ config SYS_MXC_I2C7_SPEED MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE - int "I2C7 Slave" + hex "I2C7 Slave" default 0 help MXC I2C7 Slave @@ -366,7 +415,7 @@ config SYS_MXC_I2C8_SPEED MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE - int "I2C8 Slave" + hex "I2C8 Slave" default 0 help MXC I2C8 Slave @@ -394,20 +443,6 @@ config SYS_I2C_OMAP24XX help Add support for the OMAP2+ I2C driver. -if SYS_I2C_OMAP24XX -config SYS_OMAP24_I2C_SLAVE - int "I2C Slave addr channel 0" - default 1 - help - OMAP24xx I2C Slave address channel 0 - -config SYS_OMAP24_I2C_SPEED - int "I2C Slave channel 0 speed" - default 100000 - help - OMAP24xx Slave speed channel 0 -endif - config SYS_I2C_RCAR_I2C bool "Renesas RCar I2C driver" depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C @@ -437,6 +472,73 @@ config SYS_I2C_SANDBOX bus. Devices can be attached to the bus using the device tree which specifies the driver to use. See sandbox.dts as an example. +config SYS_I2C_SH + bool "Legacy SuperH I2C interface" + depends on ARCH_RMOBILE && SYS_I2C_LEGACY + help + Enable the legacy SuperH I2C interface. + +if SYS_I2C_SH +config SYS_I2C_SH_NUM_CONTROLLERS + int + default 5 + +config SYS_I2C_SH_BASE0 + hex + default 0xE6820000 + +config SYS_I2C_SH_BASE1 + hex + default 0xE6822000 + +config SYS_I2C_SH_BASE2 + hex + default 0xE6824000 + +config SYS_I2C_SH_BASE3 + hex + default 0xE6826000 + +config SYS_I2C_SH_BASE4 + hex + default 0xE6828000 + +config SH_I2C_8BIT + bool + default y + +config SH_I2C_DATA_HIGH + int + default 4 + +config SH_I2C_DATA_LOW + int + default 5 + +config SH_I2C_CLOCK + int + default 104000000 +endif + +config SYS_I2C_SOFT + bool "Legacy software I2C interface" + help + Enable the legacy software defined I2C interface + +config SYS_I2C_SOFT_SPEED + int "Software I2C bus speed" + depends on SYS_I2C_SOFT + default 100000 + help + Speed of the software I2C bus + +config SYS_I2C_SOFT_SLAVE + hex "Software I2C slave address" + depends on SYS_I2C_SOFT + default 0xfe + help + Slave address of the software I2C bus + config SYS_I2C_OCTEON bool "Octeon II/III/TX/TX2 I2C driver" depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C @@ -449,7 +551,7 @@ config SYS_I2C_OCTEON config SYS_I2C_S3C24X0 bool "Samsung I2C driver" - depends on ARCH_EXYNOS4 && DM_I2C + depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C help Support for Samsung I2C controller as Samsung SoCs. @@ -511,7 +613,6 @@ config SYS_I2C_VERSATILE config SYS_I2C_MVTWSI bool "Marvell I2C driver" - depends on DM_I2C help Support for Marvell I2C controllers as used on the orion5x and kirkwood SoC families. @@ -526,6 +627,25 @@ config TEGRA186_BPMP_I2C by the BPMP, and can only be accessed by the main CPU via IPC requests to the BPMP. This driver covers the latter case. +config SYS_I2C_SLAVE + hex "I2C Slave address channel (all buses)" + depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY + default 0xfe + help + I2C Slave address channel 0 for all buses in the legacy drivers. + Many boards/controllers/drivers don't support an I2C slave + interface so provide a default slave address for them for use in + common code. A real value for CONFIG_SYS_I2C_SLAVE should be + defined for any board which does support a slave interface and + this default used otherwise. + +config SYS_I2C_SPEED + int "I2C Slave channel 0 speed (all buses)" + depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY + default 100000 + help + I2C Slave speed channel 0 for all buses in the legacy drivers. + config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index c16ebb2491..67841bf3e0 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o obj-$(CONFIG_I2C_MV) += mv_i2c.o -obj-$(CONFIG_SYS_I2C_LEGACY) += i2c_core.o +obj-$(CONFIG_$(SPL_)SYS_I2C_LEGACY) += i2c_core.o obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e57eed0f6c..d95f77649e 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -674,24 +674,6 @@ U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, dw_i2c_write, dw_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) -#if CONFIG_SYS_I2C_BUS_MAX >= 2 -U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1) -#endif - -#if CONFIG_SYS_I2C_BUS_MAX >= 3 -U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2) -#endif - -#if CONFIG_SYS_I2C_BUS_MAX >= 4 -U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read, - dw_i2c_write, dw_i2c_set_bus_speed, - CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3) -#endif - #else /* CONFIG_DM_I2C */ /* The DM I2C functions */ diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 2200303ea8..eafd801cdc 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -538,24 +538,24 @@ static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) */ U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) #ifdef CONFIG_SYS_FSL_I2C2_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1) #endif #ifdef CONFIG_SYS_FSL_I2C3_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2) #endif #ifdef CONFIG_SYS_FSL_I2C4_OFFSET U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read, fsl_i2c_write, fsl_i2c_set_bus_speed, - CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE, + CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3) #endif #else /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/i2c-emul-uclass.c b/drivers/i2c/i2c-emul-uclass.c index aeec6aa9fa..1107cf309f 100644 --- a/drivers/i2c/i2c-emul-uclass.c +++ b/drivers/i2c/i2c-emul-uclass.c @@ -79,7 +79,7 @@ UCLASS_DRIVER(i2c_emul) = { UCLASS_DRIVER(i2c_emul_parent) = { .id = UCLASS_I2C_EMUL_PARENT, .name = "i2c_emul_parent", -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index db1c9d9462..71bc2b5b8a 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -633,7 +633,7 @@ int i2c_deblock(struct udevice *bus) return ops->deblock(bus); } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip) { int addr; @@ -655,7 +655,7 @@ int i2c_chip_of_to_plat(struct udevice *dev, struct dm_i2c_chip *chip) static int i2c_pre_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); unsigned int max = 0; ofnode node; @@ -678,7 +678,7 @@ static int i2c_pre_probe(struct udevice *dev) static int i2c_post_probe(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); i2c->speed_hz = dev_read_u32_default(dev, "clock-frequency", @@ -692,7 +692,7 @@ static int i2c_post_probe(struct udevice *dev) static int i2c_child_post_bind(struct udevice *dev) { -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct dm_i2c_chip *plat = dev_get_parent_plat(dev); if (!dev_has_ofnode(dev)) @@ -709,7 +709,7 @@ static int i2c_post_bind(struct udevice *dev) debug("%s: %s, seq=%d\n", __func__, dev->name, dev_seq(dev)); -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) ret = dm_scan_fdt_dev(dev); #endif return ret; diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 85cf75ecd9..09f91e674d 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -190,11 +190,6 @@ __weak void i2c_init_board(void) { } -/* implement possible for i2c specific early i2c init */ -__weak void i2c_early_init_f(void) -{ -} - /* * i2c_init_all(): * diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c index 02f0144930..ecca90628e 100644 --- a/drivers/i2c/ihs_i2c.c +++ b/drivers/i2c/ihs_i2c.c @@ -6,19 +6,14 @@ #include <common.h> #include <i2c.h> -#if CONFIG_IS_ENABLED(DM_I2C) #include <dm.h> #include <regmap.h> -#else -#include <gdsys_fpga.h> -#endif #include <log.h> #include <asm/global_data.h> #include <asm/unaligned.h> #include <linux/bitops.h> #include <linux/delay.h> -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv { uint speed; struct regmap *map; @@ -39,37 +34,6 @@ struct ihs_i2c_regs { #define ihs_i2c_get(map, member, valp) \ regmap_get(map, struct ihs_i2c_regs, member, valp) -#else /* !CONFIG_DM_I2C */ -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SYS_I2C_IHS_DUAL - -#define I2C_SET_REG(fld, val) \ - do { \ - if (I2C_ADAP_HWNR & 0x10) \ - FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ - else \ - FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ - } while (0) -#else -#define I2C_SET_REG(fld, val) \ - FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val) -#endif - -#ifdef CONFIG_SYS_I2C_IHS_DUAL -#define I2C_GET_REG(fld, val) \ - do { \ - if (I2C_ADAP_HWNR & 0x10) \ - FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \ - else \ - FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \ - } while (0) -#else -#define I2C_GET_REG(fld, val) \ - FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val) -#endif -#endif /* CONFIG_DM_I2C */ - enum { I2CINT_ERROR_EV = BIT(13), I2CINT_TRANSMIT_EV = BIT(14), @@ -91,23 +55,13 @@ enum { I2COP_READ = 1, }; -#if CONFIG_IS_ENABLED(DM_I2C) static int wait_for_int(struct udevice *dev, int read) -#else -static int wait_for_int(bool read) -#endif { u16 val; uint ctr = 0; -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv *priv = dev_get_priv(dev); -#endif -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_GET_REG(interrupt_status, &val); -#endif /* Wait until error or receive/transmit interrupt was raised */ while (!(val & (I2CINT_ERROR_EV | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) { @@ -116,40 +70,24 @@ static int wait_for_int(bool read) debug("%s: timed out\n", __func__); return -ETIMEDOUT; } -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_GET_REG(interrupt_status, &val); -#endif } return (val & I2CINT_ERROR_EV) ? -EIO : 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_transfer(struct udevice *dev, uchar chip, uchar *buffer, int len, int read, bool is_last) -#else -static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, - bool is_last) -#endif { u16 val; u16 data; int res; -#if CONFIG_IS_ENABLED(DM_I2C) struct ihs_i2c_priv *priv = dev_get_priv(dev); -#endif /* Clear interrupt status */ data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV; -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, interrupt_status, data); ihs_i2c_get(priv->map, interrupt_status, &val); -#else - I2C_SET_REG(interrupt_status, data); - I2C_GET_REG(interrupt_status, &val); -#endif /* If we want to write and have data, write the bytes to the mailbox */ if (!read && len) { @@ -157,11 +95,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, if (len > 1) val |= buffer[1] << 8; -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, write_mailbox_ext, val); -#else - I2C_SET_REG(write_mailbox_ext, val); -#endif } data = I2CMB_NATIVE @@ -170,17 +104,9 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, | ((len > 1) ? I2CMB_2BYTE : 0) | (is_last ? 0 : I2CMB_HOLD_BUS); -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_set(priv->map, write_mailbox, data); -#else - I2C_SET_REG(write_mailbox, data); -#endif -#if CONFIG_IS_ENABLED(DM_I2C) res = wait_for_int(dev, read); -#else - res = wait_for_int(read); -#endif if (res) { if (res == -ETIMEDOUT) debug("%s: time out while waiting for event\n", __func__); @@ -190,11 +116,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, /* If we want to read, get the bytes from the mailbox */ if (read) { -#if CONFIG_IS_ENABLED(DM_I2C) ihs_i2c_get(priv->map, read_mailbox_ext, &val); -#else - I2C_GET_REG(read_mailbox_ext, &val); -#endif buffer[0] = val & 0xff; if (len > 1) buffer[1] = val >> 8; @@ -203,12 +125,7 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read, return 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read) -#else -static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, - int read) -#endif { int res; @@ -216,13 +133,8 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, int transfer = min(len, 2); bool is_last = len <= transfer; -#if CONFIG_IS_ENABLED(DM_I2C) res = ihs_i2c_transfer(dev, chip, data, transfer, read, hold_bus ? false : is_last); -#else - res = ihs_i2c_transfer(chip, data, transfer, read, - hold_bus ? false : is_last); -#endif if (res) return res; @@ -233,27 +145,14 @@ static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus, return 0; } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen, bool hold_bus) -#else -static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus) -#endif { -#if CONFIG_IS_ENABLED(DM_I2C) return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE); -#else - return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE); -#endif } -#if CONFIG_IS_ENABLED(DM_I2C) static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr, int alen, uchar *buffer, int len, int read) -#else -static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, - int alen, uchar *buffer, int len, int read) -#endif { int res; @@ -261,23 +160,13 @@ static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr, if (len <= 0) return -EINVAL; -#if CONFIG_IS_ENABLED(DM_I2C) res = ihs_i2c_address(dev, chip, addr, alen, len); -#else - res = ihs_i2c_address(chip, addr, alen, len); -#endif if (res) return res; -#if CONFIG_IS_ENABLED(DM_I2C) return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read); -#else - return ihs_i2c_send_buffer(chip, buffer, len, false, read); -#endif } -#if CONFIG_IS_ENABLED(DM_I2C) - int ihs_i2c_probe(struct udevice *bus) { struct ihs_i2c_priv *priv = dev_get_priv(bus); @@ -358,120 +247,3 @@ U_BOOT_DRIVER(i2c_ihs) = { .priv_auto = sizeof(struct ihs_i2c_priv), .ops = &ihs_i2c_ops, }; - -#else /* CONFIG_DM_I2C */ - -static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* - * Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif -} - -static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip) -{ - uchar buffer[2]; - int res; - - res = ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true); - if (res) - return res; - - return 0; -} - -static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - u8 addr_bytes[4]; - - put_unaligned_le32(addr, addr_bytes); - - return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, - I2COP_READ); -} - -static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - u8 addr_bytes[4]; - - put_unaligned_le32(addr, addr_bytes); - - return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len, - I2COP_WRITE); -} - -static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int speed) -{ - if (speed != adap->speed) - return -EINVAL; - return speed; -} - -/* - * Register IHS i2c adapters - */ -#ifdef CONFIG_SYS_I2C_IHS_CH0 -U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_0, - CONFIG_SYS_I2C_IHS_SLAVE_0, 0) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_0_1, - CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH1 -U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_1, - CONFIG_SYS_I2C_IHS_SLAVE_1, 1) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_1_1, - CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH2 -U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_2, - CONFIG_SYS_I2C_IHS_SLAVE_2, 2) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_2_1, - CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18) -#endif -#endif -#ifdef CONFIG_SYS_I2C_IHS_CH3 -U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_3, - CONFIG_SYS_I2C_IHS_SLAVE_3, 3) -#ifdef CONFIG_SYS_I2C_IHS_DUAL -U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe, - ihs_i2c_read, ihs_i2c_write, - ihs_i2c_set_bus_speed, - CONFIG_SYS_I2C_IHS_SPEED_3_1, - CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19) -#endif -#endif -#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 20c5de0007..0eff353161 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -80,7 +80,7 @@ static void i2c_reset(struct mv_i2c *base) i2c_clk_enable(); - writel(CONFIG_SYS_I2C_SLAVE, &base->isar); /* set our slave address */ + writel(0x0, &base->isar); /* set our slave address */ /* set control reg values */ writel(I2C_ICR_INIT | icr_mode, &base->icr); writel(I2C_ISR_INIT, &base->isr); /* set clear interrupt bits */ diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index d33e2c7c9d..236bfb8d8e 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -17,7 +17,9 @@ #include <linux/bitops.h> #include <linux/compat.h> #if CONFIG_IS_ENABLED(DM_I2C) +#include <clk.h> #include <dm.h> +#include <reset.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -835,7 +837,18 @@ static int mvtwsi_i2c_bind(struct udevice *bus) static int mvtwsi_i2c_probe(struct udevice *bus) { struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + struct reset_ctl reset; + struct clk clk; uint actual_speed; + int ret; + + ret = reset_get_by_index(bus, 0, &reset); + if (!ret) + reset_deassert(&reset); + + ret = clk_get_by_index(bus, 0, &clk); + if (!ret) + clk_enable(&clk); __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); dev->speed = actual_speed; diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 003aa33f6e..5057bd9665 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -110,32 +110,6 @@ static u16 i2c_clk_div[50][2] = { }; #endif -#ifndef CONFIG_SYS_MXC_I2C1_SPEED -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C2_SPEED -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C3_SPEED -#define CONFIG_SYS_MXC_I2C3_SPEED 100000 -#endif -#ifndef CONFIG_SYS_MXC_I2C4_SPEED -#define CONFIG_SYS_MXC_I2C4_SPEED 100000 -#endif - -#ifndef CONFIG_SYS_MXC_I2C1_SLAVE -#define CONFIG_SYS_MXC_I2C1_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C2_SLAVE -#define CONFIG_SYS_MXC_I2C2_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C3_SLAVE -#define CONFIG_SYS_MXC_I2C3_SLAVE 0 -#endif -#ifndef CONFIG_SYS_MXC_I2C4_SLAVE -#define CONFIG_SYS_MXC_I2C4_SLAVE 0 -#endif - /* * Calculate and set proper clock divider */ diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 71f6f5f7ac..a767dee986 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -936,62 +936,34 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); } -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) -#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) -#define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, - CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 0) U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, - CONFIG_SYS_OMAP24_I2C_SPEED1, - CONFIG_SYS_OMAP24_I2C_SLAVE1, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 1) #if (CONFIG_SYS_I2C_BUS_MAX > 2) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) -#define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) -#define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED2, - CONFIG_SYS_OMAP24_I2C_SLAVE2, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 2) #if (CONFIG_SYS_I2C_BUS_MAX > 3) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) -#define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) -#define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED3, - CONFIG_SYS_OMAP24_I2C_SLAVE3, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 3) #if (CONFIG_SYS_I2C_BUS_MAX > 4) -#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) -#define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED -#endif -#if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) -#define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE -#endif - U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, omap24_i2c_read, omap24_i2c_write, NULL, - CONFIG_SYS_OMAP24_I2C_SPEED4, - CONFIG_SYS_OMAP24_I2C_SLAVE4, + CONFIG_SYS_I2C_SPEED, + CONFIG_SYS_I2C_SLAVE, 4) #endif #endif @@ -1062,7 +1034,7 @@ static int omap_i2c_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int omap_i2c_of_to_plat(struct udevice *bus) { struct omap_i2c_plat *plat = dev_get_plat(bus); @@ -1091,7 +1063,7 @@ static const struct dm_i2c_ops omap_i2c_ops = { U_BOOT_DRIVER(i2c_omap) = { .name = "i2c_omap", .id = UCLASS_I2C, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_i2c_ids, .of_to_plat = omap_i2c_of_to_plat, .plat_auto = sizeof(struct omap_i2c_plat), diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c index 14bb6603d5..d9ece5e3a8 100644 --- a/drivers/i2c/rcar_i2c.c +++ b/drivers/i2c/rcar_i2c.c @@ -64,6 +64,8 @@ enum rcar_i2c_type { struct rcar_i2c_priv { void __iomem *base; struct clk clk; + u32 fall_ns; + u32 rise_ns; u32 intdelay; u32 icccr; enum rcar_i2c_type type; @@ -278,7 +280,7 @@ static int rcar_i2c_set_speed(struct udevice *dev, uint bus_freq_hz) * = F[sum * ick / 1000000000] * = F[(ick / 1000000) * sum / 1000] */ - sum = 35 + 200 + priv->intdelay; + sum = priv->fall_ns + priv->rise_ns + priv->intdelay; round = (ick + 500000) / 1000000 * sum; round = (round + 500) / 1000; @@ -323,6 +325,10 @@ static int rcar_i2c_probe(struct udevice *dev) int ret; priv->base = dev_read_addr_ptr(dev); + priv->rise_ns = dev_read_u32_default(dev, + "i2c-scl-rising-time-ns", 200); + priv->fall_ns = dev_read_u32_default(dev, + "i2c-scl-falling-time-ns", 35); priv->intdelay = dev_read_u32_default(dev, "i2c-scl-internal-delay-ns", 5); priv->type = dev_get_driver_data(dev); diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 56f0f69885..e0f499d759 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -21,12 +21,6 @@ #include <i2c.h> #include "s3c24x0_i2c.h" -#ifndef CONFIG_SYS_I2C_S3C24X0_SLAVE -#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 -#else -#define SYS_I2C_S3C24X0_SLAVE_ADDR CONFIG_SYS_I2C_S3C24X0_SLAVE -#endif - DECLARE_GLOBAL_DATA_PTR; /* @@ -83,6 +77,8 @@ static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); } +#define SYS_I2C_S3C24X0_SLAVE_ADDR 0 + static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) { struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev); diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 26a8700669..6cecec4145 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -294,20 +294,20 @@ static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, * Register RCAR i2c adapters */ U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0) #ifdef CONFIG_SYS_I2C_SH_BASE1 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1) #endif #ifdef CONFIG_SYS_I2C_SH_BASE2 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2) #endif #ifdef CONFIG_SYS_I2C_SH_BASE3 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3) #endif #ifdef CONFIG_SYS_I2C_SH_BASE4 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, - sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) + sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4) #endif diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index db69c18cb6..c72839eb01 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -438,80 +438,3 @@ U_BOOT_I2C_ADAP_COMPLETE(soft00, soft_i2c_init, soft_i2c_probe, soft_i2c_read, soft_i2c_write, NULL, CONFIG_SYS_I2C_SOFT_SPEED, CONFIG_SYS_I2C_SOFT_SLAVE, 0) -#if defined(I2C_SOFT_DECLARATIONS2) -U_BOOT_I2C_ADAP_COMPLETE(soft01, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_2, - CONFIG_SYS_I2C_SOFT_SLAVE_2, - 1) -#endif -#if defined(I2C_SOFT_DECLARATIONS3) -U_BOOT_I2C_ADAP_COMPLETE(soft02, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_3, - CONFIG_SYS_I2C_SOFT_SLAVE_3, - 2) -#endif -#if defined(I2C_SOFT_DECLARATIONS4) -U_BOOT_I2C_ADAP_COMPLETE(soft03, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_4, - CONFIG_SYS_I2C_SOFT_SLAVE_4, - 3) -#endif -#if defined(I2C_SOFT_DECLARATIONS5) -U_BOOT_I2C_ADAP_COMPLETE(soft04, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_5, - CONFIG_SYS_I2C_SOFT_SLAVE_5, - 4) -#endif -#if defined(I2C_SOFT_DECLARATIONS6) -U_BOOT_I2C_ADAP_COMPLETE(soft05, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_6, - CONFIG_SYS_I2C_SOFT_SLAVE_6, - 5) -#endif -#if defined(I2C_SOFT_DECLARATIONS7) -U_BOOT_I2C_ADAP_COMPLETE(soft06, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_7, - CONFIG_SYS_I2C_SOFT_SLAVE_7, - 6) -#endif -#if defined(I2C_SOFT_DECLARATIONS8) -U_BOOT_I2C_ADAP_COMPLETE(soft07, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_8, - CONFIG_SYS_I2C_SOFT_SLAVE_8, - 7) -#endif -#if defined(I2C_SOFT_DECLARATIONS9) -U_BOOT_I2C_ADAP_COMPLETE(soft08, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_9, - CONFIG_SYS_I2C_SOFT_SLAVE_9, - 8) -#endif -#if defined(I2C_SOFT_DECLARATIONS10) -U_BOOT_I2C_ADAP_COMPLETE(soft09, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_10, - CONFIG_SYS_I2C_SOFT_SLAVE_10, - 9) -#endif -#if defined(I2C_SOFT_DECLARATIONS11) -U_BOOT_I2C_ADAP_COMPLETE(soft10, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_11, - CONFIG_SYS_I2C_SOFT_SLAVE_11, - 10) -#endif -#if defined(I2C_SOFT_DECLARATIONS12) -U_BOOT_I2C_ADAP_COMPLETE(soft11, soft_i2c_init, soft_i2c_probe, - soft_i2c_read, soft_i2c_write, NULL, - CONFIG_SYS_I2C_SOFT_SPEED_12, - CONFIG_SYS_I2C_SOFT_SLAVE_12, - 11) -#endif diff --git a/drivers/input/i8042.c b/drivers/input/i8042.c index 565d99e7e5..d3743dc37f 100644 --- a/drivers/input/i8042.c +++ b/drivers/input/i8042.c @@ -150,8 +150,8 @@ static int kbd_reset(int quirk) else if ((quirk & QUIRK_DUP_POR) && config == KBD_POR) config = kbd_cmd_read(CMD_RD_CONFIG); - config |= CONFIG_AT_TRANS; - config &= ~(CONFIG_KIRQ_EN | CONFIG_MIRQ_EN); + config |= CFG_AT_TRANS; + config &= ~(CFG_KIRQ_EN | CFG_MIRQ_EN); if (kbd_cmd_write(CMD_WR_CONFIG, config)) goto err; diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c index 6250e274e1..c4bc88c151 100644 --- a/drivers/memory/ti-aemif.c +++ b/drivers/memory/ti-aemif.c @@ -9,11 +9,10 @@ #include <common.h> #include <asm/ti-common/ti-aemif.h> -#define AEMIF_WAITCYCLE_CONFIG (CONFIG_AEMIF_CNTRL_BASE + 0x4) -#define AEMIF_NAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x60) -#define AEMIF_ONENAND_CONTROL (CONFIG_AEMIF_CNTRL_BASE + 0x5c) -#define AEMIF_CONFIG(cs) (CONFIG_AEMIF_CNTRL_BASE + 0x10 \ - + (cs * 4)) +#define AEMIF_WAITCYCLE_CONFIG (KS2_AEMIF_CNTRL_BASE + 0x4) +#define AEMIF_NAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x60) +#define AEMIF_ONENAND_CONTROL (KS2_AEMIF_CNTRL_BASE + 0x5c) +#define AEMIF_CONFIG(cs) (KS2_AEMIF_CNTRL_BASE + 0x10 + (cs * 4)) #define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) #define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 997b713221..099ff29348 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -398,36 +398,12 @@ config SPL_I2C_EEPROM This option is an SPL-variant of the I2C_EEPROM option. See the help of I2C_EEPROM for details. -if I2C_EEPROM - config SYS_I2C_EEPROM_ADDR hex "Chip address of the EEPROM device" + depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM default 0 -config SYS_I2C_EEPROM_BUS - int "I2C bus of the EEPROM device." - default 0 - -config SYS_EEPROM_SIZE - int "Size in bytes of the EEPROM device" - default 256 - -config SYS_EEPROM_PAGE_WRITE_BITS - int "Number of bits used to address bytes in a single page" - default 0 - help - The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. - A 64 byte page, for example would require six bits. - -config SYS_EEPROM_PAGE_WRITE_DELAY_MS - int "Number of milliseconds to delay between page writes" - default 0 - -config SYS_I2C_EEPROM_ADDR_LEN - int "Length in bytes of the EEPROM memory array address" - default 1 - help - Note: This is NOT the chip address length! +if I2C_EEPROM config SYS_I2C_EEPROM_ADDR_OVERFLOW hex "EEPROM Address Overflow" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b64cd2a4de..c16a77c34c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -42,7 +42,7 @@ obj-$(CONFIG_GDSYS_IOEP) += gdsys_ioep.o obj-$(CONFIG_GDSYS_RXAUI_CTRL) += gdsys_rxaui_ctrl.o obj-$(CONFIG_GDSYS_SOC) += gdsys_soc.o obj-$(CONFIG_IRQ) += irq-uclass.o -obj-$(CONFIG_SANDBOX) += irq_sandbox.o +obj-$(CONFIG_SANDBOX) += irq_sandbox.o irq_sandbox_test.o obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 2a15094d20..1bbc0f98ae 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -1671,7 +1671,7 @@ UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros-ec", .per_device_auto = sizeof(struct cros_ec_dev), -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .flags = DM_UC_FLAG_ALLOC_PRIV_DMA, diff --git a/drivers/misc/irq-uclass.c b/drivers/misc/irq-uclass.c index 3aa26f61d9..eb9f3b902f 100644 --- a/drivers/misc/irq-uclass.c +++ b/drivers/misc/irq-uclass.c @@ -64,8 +64,8 @@ int irq_read_and_clear(struct irq *irq) } #if CONFIG_IS_ENABLED(OF_PLATDATA) -int irq_get_by_driver_info(struct udevice *dev, - struct phandle_1_arg *cells, struct irq *irq) +int irq_get_by_phandle(struct udevice *dev, const struct phandle_2_arg *cells, + struct irq *irq) { int ret; @@ -74,6 +74,12 @@ int irq_get_by_driver_info(struct udevice *dev, return ret; irq->id = cells->arg[0]; + /* + * Note: we could call irq_of_xlate_default() here to do this properly. + * For now, this is good enough for existing cases. + */ + irq->flags = cells->arg[1]; + return 0; } #else diff --git a/drivers/misc/irq_sandbox.c b/drivers/misc/irq_sandbox.c index 1f7e62e661..8b5573fcad 100644 --- a/drivers/misc/irq_sandbox.c +++ b/drivers/misc/irq_sandbox.c @@ -9,19 +9,9 @@ #include <dm.h> #include <irq.h> #include <acpi/acpi_device.h> +#include <asm/irq.h> #include <asm/test.h> -/** - * struct sandbox_irq_priv - private data for this driver - * - * @count: Counts the number calls to the read_and_clear() method - * @pending: true if an interrupt is pending, else false - */ -struct sandbox_irq_priv { - int count; - bool pending; -}; - static int sandbox_set_polarity(struct udevice *dev, uint irq, bool active_low) { if (irq > 10) @@ -103,10 +93,11 @@ static const struct udevice_id sandbox_irq_ids[] = { { } }; -U_BOOT_DRIVER(sandbox_irq_drv) = { +U_BOOT_DRIVER(sandbox_irq) = { .name = "sandbox_irq", .id = UCLASS_IRQ, .of_match = sandbox_irq_ids, .ops = &sandbox_irq_ops, .priv_auto = sizeof(struct sandbox_irq_priv), + DM_HEADER(<asm/irq.h>) }; diff --git a/drivers/misc/irq_sandbox_test.c b/drivers/misc/irq_sandbox_test.c new file mode 100644 index 0000000000..95c45c24ed --- /dev/null +++ b/drivers/misc/irq_sandbox_test.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Sandbox driver for testing interrupts with of-platdata + * + * Copyright 2021 Google LLC + */ + +#include <common.h> +#include <dm.h> +#include <irq.h> +#include <asm/irq.h> + +static const struct udevice_id sandbox_irq_test_ids[] = { + { .compatible = "sandbox,irq-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_irq_test) = { + .name = "sandbox_irq_test", + .id = UCLASS_MISC, + .of_match = sandbox_irq_test_ids, +}; diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 72720b0e59..cbfacc3801 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -70,7 +70,7 @@ int misc_set_enabled(struct udevice *dev, bool val) UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c index 94d273de9b..f24857a151 100644 --- a/drivers/misc/p2sb-uclass.c +++ b/drivers/misc/p2sb-uclass.c @@ -183,16 +183,16 @@ int p2sb_set_port_id(struct udevice *dev, int portid) static int p2sb_child_post_bind(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); - int ret; - u32 pid; - - ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); - if (ret) - return ret; - pplat->pid = pid; -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct p2sb_child_plat *pplat = dev_get_parent_plat(dev); + int ret; + u32 pid; + + ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid); + if (ret) + return ret; + pplat->pid = pid; + } return 0; } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 1569e8c44a..e0927ce1c9 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -123,7 +123,6 @@ config MMC_IO_VOLTAGE config SPL_MMC_IO_VOLTAGE bool "Support IO voltage configuration in SPL" - default n help IO voltage configuration allows selecting the voltage level of the IO lines (not the level of main supply). This is required for UHS @@ -193,7 +192,6 @@ config MMC_VERBOSE config MMC_TRACE bool "MMC debugging" - default n help This is an option for use by developer. Enable MMC core debugging. @@ -221,7 +219,6 @@ config MMC_DW_CORTINA depends on DM_MMC depends on MMC_DW depends on BLK - default n help This selects support for Cortina SoC specific extensions to the Synopsys DesignWare Memory Card Interface driver. Select this option @@ -770,7 +767,6 @@ config FTSDC010 config FTSDC010_SDIO bool "Support ftsdc010 sdio" - default n depends on FTSDC010 help This can enable ftsdc010 sdio function. @@ -805,7 +801,6 @@ config FSL_ESDHC_SUPPORT_ADMA2 config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND bool "enable eSDHC workaround for 3.3v IO reliability issue" depends on FSL_ESDHC && DM_MMC - default n help When eSDHC operates at 3.3v, damage can accumulate in an internal level shifter at a higher than expected rate. The faster the interface diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index aabf39535f..5dfd484ef9 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1411,7 +1411,6 @@ __weak void init_clk_usdhc(u32 index) static int fsl_esdhc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct fsl_esdhc_priv *priv = dev_get_priv(dev); #if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; @@ -1419,10 +1418,12 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) #endif const void *fdt = gd->fdt_blob; int node = dev_of_offset(dev); - fdt_addr_t addr; unsigned int val; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; @@ -1494,7 +1495,7 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) priv->vs18_enable = 1; } #endif -#endif + return 0; } @@ -1598,11 +1599,11 @@ static int fsl_esdhc_probe(struct udevice *dev) return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = mmc_of_parse(dev, &plat->cfg); - if (ret) - return ret; -#endif + if (CONFIG_IS_ENABLED(OF_REAL)) { + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + } mmc = &plat->mmc; mmc->cfg = &plat->cfg; diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 0fa037224f..570d54cf9d 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -30,8 +30,6 @@ #include <syscon.h> #include <linux/err.h> -DECLARE_GLOBAL_DATA_PTR; - #define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ #define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ @@ -392,34 +390,29 @@ static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswid static int ftsdc010_mmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct ftsdc_priv *priv = dev_get_priv(dev); struct ftsdc010_chip *chip = &priv->chip; - chip->name = dev->name; - chip->ioaddr = dev_read_addr_ptr(dev); - chip->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "bus-width", 4); - chip->priv = dev; - priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "fifo-depth", 0); - priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "fifo-mode"); - if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), - "clock-freq-min-max", priv->minmax, 2)) { - int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "max-frequency", -EINVAL); - if (val < 0) - return val; - - priv->minmax[0] = 400000; /* 400 kHz */ - priv->minmax[1] = val; - } else { - debug("%s: 'clock-freq-min-max' property was deprecated.\n", - __func__); + + if (CONFIG_IS_ENABLED(OF_REAL)) { + chip->name = dev->name; + chip->ioaddr = dev_read_addr_ptr(dev); + chip->buswidth = dev_read_u32_default(dev, "bus-width", 4); + chip->priv = dev; + priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0); + priv->fifo_mode = dev_read_bool(dev, "fifo-mode"); + if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) { + if (dev_read_u32(dev, "max-frequency", &priv->minmax[1])) + return -EINVAL; + + priv->minmax[0] = 400000; /* 400 kHz */ + } else { + debug("%s: 'clock-freq-min-max' property was deprecated.\n", + __func__); + } } -#endif chip->sclk = priv->minmax[1]; chip->regs = chip->ioaddr; + return 0; } @@ -440,7 +433,7 @@ static int ftsdc010_mmc_probe(struct udevice *dev) chip->priv = dev; chip->dev_index = 1; memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #endif diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 8fd4176415..35a8e21058 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -665,7 +665,7 @@ static const struct dm_mmc_ops mxsmmc_ops = { .set_ios = mxsmmc_set_ios, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxsmmc_of_to_plat(struct udevice *bus) { struct mxsmmc_plat *plat = dev_get_plat(bus); @@ -709,7 +709,7 @@ static const struct udevice_id mxsmmc_ids[] = { U_BOOT_DRIVER(fsl_imx23_mmc) = { .name = "fsl_imx23_mmc", .id = UCLASS_MMC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxsmmc_ids, .of_to_plat = mxsmmc_of_to_plat, #endif diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 306ce0fe1e..820065800f 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -42,7 +42,7 @@ #include <asm/arch/mux_dra7xx.h> #include <asm/arch/dra7xx_iodelay.h> #endif -#if !defined(CONFIG_SOC_KEYSTONE) +#if !defined(CONFIG_ARCH_KEYSTONE) #include <asm/gpio.h> #include <asm/arch/sys_proto.h> #endif @@ -1559,7 +1559,7 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, priv->base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE; #if (defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) || \ defined(CONFIG_DRA7XX) || defined(CONFIG_AM33XX) || \ - defined(CONFIG_AM43XX) || defined(CONFIG_SOC_KEYSTONE)) && \ + defined(CONFIG_AM43XX) || defined(CONFIG_ARCH_KEYSTONE)) && \ defined(CONFIG_HSMMC2_8BIT) /* Enable 8-bit interface for eMMC on OMAP4/5 or DRA7XX */ host_caps_val |= MMC_MODE_8BIT; @@ -1891,7 +1891,7 @@ static int omap_hsmmc_get_pinctrl_state(struct mmc *mmc) } #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) #ifdef CONFIG_OMAP54XX __weak const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) { @@ -2009,7 +2009,7 @@ static int omap_hsmmc_probe(struct udevice *dev) return omap_hsmmc_init_setup(mmc); } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct omap_mmc_of_data dra7_mmc_of_data = { .controller_flags = OMAP_HSMMC_REQUIRE_IODELAY, @@ -2027,7 +2027,7 @@ static const struct udevice_id omap_hsmmc_ids[] = { U_BOOT_DRIVER(omap_hsmmc) = { .name = "omap_hsmmc", .id = UCLASS_MMC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_hsmmc_ids, .of_to_plat = omap_hsmmc_of_to_plat, .plat_auto = sizeof(struct omap_hsmmc_plat), diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index d7d5361fd5..7f8dea1e34 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -52,10 +52,12 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) static int rockchip_dwmmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + host->name = dev->name; host->ioaddr = dev_read_addr_ptr(dev); host->buswidth = dev_read_u32_default(dev, "bus-width", 4); @@ -95,7 +97,7 @@ static int rockchip_dwmmc_of_to_plat(struct udevice *dev) debug("%s: 'clock-freq-min-max' property was deprecated.\n", __func__); } -#endif + return 0; } @@ -121,7 +123,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev) priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #else diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index a901ce5511..bb8cffcabc 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -31,12 +31,10 @@ if NAND_ATMEL config ATMEL_NAND_HWECC bool "Atmel Hardware ECC" - default n config ATMEL_NAND_HW_PMECC bool "Atmel Programmable Multibit ECC (PMECC)" select ATMEL_NAND_HWECC - default n help The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. @@ -59,7 +57,6 @@ config SPL_GENERATE_ATMEL_PMECC_HEADER bool "Atmel PMECC Header Generation" select ATMEL_NAND_HWECC select ATMEL_NAND_HW_PMECC - default n help Generate Programmable Multibit ECC (PMECC) header for SPL image. @@ -108,6 +105,10 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms +config KEYSTONE_RBL_NAND + depends on ARCH_KEYSTONE + def_bool y + config NAND_DENALI bool select SYS_NAND_SELF_INIT diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index 9ad3a57690..ef8e85a002 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -347,9 +347,9 @@ static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = { }; #ifdef CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 11) #elif defined(CONFIG_SYS_NAND_PAGE_4K) -#define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12 +#define KEYSTONE_NAND_MAX_RBL_PAGE (0x100000 >> 12) #endif /** @@ -371,7 +371,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, struct nand_ecclayout *saved_ecc_layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { saved_ecc_layout = chip->ecc.layout; chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; @@ -402,7 +402,7 @@ static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip, err: /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } @@ -433,7 +433,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout; /* save current ECC layout and assign Keystone RBL ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst; mtd->oobavail = chip->ecc.layout->oobavail; } @@ -463,7 +463,7 @@ static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip * } /* restore ECC layout */ - if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) { + if (page < KEYSTONE_NAND_MAX_RBL_PAGE) { chip->ecc.layout = saved_ecc_layout; mtd->oobavail = saved_ecc_layout->oobavail; } diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c index ab91db8546..c827f80281 100644 --- a/drivers/mtd/nand/raw/denali.c +++ b/drivers/mtd/nand/raw/denali.c @@ -1246,7 +1246,7 @@ int denali_init(struct denali_nand_info *denali) denali->active_bank = DENALI_INVALID_BANK; - chip->flash_node = dev_of_offset(denali->dev); + chip->flash_node = dev_ofnode(denali->dev); /* Fallback to the default name if DT did not give "label" property */ if (!mtd->name) mtd->name = "denali-nand"; diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e6bbfac4d6..748056a43e 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1379,7 +1379,7 @@ int mxs_nand_init_ctrl(struct mxs_nand_info *nand_info) nand->options |= NAND_NO_SUBPAGE_WRITE; if (nand_info->dev) - nand->flash_node = dev_of_offset(nand_info->dev); + nand->flash_node = dev_ofnode(nand_info->dev); nand->cmd_ctrl = mxs_nand_cmd_ctrl; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 3679ee727e..b1fd779884 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -29,9 +29,6 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <common.h> -#if CONFIG_IS_ENABLED(OF_CONTROL) -#include <fdtdec.h> -#endif #include <log.h> #include <malloc.h> #include <watchdog.h> @@ -4576,23 +4573,20 @@ ident_done: EXPORT_SYMBOL(nand_get_flash_type); #if CONFIG_IS_ENABLED(OF_CONTROL) -#include <asm/global_data.h> -DECLARE_GLOBAL_DATA_PTR; -static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { int ret, ecc_mode = -1, ecc_strength, ecc_step; - const void *blob = gd->fdt_blob; const char *str; - ret = fdtdec_get_int(blob, node, "nand-bus-width", -1); + ret = ofnode_read_s32_default(node, "nand-bus-width", -1); if (ret == 16) chip->options |= NAND_BUSWIDTH_16; - if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt")) + if (ofnode_read_bool(node, "nand-on-flash-bbt")) chip->bbt_options |= NAND_BBT_USE_FLASH; - str = fdt_getprop(blob, node, "nand-ecc-mode", NULL); + str = ofnode_read_string(node, "nand-ecc-mode"); if (str) { if (!strcmp(str, "none")) ecc_mode = NAND_ECC_NONE; @@ -4608,9 +4602,10 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) ecc_mode = NAND_ECC_SOFT_BCH; } - - ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1); - ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1); + ecc_strength = ofnode_read_s32_default(node, + "nand-ecc-strength", -1); + ecc_step = ofnode_read_s32_default(node, + "nand-ecc-step-size", -1); if ((ecc_step >= 0 && !(ecc_strength >= 0)) || (!(ecc_step >= 0) && ecc_strength >= 0)) { @@ -4627,13 +4622,13 @@ static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) if (ecc_step > 0) chip->ecc.size = ecc_step; - if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL)) + if (ofnode_read_bool(node, "nand-ecc-maximize")) chip->ecc.options |= NAND_ECC_MAXIMIZE; return 0; } #else -static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node) { return 0; } @@ -4657,7 +4652,7 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, struct nand_flash_dev *type; int ret; - if (chip->flash_node) { + if (ofnode_valid(chip->flash_node)) { ret = nand_dt_init(mtd, chip, chip->flash_node); if (ret) return ret; diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index fd81a9500b..e17f1f8975 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -823,7 +823,7 @@ static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) nand->cs_used[i] = cs[i]; } - nand->chip.flash_node = ofnode_to_offset(node); + nand->chip.flash_node = node; return 0; } diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 7bc6ec7bee..c378f08f68 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1711,7 +1711,7 @@ static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum) * in the DT. */ nand->ecc.mode = NAND_ECC_HW; - nand->flash_node = node; + nand->flash_node = offset_to_ofnode(node); nand->select_chip = sunxi_nfc_select_chip; nand->cmd_ctrl = sunxi_nfc_cmd_ctrl; nand->read_buf = sunxi_nfc_read_buf; diff --git a/drivers/mtd/nand/raw/vf610_nfc.c b/drivers/mtd/nand/raw/vf610_nfc.c index e33953ec7c..13fd631cb4 100644 --- a/drivers/mtd/nand/raw/vf610_nfc.c +++ b/drivers/mtd/nand/raw/vf610_nfc.c @@ -109,19 +109,19 @@ #define STATUS_BYTE1_MASK 0x000000FF /* NFC_FLASH_CONFIG Field */ -#define CONFIG_ECC_SRAM_ADDR_MASK 0x7FC00000 -#define CONFIG_ECC_SRAM_ADDR_SHIFT 22 -#define CONFIG_ECC_SRAM_REQ_BIT (1<<21) -#define CONFIG_DMA_REQ_BIT (1<<20) -#define CONFIG_ECC_MODE_MASK 0x000E0000 -#define CONFIG_ECC_MODE_SHIFT 17 -#define CONFIG_FAST_FLASH_BIT (1<<16) -#define CONFIG_16BIT (1<<7) -#define CONFIG_BOOT_MODE_BIT (1<<6) -#define CONFIG_ADDR_AUTO_INCR_BIT (1<<5) -#define CONFIG_BUFNO_AUTO_INCR_BIT (1<<4) -#define CONFIG_PAGE_CNT_MASK 0xF -#define CONFIG_PAGE_CNT_SHIFT 0 +#define CFG_ECC_SRAM_ADDR_MASK 0x7FC00000 +#define CFG_ECC_SRAM_ADDR_SHIFT 22 +#define CFG_ECC_SRAM_REQ_BIT (1<<21) +#define CFG_DMA_REQ_BIT (1<<20) +#define CFG_ECC_MODE_MASK 0x000E0000 +#define CFG_ECC_MODE_SHIFT 17 +#define CFG_FAST_FLASH_BIT (1<<16) +#define CFG_16BIT (1<<7) +#define CFG_BOOT_MODE_BIT (1<<6) +#define CFG_ADDR_AUTO_INCR_BIT (1<<5) +#define CFG_BUFNO_AUTO_INCR_BIT (1<<4) +#define CFG_PAGE_CNT_MASK 0xF +#define CFG_PAGE_CNT_SHIFT 0 /* NFC_IRQ_STATUS Field */ #define IDLE_IRQ_BIT (1<<29) @@ -342,8 +342,8 @@ static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page) static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode) { vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, - CONFIG_ECC_MODE_MASK, - CONFIG_ECC_MODE_SHIFT, ecc_mode); + CFG_ECC_MODE_MASK, + CFG_ECC_MODE_SHIFT, ecc_mode); } static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) @@ -666,16 +666,16 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) chip->ecc.size = PAGE_2K; /* Set configuration register. */ - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT); - vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT); - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_16BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_ADDR_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BUFNO_AUTO_INCR_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_BOOT_MODE_BIT); + vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CFG_DMA_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_FAST_FLASH_BIT); /* Disable virtual pages, only one elementary transfer unit */ - vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK, - CONFIG_PAGE_CNT_SHIFT, 1); + vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CFG_PAGE_CNT_MASK, + CFG_PAGE_CNT_SHIFT, 1); /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) { @@ -684,7 +684,7 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) } if (cfg.width == 16) - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_16BIT); /* Bad block options. */ if (cfg.flash_bbt) @@ -734,12 +734,12 @@ static int vf610_nfc_nand_init(struct vf610_nfc *nfc, int devnum) /* Set ECC_STATUS offset */ vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, - CONFIG_ECC_SRAM_ADDR_MASK, - CONFIG_ECC_SRAM_ADDR_SHIFT, + CFG_ECC_SRAM_ADDR_MASK, + CFG_ECC_SRAM_ADDR_SHIFT, ECC_SRAM_ADDR >> 3); /* Enable ECC status in SRAM */ - vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT); + vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CFG_ECC_SRAM_REQ_BIT); } /* second phase scan */ diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index b2291f7290..ddeef37ffc 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -99,7 +99,6 @@ config SPI_FLASH_SMART_HWCAPS config SPI_FLASH_SOFT_RESET bool "Software Reset support for SPI NOR flashes" - default n help Enable support for xSPI Software Reset. It will be used to switch from Octal DTR mode to legacy mode on shutdown and boot (if enabled). @@ -107,7 +106,6 @@ config SPI_FLASH_SOFT_RESET config SPI_FLASH_SOFT_RESET_ON_BOOT bool "Perform a Software Reset on boot on flashes that boot in stateful mode" depends on SPI_FLASH_SOFT_RESET - default n help Perform a Software Reset on boot to allow detecting flashes that are handed to us in Octal DTR mode. Do not enable this config on flashes diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index a78fd51ba7..67a3cf1d7a 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -68,7 +68,6 @@ config MTD_UBI_BEB_LIMIT config MTD_UBI_FASTMAP bool "UBI Fastmap (Experimental feature)" - default n help Important: this feature is experimental so far and the on-flash format for fastmap may change in the next kernel versions diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index d4dc72046c..6c12959f37 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2,6 +2,9 @@ source "drivers/net/phy/Kconfig" source "drivers/net/pfe_eth/Kconfig" source "drivers/net/fsl-mc/Kconfig" +config ETH + def_bool y + config DM_ETH bool "Enable Driver Model for Ethernet drivers" depends on DM @@ -557,7 +560,6 @@ endif #DM_ETH config SMC911X_32_BIT bool "Enable SMC911X 32-bit interface" - default n help Define this if data bus is 32 bits. If your processor use a narrower 16 bit bus or cannot convert one 32 bit word to two 16 bit @@ -711,7 +713,6 @@ config FEC1_PHY config PHY_NORXERR bool "PHY_NORXERR" depends on ETHER_ON_FEC1 - default n help The PHY does not have a RXERR line (RMII only). (so program the FEC to ignore it). @@ -736,7 +737,6 @@ config FEC2_PHY config FEC2_PHY_NORXERR bool "PHY_NORXERR" depends on ETHER_ON_FEC2 - default n help The PHY does not have a RXERR line (RMII only). (so program the FEC to ignore it). diff --git a/drivers/net/Makefile b/drivers/net/Makefile index b94ccea100..e4078d15a9 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -3,13 +3,14 @@ # (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. +obj-y += phy/ + obj-$(CONFIG_ALTERA_TSE) += altera_tse.o obj-$(CONFIG_AG7XXX) += ag7xxx.o obj-$(CONFIG_ARMADA100_FEC) += armada100_fec.o obj-$(CONFIG_BCM6348_ETH) += bcm6348-eth.o obj-$(CONFIG_BCM6368_ETH) += bcm6368-eth.o obj-$(CONFIG_BCMGENET) += bcmgenet.o -obj-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o obj-$(CONFIG_DRIVER_AX88180) += ax88180.o obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o @@ -33,6 +34,7 @@ obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o obj-$(CONFIG_EP93XX) += ep93xx_eth.o obj-$(CONFIG_ETHOC) += ethoc.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o +obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c deleted file mode 100644 index b4581d8c93..0000000000 --- a/drivers/net/at91_emac.c +++ /dev/null @@ -1,519 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG - * Jens Scharsig (esw@bus-elektronik.de) - * - * (C) Copyright 2003 - * Author : Hamid Ikdoumi (Atmel) - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_emac.h> -#include <asm/arch/clk.h> -#include <asm/arch/at91_pio.h> -#include <net.h> -#include <netdev.h> -#include <malloc.h> -#include <miiphy.h> -#include <linux/delay.h> -#include <linux/mii.h> - -#undef MII_DEBUG -#undef ET_DEBUG - -#if (CONFIG_SYS_RX_ETH_BUFFER > 1024) -#error AT91 EMAC supports max 1024 RX buffers. \ - Please decrease the CONFIG_SYS_RX_ETH_BUFFER value -#endif - -#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR -#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0 -#endif - -/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ -#if (AT91C_MASTER_CLOCK > 80000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_64 -#elif (AT91C_MASTER_CLOCK > 40000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_32 -#elif (AT91C_MASTER_CLOCK > 20000000) - #define HCLK_DIV AT91_EMAC_CFG_MCLK_16 -#else - #define HCLK_DIV AT91_EMAC_CFG_MCLK_8 -#endif - -#ifdef ET_DEBUG -#define DEBUG_AT91EMAC 1 -#else -#define DEBUG_AT91EMAC 0 -#endif - -#ifdef MII_DEBUG -#define DEBUG_AT91PHY 1 -#else -#define DEBUG_AT91PHY 0 -#endif - -#ifndef CONFIG_DRIVER_AT91EMAC_QUIET -#define VERBOSEP 1 -#else -#define VERBOSEP 0 -#endif - -#define RBF_ADDR 0xfffffffc -#define RBF_OWNER (1<<0) -#define RBF_WRAP (1<<1) -#define RBF_BROADCAST (1<<31) -#define RBF_MULTICAST (1<<30) -#define RBF_UNICAST (1<<29) -#define RBF_EXTERNAL (1<<28) -#define RBF_UNKNOWN (1<<27) -#define RBF_SIZE 0x07ff -#define RBF_LOCAL4 (1<<26) -#define RBF_LOCAL3 (1<<25) -#define RBF_LOCAL2 (1<<24) -#define RBF_LOCAL1 (1<<23) - -#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER -#define RBF_FRAMELEN 0x600 - -typedef struct { - unsigned long addr, size; -} rbf_t; - -typedef struct { - rbf_t rbfdt[RBF_FRAMEMAX]; - unsigned long rbindex; -} emac_device; - -void at91emac_EnableMDIO(at91_emac_t *at91mac) -{ - /* Mac CTRL reg set for MDIO enable */ - writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl); -} - -void at91emac_DisableMDIO(at91_emac_t *at91mac) -{ - /* Mac CTRL reg set for MDIO disable */ - writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl); -} - -int at91emac_read(at91_emac_t *at91mac, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - unsigned long netstat; - at91emac_EnableMDIO(at91mac); - - writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R | - AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | - AT91_EMAC_MAN_PHYA(addr), - &at91mac->man); - - do { - netstat = readl(&at91mac->sr); - debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); - } while (!(netstat & AT91_EMAC_SR_IDLE)); - - *value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK; - - at91emac_DisableMDIO(at91mac); - - debug_cond(DEBUG_AT91PHY, - "AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value); - - return 0; -} - -int at91emac_write(at91_emac_t *at91mac, unsigned char addr, - unsigned char reg, unsigned short value) -{ - unsigned long netstat; - debug_cond(DEBUG_AT91PHY, - "AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value); - - at91emac_EnableMDIO(at91mac); - - writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W | - AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 | - AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK), - &at91mac->man); - - do { - netstat = readl(&at91mac->sr); - debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat); - } while (!(netstat & AT91_EMAC_SR_IDLE)); - - at91emac_DisableMDIO(at91mac); - - return 0; -} - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - -at91_emac_t *get_emacbase_by_name(const char *devname) -{ - struct eth_device *netdev; - - netdev = eth_get_dev_by_name(devname); - return (at91_emac_t *) netdev->iobase; -} - -int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg) -{ - unsigned short value = 0; - at91_emac_t *emac; - - emac = get_emacbase_by_name(bus->name); - at91emac_read(emac , addr, reg, &value); - return value; -} - - -int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg, - u16 value) -{ - at91_emac_t *emac; - - emac = get_emacbase_by_name(bus->name); - at91emac_write(emac, addr, reg, value); - return 0; -} - -#endif - -static int at91emac_phy_reset(struct eth_device *netdev) -{ - int i; - u16 status, adv; - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_ADVERTISE, adv); - debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name); - at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR, - (BMCR_ANENABLE | BMCR_ANRESTART)); - - for (i = 0; i < 30000; i++) { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } - - if (status & BMSR_ANEGCOMPLETE) { - debug_cond(VERBOSEP, - "%s: Autonegotiation complete\n", netdev->name); - } else { - printf("%s: Autonegotiation timed out (status=0x%04x)\n", - netdev->name, status); - return -1; - } - return 0; -} - -static int at91emac_phy_init(struct eth_device *netdev) -{ - u16 phy_id, status, adv, lpa; - int media, speed, duplex; - int i; - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - /* Check if the PHY is up to snuff... */ - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_PHYSID1, &phy_id); - if (phy_id == 0xffff) { - printf("%s: No PHY present\n", netdev->name); - return -1; - } - - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - - if (!(status & BMSR_LSTATUS)) { - /* Try to re-negotiate if we don't have link already. */ - if (at91emac_phy_reset(netdev)) - return -2; - - for (i = 0; i < 100000 / 100; i++) { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_BMSR, &status); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - if (!(status & BMSR_LSTATUS)) { - debug_cond(VERBOSEP, "%s: link down\n", netdev->name); - return -3; - } else { - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_ADVERTISE, &adv); - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, - MII_LPA, &lpa); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n", - netdev->name, - speed ? "100" : "10", - duplex ? "full" : "half"); - } - return 0; -} - -int at91emac_UpdateLinkSpeed(at91_emac_t *emac) -{ - unsigned short stat1; - - at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1); - - if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ - return -1; - - if (stat1 & BMSR_100FULL) { - /*set Emac for 100BaseTX and Full Duplex */ - writel(readl(&emac->cfg) | - AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_10FULL) { - /*set MII for 10BaseT and Full Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) - ) | AT91_EMAC_CFG_FD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_100HALF) { - /*set MII for 100BaseTX and Half Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD) - ) | AT91_EMAC_CFG_SPD, - &emac->cfg); - return 0; - } - - if (stat1 & BMSR_10HALF) { - /*set MII for 10BaseT and Half Duplex */ - writel((readl(&emac->cfg) & - ~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)), - &emac->cfg); - return 0; - } - return 0; -} - -static int at91emac_init(struct eth_device *netdev, struct bd_info *bd) -{ - int i; - u32 value; - emac_device *dev; - at91_emac_t *emac; - at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; - - emac = (at91_emac_t *) netdev->iobase; - dev = (emac_device *) netdev->priv; - - /* PIO Disable Register */ - value = ATMEL_PMX_AA_EMDIO | ATMEL_PMX_AA_EMDC | - ATMEL_PMX_AA_ERXER | ATMEL_PMX_AA_ERX1 | - ATMEL_PMX_AA_ERX0 | ATMEL_PMX_AA_ECRS | - ATMEL_PMX_AA_ETX1 | ATMEL_PMX_AA_ETX0 | - ATMEL_PMX_AA_ETXEN | ATMEL_PMX_AA_EREFCK; - - writel(value, &pio->pioa.pdr); - writel(value, &pio->pioa.mux.pio2.asr); - -#ifdef CONFIG_RMII - value = ATMEL_PMX_BA_ERXCK; -#else - value = ATMEL_PMX_BA_ERXCK | ATMEL_PMX_BA_ECOL | - ATMEL_PMX_BA_ERXDV | ATMEL_PMX_BA_ERX3 | - ATMEL_PMX_BA_ERX2 | ATMEL_PMX_BA_ETXER | - ATMEL_PMX_BA_ETX3 | ATMEL_PMX_BA_ETX2; -#endif - writel(value, &pio->piob.pdr); - writel(value, &pio->piob.mux.pio2.bsr); - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl); - - /* Init Ethernet buffers */ - for (i = 0; i < RBF_FRAMEMAX; i++) { - dev->rbfdt[i].addr = (unsigned long) net_rx_packets[i]; - dev->rbfdt[i].size = 0; - } - dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; - dev->rbindex = 0; - writel((u32) &(dev->rbfdt[0]), &emac->rbqp); - - writel(readl(&emac->rsr) & - ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA), - &emac->rsr); - - value = AT91_EMAC_CFG_CAF | AT91_EMAC_CFG_NBC | - HCLK_DIV; -#ifdef CONFIG_RMII - value |= AT91_EMAC_CFG_RMII; -#endif - writel(value, &emac->cfg); - - writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE, - &emac->ctl); - - if (!at91emac_phy_init(netdev)) { - at91emac_UpdateLinkSpeed(emac); - return 0; - } - return -1; -} - -static void at91emac_halt(struct eth_device *netdev) -{ - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE), - &emac->ctl); - debug_cond(DEBUG_AT91EMAC, "halt MAC\n"); -} - -static int at91emac_send(struct eth_device *netdev, void *packet, int length) -{ - at91_emac_t *emac; - - emac = (at91_emac_t *) netdev->iobase; - - while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ)) - ; - writel((u32) packet, &emac->tar); - writel(AT91_EMAC_TCR_LEN(length), &emac->tcr); - while (AT91_EMAC_TCR_LEN(readl(&emac->tcr))) - ; - debug_cond(DEBUG_AT91EMAC, "Send %d\n", length); - writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr); - return 0; -} - -static int at91emac_recv(struct eth_device *netdev) -{ - emac_device *dev; - at91_emac_t *emac; - rbf_t *rbfp; - int size; - - emac = (at91_emac_t *) netdev->iobase; - dev = (emac_device *) netdev->priv; - - rbfp = &dev->rbfdt[dev->rbindex]; - while (rbfp->addr & RBF_OWNER) { - size = rbfp->size & RBF_SIZE; - net_process_received_packet(net_rx_packets[dev->rbindex], size); - - debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n", - dev->rbindex, size, rbfp->addr); - - rbfp->addr &= ~RBF_OWNER; - rbfp->size = 0; - if (dev->rbindex < (RBF_FRAMEMAX-1)) - dev->rbindex++; - else - dev->rbindex = 0; - - rbfp = &(dev->rbfdt[dev->rbindex]); - if (!(rbfp->addr & RBF_OWNER)) - writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC, - &emac->rsr); - } - - if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) { - /* EMAC silicon bug 41.3.1 workaround 1 */ - writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl); - writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl); - dev->rbindex = 0; - printf("%s: reset receiver (EMAC dead lock bug)\n", - netdev->name); - } - return 0; -} - -static int at91emac_write_hwaddr(struct eth_device *netdev) -{ - at91_emac_t *emac; - emac = (at91_emac_t *) netdev->iobase; - - at91_periph_clk_enable(ATMEL_ID_EMAC); - - debug_cond(DEBUG_AT91EMAC, - "init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n", - netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3], - netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]); - writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 | - netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24), - &emac->sa2l); - writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h); - debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n", - readl(&emac->sa2h), readl(&emac->sa2l)); - return 0; -} - -int at91emac_register(struct bd_info *bis, unsigned long iobase) -{ - emac_device *emac; - emac_device *emacfix; - struct eth_device *dev; - - if (iobase == 0) - iobase = ATMEL_BASE_EMAC; - emac = malloc(sizeof(*emac)+512); - if (emac == NULL) - return -1; - dev = malloc(sizeof(*dev)); - if (dev == NULL) { - free(emac); - return -1; - } - /* alignment as per Errata (64 bytes) is insufficient! */ - emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00); - memset(emacfix, 0, sizeof(emac_device)); - - memset(dev, 0, sizeof(*dev)); - strcpy(dev->name, "emac"); - dev->iobase = iobase; - dev->priv = emacfix; - dev->init = at91emac_init; - dev->halt = at91emac_halt; - dev->send = at91emac_send; - dev->recv = at91emac_recv; - dev->write_hwaddr = at91emac_write_hwaddr; - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - int retval; - struct mii_dev *mdiodev = mdio_alloc(); - if (!mdiodev) - return -ENOMEM; - strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN); - mdiodev->read = at91emac_mii_read; - mdiodev->write = at91emac_mii_write; - - retval = mdio_register(mdiodev); - if (retval < 0) - return retval; -#endif - return 1; -} diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 64d5ddf238..68ee7d7a2d 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -71,7 +71,6 @@ menuconfig PHY_AQUANTIA config PHY_AQUANTIA_UPLOAD_FW bool "Aquantia firmware loading support" - default n depends on PHY_AQUANTIA help Aquantia PHYs use firmware which can be either loaded automatically @@ -102,7 +101,6 @@ config PHY_CORTINA config SYS_CORTINA_NO_FW_UPLOAD bool "Cortina firmware loading support" - default n depends on PHY_CORTINA help Cortina phy has provision to store phy firmware in attached dedicated @@ -250,7 +248,6 @@ config RTL8211X_PHY_FORCE_MASTER config RTL8211F_PHY_FORCE_EEE_RXC_ON bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI" depends on PHY_REALTEK - default n help The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate transitions to/from a lower power consumption level (Low Power Idle diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 4c3acba35a..db324c17d6 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -251,18 +251,14 @@ struct smc91111_priv{ * We have only 16 Bit PCMCIA access on Socket 0 */ -#ifdef CONFIG_ADNPESC1 -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) -#elif CONFIG_ARM64 +#if CONFIG_ARM64 #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else #define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) #endif #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) -#ifdef CONFIG_ADNPESC1 -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) -#elif CONFIG_ARM64 +#if CONFIG_ARM64 #define SMC_outw(a, d, r) \ (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else @@ -442,11 +438,6 @@ struct smc91111_priv{ #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) -#elif defined(CONFIG_ADNPESC1) -/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */ -#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ - | (RPC_LED_TX_RX << RPC_LSXA_SHFT) \ - | (RPC_LED_100_10 << RPC_LSXB_SHFT) ) #else /* SMSC reference design: LEDa --> green, LEDb --> yellow */ #define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \ diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 7bc2372e96..af028f9cec 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -66,7 +66,7 @@ int pch_ioctl(struct udevice *dev, ulong req, void *data, int size) UCLASS_DRIVER(pch) = { .id = UCLASS_PCH, .name = "pch", -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index e4123ba820..cc139af6cb 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -21,7 +21,6 @@ config DM_PCI_COMPAT config PCI_AARDVARK bool "Enable Aardvark PCIe driver" - default n depends on DM_GPIO depends on ARMADA_3700 help @@ -37,7 +36,6 @@ config PCI_PNP config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" - default n help Enable PCI memory regions to be of multiple entry. Multiple entry here refers to allow more than one count of address ranges for MEMORY @@ -47,7 +45,6 @@ config PCI_REGION_MULTI_ENTRY config PCI_MAP_SYSTEM_MEMORY bool "Map local system memory from a virtual base address" depends on MIPS - default n help Say Y if base address of system memory is being used as a virtual address instead of a physical address (e.g. on MIPS). The PCI core will then remap @@ -58,7 +55,6 @@ config PCI_MAP_SYSTEM_MEMORY config PCI_SRIOV bool "Enable Single Root I/O Virtualization support for PCI" - default n help Say Y here if you want to enable PCI Single Root I/O Virtualization capability support. This helps to enumerate Virtual Function devices @@ -67,7 +63,6 @@ config PCI_SRIOV config PCI_ARID bool "Enable Alternate Routing-ID support for PCI" - default n help Say Y here if you want to enable Alternate Routing-ID capability support on PCI devices. This helps to skip some devices in BDF @@ -75,14 +70,12 @@ config PCI_ARID config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" - default n help Say Y here if you want to enable support for generic ECAM-based PCIe host controllers, such as the one emulated by QEMU. config PCIE_ECAM_SYNQUACER bool "SynQuacer ECAM-based PCI host controller support" - default n select PCI_INIT_R select PCI_REGION_MULTI_ENTRY help @@ -186,7 +179,6 @@ config PCI_XILINX config PCIE_LAYERSCAPE bool - default n config PCIE_LAYERSCAPE_RC bool "Layerscape PCIe Root Complex mode support" diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index ce2eb5da2c..4d0e938fe5 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -856,10 +856,7 @@ int pci_bind_bus_devices(struct udevice *bus) /* Check only the first access, we don't expect problems */ ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor, PCI_SIZE_16); - if (ret) - goto error; - - if (vendor == 0xffff || vendor == 0x0000) + if (ret || vendor == 0xffff || vendor == 0x0000) continue; pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE, @@ -940,10 +937,6 @@ int pci_bind_bus_devices(struct udevice *bus) } return 0; -error: - printf("Cannot read bus configuration: %d\n", ret); - - return ret; } static void decode_regions(struct pci_controller *hose, ofnode parent_node, diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index b128a05dd3..7b6e629cae 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; + u8 io_32; struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); @@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; /* Configure bus number registers */ dm_pci_write_config8(dev, PCI_PRIMARY_BUS, @@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_MEMORY_BASE, - (pci_mem->bus_lower & 0xfff00000) >> 16); + ((pci_mem->bus_lower & 0xfff00000) >> 16) & + PCI_MEMORY_RANGE_MASK); cmdstat |= PCI_COMMAND_MEMORY; } @@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, - (pci_prefetch->bus_lower & 0xfff00000) >> 16); + (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, @@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); - dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | + prefechable_64); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | + prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); @@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_BASE, - (pci_io->bus_lower & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, + (((pci_io->bus_lower & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, (pci_io->bus_lower & 0xffff0000) >> 16); cmdstat |= PCI_COMMAND_IO; @@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_mem, 0x100000); dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, - (pci_mem->bus_lower - 1) >> 16); + ((pci_mem->bus_lower - 1) >> 16) & + PCI_MEMORY_RANGE_MASK); } if (pci_prefetch) { @@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_prefetch, 0x100000); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, - (pci_prefetch->bus_lower - 1) >> 16); + (((pci_prefetch->bus_lower - 1) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, @@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) } if (pci_io) { + u8 io_32; + + dm_pci_read_config8(dev, PCI_IO_LIMIT, + &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; + /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_LIMIT, - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, + ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); } } diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 12ce9d525c..be03dcbd97 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020 Broadcom + * Copyright (C) 2020-2021 Broadcom * */ @@ -12,6 +12,7 @@ #include <malloc.h> #include <asm/io.h> #include <dm/device_compat.h> +#include <linux/delay.h> #include <linux/log2.h> #define EP_PERST_SOURCE_SELECT_SHIFT 2 @@ -884,7 +885,7 @@ static int iproc_pcie_map_ranges(struct udevice *dev) for (i = 0; i < hose->region_count; i++) { if (hose->regions[i].flags == PCI_REGION_MEM || hose->regions[i].flags == PCI_REGION_PREFETCH) { - debug("%d: bus_addr %p, axi_addr %p, size 0x%lx\n", + debug("%d: bus_addr %p, axi_addr %p, size 0x%llx\n", i, &hose->regions[i].bus_start, &hose->regions[i].phys_start, hose->regions[i].size); @@ -1049,7 +1050,7 @@ static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie) while (!pci_get_dma_regions(pcie->dev, ®ions, i)) { dev_dbg(pcie->dev, - "dma %d: bus_addr %#lx, axi_addr %#llx, size %#lx\n", + "dma %d: bus_addr %#llx, axi_addr %#llx, size %#llx\n", i, regions.bus_start, regions.phys_start, regions.size); /* Each range entry corresponds to an inbound mapping region */ diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig index 4240028403..b5f69c0a96 100644 --- a/drivers/phy/marvell/Kconfig +++ b/drivers/phy/marvell/Kconfig @@ -1,6 +1,5 @@ config MVEBU_COMPHY_SUPPORT bool "ComPhy SerDes driver" - default n help Choose this option to add support for Comphy driver. diff --git a/drivers/pinctrl/intel/pinctrl_apl.c b/drivers/pinctrl/intel/pinctrl_apl.c index acaa55d2e7..181a6ff270 100644 --- a/drivers/pinctrl/intel/pinctrl_apl.c +++ b/drivers/pinctrl/intel/pinctrl_apl.c @@ -155,7 +155,7 @@ static int apl_pinctrl_of_to_plat(struct udevice *dev) return intel_pinctrl_of_to_plat(dev, comm, 2); } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id apl_gpio_ids[] = { { .compatible = "intel,apl-pinctrl"}, { } @@ -168,7 +168,7 @@ U_BOOT_DRIVER(intel_apl_pinctrl) = { .of_match = of_match_ptr(apl_gpio_ids), .probe = intel_pinctrl_probe, .ops = &intel_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .of_to_plat = apl_pinctrl_of_to_plat, diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index e6b10a377b..9a54b8bbe9 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -186,7 +186,7 @@ U_BOOT_DRIVER(fsl_imx23_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(mxs_pinctrl_match), .probe = mxs_pinctrl_probe, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .priv_auto = sizeof(struct mxs_pinctrl_priv), diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c index e129ab2f83..dc0be7ce3b 100644 --- a/drivers/pinctrl/pinctrl-qe-io.c +++ b/drivers/pinctrl/pinctrl-qe-io.c @@ -248,7 +248,7 @@ U_BOOT_DRIVER(par_io_pinctrl) = { .of_to_plat = qe_io_of_to_plat, .plat_auto = sizeof(struct qe_io_plat), .ops = &par_io_pinctrl_ops, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .flags = DM_FLAG_PRE_RELOC, #endif }; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index dfe60b6dad..4462ed20e2 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -421,7 +421,7 @@ static int __maybe_unused pinctrl_post_bind(struct udevice *dev) UCLASS_DRIVER(pinctrl) = { .id = UCLASS_PINCTRL, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = pinctrl_post_bind, #endif .flags = DM_UC_FLAG_SEQ_ALIAS, diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index 6058d0f4c1..9de29c0b8b 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -363,7 +363,7 @@ U_BOOT_DRIVER(pinctrl_px30) = { .of_match = px30_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3036.c b/drivers/pinctrl/rockchip/pinctrl-rk3036.c index 9ccee465b0..afcd34396e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3036.c @@ -103,7 +103,7 @@ U_BOOT_DRIVER(pinctrl_rockchip) = { .of_match = rk3036_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index 85c2e611b6..e6dc1af86e 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -205,7 +205,7 @@ U_BOOT_DRIVER(pinctrl_rk3128) = { .of_match = rk3128_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3188.c b/drivers/pinctrl/rockchip/pinctrl-rk3188.c index 06d53e22d2..9a982cbfad 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3188.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3188.c @@ -126,7 +126,7 @@ U_BOOT_DRIVER(rockchip_rk3188_pinctrl) = { .of_match = rk3188_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index fe386933c5..7c58f40d93 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -292,7 +292,7 @@ U_BOOT_DRIVER(pinctrl_rk3228) = { .of_match = rk3228_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index fc2810248b..5894f47f53 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -248,7 +248,7 @@ U_BOOT_DRIVER(rockchip_rk3288_pinctrl) = { .of_match = rk3288_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index a9b87b7457..83186f40f6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -459,7 +459,7 @@ U_BOOT_DRIVER(pinctrl_rk3308) = { .of_match = rk3308_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index aa8bd76d6f..1c3c5986a5 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -323,7 +323,7 @@ U_BOOT_DRIVER(rockchip_rk3328_pinctrl) = { .of_match = rk3328_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c index 18d3e3a9b5..ba867a8917 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c @@ -177,7 +177,7 @@ U_BOOT_DRIVER(rockchip_rk3368_pinctrl) = { .of_match = rk3368_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index 0c1adc3794..caa92200c6 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -317,7 +317,7 @@ U_BOOT_DRIVER(pinctrl_rk3399) = { .of_match = rk3399_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1108.c b/drivers/pinctrl/rockchip/pinctrl-rv1108.c index d35425b5fa..5b70b503d2 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl-rv1108.c @@ -291,7 +291,7 @@ U_BOOT_DRIVER(pinctrl_rv1108) = { .of_match = rv1108_pinctrl_ids, .priv_auto = sizeof(struct rockchip_pinctrl_priv), .ops = &rockchip_pinctrl_ops, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .bind = dm_scan_fdt_dev, #endif .probe = rockchip_pinctrl_probe, diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index c5fbf1f832..2c20dc7c83 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,4 +1,46 @@ -menu "Power" +menuconfig POWER + bool "Power" + default y + help + Enable support for power control in U-Boot. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in U-Boot to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. + +if POWER + +config POWER_LEGACY + bool "Legacy power support" + help + Note: This is a legacy option. Use DM_PMIC instead. + + Enable support for power control in U-Boot. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in U-Boot to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. + +config SPL_POWER_LEGACY + bool "Legacy power support in SPL" + default y if POWER_LEGACY + help + Note: This is a legacy option. Use SPL_DM_PMIC instead. + + Enable support for power control in SPL. This includes support + for PMICs (Power-management Integrated Circuits) and some of the + features provided by PMICs. In particular, voltage regulators can + be used to enable/disable power and vary its voltage. That can be + useful in SPL to turn on boot peripherals and adjust CPU voltage + so that the clock speed can be increased. This enables the drivers + in drivers/power, drivers/power/pmic and drivers/power/regulator + as part of a build. source "drivers/power/acpi_pmc/Kconfig" @@ -248,7 +290,6 @@ endchoice config AXP_ALDO3_INRUSH_QUIRK bool "axp pmic (a)ldo3 inrush quirk" depends on AXP209_POWER - default n ---help--- The reference design denotes a value of 4.7 uF for the output capacitor of LDO3. Some boards have too high capacitance causing an inrush current @@ -357,7 +398,6 @@ config AXP_FLDO3_VOLT config AXP_SW_ON bool "axp pmic sw on" depends on AXP809_POWER || AXP818_POWER - default n ---help--- Enable to turn on axp pmic sw. @@ -385,4 +425,25 @@ config POWER_MT6323 This adds poweroff driver for mt6323 this pmic is used on mt7623 / Bananapi R2 -endmenu +config POWER_I2C + bool "I2C-based power control for legacy power" + depends on POWER_LEGACY + help + Enable this to use the I2C driver designed for the legacy PMIC + interface. + + Not to be used for new designs and existing ones should be moved to + the new PMIC interface based on driver model. + +config SPL_POWER_I2C + bool "I2C-based power control for legacy power" + depends on SPL_POWER_LEGACY + default y if POWER_I2C + help + Enable this to use the I2C driver designed for the legacy PMIC + interface. + + Not to be used for new designs and existing ones should be moved to + the new PMIC interface based on driver model. + +endif diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 0bef06920a..f805027784 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -3,6 +3,14 @@ # Copyright (c) 2009 Wind River Systems, Inc. # Tom Rix <Tom.Rix at windriver.com> +obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ +obj-y += battery/ +obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ +obj-y += fuel_gauge/ +obj-y += mfd/ +obj-y += pmic/ +obj-y += regulator/ + obj-$(CONFIG_AXP152_POWER) += axp152.o obj-$(CONFIG_AXP209_POWER) += axp209.o obj-$(CONFIG_AXP221_POWER) += axp221.o @@ -16,9 +24,9 @@ obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o obj-$(CONFIG_TWL6030_POWER) += twl6030.o obj-$(CONFIG_PALMAS_POWER) += palmas.o -obj-$(CONFIG_POWER) += power_core.o +obj-$(CONFIG_$(SPL_TPL_)POWER_LEGACY) += power_core.o obj-$(CONFIG_DIALOG_POWER) += power_dialog.o obj-$(CONFIG_POWER_FSL) += power_fsl.o -obj-$(CONFIG_POWER_I2C) += power_i2c.o +obj-$(CONFIG_$(SPL_TPL_)POWER_I2C) += power_i2c.o obj-$(CONFIG_POWER_SPI) += power_spi.o obj-$(CONFIG_POWER_MT6323) += mt6323.o diff --git a/drivers/power/acpi_pmc/Makefile b/drivers/power/acpi_pmc/Makefile index 115788f109..0db52a6582 100644 --- a/drivers/power/acpi_pmc/Makefile +++ b/drivers/power/acpi_pmc/Makefile @@ -2,5 +2,5 @@ # # Copyright 2019 Google LLC -obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi-pmc-uclass.o +obj-y += acpi-pmc-uclass.o obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC_SANDBOX) += sandbox.o pmc_emul.o diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index 00d1489ea2..33f9206bd0 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -112,7 +112,7 @@ int power_domain_off(struct power_domain *power_domain) return ops->off(power_domain); } -#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) +#if CONFIG_IS_ENABLED(OF_REAL) static int dev_power_domain_ctrl(struct udevice *dev, bool on) { struct power_domain pd; @@ -162,7 +162,7 @@ int dev_power_domain_off(struct udevice *dev) { return dev_power_domain_ctrl(dev, false); } -#endif +#endif /* OF_REAL */ UCLASS_DRIVER(power_domain) = { .id = UCLASS_POWER_DOMAIN, diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index fd6648b313..cf2a9b2c17 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -10,6 +10,19 @@ config DM_PMIC - 'drivers/power/pmic/pmic-uclass.c' - 'include/power/pmic.h' +config SPL_DM_PMIC + bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" + depends on SPL_DM + default y if DM_PMIC + ---help--- + This config enables the driver-model PMIC support in SPL. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' + config PMIC_CHILDREN bool "Allow child devices for PMICs" depends on DM_PMIC @@ -205,6 +218,15 @@ config PMIC_RK8XX accessed via an I2C interface. The device is used with Rockchip SoCs. This driver implements register read/write operations. +config SPL_PMIC_RK8XX + bool "Enable support for Rockchip PMIC RK8XX" + depends on DM_PMIC + ---help--- + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. + config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 5d1a97e5f6..5250eac12f 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -3,7 +3,7 @@ # Copyright (C) 2012 Samsung Electronics # Lukasz Majewski <l.majewski@samsung.com> -obj-$(CONFIG_DM_PMIC) += pmic-uclass.o +obj-$(CONFIG_$(SPL_TPL_)DM_PMIC) += pmic-uclass.o obj-$(CONFIG_DM_PMIC_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_PMIC_DA9063) += da9063.o obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o @@ -20,7 +20,7 @@ obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_AS3722) += as3722.o as3722_gpio.o obj-$(CONFIG_PMIC_MAX8997) += max8997.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o -obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o +obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 677134c822..4efb32a322 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o -obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o +obj-$(CONFIG_$(SPL_TPL_)REGULATOR_RK8XX) += rk8xx.o obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index 049b9dc249..576d5af868 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -3,7 +3,6 @@ if RAM || SPL_RAM config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on DM && OF_CONTROL && ARCH_ASPEED - default n help Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram controller needs to know if the memory chip mounted on the board is dual @@ -42,14 +41,12 @@ endchoice config ASPEED_BYPASS_SELFTEST bool "bypass self test during DRAM initialization" - default n help Say Y here to bypass DRAM self test to speed up the boot time config ASPEED_ECC bool "aspeed SDRAM error correcting code" depends on DM && OF_CONTROL && ARCH_ASPEED - default n help enable SDRAM ECC function diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig index eb5a1208ed..f19957293f 100644 --- a/drivers/ram/octeon/Kconfig +++ b/drivers/ram/octeon/Kconfig @@ -1,7 +1,6 @@ config RAM_OCTEON bool "Ram drivers for Octeon SoCs" depends on RAM && ARCH_OCTEON - default n help This enables support for RAM drivers for Octeon SoCs. @@ -9,7 +8,6 @@ if RAM_OCTEON config RAM_OCTEON_DDR4 bool "Octeon III DDR4 RAM support" - default n help This enables support for DDR4 RAM suppoort for Octeon III. This does not include support for Octeon CN70XX. diff --git a/drivers/ram/rockchip/dmc-rk3368.c b/drivers/ram/rockchip/dmc-rk3368.c index a9d051852a..69c454a4ba 100644 --- a/drivers/ram/rockchip/dmc-rk3368.c +++ b/drivers/ram/rockchip/dmc-rk3368.c @@ -883,13 +883,13 @@ static int rk3368_dmc_of_to_plat(struct udevice *dev) { int ret = 0; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3368_sdram_params *plat = dev_get_plat(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rk3368_sdram_params *plat = dev_get_plat(dev); - ret = regmap_init_mem(dev_ofnode(dev), &plat->map); - if (ret) - return ret; -#endif + ret = regmap_init_mem(dev_ofnode(dev), &plat->map); + if (ret) + return ret; + } return ret; } diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c index 25ae69e9ac..d9ed8adfcf 100644 --- a/drivers/ram/rockchip/sdram_rk3188.c +++ b/drivers/ram/rockchip/sdram_rk3188.c @@ -816,10 +816,12 @@ static int setup_sdram(struct udevice *dev) static int rk3188_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3188_sdram_params *params = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + /* rk3188 supports only one-channel */ params->num_channels = 1; ret = dev_read_u32_array(dev, "rockchip,pctl-timing", @@ -846,7 +848,6 @@ static int rk3188_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index 9057ccacd9..30e9c3ddc4 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -716,12 +716,14 @@ out: static int rk322x_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk322x_sdram_params *params = dev_get_plat(dev); const void *blob = gd->fdt_blob; int node = dev_of_offset(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + params->num_channels = 1; ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", @@ -748,7 +750,6 @@ static int rk322x_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } diff --git a/drivers/ram/rockchip/sdram_rk3288.c b/drivers/ram/rockchip/sdram_rk3288.c index a933abf0d4..f3e4a2808a 100644 --- a/drivers/ram/rockchip/sdram_rk3288.c +++ b/drivers/ram/rockchip/sdram_rk3288.c @@ -973,10 +973,12 @@ static int setup_sdram(struct udevice *dev) static int rk3288_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_sdram_params *params = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + /* Rk3288 supports dual-channel, set default channel num to 2 */ params->num_channels = 2; ret = dev_read_u32_array(dev, "rockchip,pctl-timing", @@ -1008,7 +1010,6 @@ static int rk3288_dmc_of_to_plat(struct udevice *dev) ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map); if (ret) return ret; -#endif return 0; } diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 9af4c372d5..9c6798f816 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -517,7 +517,7 @@ static int rk3328_dmc_init(struct udevice *dev) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rk3328_sdram_params *params = &plat->sdram_params; #else struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat; @@ -549,7 +549,7 @@ static int rk3328_dmc_init(struct udevice *dev) static int rk3328_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index a83a670b32..c0a06dcaed 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -3013,10 +3013,12 @@ static int sdram_init(struct dram_info *dram, static int rk3399_dmc_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; + if (!CONFIG_IS_ENABLED(OF_REAL)) + return 0; + ret = dev_read_u32_array(dev, "rockchip,sdram-params", (u32 *)&plat->sdram_params, sizeof(plat->sdram_params) / sizeof(u32)); @@ -3029,7 +3031,6 @@ static int rk3399_dmc_of_to_plat(struct udevice *dev) if (ret) printf("%s: regmap failed %d\n", __func__, ret); -#endif return 0; } @@ -3068,7 +3069,7 @@ static int rk3399_dmc_init(struct udevice *dev) struct dram_info *priv = dev_get_priv(dev); struct rockchip_dmc_plat *plat = dev_get_plat(dev); int ret; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct rk3399_sdram_params *params = &plat->sdram_params; #else struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; @@ -3106,7 +3107,7 @@ static int rk3399_dmc_init(struct udevice *dev) priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu); #if CONFIG_IS_ENABLED(OF_PLATDATA) - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->ddr_clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->ddr_clk); #else ret = clk_get_by_index(dev, 0, &priv->ddr_clk); #endif diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig index 2fd8c7b7e3..1aaf064c30 100644 --- a/drivers/ram/stm32mp1/Kconfig +++ b/drivers/ram/stm32mp1/Kconfig @@ -23,7 +23,6 @@ config STM32MP1_DDR_INTERACTIVE config STM32MP1_DDR_INTERACTIVE_FORCE bool "STM32MP1 DDR driver : force interactive mode" depends on STM32MP1_DDR_INTERACTIVE - default n help force interactive mode in STM32MP1 DDR controller driver skip the polling of character 'd' in console diff --git a/drivers/reboot-mode/Kconfig b/drivers/reboot-mode/Kconfig index ac67bfcef6..63ea18cdf0 100644 --- a/drivers/reboot-mode/Kconfig +++ b/drivers/reboot-mode/Kconfig @@ -9,7 +9,6 @@ menu "Reboot Mode Support" config DM_REBOOT_MODE bool "Enable reboot mode using Driver Model" depends on DM - default n help Enable support for reboot mode control. This will allow users to adjust the boot process based on reboot mode parameter @@ -18,7 +17,6 @@ config DM_REBOOT_MODE config DM_REBOOT_MODE_GPIO bool "Use GPIOs as reboot mode backend" depends on DM_REBOOT_MODE - default n help Use GPIOs to control the reboot mode. This will allow users to boot a device in a specific mode by using a GPIO that can be controlled @@ -27,7 +25,6 @@ config DM_REBOOT_MODE_GPIO config DM_REBOOT_MODE_RTC bool "Use RTC as reboot mode backend" depends on DM_REBOOT_MODE - default n help Use RTC non volatile memory to control the reboot mode. This will allow users to boot a device in a specific mode by using a register(s) that can be controlled diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index 94915d45b3..b1c5ab93d1 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -34,14 +34,12 @@ config RNG_MSM config RNG_STM32MP1 bool "Enable random number generator for STM32MP1" depends on ARCH_STM32MP - default n help Enable STM32MP1 rng driver. config RNG_ROCKCHIP bool "Enable random number generator for rockchip crypto rng" depends on ARCH_ROCKCHIP && DM_RNG - default n help Enable random number generator for rockchip.This driver is support rng module of crypto v1 and crypto v2. @@ -49,7 +47,6 @@ config RNG_ROCKCHIP config RNG_IPROC200 bool "Broadcom iProc RNG200 random number generator" depends on DM_RNG - default n help Enable random number generator for RPI4. endif diff --git a/drivers/rtc/ds1307.c b/drivers/rtc/ds1307.c index 2015ce9bbc..3be97c9d93 100644 --- a/drivers/rtc/ds1307.c +++ b/drivers/rtc/ds1307.c @@ -43,11 +43,21 @@ enum ds_type { #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ +/* DS1307-specific bits */ #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ +/* DS1337-specific bits */ +#define DS1337_CTL_BIT_RS1 0x08 /* Rate select 1 */ +#define DS1337_CTL_BIT_RS2 0x10 /* Rate select 2 */ +#define DS1337_CTL_BIT_EOSC 0x80 /* Enable Oscillator */ + +/* DS1340-specific bits */ +#define DS1340_SEC_BIT_EOSC 0x80 /* Enable Oscillator */ +#define DS1340_CTL_BIT_OUT 0x80 /* Output Control */ + /* MCP7941X-specific bits */ #define MCP7941X_BIT_ST 0x80 #define MCP7941X_BIT_VBATEN 0x08 @@ -261,9 +271,25 @@ read_rtc: buf[RTC_SEC_REG_ADDR]); return -1; } - } - - if (type == m41t11) { + } else if (type == ds_1337) { + if (buf[RTC_CTL_REG_ADDR] & DS1337_CTL_BIT_EOSC) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the not oscillator enable (~EOSC) flag */ + buf[RTC_CTL_REG_ADDR] &= ~DS1337_CTL_BIT_EOSC; + dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + buf[RTC_CTL_REG_ADDR]); + return -1; + } + } else if (type == ds_1340) { + if (buf[RTC_SEC_REG_ADDR] & DS1340_SEC_BIT_EOSC) { + printf("### Warning: RTC oscillator has stopped\n"); + /* clear the not oscillator enable (~EOSC) flag */ + buf[RTC_SEC_REG_ADDR] &= ~DS1340_SEC_BIT_EOSC; + dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, + buf[RTC_SEC_REG_ADDR]); + return -1; + } + } else if (type == m41t11) { /* clock halted? turn it on, so clock can tick. */ if (buf[RTC_SEC_REG_ADDR] & RTC_SEC_BIT_CH) { buf[RTC_SEC_REG_ADDR] &= ~RTC_SEC_BIT_CH; @@ -273,9 +299,7 @@ read_rtc: buf[RTC_SEC_REG_ADDR]); goto read_rtc; } - } - - if (type == mcp794xx) { + } else if (type == mcp794xx) { /* make sure that the backup battery is enabled */ if (!(buf[RTC_DAY_REG_ADDR] & MCP7941X_BIT_VBATEN)) { dm_i2c_reg_write(dev, RTC_DAY_REG_ADDR, @@ -314,18 +338,37 @@ read_rtc: static int ds1307_rtc_reset(struct udevice *dev) { int ret; + enum ds_type type = dev_get_driver_data(dev); - /* clear Clock Halt */ + /* + * reset clock/oscillator in the seconds register: + * on DS1307 bit 7 enables Clock Halt (CH), + * on DS1340 bit 7 disables the oscillator (not EOSC) + * on MCP794xx bit 7 enables Start Oscillator (ST) + */ ret = dm_i2c_reg_write(dev, RTC_SEC_REG_ADDR, 0x00); if (ret < 0) return ret; - ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, - RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | - RTC_CTL_BIT_RS0); - if (ret < 0) - return ret; - return 0; + if (type == ds_1307) { + /* Write control register in order to enable square-wave + * output (SQWE) and set a default rate of 32.768kHz (RS1|RS0). + */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | + RTC_CTL_BIT_RS0); + } else if (type == ds_1337) { + /* Write control register in order to enable oscillator output + * (not EOSC) and set a default rate of 32.768kHz (RS2|RS1). + */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, + DS1337_CTL_BIT_RS2 | DS1337_CTL_BIT_RS1); + } else if (type == ds_1340 || type == mcp794xx || type == m41t11) { + /* Reset clock calibration, frequency test and output level. */ + ret = dm_i2c_reg_write(dev, RTC_CTL_REG_ADDR, 0x00); + } + + return ret; } static int ds1307_probe(struct udevice *dev) diff --git a/drivers/rtc/emul_rtc.c b/drivers/rtc/emul_rtc.c index 8f0e1ab5ac..6f47d82522 100644 --- a/drivers/rtc/emul_rtc.c +++ b/drivers/rtc/emul_rtc.c @@ -9,8 +9,8 @@ #include <div64.h> #include <dm.h> #include <env.h> -#include <generated/timestamp_autogenerated.h> #include <rtc.h> +#include <timestamp.h> /** * struct emul_rtc - private data for emulated RTC driver diff --git a/drivers/rtc/rtc-uclass.c b/drivers/rtc/rtc-uclass.c index 321b8732ed..e5ae6ea4d5 100644 --- a/drivers/rtc/rtc-uclass.c +++ b/drivers/rtc/rtc-uclass.c @@ -177,7 +177,7 @@ UCLASS_DRIVER(rtc) = { .name = "rtc", .id = UCLASS_RTC, .flags = DM_UC_FLAG_SEQ_ALIAS, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif }; diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index 6fc5f4a9f9..e9f848636c 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_SCSI) += scsi.o endif ifdef CONFIG_SPL_BUILD -ifdef CONFIG_SPL_SATA_SUPPORT +ifdef CONFIG_SPL_SATA obj-$(CONFIG_DM_SCSI) += scsi-uclass.o obj-$(CONFIG_SCSI) += scsi.o endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 93348c0929..36ee43210a 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -2,7 +2,18 @@ # Serial device configuration # -menu "Serial drivers" +menuconfig SERIAL + bool "Serial" + default y + help + Enable support for serial drivers. This allows use of a serial UART + for displaying messages while U-Boot is running. It also brings in + printf() and panic() functions. This should normally be enabled + unless there are space reasons not to. If you just need to disable + the console you can adjust the stdout environment variable or use + SILENT_CONSOLE. + +if SERIAL config BAUDRATE int "Default baudrate" @@ -137,7 +148,6 @@ config SERIAL_SEARCH_ALL config SERIAL_PROBE_ALL bool "Probe all available serial devices" depends on DM_SERIAL - default n help The serial subsystem only probes for a single serial device, but does not probe for other remaining serial devices. @@ -621,7 +631,6 @@ config FSL_LPUART config MVEBU_A3700_UART bool "UART support for Armada 3700" - default n help Choose this option to add support for UART driver on the Marvell Armada 3700 SoC. The base address is configured via DT. @@ -939,4 +948,4 @@ config SYS_SDMR depends on MPC8XX_CONS default 0 -endmenu +endif diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index cc121eee27..796ff1658c 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -41,7 +41,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif #endif /* !CONFIG_DM_SERIAL */ -#if defined(CONFIG_SOC_KEYSTONE) +#if defined(CONFIG_ARCH_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) #undef UART_MCRVAL @@ -267,7 +267,7 @@ void ns16550_init(struct ns16550 *com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif -#if defined(CONFIG_SOC_KEYSTONE) +#if defined(CONFIG_ARCH_KEYSTONE) serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); #endif } @@ -533,7 +533,7 @@ enum { }; #endif -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) int ns16550_serial_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); @@ -588,7 +588,7 @@ const struct dm_serial_ops ns16550_serial_ops = { .getinfo = ns16550_serial_getinfo, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /* * Please consider existing compatible strings before adding a new * one to keep this table compact. Or you may add a generic "ns16550" @@ -602,7 +602,7 @@ static const struct udevice_id ns16550_serial_ids[] = { { .compatible = "snps,dw-apb-uart", .data = PORT_NS16550 }, {} }; -#endif /* OF_CONTROL && !OF_PLATDATA */ +#endif /* OF_REAL */ #if CONFIG_IS_ENABLED(SERIAL_PRESENT) @@ -611,7 +611,7 @@ static const struct udevice_id ns16550_serial_ids[] = { U_BOOT_DRIVER(ns16550_serial) = { .name = "ns16550_serial", .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = ns16550_serial_ids, .of_to_plat = ns16550_serial_of_to_plat, .plat_auto = sizeof(struct ns16550_plat), diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 5243c955fb..dbbcea5bb4 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -237,7 +237,7 @@ U_BOOT_DRIVER(sandbox_serial) = { .flags = DM_FLAG_PRE_RELOC, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct sandbox_serial_plat platdata_non_fdt = { .colour = -1, }; diff --git a/drivers/serial/serial_mt7620.c b/drivers/serial/serial_mt7620.c index 826a14b49f..76ecc2b38c 100644 --- a/drivers/serial/serial_mt7620.c +++ b/drivers/serial/serial_mt7620.c @@ -145,7 +145,7 @@ static int mt7620_serial_probe(struct udevice *dev) return 0; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mt7620_serial_of_to_plat(struct udevice *dev) { struct mt7620_serial_plat *plat = dev_get_plat(dev); @@ -200,7 +200,7 @@ static const struct dm_serial_ops mt7620_serial_ops = { U_BOOT_DRIVER(serial_mt7620) = { .name = "serial_mt7620", .id = UCLASS_SERIAL, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mt7620_serial_ids, .of_to_plat = mt7620_serial_of_to_plat, #endif diff --git a/drivers/serial/serial_omap.c b/drivers/serial/serial_omap.c index 2b23ece442..ee938f6763 100644 --- a/drivers/serial/serial_omap.c +++ b/drivers/serial/serial_omap.c @@ -98,7 +98,7 @@ DEBUG_UART_FUNCS #if CONFIG_IS_ENABLED(DM_SERIAL) -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int omap_serial_of_to_plat(struct udevice *dev) { struct ns16550_plat *plat = dev_get_plat(dev); @@ -149,13 +149,13 @@ static const struct udevice_id omap_serial_ids[] = { { .compatible = "ti,am654-uart", }, {} }; -#endif /* OF_CONTROL && !OF_PLATDATA */ +#endif /* OF_REAL */ #if CONFIG_IS_ENABLED(SERIAL_PRESENT) U_BOOT_DRIVER(omap_serial) = { .name = "omap_serial", .id = UCLASS_SERIAL, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap_serial_ids, .of_to_plat = omap_serial_of_to_plat, .plat_auto = sizeof(struct ns16550_plat), diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index fadc9f3965..989679e881 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -19,9 +19,7 @@ #define ALTERA_SPI_STATUS_RRDY_MSK BIT(7) #define ALTERA_SPI_CONTROL_SSO_MSK BIT(10) -#ifndef CONFIG_ALTERA_SPI_IDLE_VAL -#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff -#endif +#define ALTERA_SPI_IDLE_VAL 0xff struct altera_spi_regs { u32 rxdata; @@ -119,7 +117,7 @@ static int altera_spi_xfer(struct udevice *dev, unsigned int bitlen, if (txp) data = *txp++; else - data = CONFIG_ALTERA_SPI_IDLE_VAL; + data = ALTERA_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, data); writel(data, ®s->txdata); diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 6511c0e0e5..ea23357090 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -384,7 +384,7 @@ static int coldfire_spi_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int coldfire_dspi_of_to_plat(struct udevice *bus) { fdt_addr_t addr; @@ -450,7 +450,7 @@ static const struct dm_spi_ops coldfire_spi_ops = { U_BOOT_DRIVER(coldfire_spi) = { .name = "spi_coldfire", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = coldfire_spi_ids, .of_to_plat = coldfire_dspi_of_to_plat, .plat_auto = sizeof(struct coldfire_spi_plat), diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 15557a6230..0ee6171108 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -391,7 +391,7 @@ static int davinci_spi_probe(struct udevice *bus) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int davinci_ofdata_to_platadata(struct udevice *bus) { struct davinci_spi_plat *plat = dev_get_plat(bus); @@ -418,7 +418,7 @@ static const struct udevice_id davinci_spi_ids[] = { U_BOOT_DRIVER(davinci_spi) = { .name = "davinci_spi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = davinci_spi_ids, .of_to_plat = davinci_ofdata_to_platadata, .plat_auto = sizeof(struct davinci_spi_plat), diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 387b547159..c7a692623f 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -541,7 +541,7 @@ static const struct dm_spi_ops fsl_espi_ops = { .set_mode = fsl_espi_set_mode, }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int fsl_espi_of_to_plat(struct udevice *bus) { fdt_addr_t addr; @@ -572,7 +572,7 @@ static const struct udevice_id fsl_espi_ids[] = { U_BOOT_DRIVER(fsl_espi) = { .name = "fsl_espi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = fsl_espi_ids, .of_to_plat = fsl_espi_of_to_plat, #endif diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 08d54e86f4..42071bb70c 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -604,7 +604,7 @@ static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /** * ich_spi_get_basics() - Get basic information about the ICH device * @@ -672,7 +672,7 @@ static int ich_get_mmap_bus(struct udevice *bus, ulong *map_basep, uint *map_sizep, uint *offsetp) { pci_dev_t spi_bdf; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) if (device_is_on_pci_bus(bus)) { struct pci_child_plat *pplat; @@ -940,7 +940,7 @@ static int ich_spi_of_to_plat(struct udevice *dev) { struct ich_spi_plat *plat = dev_get_plat(dev); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) struct ich_spi_priv *priv = dev_get_priv(dev); int ret; diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index d41352a0bb..773e26bbed 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -440,7 +440,7 @@ static const struct dm_spi_ops mxs_spi_ops = { */ }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int mxs_of_to_plat(struct udevice *bus) { struct mxs_spi_plat *plat = dev_get_plat(bus); @@ -483,7 +483,7 @@ static const struct udevice_id mxs_spi_ids[] = { U_BOOT_DRIVER(fsl_imx23_spi) = { .name = "fsl_imx23_spi", .id = UCLASS_SPI, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = mxs_spi_ids, .of_to_plat = mxs_of_to_plat, #endif diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index c69f8fee6e..ea38a0ffba 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -481,7 +481,7 @@ static const struct dm_spi_ops omap3_spi_ops = { */ }; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static struct omap2_mcspi_platform_config omap2_pdata = { .regs_offset = 0, }; @@ -516,7 +516,7 @@ U_BOOT_DRIVER(omap3_spi) = { .name = "omap3_spi", .id = UCLASS_SPI, .flags = DM_FLAG_PRE_RELOC, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = omap3_spi_ids, .of_to_plat = omap3_spi_of_to_plat, .plat_auto = sizeof(struct omap3_spi_plat), diff --git a/drivers/spi/pl022_spi.c b/drivers/spi/pl022_spi.c index 9856a5669c..ea1691438b 100644 --- a/drivers/spi/pl022_spi.c +++ b/drivers/spi/pl022_spi.c @@ -286,7 +286,7 @@ static const struct dm_spi_ops pl022_spi_ops = { .cs_info = pl022_cs_info, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int pl022_spi_of_to_plat(struct udevice *bus) { struct pl022_spi_pdata *plat = dev_get_plat(bus); @@ -315,7 +315,7 @@ static const struct udevice_id pl022_spi_ids[] = { U_BOOT_DRIVER(pl022_spi) = { .name = "pl022_spi", .id = UCLASS_SPI, -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .of_match = pl022_spi_ids, .of_to_plat = pl022_spi_of_to_plat, #endif diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c index 40bd8851b7..cb80be77ae 100644 --- a/drivers/spi/rk_spi.c +++ b/drivers/spi/rk_spi.c @@ -183,7 +183,7 @@ static int conv_of_plat(struct udevice *dev) plat->base = dtplat->reg[0]; plat->frequency = 20000000; - ret = clk_get_by_driver_info(dev, dtplat->clocks, &priv->clk); + ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk); if (ret < 0) return ret; @@ -193,31 +193,31 @@ static int conv_of_plat(struct udevice *dev) static int rockchip_spi_of_to_plat(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_spi_plat *plat = dev_get_plat(bus); struct rockchip_spi_priv *priv = dev_get_priv(bus); int ret; - plat->base = dev_read_addr(bus); + if (CONFIG_IS_ENABLED(OF_REAL)) { + plat->base = dev_read_addr(bus); - ret = clk_get_by_index(bus, 0, &priv->clk); - if (ret < 0) { - debug("%s: Could not get clock for %s: %d\n", __func__, - bus->name, ret); - return ret; - } + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) { + debug("%s: Could not get clock for %s: %d\n", __func__, + bus->name, ret); + return ret; + } - plat->frequency = - dev_read_u32_default(bus, "spi-max-frequency", 50000000); - plat->deactivate_delay_us = - dev_read_u32_default(bus, "spi-deactivate-delay", 0); - plat->activate_delay_us = - dev_read_u32_default(bus, "spi-activate-delay", 0); + plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", + 50000000); + plat->deactivate_delay_us = + dev_read_u32_default(bus, "spi-deactivate-delay", 0); + plat->activate_delay_us = + dev_read_u32_default(bus, "spi-activate-delay", 0); - debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", - __func__, (uint)plat->base, plat->frequency, - plat->deactivate_delay_us); -#endif + debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", + __func__, (uint)plat->base, plat->frequency, + plat->deactivate_delay_us); + } return 0; } diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index d867b27806..f8ec312d71 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -162,7 +162,7 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, return ret; } -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); @@ -176,11 +176,11 @@ static int spi_child_post_bind(struct udevice *dev) static int spi_post_probe(struct udevice *bus) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct dm_spi_bus *spi = dev_get_uclass_priv(bus); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct dm_spi_bus *spi = dev_get_uclass_priv(bus); - spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); -#endif + spi->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + } #if defined(CONFIG_NEEDS_MANUAL_RELOC) struct dm_spi_ops *ops = spi_get_ops(bus); static int reloc_done; @@ -531,7 +531,7 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .post_probe = spi_post_probe, @@ -539,7 +539,7 @@ UCLASS_DRIVER(spi) = { .per_device_auto = sizeof(struct dm_spi_bus), .per_child_auto = sizeof(struct spi_slave), .per_child_plat_auto = sizeof(struct dm_spi_slave_plat), -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .child_post_bind = spi_child_post_bind, #endif }; diff --git a/drivers/sysreset/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 08685823e9..0ee286cbb3 100644 --- a/drivers/sysreset/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c @@ -133,7 +133,7 @@ U_BOOT_DRIVER(warm_sysreset_sandbox) = { .ops = &sandbox_warm_sysreset_ops, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) /* This is here in case we don't have a device tree */ U_BOOT_DRVINFO(sysreset_sandbox_non_fdt) = { .name = "sysreset_sandbox", diff --git a/drivers/timer/rockchip_timer.c b/drivers/timer/rockchip_timer.c index 18c61450af..62eacb9868 100644 --- a/drivers/timer/rockchip_timer.c +++ b/drivers/timer/rockchip_timer.c @@ -55,8 +55,7 @@ ulong timer_get_boot_us(void) /* The timer is available */ rate = timer_get_rate(gd->timer); timer_get_count(gd->timer, &ticks); -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - } else if (ret == -EAGAIN) { + } else if (CONFIG_IS_ENABLED(OF_REAL) && ret == -EAGAIN) { /* We have been called so early that the DM is not ready,... */ ofnode node = offset_to_ofnode(-1); struct rk_timer *timer = NULL; @@ -79,7 +78,6 @@ ulong timer_get_boot_us(void) debug("%s: could not read clock-frequency\n", __func__); return 0; } -#endif } else { return 0; } @@ -100,13 +98,13 @@ static u64 rockchip_timer_get_count(struct udevice *dev) static int rockchip_clk_of_to_plat(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rockchip_timer_priv *priv = dev_get_priv(dev); + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct rockchip_timer_priv *priv = dev_get_priv(dev); - priv->timer = dev_read_addr_ptr(dev); - if (!priv->timer) - return -ENOENT; -#endif + priv->timer = dev_read_addr_ptr(dev); + if (!priv->timer) + return -ENOENT; + } return 0; } diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index c8e8419b22..6ea9e39e12 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -50,27 +50,29 @@ unsigned long notrace timer_get_rate(struct udevice *dev) static int timer_pre_probe(struct udevice *dev) { -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); - struct clk timer_clk; - int err; - ulong ret; + if (CONFIG_IS_ENABLED(OF_REAL)) { + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct clk timer_clk; + int err; + ulong ret; - /* It is possible that a timer device has a null ofnode */ - if (!dev_has_ofnode(dev)) - return 0; + /* + * It is possible that a timer device has a null ofnode + */ + if (!dev_has_ofnode(dev)) + return 0; - err = clk_get_by_index(dev, 0, &timer_clk); - if (!err) { - ret = clk_get_rate(&timer_clk); - if (IS_ERR_VALUE(ret)) - return ret; - uc_priv->clock_rate = ret; - } else { - uc_priv->clock_rate = - dev_read_u32_default(dev, "clock-frequency", 0); + err = clk_get_by_index(dev, 0, &timer_clk); + if (!err) { + ret = clk_get_rate(&timer_clk); + if (IS_ERR_VALUE(ret)) + return ret; + uc_priv->clock_rate = ret; + } else { + uc_priv->clock_rate = + dev_read_u32_default(dev, "clock-frequency", 0); + } } -#endif return 0; } @@ -136,23 +138,23 @@ int notrace dm_timer_init(void) if (gd->dm_root == NULL) return -EAGAIN; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - /* Check for a chosen timer to be used for tick */ - node = ofnode_get_chosen_node("tick-timer"); - - if (ofnode_valid(node) && - uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { - /* - * If the timer is not marked to be bound before - * relocation, bind it anyway. - */ - if (!lists_bind_fdt(dm_root(), node, &dev, false)) { - ret = device_probe(dev); - if (ret) - return ret; + if (CONFIG_IS_ENABLED(OF_REAL)) { + /* Check for a chosen timer to be used for tick */ + node = ofnode_get_chosen_node("tick-timer"); + + if (ofnode_valid(node) && + uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { + /* + * If the timer is not marked to be bound before + * relocation, bind it anyway. + */ + if (!lists_bind_fdt(dm_root(), node, &dev, false)) { + ret = device_probe(dev); + if (ret) + return ret; + } } } -#endif if (!dev) { /* Fall back to the first available timer */ diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c index adef50c374..192c7b71a5 100644 --- a/drivers/timer/tsc_timer.c +++ b/drivers/timer/tsc_timer.c @@ -479,7 +479,7 @@ static const struct timer_ops tsc_timer_ops = { .get_count = tsc_timer_get_count, }; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) static const struct udevice_id tsc_timer_ids[] = { { .compatible = "x86,tsc-timer", }, { } diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index 35774a6289..f67fe1019b 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -140,7 +140,7 @@ UCLASS_DRIVER(tpm) = { .id = UCLASS_TPM, .name = "tpm", .flags = DM_UC_FLAG_SEQ_ALIAS, -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +#if CONFIG_IS_ENABLED(OF_REAL) .post_bind = dm_scan_fdt_dev, #endif .per_device_auto = sizeof(struct tpm_chip_priv), diff --git a/drivers/tpm/tpm2_tis_spi.c b/drivers/tpm/tpm2_tis_spi.c index 4b33ac8fd3..1d24d32d86 100644 --- a/drivers/tpm/tpm2_tis_spi.c +++ b/drivers/tpm/tpm2_tis_spi.c @@ -589,18 +589,25 @@ static int tpm_tis_spi_probe(struct udevice *dev) if (CONFIG_IS_ENABLED(DM_GPIO)) { struct gpio_desc reset_gpio; - ret = gpio_request_by_name(dev, "gpio-reset", 0, + ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset_gpio, GPIOD_IS_OUT); if (ret) { - log(LOGC_NONE, LOGL_NOTICE, "%s: missing reset GPIO\n", - __func__); - } else { - dm_gpio_set_value(&reset_gpio, 1); - mdelay(1); - dm_gpio_set_value(&reset_gpio, 0); + /* legacy reset */ + ret = gpio_request_by_name(dev, "gpio-reset", 0, + &reset_gpio, GPIOD_IS_OUT); + if (ret) { + log(LOGC_NONE, LOGL_NOTICE, + "%s: missing reset GPIO\n", __func__); + goto init; + } + log(LOGC_NONE, LOGL_NOTICE, + "%s: gpio-reset is deprecated\n", __func__); } + dm_gpio_set_value(&reset_gpio, 1); + mdelay(1); + dm_gpio_set_value(&reset_gpio, 0); } - +init: /* Ensure a minimum amount of time elapsed since reset of the TPM */ mdelay(drv_data->time_before_first_cmd_ms); diff --git a/drivers/usb/gadget/f_rockusb.c b/drivers/usb/gadget/f_rockusb.c index bd846ce9a7..98a7ffa2a7 100644 --- a/drivers/usb/gadget/f_rockusb.c +++ b/drivers/usb/gadget/f_rockusb.c @@ -17,7 +17,6 @@ #include <linux/usb/gadget.h> #include <linux/usb/composite.h> #include <linux/compiler.h> -#include <version.h> #include <g_dnl.h> #include <asm/arch-rockchip/f_rockusb.h> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 427b360af1..10b0479a8a 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -57,6 +57,16 @@ config USB_XHCI_OCTEON family SoCs. This is a driver for the dwc3 to provide the glue logic to configure the controller. +config USB_XHCI_OMAP + bool "Support for TI OMAP family xHCI USB controller" + depends on ARCH_OMAP2PLUS + help + Enables support for the on-chip xHCI controller found on some TI SoC + families. Note that some families have multiple contollers while + others only have something such as DesignWare-based controllers. + Consult the SoC documentation to determine if this option applies + to your hardware. + config USB_XHCI_PCI bool "Support for PCI-based xHCI USB controller" depends on DM_USB @@ -146,7 +156,6 @@ config USB_EHCI_MARVELL config USB_EHCI_MX5 bool "Support for i.MX5 on-chip EHCI USB controller" depends on ARCH_MX5 - default n help Enables support for the on-chip EHCI controller on i.MX5 SoCs. @@ -174,6 +183,40 @@ config USB_EHCI_OMAP Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. +if USB_EHCI_OMAP + +config HAS_OMAP_EHCI_PHY1_RESET_GPIO + bool "PHY #1 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY1_RESET_GPIO + int "GPIO number to hold PHY #1 in RESET" + depends on HAS_OMAP_EHCI_PHY1_RESET_GPIO + +config HAS_OMAP_EHCI_PHY2_RESET_GPIO + bool "PHY #2 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY2_RESET_GPIO + int "GPIO number to hold PHY #2 in RESET" + depends on HAS_OMAP_EHCI_PHY2_RESET_GPIO + +config HAS_OMAP_EHCI_PHY3_RESET_GPIO + bool "PHY #3 requires a GPIO hold to it in RESET while PHY settles" + help + Enable this to be able to configure the GPIO number used to hold the + PHY in RESET for enough time until the PHY is settled and ready. + +config OMAP_EHCI_PHY3_RESET_GPIO + int "GPIO number to hold PHY #3 in RESET" + depends on HAS_OMAP_EHCI_PHY3_RESET_GPIO + +endif + config USB_EHCI_VF bool "Support for Vybrid on-chip EHCI USB controller" depends on ARCH_VF610 @@ -195,7 +238,6 @@ config USB_EHCI_MSM depends on DM_USB select USB_ULPI_VIEWPORT select MSM8916_USB_PHY - default n ---help--- Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. @@ -222,13 +264,11 @@ config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on DM_USB default ARCH_SUNXI - default n ---help--- Enables support for generic EHCI controller. config USB_EHCI_FSL bool "Support for FSL on-chip EHCI USB controller" - default n select CONFIG_EHCI_HCD_INIT_AFTER_RESET ---help--- Enables support for the on-chip EHCI controller on FSL chips. diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c index 43cc2e0433..23060fc369 100644 --- a/drivers/usb/host/dwc2.c +++ b/drivers/usb/host/dwc2.c @@ -86,14 +86,14 @@ static void init_fslspclksel(struct dwc2_core_regs *regs) { uint32_t phyclk; -#if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */ #else /* High speed PHY running at full speed or high speed */ phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ; #endif -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(®s->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -257,28 +257,28 @@ static void dwc_otg_core_host_init(struct udevice *dev, /* Initialize Host Configuration Register */ init_fslspclksel(regs); -#ifdef CONFIG_DWC2_DFLT_SPEED_FULL +#ifdef DWC2_DFLT_SPEED_FULL setbits_le32(®s->host_regs.hcfg, DWC2_HCFG_FSLSSUPP); #endif /* Configure data FIFO sizes */ -#ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO +#ifdef DWC2_ENABLE_DYNAMIC_FIFO if (readl(®s->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) { /* Rx FIFO */ - writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); + writel(DWC2_HOST_RX_FIFO_SIZE, ®s->grxfsiz); /* Non-periodic Tx FIFO */ - nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_NPERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE << + nptxfifosize |= DWC2_HOST_RX_FIFO_SIZE << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(nptxfifosize, ®s->gnptxfsiz); /* Periodic Tx FIFO */ - ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE << + ptxfifosize |= DWC2_HOST_PERIO_TX_FIFO_SIZE << DWC2_FIFOSIZE_DEPTH_OFFSET; - ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE + - CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) << + ptxfifosize |= (DWC2_HOST_RX_FIFO_SIZE + + DWC2_HOST_NPERIO_TX_FIFO_SIZE) << DWC2_FIFOSIZE_STARTADDR_OFFSET; writel(ptxfifosize, ®s->hptxfsiz); } @@ -340,7 +340,7 @@ static void dwc_otg_core_init(struct udevice *dev) struct dwc2_core_regs *regs = priv->regs; uint32_t ahbcfg = 0; uint32_t usbcfg = 0; - uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE; + uint8_t brst_sz = DWC2_DMA_BURST_SIZE; /* Common Initialization */ usbcfg = readl(®s->gusbcfg); @@ -357,7 +357,7 @@ static void dwc_otg_core_init(struct udevice *dev) } /* Set external TS Dline pulsing */ -#ifdef CONFIG_DWC2_TS_DLINE +#ifdef DWC2_TS_DLINE usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE; #else usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE; @@ -371,8 +371,8 @@ static void dwc_otg_core_init(struct udevice *dev) * This programming sequence needs to happen in FS mode before * any other programming occurs */ -#if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \ - (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) +#if defined(DWC2_DFLT_SPEED_FULL) && \ + (DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS) /* If FS mode with FS PHY */ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_PHYSEL); @@ -387,7 +387,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (readl(®s->gintsts) & DWC2_GINTSTS_CURMODE_HOST) init_fslspclksel(regs); -#ifdef CONFIG_DWC2_I2C_ENABLE +#ifdef DWC2_I2C_ENABLE /* Program GUSBCFG.OtgUtmifsSel to I2C */ setbits_le32(®s->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL); @@ -407,16 +407,16 @@ static void dwc_otg_core_init(struct udevice *dev) * immediately after setting phyif. */ usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF); - usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; + usbcfg |= DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET; if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ -#ifdef CONFIG_DWC2_PHY_ULPI_DDR +#ifdef DWC2_PHY_ULPI_DDR usbcfg |= DWC2_GUSBCFG_DDRSEL; #else usbcfg &= ~DWC2_GUSBCFG_DDRSEL; #endif } else { /* UTMI+ interface */ -#if (CONFIG_DWC2_UTMI_WIDTH == 16) +#if (DWC2_UTMI_WIDTH == 16) usbcfg |= DWC2_GUSBCFG_PHYIF; #endif } @@ -429,7 +429,7 @@ static void dwc_otg_core_init(struct udevice *dev) usbcfg = readl(®s->gusbcfg); usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M); -#ifdef CONFIG_DWC2_ULPI_FS_LS +#ifdef DWC2_ULPI_FS_LS uint32_t hwcfg2 = readl(®s->ghwcfg2); uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >> DWC2_HWCFG2_HS_PHY_TYPE_OFFSET; @@ -456,14 +456,14 @@ static void dwc_otg_core_init(struct udevice *dev) brst_sz >>= 1; } -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; case DWC2_HWCFG2_ARCHITECTURE_INT_DMA: ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4; -#ifdef CONFIG_DWC2_DMA_ENABLE +#ifdef DWC2_DMA_ENABLE ahbcfg |= DWC2_GAHBCFG_DMAENABLE; #endif break; @@ -476,7 +476,7 @@ static void dwc_otg_core_init(struct udevice *dev) if (!priv->hnp_srp_disable) usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP; -#ifdef CONFIG_DWC2_IC_USB_CAP +#ifdef DWC2_IC_USB_CAP usbcfg |= DWC2_GUSBCFG_IC_USB_CAP; #endif @@ -939,9 +939,9 @@ int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev, debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid, in, len); - max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max; - if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE) - max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE; + max_xfer_len = DWC2_MAX_PACKET_COUNT * max; + if (max_xfer_len > DWC2_MAX_TRANSFER_SIZE) + max_xfer_len = DWC2_MAX_TRANSFER_SIZE; if (max_xfer_len > DWC2_DATA_BUF_SIZE) max_xfer_len = DWC2_DATA_BUF_SIZE; @@ -1198,7 +1198,7 @@ static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv) return -ENODEV; } -#ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS +#ifdef DWC2_PHY_ULPI_EXT_VBUS priv->ext_vbus = 1; #else priv->ext_vbus = 0; diff --git a/drivers/usb/host/dwc2.h b/drivers/usb/host/dwc2.h index 97a06c48f2..a6f562fe60 100644 --- a/drivers/usb/host/dwc2.h +++ b/drivers/usb/host/dwc2.h @@ -759,32 +759,32 @@ struct dwc2_core_regs { #define RH_B_PPCM 0xffff0000 /* port power control mask */ /* Default driver configuration */ -#define CONFIG_DWC2_DMA_ENABLE -#define CONFIG_DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ -#undef CONFIG_DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ -#define CONFIG_DWC2_MAX_CHANNELS 16 /* Max # of EPs */ -#define CONFIG_DWC2_HOST_RX_FIFO_SIZE (516 + CONFIG_DWC2_MAX_CHANNELS) -#define CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ -#define CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ -#define CONFIG_DWC2_MAX_TRANSFER_SIZE 65535 -#define CONFIG_DWC2_MAX_PACKET_COUNT 511 +#define DWC2_DMA_ENABLE +#define DWC2_DMA_BURST_SIZE 32 /* DMA burst len */ +#undef DWC2_DFLT_SPEED_FULL /* Do not force DWC2 to FS */ +#define DWC2_ENABLE_DYNAMIC_FIFO /* Runtime FIFO size detect */ +#define DWC2_MAX_CHANNELS 16 /* Max # of EPs */ +#define DWC2_HOST_RX_FIFO_SIZE (516 + DWC2_MAX_CHANNELS) +#define DWC2_HOST_NPERIO_TX_FIFO_SIZE 0x100 /* nPeriodic TX FIFO */ +#define DWC2_HOST_PERIO_TX_FIFO_SIZE 0x200 /* Periodic TX FIFO */ +#define DWC2_MAX_TRANSFER_SIZE 65535 +#define DWC2_MAX_PACKET_COUNT 511 #define DWC2_PHY_TYPE_FS 0 #define DWC2_PHY_TYPE_UTMI 1 #define DWC2_PHY_TYPE_ULPI 2 -#define CONFIG_DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ -#ifndef CONFIG_DWC2_UTMI_WIDTH -#define CONFIG_DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ +#define DWC2_PHY_TYPE DWC2_PHY_TYPE_UTMI /* PHY type */ +#ifndef DWC2_UTMI_WIDTH +#define DWC2_UTMI_WIDTH 8 /* UTMI bus width (8/16) */ #endif -#undef CONFIG_DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ -#define CONFIG_DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ -#undef CONFIG_DWC2_I2C_ENABLE /* Enable I2C */ -#undef CONFIG_DWC2_ULPI_FS_LS /* ULPI is FS/LS */ -#undef CONFIG_DWC2_TS_DLINE /* External DLine pulsing */ -#undef CONFIG_DWC2_THR_CTL /* Threshold control */ -#define CONFIG_DWC2_TX_THR_LENGTH 64 -#undef CONFIG_DWC2_IC_USB_CAP /* IC Cap */ +#undef DWC2_PHY_ULPI_DDR /* ULPI PHY uses DDR mode */ +#define DWC2_PHY_ULPI_EXT_VBUS /* ULPI PHY controls VBUS */ +#undef DWC2_I2C_ENABLE /* Enable I2C */ +#undef DWC2_ULPI_FS_LS /* ULPI is FS/LS */ +#undef DWC2_TS_DLINE /* External DLine pulsing */ +#undef DWC2_THR_CTL /* Threshold control */ +#define DWC2_TX_THR_LENGTH 64 +#undef DWC2_IC_USB_CAP /* IC Cap */ #endif /* __DWC2_H__ */ diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c index 12c422d811..d5facf10e1 100644 --- a/drivers/usb/host/ehci-omap.c +++ b/drivers/usb/host/ehci-omap.c @@ -183,17 +183,8 @@ int omap_ehci_hcd_stop(void) * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 * See there for additional Copyrights. */ -#if !CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL) - -int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); - *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); -#else int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata) { -#endif int ret; unsigned int i, reg = 0, rev = 0; @@ -304,8 +295,6 @@ int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata) return 0; } -#if CONFIG_IS_ENABLED(DM_USB) - static struct omap_usbhs_board_data usbhs_bdata = { .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, @@ -409,5 +398,3 @@ U_BOOT_DRIVER(usb_omap_ehci) = { .ops = &ehci_usb_ops, .flags = DM_FLAG_ALLOC_PRIV_DMA, }; - -#endif diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index a9a7c2675e..6dd830cb73 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -34,7 +34,6 @@ config USB_MUSB_TI bool "Enable TI OTG USB controller" depends on AM33XX select USB_MUSB_DSPS - default n help Say y here to enable support for the dual role high speed USB controller based on the Mentor Graphics @@ -53,7 +52,6 @@ config USB_MUSB_DSPS config USB_MUSB_MT85XX bool "Enable Mediatek MT85XX DRC USB controller" depends on ARCH_MEDIATEK - default n help Say y to enable Mediatek MT85XX USB DRC controller support if it is available on your Mediatek MUSB IP based platform. diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 8741553d09..c505862f1e 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -8,8 +8,5 @@ comment "USB Phy" config TWL4030_USB bool "TWL4030 PHY" -config OMAP_USB_PHY - bool "OMAP PHY" - config ROCKCHIP_USB2_PHY bool "Rockchip USB2 PHY" diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 20f7edf48d..b67a70bbe8 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -4,5 +4,4 @@ # Tom Rix <Tom.Rix@windriver.com> obj-$(CONFIG_TWL4030_USB) += twl4030.o -obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o diff --git a/drivers/usb/phy/omap_usb_phy.c b/drivers/usb/phy/omap_usb_phy.c deleted file mode 100644 index be733f39b2..0000000000 --- a/drivers/usb/phy/omap_usb_phy.c +++ /dev/null @@ -1,267 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * OMAP USB PHY Support - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * Author: Dan Murphy <dmurphy@ti.com> - */ - -#include <common.h> -#include <usb.h> -#include <dm/device_compat.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/omap_common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/sys_proto.h> - -#include <linux/compat.h> -#include <linux/usb/dwc3.h> -#include <linux/usb/xhci-omap.h> - -#include <usb/xhci.h> - -#ifdef CONFIG_OMAP_USB3PHY1_HOST -struct usb3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct usb3_dpll_map { - unsigned long rate; - struct usb3_dpll_params params; - struct usb3_dpll_map *dpll_map; -}; - -static struct usb3_dpll_map dpll_map_usb[] = { - {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */ - {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */ - {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */ - {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */ - {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */ - {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -static struct usb3_dpll_params *omap_usb3_get_dpll_params(void) -{ - unsigned long rate; - struct usb3_dpll_map *dpll_map = dpll_map_usb; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate); - - return NULL; -} - -static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs) -{ - u32 val; - - writel(SET_PLL_GO, &phy_regs->pll_go); - do { - val = readl(&phy_regs->pll_status); - if (val & PLL_LOCK) - break; - } while (1); -} - -static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs) -{ - struct usb3_dpll_params *dpll_params; - u32 val; - - dpll_params = omap_usb3_get_dpll_params(); - if (!dpll_params) - return; - - val = readl(&phy_regs->pll_config_1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - writel(val, &phy_regs->pll_config_1); - - val = readl(&phy_regs->pll_config_2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - writel(val, &phy_regs->pll_config_2); - - val = readl(&phy_regs->pll_config_1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - writel(val, &phy_regs->pll_config_1); - - val = readl(&phy_regs->pll_config_4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - writel(val, &phy_regs->pll_config_4); - - val = readl(&phy_regs->pll_config_3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - writel(val, &phy_regs->pll_config_3); - - omap_usb_dpll_relock(phy_regs); -} - -static void usb3_phy_partial_powerup(struct omap_usb3_phy *phy_regs) -{ - u32 rate = get_sys_clk_freq()/1000000; - u32 val; - - val = readl((*ctrl)->control_phy_power_usb); - val &= ~(USB3_PWRCTL_CLK_CMD_MASK | USB3_PWRCTL_CLK_FREQ_MASK); - val |= (USB3_PHY_PARTIAL_RX_POWERON | USB3_PHY_TX_RX_POWERON); - val |= rate << USB3_PWRCTL_CLK_FREQ_SHIFT; - - writel(val, (*ctrl)->control_phy_power_usb); -} - -void usb_phy_power(int on) -{ - u32 val; - - val = readl((*ctrl)->control_phy_power_usb); - if (on) { - val &= ~USB3_PWRCTL_CLK_CMD_MASK; - val |= USB3_PHY_TX_RX_POWERON; - } else { - val &= (~USB3_PWRCTL_CLK_CMD_MASK & ~USB3_PHY_TX_RX_POWERON); - } - - writel(val, (*ctrl)->control_phy_power_usb); -} - -void omap_usb3_phy_init(struct omap_usb3_phy *phy_regs) -{ - omap_usb_dpll_lock(phy_regs); - usb3_phy_partial_powerup(phy_regs); - /* - * Give enough time for the PHY to partially power-up before - * powering it up completely. delay value suggested by the HW - * team. - */ - mdelay(100); -} - -static void omap_enable_usb3_phy(struct omap_xhci *omap) -{ - u32 val; - - val = (USBOTGSS_DMADISABLE | - USBOTGSS_STANDBYMODE_SMRT_WKUP | - USBOTGSS_IDLEMODE_NOIDLE); - writel(val, &omap->otg_wrapper->sysconfig); - - /* Clear the utmi OTG status */ - val = readl(&omap->otg_wrapper->utmi_otg_status); - writel(val, &omap->otg_wrapper->utmi_otg_status); - - /* Enable interrupts */ - writel(USBOTGSS_COREIRQ_EN, &omap->otg_wrapper->irqenable_set_0); - val = (USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN | - USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN | - USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN | - USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN | - USBOTGSS_IRQ_SET_1_OEVT_EN); - writel(val, &omap->otg_wrapper->irqenable_set_1); - - /* Clear the IRQ status */ - val = readl(&omap->otg_wrapper->irqstatus_1); - writel(val, &omap->otg_wrapper->irqstatus_1); - val = readl(&omap->otg_wrapper->irqstatus_0); - writel(val, &omap->otg_wrapper->irqstatus_0); -}; -#endif /* CONFIG_OMAP_USB3PHY1_HOST */ - -#ifdef CONFIG_OMAP_USB2PHY2_HOST -static void omap_enable_usb2_phy2(struct omap_xhci *omap) -{ - u32 reg, val; - - val = (~USB2PHY_AUTORESUME_EN & USB2PHY_DISCHGDET); - writel(val, (*ctrl)->control_srcomp_north_side); - - setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, - USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); - - setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, - (USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K | - OTG_SS_CLKCTRL_MODULEMODE_HW)); - - /* This is an undocumented Reserved register */ - reg = 0x4a0086c0; - val = readl(reg); - val |= 0x100; - setbits_le32(reg, val); -} - -void usb_phy_power(int on) -{ - return; -} -#endif /* CONFIG_OMAP_USB2PHY2_HOST */ - -#ifdef CONFIG_AM437X_USB2PHY2_HOST -static void am437x_enable_usb2_phy2(struct omap_xhci *omap) -{ - const u32 usb_otg_ss_clk_val = (USBOTGSSX_CLKCTRL_MODULE_EN | - USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960); - - writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS0_CLKCTRL); - writel(usb_otg_ss_clk_val, PRM_PER_USB_OTG_SS1_CLKCTRL); - - writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP0_CLKCTRL); - writel(USBPHYOCPSCP_MODULE_EN, PRM_PER_USBPHYOCP2SCP1_CLKCTRL); -} - -void usb_phy_power(int on) -{ - u32 val; - - /* USB1_CTRL */ - val = readl(USB1_CTRL); - if (on) { - /* - * these bits are re-used on AM437x to power up/down the USB - * CM and OTG PHYs, if we don't toggle them, USB will not be - * functional on newer silicon revisions - */ - val &= ~(USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN); - } else { - val |= USB1_CTRL_CM_PWRDN | USB1_CTRL_OTG_PWRDN; - } - - writel(val, USB1_CTRL); -} -#endif /* CONFIG_AM437X_USB2PHY2_HOST */ - -void omap_enable_phy(struct omap_xhci *omap) -{ -#ifdef CONFIG_OMAP_USB2PHY2_HOST - omap_enable_usb2_phy2(omap); -#endif - -#ifdef CONFIG_AM437X_USB2PHY2_HOST - am437x_enable_usb2_phy2(omap); -#endif - -#ifdef CONFIG_OMAP_USB3PHY1_HOST - omap_enable_usb3_phy(omap); - omap_usb3_phy_init(omap->usb3_phy); -#endif -} diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 8b940d70eb..b1f8a9c1e6 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -259,7 +259,6 @@ config VIDEO_EFI config VIDEO_VESA bool "Enable VESA video driver support" - default n help Turn on this option to enable a very simple driver which uses vesa to discover the video mode and then provides a frame buffer for use @@ -406,7 +405,6 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - default n ---help--- Support for the ANX9804 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fy into a DP @@ -416,7 +414,6 @@ config VIDEO_LCD_ORISETECH_OTM8009A bool "OTM8009A DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for Orise Technology otm8009a 480x800 dsi 2dl panel. @@ -425,14 +422,12 @@ config VIDEO_LCD_RAYDIUM_RM68200 bool "RM68200 DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for Raydium RM68200 720x1280 DSI video mode panel. config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - default n ---help--- Support for the SSD2828 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fly into MIPI DSI @@ -463,14 +458,12 @@ config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" depends on DM_VIDEO select VIDEO_MIPI_DSI - default n help Say Y here if you want to enable support for TDO TL070WSH30 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - default n ---help--- Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a lcd controller which needs to be initialized over SPI, once that is @@ -523,7 +516,6 @@ source "drivers/video/meson/Kconfig" config VIDEO_MVEBU bool "Armada XP LCD controller" - default n ---help--- Support for the LCD controller integrated in the Marvell Armada XP SoC. @@ -536,14 +528,12 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" - default n help This enables library for accessing EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM - default n select I2C_EDID help This supports drivers that provide a display, such as eDP (Embedded @@ -554,7 +544,6 @@ config DISPLAY config NXP_TDA19988 bool "Enable NXP TDA19988 support" depends on DISPLAY - default n help This enables support for the NXP TDA19988 HDMI encoder. This encoder will convert RGB data streams into HDMI-encoded signals. @@ -868,7 +857,6 @@ config VIDEO_MCDE_SIMPLE config OSD bool "Enable OSD support" depends on DM - default n help This supports drivers that provide a OSD (on-screen display), which is a (usually text-oriented) graphics buffer to show information on @@ -1008,7 +996,6 @@ config BMP_32BPP config VIDEO_VCXK bool "Enable VCXK video controller driver support" - default n help This enables VCXK driver which can be used with VC2K, VC4K and VC8K devices on various boards from BuS Elektronik GmbH. diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 7ae0ab2b35..f6d07b343f 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -25,7 +25,6 @@ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ obj-y += ti/ -obj-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o diff --git a/drivers/video/ati_ids.h b/drivers/video/ati_ids.h deleted file mode 100644 index 3e72a7dd4c..0000000000 --- a/drivers/video/ati_ids.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * ATI PCI IDs from XFree86, kept here to make sync'ing with - * XFree much simpler. Currently, this list is only used by - * radeonfb - */ - -#define PCI_CHIP_RV380_3150 0x3150 -#define PCI_CHIP_RV380_3151 0x3151 -#define PCI_CHIP_RV380_3152 0x3152 -#define PCI_CHIP_RV380_3153 0x3153 -#define PCI_CHIP_RV380_3154 0x3154 -#define PCI_CHIP_RV380_3156 0x3156 -#define PCI_CHIP_RV380_3E50 0x3E50 -#define PCI_CHIP_RV380_3E51 0x3E51 -#define PCI_CHIP_RV380_3E52 0x3E52 -#define PCI_CHIP_RV380_3E53 0x3E53 -#define PCI_CHIP_RV380_3E54 0x3E54 -#define PCI_CHIP_RV380_3E56 0x3E56 -#define PCI_CHIP_RS100_4136 0x4136 -#define PCI_CHIP_RS200_4137 0x4137 -#define PCI_CHIP_R300_AD 0x4144 -#define PCI_CHIP_R300_AE 0x4145 -#define PCI_CHIP_R300_AF 0x4146 -#define PCI_CHIP_R300_AG 0x4147 -#define PCI_CHIP_R350_AH 0x4148 -#define PCI_CHIP_R350_AI 0x4149 -#define PCI_CHIP_R350_AJ 0x414A -#define PCI_CHIP_R350_AK 0x414B -#define PCI_CHIP_RV350_AP 0x4150 -#define PCI_CHIP_RV350_AQ 0x4151 -#define PCI_CHIP_RV360_AR 0x4152 -#define PCI_CHIP_RV350_AS 0x4153 -#define PCI_CHIP_RV350_AT 0x4154 -#define PCI_CHIP_RV350_AV 0x4156 -#define PCI_CHIP_MACH32 0x4158 -#define PCI_CHIP_RS250_4237 0x4237 -#define PCI_CHIP_R200_BB 0x4242 -#define PCI_CHIP_R200_BC 0x4243 -#define PCI_CHIP_RS100_4336 0x4336 -#define PCI_CHIP_RS200_4337 0x4337 -#define PCI_CHIP_MACH64CT 0x4354 -#define PCI_CHIP_MACH64CX 0x4358 -#define PCI_CHIP_RS250_4437 0x4437 -#define PCI_CHIP_MACH64ET 0x4554 -#define PCI_CHIP_MACH64GB 0x4742 -#define PCI_CHIP_MACH64GD 0x4744 -#define PCI_CHIP_MACH64GI 0x4749 -#define PCI_CHIP_MACH64GL 0x474C -#define PCI_CHIP_MACH64GM 0x474D -#define PCI_CHIP_MACH64GN 0x474E -#define PCI_CHIP_MACH64GO 0x474F -#define PCI_CHIP_MACH64GP 0x4750 -#define PCI_CHIP_MACH64GQ 0x4751 -#define PCI_CHIP_MACH64GR 0x4752 -#define PCI_CHIP_MACH64GS 0x4753 -#define PCI_CHIP_MACH64GT 0x4754 -#define PCI_CHIP_MACH64GU 0x4755 -#define PCI_CHIP_MACH64GV 0x4756 -#define PCI_CHIP_MACH64GW 0x4757 -#define PCI_CHIP_MACH64GX 0x4758 -#define PCI_CHIP_MACH64GY 0x4759 -#define PCI_CHIP_MACH64GZ 0x475A -#define PCI_CHIP_RV250_Id 0x4964 -#define PCI_CHIP_RV250_Ie 0x4965 -#define PCI_CHIP_RV250_If 0x4966 -#define PCI_CHIP_RV250_Ig 0x4967 -#define PCI_CHIP_R420_JH 0x4A48 -#define PCI_CHIP_R420_JI 0x4A49 -#define PCI_CHIP_R420_JJ 0x4A4A -#define PCI_CHIP_R420_JK 0x4A4B -#define PCI_CHIP_R420_JL 0x4A4C -#define PCI_CHIP_R420_JM 0x4A4D -#define PCI_CHIP_R420_JN 0x4A4E -#define PCI_CHIP_R420_JP 0x4A50 -#define PCI_CHIP_MACH64LB 0x4C42 -#define PCI_CHIP_MACH64LD 0x4C44 -#define PCI_CHIP_RAGE128LE 0x4C45 -#define PCI_CHIP_RAGE128LF 0x4C46 -#define PCI_CHIP_MACH64LG 0x4C47 -#define PCI_CHIP_MACH64LI 0x4C49 -#define PCI_CHIP_MACH64LM 0x4C4D -#define PCI_CHIP_MACH64LN 0x4C4E -#define PCI_CHIP_MACH64LP 0x4C50 -#define PCI_CHIP_MACH64LQ 0x4C51 -#define PCI_CHIP_MACH64LR 0x4C52 -#define PCI_CHIP_MACH64LS 0x4C53 -#define PCI_CHIP_MACH64LT 0x4C54 -#define PCI_CHIP_RADEON_LW 0x4C57 -#define PCI_CHIP_RADEON_LX 0x4C58 -#define PCI_CHIP_RADEON_LY 0x4C59 -#define PCI_CHIP_RADEON_LZ 0x4C5A -#define PCI_CHIP_RV250_Ld 0x4C64 -#define PCI_CHIP_RV250_Le 0x4C65 -#define PCI_CHIP_RV250_Lf 0x4C66 -#define PCI_CHIP_RV250_Lg 0x4C67 -#define PCI_CHIP_RV250_Ln 0x4C6E -#define PCI_CHIP_RAGE128MF 0x4D46 -#define PCI_CHIP_RAGE128ML 0x4D4C -#define PCI_CHIP_R300_ND 0x4E44 -#define PCI_CHIP_R300_NE 0x4E45 -#define PCI_CHIP_R300_NF 0x4E46 -#define PCI_CHIP_R300_NG 0x4E47 -#define PCI_CHIP_R350_NH 0x4E48 -#define PCI_CHIP_R350_NI 0x4E49 -#define PCI_CHIP_R360_NJ 0x4E4A -#define PCI_CHIP_R350_NK 0x4E4B -#define PCI_CHIP_RV350_NP 0x4E50 -#define PCI_CHIP_RV350_NQ 0x4E51 -#define PCI_CHIP_RV350_NR 0x4E52 -#define PCI_CHIP_RV350_NS 0x4E53 -#define PCI_CHIP_RV350_NT 0x4E54 -#define PCI_CHIP_RV350_NV 0x4E56 -#define PCI_CHIP_RAGE128PA 0x5041 -#define PCI_CHIP_RAGE128PB 0x5042 -#define PCI_CHIP_RAGE128PC 0x5043 -#define PCI_CHIP_RAGE128PD 0x5044 -#define PCI_CHIP_RAGE128PE 0x5045 -#define PCI_CHIP_RAGE128PF 0x5046 -#define PCI_CHIP_RAGE128PG 0x5047 -#define PCI_CHIP_RAGE128PH 0x5048 -#define PCI_CHIP_RAGE128PI 0x5049 -#define PCI_CHIP_RAGE128PJ 0x504A -#define PCI_CHIP_RAGE128PK 0x504B -#define PCI_CHIP_RAGE128PL 0x504C -#define PCI_CHIP_RAGE128PM 0x504D -#define PCI_CHIP_RAGE128PN 0x504E -#define PCI_CHIP_RAGE128PO 0x504F -#define PCI_CHIP_RAGE128PP 0x5050 -#define PCI_CHIP_RAGE128PQ 0x5051 -#define PCI_CHIP_RAGE128PR 0x5052 -#define PCI_CHIP_RAGE128PS 0x5053 -#define PCI_CHIP_RAGE128PT 0x5054 -#define PCI_CHIP_RAGE128PU 0x5055 -#define PCI_CHIP_RAGE128PV 0x5056 -#define PCI_CHIP_RAGE128PW 0x5057 -#define PCI_CHIP_RAGE128PX 0x5058 -#define PCI_CHIP_RADEON_QD 0x5144 -#define PCI_CHIP_RADEON_QE 0x5145 -#define PCI_CHIP_RADEON_QF 0x5146 -#define PCI_CHIP_RADEON_QG 0x5147 -#define PCI_CHIP_R200_QH 0x5148 -#define PCI_CHIP_R200_QI 0x5149 -#define PCI_CHIP_R200_QJ 0x514A -#define PCI_CHIP_R200_QK 0x514B -#define PCI_CHIP_R200_QL 0x514C -#define PCI_CHIP_R200_QM 0x514D -#define PCI_CHIP_R200_QN 0x514E -#define PCI_CHIP_R200_QO 0x514F -#define PCI_CHIP_RV200_QW 0x5157 -#define PCI_CHIP_RV200_QX 0x5158 -#define PCI_CHIP_RV100_QY 0x5159 -#define PCI_CHIP_RV100_QZ 0x515A -#define PCI_CHIP_RN50 0x515E -#define PCI_CHIP_RAGE128RE 0x5245 -#define PCI_CHIP_RAGE128RF 0x5246 -#define PCI_CHIP_RAGE128RG 0x5247 -#define PCI_CHIP_RAGE128RK 0x524B -#define PCI_CHIP_RAGE128RL 0x524C -#define PCI_CHIP_RAGE128SE 0x5345 -#define PCI_CHIP_RAGE128SF 0x5346 -#define PCI_CHIP_RAGE128SG 0x5347 -#define PCI_CHIP_RAGE128SH 0x5348 -#define PCI_CHIP_RAGE128SK 0x534B -#define PCI_CHIP_RAGE128SL 0x534C -#define PCI_CHIP_RAGE128SM 0x534D -#define PCI_CHIP_RAGE128SN 0x534E -#define PCI_CHIP_RAGE128TF 0x5446 -#define PCI_CHIP_RAGE128TL 0x544C -#define PCI_CHIP_RAGE128TR 0x5452 -#define PCI_CHIP_RAGE128TS 0x5453 -#define PCI_CHIP_RAGE128TT 0x5454 -#define PCI_CHIP_RAGE128TU 0x5455 -#define PCI_CHIP_RV370_5460 0x5460 -#define PCI_CHIP_RV370_5461 0x5461 -#define PCI_CHIP_RV370_5462 0x5462 -#define PCI_CHIP_RV370_5463 0x5463 -#define PCI_CHIP_RV370_5464 0x5464 -#define PCI_CHIP_RV370_5465 0x5465 -#define PCI_CHIP_RV370_5466 0x5466 -#define PCI_CHIP_RV370_5467 0x5467 -#define PCI_CHIP_R423_UH 0x5548 -#define PCI_CHIP_R423_UI 0x5549 -#define PCI_CHIP_R423_UJ 0x554A -#define PCI_CHIP_R423_UK 0x554B -#define PCI_CHIP_R423_UQ 0x5551 -#define PCI_CHIP_R423_UR 0x5552 -#define PCI_CHIP_R423_UT 0x5554 -#define PCI_CHIP_MACH64VT 0x5654 -#define PCI_CHIP_MACH64VU 0x5655 -#define PCI_CHIP_MACH64VV 0x5656 -#define PCI_CHIP_RS300_5834 0x5834 -#define PCI_CHIP_RS300_5835 0x5835 -#define PCI_CHIP_RS300_5836 0x5836 -#define PCI_CHIP_RS300_5837 0x5837 -#define PCI_CHIP_RV370_5B60 0x5B60 -#define PCI_CHIP_RV370_5B61 0x5B61 -#define PCI_CHIP_RV370_5B62 0x5B62 -#define PCI_CHIP_RV370_5B63 0x5B63 -#define PCI_CHIP_RV370_5B64 0x5B64 -#define PCI_CHIP_RV370_5B65 0x5B65 -#define PCI_CHIP_RV370_5B66 0x5B66 -#define PCI_CHIP_RV370_5B67 0x5B67 -#define PCI_CHIP_RV280_5960 0x5960 -#define PCI_CHIP_RV280_5961 0x5961 -#define PCI_CHIP_RV280_5962 0x5962 -#define PCI_CHIP_RV280_5964 0x5964 -#define PCI_CHIP_RV280_5C61 0x5C61 -#define PCI_CHIP_RV280_5C63 0x5C63 -#define PCI_CHIP_R423_5D57 0x5D57 -#define PCI_CHIP_RS350_7834 0x7834 -#define PCI_CHIP_RS350_7835 0x7835 diff --git a/drivers/video/ati_radeon_fb.c b/drivers/video/ati_radeon_fb.c deleted file mode 100644 index 383666781c..0000000000 --- a/drivers/video/ati_radeon_fb.c +++ /dev/null @@ -1,761 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ATI Radeon Video card Framebuffer driver. - * - * Copyright 2007 Freescale Semiconductor, Inc. - * Zhang Wei <wei.zhang@freescale.com> - * Jason Jin <jason.jin@freescale.com> - * - * Some codes of this file is partly ported from Linux kernel - * ATI video framebuffer driver. - * - * Now the driver is tested on below ATI chips: - * 9200 - * X300 - * X700 - */ - -#include <common.h> -#include <linux/delay.h> - -#include <command.h> -#include <bios_emul.h> -#include <env.h> -#include <pci.h> -#include <asm/processor.h> -#include <linux/errno.h> -#include <asm/io.h> -#include <malloc.h> -#include <video_fb.h> -#include "videomodes.h" - -#include <radeon.h> -#include "ati_ids.h" -#include "ati_radeon_fb.h" - -#undef DEBUG - -#ifdef DEBUG -#define DPRINT(x...) printf(x) -#else -#define DPRINT(x...) do{}while(0) -#endif - -#define MAX_MAPPED_VRAM (2048*2048*4) -#define MIN_MAPPED_VRAM (1024*768*1) - -#define RADEON_BUFFER_ALIGN 0x00000fff -#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ - & ~RADEON_BUFFER_ALIGN) - 1) -#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ - ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16)) - -#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \ - (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16)) -#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \ - (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16)) -#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \ - ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16)) -#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \ - ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16)) - -/*#define PCI_VENDOR_ID_ATI*/ -#define PCI_CHIP_RV280_5960 0x5960 -#define PCI_CHIP_RV280_5961 0x5961 -#define PCI_CHIP_RV280_5962 0x5962 -#define PCI_CHIP_RV280_5964 0x5964 -#define PCI_CHIP_RV280_5C63 0x5C63 -#define PCI_CHIP_RV370_5B60 0x5B60 -#define PCI_CHIP_RV380_5657 0x5657 -#define PCI_CHIP_R420_554d 0x554d - -static struct pci_device_id ati_radeon_pci_ids[] = { - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5C63}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, - {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, - {0, 0} -}; - -static u16 ati_radeon_id_family_table[][2] = { - {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV280_5C63, CHIP_FAMILY_RV280}, - {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, - {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, - {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, - {0, 0} -}; - -u16 get_radeon_id_family(u16 device) -{ - int i; - for (i=0; ati_radeon_id_family_table[0][i]; i+=2) - if (ati_radeon_id_family_table[0][i] == device) - return ati_radeon_id_family_table[0][i + 1]; - return 0; -} - -struct radeonfb_info *rinfo; - -static void radeon_identify_vram(struct radeonfb_info *rinfo) -{ - u32 tmp; - - /* framebuffer size */ - if ((rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200) || - (rinfo->family == CHIP_FAMILY_RS300)) { - u32 tom = INREG(NB_TOM); - tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); - - radeon_fifo_wait(6); - OUTREG(MC_FB_LOCATION, tom); - OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); - OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); - - /* This is supposed to fix the crtc2 noise problem. */ - OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); - - if ((rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200)) { - /* This is to workaround the asic bug for RMX, some versions - of BIOS dosen't have this register initialized correctly. - */ - OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, - ~CRTC_H_CUTOFF_ACTIVE_EN); - } - } else { - tmp = INREG(CONFIG_MEMSIZE); - } - - /* mem size is bits [28:0], mask off the rest */ - rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; - - /* - * Hack to get around some busted production M6's - * reporting no ram - */ - if (rinfo->video_ram == 0) { - switch (rinfo->pdev.device) { - case PCI_CHIP_RADEON_LY: - case PCI_CHIP_RADEON_LZ: - rinfo->video_ram = 8192 * 1024; - break; - default: - break; - } - } - - /* - * Now try to identify VRAM type - */ - if ((rinfo->family >= CHIP_FAMILY_R300) || - (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) - rinfo->vram_ddr = 1; - else - rinfo->vram_ddr = 0; - - tmp = INREG(MEM_CNTL); - if (IS_R300_VARIANT(rinfo)) { - tmp &= R300_MEM_NUM_CHANNELS_MASK; - switch (tmp) { - case 0: rinfo->vram_width = 64; break; - case 1: rinfo->vram_width = 128; break; - case 2: rinfo->vram_width = 256; break; - default: rinfo->vram_width = 128; break; - } - } else if ((rinfo->family == CHIP_FAMILY_RV100) || - (rinfo->family == CHIP_FAMILY_RS100) || - (rinfo->family == CHIP_FAMILY_RS200)){ - if (tmp & RV100_MEM_HALF_MODE) - rinfo->vram_width = 32; - else - rinfo->vram_width = 64; - } else { - if (tmp & MEM_NUM_CHANNELS_MASK) - rinfo->vram_width = 128; - else - rinfo->vram_width = 64; - } - - /* This may not be correct, as some cards can have half of channel disabled - * ToDo: identify these cases - */ - - DPRINT("radeonfb: Found %dk of %s %d bits wide videoram\n", - rinfo->video_ram / 1024, - rinfo->vram_ddr ? "DDR" : "SDRAM", - rinfo->vram_width); - -} - -static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) -{ - int i; - - radeon_fifo_wait(20); - -#if 0 - /* Workaround from XFree */ - if (rinfo->is_mobility) { - /* A temporal workaround for the occational blanking on certain laptop - * panels. This appears to related to the PLL divider registers - * (fail to lock?). It occurs even when all dividers are the same - * with their old settings. In this case we really don't need to - * fiddle with PLL registers. By doing this we can avoid the blanking - * problem with some panels. - */ - if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && - (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & - (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { - /* We still have to force a switch to selected PPLL div thanks to - * an XFree86 driver bug which will switch it away in some cases - * even when using UseFDev */ - OUTREGP(CLOCK_CNTL_INDEX, - mode->clk_cntl_index & PPLL_DIV_SEL_MASK, - ~PPLL_DIV_SEL_MASK); - radeon_pll_errata_after_index(rinfo); - radeon_pll_errata_after_data(rinfo); - return; - } - } -#endif - if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; - - /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ - OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); - - /* Reset PPLL & enable atomic update */ - OUTPLLP(PPLL_CNTL, - PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, - ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); - - /* Switch to selected PPLL divider */ - OUTREGP(CLOCK_CNTL_INDEX, - mode->clk_cntl_index & PPLL_DIV_SEL_MASK, - ~PPLL_DIV_SEL_MASK); - - /* Set PPLL ref. div */ - if (rinfo->family == CHIP_FAMILY_R300 || - rinfo->family == CHIP_FAMILY_RS300 || - rinfo->family == CHIP_FAMILY_R350 || - rinfo->family == CHIP_FAMILY_RV350) { - if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { - /* When restoring console mode, use saved PPLL_REF_DIV - * setting. - */ - OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); - } else { - /* R300 uses ref_div_acc field as real ref divider */ - OUTPLLP(PPLL_REF_DIV, - (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), - ~R300_PPLL_REF_DIV_ACC_MASK); - } - } else - OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); - - /* Set PPLL divider 3 & post divider*/ - OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); - OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); - - /* Write update */ - while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) - ; - OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); - - /* Wait read update complete */ - /* FIXME: Certain revisions of R300 can't recover here. Not sure of - the cause yet, but this workaround will mask the problem for now. - Other chips usually will pass at the very first test, so the - workaround shouldn't have any effect on them. */ - for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) - ; - - OUTPLL(HTOTAL_CNTL, 0); - - /* Clear reset & atomic update */ - OUTPLLP(PPLL_CNTL, 0, - ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); - - /* We may want some locking ... oh well */ - udelay(5000); - - /* Switch back VCLK source to PPLL */ - OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); -} - -typedef struct { - u16 reg; - u32 val; -} reg_val; - -#if 0 /* unused ? -> scheduled for removal */ -/* these common regs are cleared before mode setting so they do not - * interfere with anything - */ -static reg_val common_regs[] = { - { OVR_CLR, 0 }, - { OVR_WID_LEFT_RIGHT, 0 }, - { OVR_WID_TOP_BOTTOM, 0 }, - { OV0_SCALE_CNTL, 0 }, - { SUBPIC_CNTL, 0 }, - { VIPH_CONTROL, 0 }, - { I2C_CNTL_1, 0 }, - { GEN_INT_CNTL, 0 }, - { CAP0_TRIG_CNTL, 0 }, - { CAP1_TRIG_CNTL, 0 }, -}; -#endif /* 0 */ - -void radeon_setmode(void) -{ - struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); - - mode->crtc_gen_cntl = 0x03000200; - mode->crtc_ext_cntl = 0x00008048; - mode->dac_cntl = 0xff002100; - mode->crtc_h_total_disp = 0x4f0063; - mode->crtc_h_sync_strt_wid = 0x8c02a2; - mode->crtc_v_total_disp = 0x01df020c; - mode->crtc_v_sync_strt_wid = 0x8201ea; - mode->crtc_pitch = 0x00500050; - - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); - OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); - OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); - OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); - OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); - OUTREG(CRTC_OFFSET, 0); - OUTREG(CRTC_OFFSET_CNTL, 0); - OUTREG(CRTC_PITCH, mode->crtc_pitch); - - mode->clk_cntl_index = 0x300; - mode->ppll_ref_div = 0xc; - mode->ppll_div_3 = 0x00030059; - - radeon_write_pll_regs(rinfo, mode); -} - -static void set_pal(void) -{ - int idx, val = 0; - - for (idx = 0; idx < 256; idx++) { - OUTREG8(PALETTE_INDEX, idx); - OUTREG(PALETTE_DATA, val); - val += 0x00010101; - } -} - -void radeon_setmode_9200(int vesa_idx, int bpp) -{ - struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); - - mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; - mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; - mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; - mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; - - switch (bpp) { - case 24: - mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ -#if defined(__BIG_ENDIAN) - mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; - mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; -#endif - break; - case 16: - mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ -#if defined(__BIG_ENDIAN) - mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; - mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; -#endif - break; - default: - mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ - mode->surface_cntl = 0x00000000; - break; - } - - switch (vesa_idx) { - case RES_MODE_1280x1024: - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); - mode->ppll_div_3 = 0x00010078; -#else /* default @ 60 Hz */ - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); - mode->ppll_div_3 = 0x00010060; -#endif - /* - * for this mode pitch expands to the same value for 32, 16 and 8 bpp, - * so we set it here once only. - */ - mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); - break; - default: /* 8 bpp */ - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); - break; - } - break; - case RES_MODE_1024x768: -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); - mode->ppll_div_3 = 0x0002008c; -#else /* @ 60 Hz */ - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00020074; -#endif - /* also same pitch value for 32, 16 and 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); - break; - default: /* 8 bpp */ - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); - break; - } - break; - case RES_MODE_800x600: - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); - mode->ppll_div_3 = 0x000300b0; -#else /* @ 60 Hz */ - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); - mode->ppll_div_3 = 0x0003008e; -#endif - switch (bpp) { - case 24: - mode->crtc_pitch = RADEON_CRT_PITCH(832,32); - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); - break; - case 16: - mode->crtc_pitch = RADEON_CRT_PITCH(896,16); - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); - break; - default: /* 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); - mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); - break; - } - break; - default: /* RES_MODE_640x480 */ -#if defined(CONFIG_RADEON_VREFRESH_75HZ) - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00030070; -#else /* @ 60 Hz */ - mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); - mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; - mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); - mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; - mode->ppll_div_3 = 0x00030059; -#endif - /* also same pitch value for 32, 16 and 8 bpp */ - mode->crtc_pitch = RADEON_CRT_PITCH(640,32); - switch (bpp) { - case 24: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); - break; - case 16: - mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); - mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); - break; - default: /* 8 bpp */ - mode->crtc_offset_cntl = 0x00000000; - break; - } - break; - } - - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); - OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); - OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); - OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); - OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); - OUTREG(CRTC_OFFSET, 0); - OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); - OUTREG(CRTC_PITCH, mode->crtc_pitch); - OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); - - mode->clk_cntl_index = 0x300; - mode->ppll_ref_div = 0xc; - - radeon_write_pll_regs(rinfo, mode); - - OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, - ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); - OUTREG(SURFACE0_INFO, mode->surf_info[0]); - OUTREG(SURFACE0_LOWER_BOUND, 0); - OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); - OUTREG(SURFACE_CNTL, mode->surface_cntl); - - if (bpp > 8) - set_pal(); - - free(mode); -} - -#include "../bios_emulator/include/biosemu.h" - -int radeon_probe(struct radeonfb_info *rinfo) -{ - pci_dev_t pdev; - u16 did; - - pdev = pci_find_devices(ati_radeon_pci_ids, 0); - - if (pdev != -1) { - pci_read_config_word(pdev, PCI_DEVICE_ID, &did); - printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", - PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, - (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); - - strcpy(rinfo->name, "ATI Radeon"); - rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; - rinfo->pdev.device = did; - rinfo->family = get_radeon_id_family(rinfo->pdev.device); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, - &rinfo->fb_base_bus); - pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, - &rinfo->mmio_base_bus); - rinfo->fb_base_bus &= 0xfffff000; - rinfo->mmio_base_bus &= ~0x04; - - rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, - PCI_REGION_MEM, 0, MAP_NOCACHE); - DPRINT("rinfo->mmio_base = 0x%p bus=0x%x\n", - rinfo->mmio_base, rinfo->mmio_base_bus); - rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; - DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); - /* PostBIOS with x86 emulater */ - if (!BootVideoCardBIOS(pdev, NULL, 0)) - return -1; - - /* - * Check for errata - * (These will be added in the future for the chipfamily - * R300, RV200, RS200, RV100, RS100.) - */ - - /* Get VRAM size and type */ - radeon_identify_vram(rinfo); - - rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, - rinfo->video_ram); - rinfo->fb_base = pci_bus_to_virt(pdev, rinfo->fb_base_bus, - PCI_REGION_MEM, 0, MAP_NOCACHE); - DPRINT("Radeon: framebuffer base address 0x%08x, " - "bus address 0x%08x\n" - "MMIO base address 0x%08x, bus address 0x%08x, " - "framebuffer local base 0x%08x.\n ", - (u32)rinfo->fb_base, rinfo->fb_base_bus, - (u32)rinfo->mmio_base, rinfo->mmio_base_bus, - rinfo->fb_local_base); - return 0; - } - return -1; -} - -/* - * The Graphic Device - */ -GraphicDevice ctfb; - -#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ -#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ -#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ -#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ - -void *video_hw_init(void) -{ - GraphicDevice *pGD = (GraphicDevice *) & ctfb; - u32 *vm; - char *penv; - unsigned long t1, hsynch, vsynch; - int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; - struct ctfb_res_modes *res_mode; - struct ctfb_res_modes var_mode; - - rinfo = malloc(sizeof(struct radeonfb_info)); - - printf("Video: "); - if(radeon_probe(rinfo)) { - printf("No radeon video card found!\n"); - return NULL; - } - - tmp = 0; - - videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; - /* get video mode via environment */ - penv = env_get("videomode"); - if (penv) { - /* deceide if it is a string */ - if (penv[0] <= '9') { - videomode = (int)hextoul(penv, NULL); - tmp = 1; - } - } else { - tmp = 1; - } - if (tmp) { - /* parameter are vesa modes */ - /* search params */ - for (i = 0; i < VESA_MODES_COUNT; i++) { - if (vesa_modes[i].vesanr == videomode) - break; - } - if (i == VESA_MODES_COUNT) { - printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); - i = 0; - } - res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; - bits_per_pixel = vesa_modes[i].bits_per_pixel; - vesa_idx = vesa_modes[i].resindex; - } else { - res_mode = (struct ctfb_res_modes *) &var_mode; - bits_per_pixel = video_get_params (res_mode, penv); - } - - /* calculate hsynch and vsynch freq (info only) */ - t1 = (res_mode->left_margin + res_mode->xres + - res_mode->right_margin + res_mode->hsync_len) / 8; - t1 *= 8; - t1 *= res_mode->pixclock; - t1 /= 1000; - hsynch = 1000000000L / t1; - t1 *= (res_mode->upper_margin + res_mode->yres + - res_mode->lower_margin + res_mode->vsync_len); - t1 /= 1000; - vsynch = 1000000000L / t1; - - /* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, - res_mode->yres, bits_per_pixel, (hsynch / 1000), - (vsynch / 1000)); - printf ("%s\n", pGD->modeIdent); - pGD->winSizeX = res_mode->xres; - pGD->winSizeY = res_mode->yres; - pGD->plnSizeX = res_mode->xres; - pGD->plnSizeY = res_mode->yres; - - switch (bits_per_pixel) { - case 24: - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; - if (res_mode->xres == 800) { - pGD->winSizeX = 832; - pGD->plnSizeX = 832; - } - break; - case 16: - pGD->gdfBytesPP = 2; - pGD->gdfIndex = GDF_16BIT_565RGB; - if (res_mode->xres == 800) { - pGD->winSizeX = 896; - pGD->plnSizeX = 896; - } - break; - default: - if (res_mode->xres == 800) { - pGD->winSizeX = 1024; - pGD->plnSizeX = 1024; - } - pGD->gdfBytesPP = 1; - pGD->gdfIndex = GDF__8BIT_INDEX; - break; - } - - pGD->isaBase = CONFIG_SYS_ISA_IO_BASE_ADDRESS; - pGD->pciBase = (unsigned int)rinfo->fb_base; - pGD->frameAdrs = (unsigned int)rinfo->fb_base; - pGD->memSize = 64 * 1024 * 1024; - - /* Cursor Start Address */ - pGD->dprBase = (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + - (unsigned int)rinfo->fb_base; - if ((pGD->dprBase & 0x0fff) != 0) { - /* allign it */ - pGD->dprBase &= 0xfffff000; - pGD->dprBase += 0x00001000; - } - DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, - PATTERN_ADR); - pGD->vprBase = (unsigned int)rinfo->fb_base; /* Dummy */ - pGD->cprBase = (unsigned int)rinfo->fb_base; /* Dummy */ - /* set up Hardware */ - - /* Clear video memory (only visible screen area) */ - i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; - vm = (unsigned int *) pGD->pciBase; - while (i--) - *vm++ = 0; - /*SetDrawingEngine (bits_per_pixel);*/ - - if (rinfo->family == CHIP_FAMILY_RV280) - radeon_setmode_9200(vesa_idx, bits_per_pixel); - else - radeon_setmode(); - - return ((void *) pGD); -} - -void video_set_lut (unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ) -{ - OUTREG(PALETTE_INDEX, index); - OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); -} diff --git a/drivers/video/ati_radeon_fb.h b/drivers/video/ati_radeon_fb.h deleted file mode 100644 index 9dd638bb9e..0000000000 --- a/drivers/video/ati_radeon_fb.h +++ /dev/null @@ -1,282 +0,0 @@ -#ifndef __ATI_RADEON_FB_H -#define __ATI_RADEON_FB_H - -/*************************************************************** - * Most of the definitions here are adapted right from XFree86 * - ***************************************************************/ - -/* - * Chip families. Must fit in the low 16 bits of a long word - */ -enum radeon_family { - CHIP_FAMILY_UNKNOW, - CHIP_FAMILY_LEGACY, - CHIP_FAMILY_RADEON, - CHIP_FAMILY_RV100, - CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ - CHIP_FAMILY_RV200, - CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), - RS250 (IGP 7000) */ - CHIP_FAMILY_R200, - CHIP_FAMILY_RV250, - CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ - CHIP_FAMILY_RV280, - CHIP_FAMILY_R300, - CHIP_FAMILY_R350, - CHIP_FAMILY_RV350, - CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ - CHIP_FAMILY_R420, /* R420/R423/M18 */ - CHIP_FAMILY_LAST, -}; - -#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ - ((rinfo)->family == CHIP_FAMILY_RV200) || \ - ((rinfo)->family == CHIP_FAMILY_RS100) || \ - ((rinfo)->family == CHIP_FAMILY_RS200) || \ - ((rinfo)->family == CHIP_FAMILY_RV250) || \ - ((rinfo)->family == CHIP_FAMILY_RV280) || \ - ((rinfo)->family == CHIP_FAMILY_RS300)) - -#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ - ((rinfo)->family == CHIP_FAMILY_RV350) || \ - ((rinfo)->family == CHIP_FAMILY_R350) || \ - ((rinfo)->family == CHIP_FAMILY_RV380) || \ - ((rinfo)->family == CHIP_FAMILY_R420)) - -struct radeonfb_info { - char name[20]; - - struct pci_device_id pdev; - u16 family; - - u32 fb_base_bus; - u32 mmio_base_bus; - - void *mmio_base; - void *fb_base; - - u32 video_ram; - u32 mapped_vram; - int vram_width; - int vram_ddr; - - u32 fb_local_base; -}; - -#define INREG8(addr) readb((rinfo->mmio_base)+addr) -#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) -#define INREG16(addr) readw((rinfo->mmio_base)+addr) -#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) -#define INREG(addr) readl((rinfo->mmio_base)+addr) -#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) - -static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, - u32 val, u32 mask) -{ - unsigned int tmp; - - tmp = INREG(addr); - tmp &= (mask); - tmp |= (val); - OUTREG(addr, tmp); -} - -#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) - -/* - * 2D Engine helper routines - */ -static inline void radeon_engine_flush (struct radeonfb_info *rinfo) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - return; - udelay(1); - } - printf("radeonfb: Flush Timeout !\n"); -} - -static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) -{ - int i; - - for (i=0; i<2000000; i++) { - if ((INREG(RBBM_STATUS) & 0x7f) >= entries) - return; - udelay(1); - } - printf("radeonfb: FIFO Timeout !\n"); -} - -static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - _radeon_fifo_wait (rinfo, 64); - - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { - radeon_engine_flush (rinfo); - return; - } - udelay(1); - } - printf("radeonfb: Idle Timeout !\n"); -} - -#define radeon_engine_idle() _radeon_engine_idle(rinfo) -#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) -#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) - -/* - * This structure contains the various registers manipulated by this - * driver for setting or restoring a mode. It's mostly copied from - * XFree's RADEONSaveRec structure. A few chip settings might still be - * tweaked without beeing reflected or saved in these registers though - */ -struct radeon_regs { - /* Common registers */ - u32 ovr_clr; - u32 ovr_wid_left_right; - u32 ovr_wid_top_bottom; - u32 ov0_scale_cntl; - u32 mpp_tb_config; - u32 mpp_gp_config; - u32 subpic_cntl; - u32 viph_control; - u32 i2c_cntl_1; - u32 gen_int_cntl; - u32 cap0_trig_cntl; - u32 cap1_trig_cntl; - u32 bus_cntl; - u32 surface_cntl; - u32 bios_5_scratch; - - /* Other registers to save for VT switches or driver load/unload */ - u32 dp_datatype; - u32 rbbm_soft_reset; - u32 clock_cntl_index; - u32 amcgpio_en_reg; - u32 amcgpio_mask; - - /* Surface/tiling registers */ - u32 surf_lower_bound[8]; - u32 surf_upper_bound[8]; - u32 surf_info[8]; - - /* CRTC registers */ - u32 crtc_gen_cntl; - u32 crtc_ext_cntl; - u32 dac_cntl; - u32 crtc_h_total_disp; - u32 crtc_h_sync_strt_wid; - u32 crtc_v_total_disp; - u32 crtc_v_sync_strt_wid; - u32 crtc_offset; - u32 crtc_offset_cntl; - u32 crtc_pitch; - u32 disp_merge_cntl; - u32 grph_buffer_cntl; - u32 crtc_more_cntl; - - /* CRTC2 registers */ - u32 crtc2_gen_cntl; - u32 dac2_cntl; - u32 disp_output_cntl; - u32 disp_hw_debug; - u32 disp2_merge_cntl; - u32 grph2_buffer_cntl; - u32 crtc2_h_total_disp; - u32 crtc2_h_sync_strt_wid; - u32 crtc2_v_total_disp; - u32 crtc2_v_sync_strt_wid; - u32 crtc2_offset; - u32 crtc2_offset_cntl; - u32 crtc2_pitch; - - /* Flat panel regs */ - u32 fp_crtc_h_total_disp; - u32 fp_crtc_v_total_disp; - u32 fp_gen_cntl; - u32 fp2_gen_cntl; - u32 fp_h_sync_strt_wid; - u32 fp2_h_sync_strt_wid; - u32 fp_horz_stretch; - u32 fp_panel_cntl; - u32 fp_v_sync_strt_wid; - u32 fp2_v_sync_strt_wid; - u32 fp_vert_stretch; - u32 lvds_gen_cntl; - u32 lvds_pll_cntl; - u32 tmds_crc; - u32 tmds_transmitter_cntl; - - /* Computed values for PLL */ - u32 dot_clock_freq; - int feedback_div; - int post_div; - - /* PLL registers */ - u32 ppll_div_3; - u32 ppll_ref_div; - u32 vclk_ecp_cntl; - u32 clk_cntl_index; - - /* Computed values for PLL2 */ - u32 dot_clock_freq_2; - int feedback_div_2; - int post_div_2; - - /* PLL2 registers */ - u32 p2pll_ref_div; - u32 p2pll_div_0; - u32 htotal_cntl2; - - /* Palette */ - int palette_valid; -}; - -static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) -{ - u32 data; - - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); - /* radeon_pll_errata_after_index(rinfo); */ - data = INREG(CLOCK_CNTL_DATA); - /* radeon_pll_errata_after_data(rinfo); */ - return data; -} - -static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, - u32 val) -{ - - OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); - /* radeon_pll_errata_after_index(rinfo); */ - OUTREG(CLOCK_CNTL_DATA, val); - /* radeon_pll_errata_after_data(rinfo); */ -} - -static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, - u32 val, u32 mask) -{ - unsigned int tmp; - - tmp = __INPLL(rinfo, index); - tmp &= (mask); - tmp |= (val); - __OUTPLL(rinfo, index, tmp); -} - -#define INPLL(addr) __INPLL(rinfo, addr) -#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) -#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) - -#endif diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 5e1ee061e8..566fc1e01a 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -71,10 +71,11 @@ #include <fdtdec.h> #include <gzip.h> #include <log.h> -#include <version.h> +#include <version_string.h> #include <malloc.h> #include <video.h> #include <asm/global_data.h> +#include <dm/ofnode.h> #include <linux/compiler.h> #if defined(CONFIG_VIDEO_MXS) @@ -108,7 +109,6 @@ * Console device */ -#include <version.h> #include <linux/types.h> #include <stdio_dev.h> #include <video_font.h> @@ -2138,8 +2138,7 @@ int drv_video_init(void) #if defined(CONFIG_VGA_AS_SINGLE_DEVICE) have_keyboard = false; #elif defined(CONFIG_OF_CONTROL) - have_keyboard = !fdtdec_get_config_bool(gd->fdt_blob, - "u-boot,no-keyboard"); + have_keyboard = !ofnode_conf_read_bool("u-boot,no-keyboard"); #else have_keyboard = true; #endif diff --git a/drivers/video/exynos/exynos_mipi_dsi.c b/drivers/video/exynos/exynos_mipi_dsi.c index c56eadc823..804fcd0b24 100644 --- a/drivers/video/exynos/exynos_mipi_dsi.c +++ b/drivers/video/exynos/exynos_mipi_dsi.c @@ -288,8 +288,8 @@ int exynos_dsim_config_parse_dt(const void *blob, struct mipi_dsim_config *dt, dt->rx_timeout = fdtdec_get_int(blob, node, "samsung,dsim-config-rx-timeout", 0); - lcd_dt->name = fdtdec_get_config_string(blob, - "samsung,dsim-device-name"); + lcd_dt->name = fdt_getprop(blob, node, "samsung,dsim-device-name", + NULL); lcd_dt->id = fdtdec_get_int(blob, node, "samsung,dsim-device-id", 0); diff --git a/drivers/video/pxa_lcd.c b/drivers/video/pxa_lcd.c index 67f5266164..21ade8d93c 100644 --- a/drivers/video/pxa_lcd.c +++ b/drivers/video/pxa_lcd.c @@ -199,72 +199,6 @@ vidinfo_t panel_info = { /*----------------------------------------------------------------------*/ -#ifdef CONFIG_ACX517AKN - -# define LCD_BPP LCD_COLOR8 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x03700006 - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 320, - .vl_width = 320, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_HIGH, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_HIGH, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 1, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x04, - .vl_blw = 0x1c, - .vl_elw = 0x08, - .vl_vpw = 0x01, - .vl_bfw = 0x07, - .vl_efw = 0x08, -}; -#endif /* CONFIG_ACX517AKN */ - -#ifdef CONFIG_ACX544AKN - -# define LCD_BPP LCD_COLOR16 - -/* you have to set lccr0 and lccr3 (including pcd) */ -# define REG_LCCR0 0x003008f9 -# define REG_LCCR3 0x04700007 /* 16bpp */ - -vidinfo_t panel_info = { - .vl_col = 320, - .vl_row = 320, - .vl_width = 320, - .vl_height = 320, - .vl_clkp = CONFIG_SYS_LOW, - .vl_oep = CONFIG_SYS_LOW, - .vl_hsp = CONFIG_SYS_LOW, - .vl_vsp = CONFIG_SYS_LOW, - .vl_dp = CONFIG_SYS_LOW, - .vl_bpix = LCD_BPP, - .vl_lbw = 0, - .vl_splt = 0, - .vl_clor = 1, - .vl_tft = 1, - .vl_hpw = 0x05, - .vl_blw = 0x13, - .vl_elw = 0x08, - .vl_vpw = 0x02, - .vl_bfw = 0x07, - .vl_efw = 0x05, -}; -#endif /* CONFIG_ACX544AKN */ - -/*----------------------------------------------------------------------*/ - #ifdef CONFIG_LQ038J7DH53 # define LCD_BPP LCD_COLOR8 @@ -295,7 +229,7 @@ vidinfo_t panel_info = { .vl_bfw = 0x04, .vl_efw = 0x01, }; -#endif /* CONFIG_ACX517AKN */ +#endif /* CONFIG_LQ038J7DH53 */ /*----------------------------------------------------------------------*/ diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig index 031bab25ae..a2c51083b1 100644 --- a/drivers/w1/Kconfig +++ b/drivers/w1/Kconfig @@ -6,7 +6,6 @@ menu "1-Wire support" config W1 bool "Enable 1-wire controllers support" - default no depends on DM help Support for the Dallas 1-Wire bus. @@ -15,14 +14,12 @@ if W1 config W1_GPIO bool "Enable 1-wire GPIO bitbanging" - default no depends on DM_GPIO help Emulate a 1-wire bus using a GPIO. config W1_MXC bool "Enable 1-wire controller on i.MX processors" - default no depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 help Support the one wire controller found in some members of the NXP diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f0ff2612a6..6fbb5c1b6d 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -147,6 +147,15 @@ config WDT_CORTINA This driver support all CPU ISAs supported by Cortina Access CAxxxx SoCs. +config WDT_GPIO + bool "External gpio watchdog support" + depends on WDT + depends on DM_GPIO + help + Support for external watchdog fed by toggling a gpio. See + doc/device-tree-bindings/watchdog/gpio-wdt.txt for + information on how to describe the watchdog in device tree. + config WDT_MPC8xx bool "MPC8xx watchdog timer support" depends on WDT && MPC8xx diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5c7ef593fe..f14415bb8e 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o obj-$(CONFIG_WDT_ORION) += orion_wdt.o obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o +obj-$(CONFIG_WDT_GPIO) += gpio_wdt.o obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o diff --git a/drivers/watchdog/gpio_wdt.c b/drivers/watchdog/gpio_wdt.c new file mode 100644 index 0000000000..982a66b3f9 --- /dev/null +++ b/drivers/watchdog/gpio_wdt.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <dm.h> +#include <dm/device_compat.h> +#include <wdt.h> +#include <asm/gpio.h> + +struct gpio_wdt_priv { + struct gpio_desc gpio; + bool always_running; + int state; +}; + +static int gpio_wdt_reset(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + priv->state = !priv->state; + + return dm_gpio_set_value(&priv->gpio, priv->state); +} + +static int gpio_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + + if (priv->always_running) + return 0; + + return -ENOSYS; +} + +static int dm_probe(struct udevice *dev) +{ + struct gpio_wdt_priv *priv = dev_get_priv(dev); + int ret; + + priv->always_running = dev_read_bool(dev, "always-running"); + ret = gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT); + if (ret < 0) { + dev_err(dev, "Request for wdt gpio failed: %d\n", ret); + return ret; + } + + if (priv->always_running) + ret = gpio_wdt_reset(dev); + + return ret; +} + +static const struct wdt_ops gpio_wdt_ops = { + .start = gpio_wdt_start, + .reset = gpio_wdt_reset, +}; + +static const struct udevice_id gpio_wdt_ids[] = { + { .compatible = "linux,wdt-gpio" }, + {} +}; + +U_BOOT_DRIVER(wdt_gpio) = { + .name = "wdt_gpio", + .id = UCLASS_WDT, + .of_match = gpio_wdt_ids, + .ops = &gpio_wdt_ops, + .probe = dm_probe, + .priv_auto = sizeof(struct gpio_wdt_priv), +}; diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 17334dbda6..7570710c4d 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -20,53 +20,67 @@ DECLARE_GLOBAL_DATA_PTR; #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) -/* - * Reset every 1000ms, or however often is required as indicated by a - * hw_margin_ms property. - */ -static ulong reset_period = 1000; +struct wdt_priv { + /* Timeout, in seconds, to configure this device to. */ + u32 timeout; + /* + * Time, in milliseconds, between calling the device's ->reset() + * method from watchdog_reset(). + */ + ulong reset_period; + /* + * Next time (as returned by get_timer(0)) to call + * ->reset(). + */ + ulong next_reset; + /* Whether watchdog_start() has been called on the device. */ + bool running; +}; -int initr_watchdog(void) +static void init_watchdog_dev(struct udevice *dev) { - u32 timeout = WATCHDOG_TIMEOUT_SECS; + struct wdt_priv *priv; int ret; - /* - * Init watchdog: This will call the probe function of the - * watchdog driver, enabling the use of the device - */ - if (uclass_get_device_by_seq(UCLASS_WDT, 0, - (struct udevice **)&gd->watchdog_dev)) { - debug("WDT: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, - (struct udevice **)&gd->watchdog_dev)) { - printf("WDT: Not found!\n"); - return 0; - } - } - - if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { - timeout = dev_read_u32_default(gd->watchdog_dev, "timeout-sec", - WATCHDOG_TIMEOUT_SECS); - reset_period = dev_read_u32_default(gd->watchdog_dev, - "hw_margin_ms", - 4 * reset_period) / 4; - } + priv = dev_get_uclass_priv(dev); if (!IS_ENABLED(CONFIG_WATCHDOG_AUTOSTART)) { - printf("WDT: Not starting\n"); - return 0; + printf("WDT: Not starting %s\n", dev->name); + return; } - ret = wdt_start(gd->watchdog_dev, timeout * 1000, 0); + ret = wdt_start(dev, priv->timeout * 1000, 0); if (ret != 0) { - printf("WDT: Failed to start\n"); + printf("WDT: Failed to start %s\n", dev->name); + return; + } + + printf("WDT: Started %s with%s servicing (%ds timeout)\n", dev->name, + IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", priv->timeout); +} + +int initr_watchdog(void) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_WDT, &uc); + if (ret) { + log_debug("Error getting UCLASS_WDT: %d\n", ret); return 0; } - printf("WDT: Started with%s servicing (%ds timeout)\n", - IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out", timeout); + uclass_foreach_dev(dev, uc) { + ret = device_probe(dev); + if (ret) { + log_debug("Error probing %s: %d\n", dev->name, ret); + continue; + } + init_watchdog_dev(dev); + } + gd->flags |= GD_FLG_WDT_READY; return 0; } @@ -79,8 +93,11 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) return -ENOSYS; ret = ops->start(dev, timeout_ms, flags); - if (ret == 0) - gd->flags |= GD_FLG_WDT_READY; + if (ret == 0) { + struct wdt_priv *priv = dev_get_uclass_priv(dev); + + priv->running = true; + } return ret; } @@ -94,8 +111,36 @@ int wdt_stop(struct udevice *dev) return -ENOSYS; ret = ops->stop(dev); - if (ret == 0) - gd->flags &= ~GD_FLG_WDT_READY; + if (ret == 0) { + struct wdt_priv *priv = dev_get_uclass_priv(dev); + + priv->running = false; + } + + return ret; +} + +int wdt_stop_all(void) +{ + struct wdt_priv *priv; + struct udevice *dev; + struct uclass *uc; + int ret, err; + + ret = uclass_get(UCLASS_WDT, &uc); + if (ret) + return ret; + + uclass_foreach_dev(dev, uc) { + if (!device_active(dev)) + continue; + priv = dev_get_uclass_priv(dev); + if (!priv->running) + continue; + err = wdt_stop(dev); + if (!ret) + ret = err; + } return ret; } @@ -120,10 +165,8 @@ int wdt_expire_now(struct udevice *dev, ulong flags) if (ops->expire_now) { return ops->expire_now(dev, flags); } else { - if (!ops->start) - return -ENOSYS; + ret = wdt_start(dev, 1, flags); - ret = ops->start(dev, 1, flags); if (ret < 0) return ret; @@ -141,18 +184,36 @@ int wdt_expire_now(struct udevice *dev, ulong flags) */ void watchdog_reset(void) { - static ulong next_reset; + struct wdt_priv *priv; + struct udevice *dev; + struct uclass *uc; ulong now; /* Exit if GD is not ready or watchdog is not initialized yet */ if (!gd || !(gd->flags & GD_FLG_WDT_READY)) return; - /* Do not reset the watchdog too often */ - now = get_timer(0); - if (time_after_eq(now, next_reset)) { - next_reset = now + reset_period; - wdt_reset(gd->watchdog_dev); + if (uclass_get(UCLASS_WDT, &uc)) + return; + + /* + * All devices bound to the wdt uclass should have been probed + * in initr_watchdog(). But just in case something went wrong, + * check device_active() before accessing the uclass private + * data. + */ + uclass_foreach_dev(dev, uc) { + if (!device_active(dev)) + continue; + priv = dev_get_uclass_priv(dev); + if (!priv->running) + continue; + /* Do not reset the watchdog too often */ + now = get_timer(0); + if (time_after_eq(now, priv->next_reset)) { + priv->next_reset = now + priv->reset_period; + wdt_reset(dev); + } } } #endif @@ -179,9 +240,38 @@ static int wdt_post_bind(struct udevice *dev) return 0; } +static int wdt_pre_probe(struct udevice *dev) +{ + u32 timeout = WATCHDOG_TIMEOUT_SECS; + /* + * Reset every 1000ms, or however often is required as + * indicated by a hw_margin_ms property. + */ + ulong reset_period = 1000; + struct wdt_priv *priv; + + if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { + timeout = dev_read_u32_default(dev, "timeout-sec", timeout); + reset_period = dev_read_u32_default(dev, "hw_margin_ms", + 4 * reset_period) / 4; + } + priv = dev_get_uclass_priv(dev); + priv->timeout = timeout; + priv->reset_period = reset_period; + /* + * Pretend this device was last reset "long" ago so the first + * watchdog_reset will actually call its ->reset method. + */ + priv->next_reset = get_timer(0); + + return 0; +} + UCLASS_DRIVER(wdt) = { - .id = UCLASS_WDT, - .name = "watchdog", - .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = wdt_post_bind, + .id = UCLASS_WDT, + .name = "watchdog", + .flags = DM_UC_FLAG_SEQ_ALIAS, + .post_bind = wdt_post_bind, + .pre_probe = wdt_pre_probe, + .per_device_auto = sizeof(struct wdt_priv), }; |