diff options
Diffstat (limited to 'drivers')
189 files changed, 10805 insertions, 13331 deletions
diff --git a/drivers/Makefile b/drivers/Makefile index 83b14ef1fd..15d19d0c8a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -59,7 +59,6 @@ obj-$(CONFIG_SPL_USB_GADGET) += usb/common/ obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/udc/ obj-$(CONFIG_SPL_WATCHDOG) += watchdog/ obj-$(CONFIG_SPL_USB_HOST) += usb/host/ -obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA) += ata/ scsi/ obj-$(CONFIG_SPL_LEGACY_BLOCK) += block/ obj-$(CONFIG_SPL_THERMAL) += thermal/ diff --git a/drivers/button/button-gpio.c b/drivers/button/button-gpio.c index dbb000622c..7b5b3affe2 100644 --- a/drivers/button/button-gpio.c +++ b/drivers/button/button-gpio.c @@ -13,6 +13,7 @@ struct button_gpio_priv { struct gpio_desc gpio; + int linux_code; }; static enum button_state_t button_gpio_get_state(struct udevice *dev) @@ -29,6 +30,17 @@ static enum button_state_t button_gpio_get_state(struct udevice *dev) return ret ? BUTTON_ON : BUTTON_OFF; } +static int button_gpio_get_code(struct udevice *dev) +{ + struct button_gpio_priv *priv = dev_get_priv(dev); + int code = priv->linux_code; + + if (!code) + return -ENODATA; + + return code; +} + static int button_gpio_probe(struct udevice *dev) { struct button_uc_plat *uc_plat = dev_get_uclass_plat(dev); @@ -43,7 +55,9 @@ static int button_gpio_probe(struct udevice *dev) if (ret) return ret; - return 0; + ret = dev_read_u32(dev, "linux,code", &priv->linux_code); + + return ret; } static int button_gpio_remove(struct udevice *dev) @@ -92,6 +106,7 @@ static int button_gpio_bind(struct udevice *parent) static const struct button_ops button_gpio_ops = { .get_state = button_gpio_get_state, + .get_code = button_gpio_get_code, }; static const struct udevice_id button_gpio_ids[] = { diff --git a/drivers/button/button-uclass.c b/drivers/button/button-uclass.c index e33ed7d01d..032191d61a 100644 --- a/drivers/button/button-uclass.c +++ b/drivers/button/button-uclass.c @@ -38,6 +38,16 @@ enum button_state_t button_get_state(struct udevice *dev) return ops->get_state(dev); } +int button_get_code(struct udevice *dev) +{ + struct button_ops *ops = button_get_ops(dev); + + if (!ops->get_code) + return -ENOSYS; + + return ops->get_code(dev); +} + UCLASS_DRIVER(button) = { .id = UCLASS_BUTTON, .name = "button", diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 7e8e62feee..6ab137a72b 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -81,7 +81,7 @@ static ulong clk_divider_recalc_rate(struct clk *clk) unsigned long parent_rate = clk_get_parent_rate(clk); unsigned int val; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) val = divider->io_divider_val; #else val = readl(divider->reg); @@ -210,7 +210,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, div->width = width; div->flags = clk_divider_flags; div->table = table; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) div->io_divider_val = *(u32 *)reg; #endif diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index aa40daf3d7..a8775c77dc 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -62,7 +62,7 @@ static void clk_gate_endisable(struct clk *clk, int enable) if (set) reg |= BIT(gate->bit_idx); } else { -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) reg = gate->io_gate_val; #else reg = readl(gate->reg); @@ -96,7 +96,7 @@ int clk_gate_is_enabled(struct clk *clk) struct clk_gate *gate = to_clk_gate(clk); u32 reg; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) reg = gate->io_gate_val; #else reg = readl(gate->reg); @@ -142,7 +142,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name, gate->reg = reg; gate->bit_idx = bit_idx; gate->flags = clk_gate_flags; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) gate->io_gate_val = *(u32 *)reg; #endif diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index b49946fbcd..184d426d0b 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -90,7 +90,7 @@ u8 clk_mux_get_parent(struct clk *clk) struct clk_mux *mux = to_clk_mux(clk); u32 val; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) val = mux->io_mux_val; #else val = readl(mux->reg); @@ -137,7 +137,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent) if (mux->flags & CLK_MUX_HIWORD_MASK) { reg = mux->mask << (mux->shift + 16); } else { -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) reg = mux->io_mux_val; #else reg = readl(mux->reg); @@ -146,7 +146,7 @@ static int clk_mux_set_parent(struct clk *clk, struct clk *parent) } val = val << mux->shift; reg |= val; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) mux->io_mux_val = reg; #else writel(reg, mux->reg); @@ -194,7 +194,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, mux->mask = mask; mux->flags = clk_mux_flags; mux->table = table; -#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF) +#if IS_ENABLED(CONFIG_SANDBOX_CLK_CCF) mux->io_mux_val = *(u32 *)reg; #endif diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index f7d36963f8..c534cc07e0 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -308,7 +308,7 @@ enum k210_clk_flags { * @gate: An &enum k210_gate_id of this clock's gate */ struct k210_clk_params { -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) const char *name; #endif u8 flags; @@ -326,7 +326,7 @@ struct k210_clk_params { }; static const struct k210_clk_params k210_clks[] = { -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) #define NAME(_name) .name = (_name), #else #define NAME(name) @@ -1284,7 +1284,7 @@ U_BOOT_DRIVER(k210_clk) = { .priv_auto = sizeof(struct k210_clk_priv), }; -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) static char show_enabled(struct k210_clk_priv *priv, int id) { bool enabled; diff --git a/drivers/clk/clk_versaclock.c b/drivers/clk/clk_versaclock.c index 26c014cc4f..699df3cf3e 100644 --- a/drivers/clk/clk_versaclock.c +++ b/drivers/clk/clk_versaclock.c @@ -17,7 +17,7 @@ #include <linux/kernel.h> #include <linux/math64.h> -#include <dt-bindings/clk/versaclock.h> +#include <dt-bindings/clock/versaclock.h> /* VersaClock5 registers */ #define VC5_OTP_CONTROL 0x00 diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index b3dc138c4b..24bdab28aa 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -42,7 +42,7 @@ static int imx8_clk_enable(struct clk *clk) return __imx8_clk_enable(clk, 1); } -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) int soc_clk_dump(void) { struct udevice *dev; diff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h index 68ad6755e8..6e850ba266 100644 --- a/drivers/clk/imx/clk-imx8.h +++ b/drivers/clk/imx/clk-imx8.h @@ -9,7 +9,7 @@ struct imx8_clks { const char *name; }; -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) extern struct imx8_clks imx8_clk_names[]; extern int num_clks; #endif diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 7759dc63ee..b874915ba6 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -16,7 +16,7 @@ #include "clk-imx8.h" -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) struct imx8_clks imx8_clk_names[] = { { IMX8QM_A53_DIV, "A53_DIV" }, { IMX8QM_UART0_CLK, "UART0" }, diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index ffa2fcee0b..d580b43722 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -16,7 +16,7 @@ #include "clk-imx8.h" -#if CONFIG_IS_ENABLED(CMD_CLK) +#if IS_ENABLED(CONFIG_CMD_CLK) struct imx8_clks imx8_clk_names[] = { { IMX8QXP_A35_DIV, "A35_DIV" }, { IMX8QXP_I2C0_CLK, "I2C0" }, diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index f4d6ef9f93..1686410d6d 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -4,6 +4,9 @@ config CLK_RENESAS help Enable support for clock present on Renesas RCar SoCs. +config CLK_RCAR_CPG_LIB + bool "CPG/MSSR library functions" + config CLK_RCAR_GEN2 bool "Renesas RCar Gen2 clock driver" def_bool y if RCAR_32 @@ -45,6 +48,7 @@ config CLK_RCAR_GEN3 bool "Renesas RCar Gen3 clock driver" def_bool y if RCAR_GEN3 depends on CLK_RENESAS + select CLK_RCAR_CPG_LIB help Enable this to support the clocks on Renesas RCar Gen3 SoC. @@ -79,11 +83,17 @@ config CLK_R8A7795 help Enable this to support the clocks on Renesas R8A7795 SoC. -config CLK_R8A7796 - bool "Renesas R8A7796 clock driver" +config CLK_R8A77960 + bool "Renesas R8A77960 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A77960 SoC. + +config CLK_R8A77961 + bool "Renesas R8A77961 clock driver" depends on CLK_RCAR_GEN3 help - Enable this to support the clocks on Renesas R8A7796 SoC. + Enable this to support the clocks on Renesas R8A77961 SoC. config CLK_R8A77965 bool "Renesas R8A77965 clock driver" diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 36a5ca65f4..8f82a7aa3e 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o +obj-$(CONFIG_CLK_RCAR_CPG_LIB) += rcar-cpg-lib.o obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o @@ -11,7 +12,8 @@ obj-$(CONFIG_CLK_R8A7793) += r8a7791-cpg-mssr.o obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o obj-$(CONFIG_CLK_RCAR_GEN3) += clk-rcar-gen3.o obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o -obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77960) += r8a7796-cpg-mssr.o +obj-$(CONFIG_CLK_R8A77961) += r8a7796-cpg-mssr.o obj-$(CONFIG_CLK_R8A77965) += r8a77965-cpg-mssr.o obj-$(CONFIG_CLK_R8A77970) += r8a77970-cpg-mssr.o obj-$(CONFIG_CLK_R8A77980) += r8a77980-cpg-mssr.o diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 3a68c5ad0e..850d641119 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -17,6 +17,7 @@ #include <log.h> #include <asm/global_data.h> #include <asm/io.h> +#include <linux/clk-provider.h> #include <dt-bindings/clock/renesas-cpg-mssr.h> @@ -26,11 +27,6 @@ #define CPG_PLL0CR 0x00d8 #define CPG_SDCKCR 0x0074 -struct clk_div_table { - u8 val; - u8 div; -}; - /* SDHI divisors */ static const struct clk_div_table cpg_sdh_div_table[] = { { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index bcf5865222..d778db6569 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -13,77 +13,42 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <errno.h> #include <log.h> #include <wait_bit.h> #include <asm/global_data.h> #include <asm/io.h> +#include <linux/bitfield.h> #include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <reset-uclass.h> #include <dt-bindings/clock/renesas-cpg-mssr.h> #include "renesas-cpg-mssr.h" #include "rcar-gen3-cpg.h" +#include "rcar-cpg-lib.h" #define CPG_PLL0CR 0x00d8 #define CPG_PLL2CR 0x002c #define CPG_PLL4CR 0x01f4 -#define CPG_RPC_PREDIV_MASK 0x3 -#define CPG_RPC_PREDIV_OFFSET 3 -#define CPG_RPC_POSTDIV_MASK 0x7 -#define CPG_RPC_POSTDIV_OFFSET 0 - -/* - * SDn Clock - */ -#define CPG_SD_STP_HCK BIT(9) -#define CPG_SD_STP_CK BIT(8) - -#define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK) -#define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0) - -#define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \ -{ \ - .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \ - ((stp_ck) ? CPG_SD_STP_CK : 0) | \ - ((sd_srcfc) << 2) | \ - ((sd_fc) << 0), \ - .div = (sd_div), \ -} +static const struct clk_div_table cpg_rpcsrc_div_table[] = { + { 2, 5 }, { 3, 6 }, { 0, 0 }, +}; -struct sd_div_table { - u32 val; - unsigned int div; +static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = { + { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, + { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, + { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 }, }; -/* SDn divider - * sd_srcfc sd_fc div - * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc - *------------------------------------------------------------------- - * 0 0 0 (1) 1 (4) 4 - * 0 0 1 (2) 1 (4) 8 - * 1 0 2 (4) 1 (4) 16 - * 1 0 3 (8) 1 (4) 32 - * 1 0 4 (16) 1 (4) 64 - * 0 0 0 (1) 0 (2) 2 - * 0 0 1 (2) 0 (2) 4 - * 1 0 2 (4) 0 (2) 8 - * 1 0 3 (8) 0 (2) 16 - * 1 0 4 (16) 0 (2) 32 - */ -static const struct sd_div_table cpg_sd_div_table[] = { -/* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */ - CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4), - CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8), - CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16), - CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32), - CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64), - CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2), - CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4), - CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8), - CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16), - CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32), +static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = { + { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 }, + { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 }, + { 0, 0 }, }; static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, @@ -108,18 +73,44 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, return renesas_clk_get_parent(clk, info, parent); } +static int gen3_clk_enable(struct clk *clk) +{ + struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + + return renesas_clk_endisable(clk, priv->base, priv->info, true); +} + +static int gen3_clk_disable(struct clk *clk) +{ + struct gen3_clk_priv *priv = dev_get_priv(clk->dev); + + return renesas_clk_endisable(clk, priv->base, priv->info, false); +} + +static u64 gen3_clk_get_rate64(struct clk *clk); + static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) { struct gen3_clk_priv *priv = dev_get_priv(clk->dev); struct cpg_mssr_info *info = priv->info; const struct cpg_core_clk *core; - struct clk parent; + struct clk parent, grandparent; int ret; - ret = gen3_clk_get_parent(priv, clk, info, &parent); - if (ret) { - printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); - return ret; + /* + * The clk may be either CPG_MOD or core clock, in case this is MOD + * clock, use core clock one level up, otherwise use the clock as-is. + * Note that parent clock here always represents core clock. Also note + * that grandparent clock are the parent clock of the core clock here. + */ + if (renesas_clk_is_mod(clk)) { + ret = gen3_clk_get_parent(priv, clk, info, &parent); + if (ret) { + printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } + } else { + parent = *clk; } if (renesas_clk_is_mod(&parent)) @@ -129,35 +120,40 @@ static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) if (ret) return ret; - if (core->type != CLK_TYPE_GEN3_SD) - return 0; + ret = renesas_clk_get_parent(&parent, info, &grandparent); + if (ret) { + printf("%s[%i] grandparent fail, ret=%i\n", __func__, __LINE__, ret); + return ret; + } - debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset); + switch (core->type) { + case CLK_TYPE_GEN3_SDH: + fallthrough; + case CLK_TYPE_GEN4_SDH: + return rcar_clk_set_rate64_sdh(core->parent, + gen3_clk_get_rate64(&grandparent), + rate, priv->base + core->offset); - writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); + case CLK_TYPE_GEN3_SD: + fallthrough; + case CLK_TYPE_GEN4_SD: + return rcar_clk_set_rate64_sd(core->parent, + gen3_clk_get_rate64(&grandparent), + rate, priv->base + core->offset); + + case CLK_TYPE_R8A77970_SD0: + return rcar_clk_set_rate64_div_table(core->parent, + gen3_clk_get_rate64(&grandparent), + rate, priv->base + core->offset, + CPG_SDCKCR_SD0FC_MASK, + r8a77970_cpg_sd0_div_table, "SD"); + } return 0; } -static int gen3_clk_enable(struct clk *clk) -{ - struct gen3_clk_priv *priv = dev_get_priv(clk->dev); - - return renesas_clk_endisable(clk, priv->base, priv->info, true); -} - -static int gen3_clk_disable(struct clk *clk) -{ - struct gen3_clk_priv *priv = dev_get_priv(clk->dev); - - return renesas_clk_endisable(clk, priv->base, priv->info, false); -} - -static u64 gen3_clk_get_rate64(struct clk *clk); - static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv, struct clk *parent, - const struct cpg_core_clk *core, u32 mul_reg, u32 mult, u32 div, char *name) { @@ -172,8 +168,8 @@ static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv, rate = (gen3_clk_get_rate64(parent) * mult) / div; - debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n", - __func__, __LINE__, name, core->parent, mult, div, rate); + debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n", + __func__, __LINE__, name, mult, div, rate); return rate; } @@ -185,9 +181,9 @@ static u64 gen3_clk_get_rate64(struct clk *clk) const struct cpg_core_clk *core; const struct rcar_gen3_cpg_pll_config *pll_config = priv->cpg_pll_config; - u32 value, div, prediv, postdiv; + u32 value, div; u64 rate = 0; - int i, ret; + int ret; debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id); @@ -227,56 +223,56 @@ static u64 gen3_clk_get_rate64(struct clk *clk) return -EINVAL; case CLK_TYPE_GEN3_MAIN: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, 1, pll_config->extal_div, "MAIN"); case CLK_TYPE_GEN3_PLL0: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, CPG_PLL0CR, 0, 0, "PLL0"); case CLK_TYPE_GEN3_PLL1: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, pll_config->pll1_mult, pll_config->pll1_div, "PLL1"); case CLK_TYPE_GEN3_PLL2: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, CPG_PLL2CR, 0, 0, "PLL2"); case CLK_TYPE_GEN3_PLL3: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, pll_config->pll3_mult, pll_config->pll3_div, "PLL3"); case CLK_TYPE_GEN3_PLL4: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, CPG_PLL4CR, 0, 0, "PLL4"); - case CLK_TYPE_R8A779A0_MAIN: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + case CLK_TYPE_GEN4_MAIN: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, 1, pll_config->extal_div, "V3U_MAIN"); - case CLK_TYPE_R8A779A0_PLL1: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + case CLK_TYPE_GEN4_PLL1: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, pll_config->pll1_mult, pll_config->pll1_div, "V3U_PLL1"); - case CLK_TYPE_R8A779A0_PLL2X_3X: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + case CLK_TYPE_GEN4_PLL2X_3X: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core->offset, 0, 0, "V3U_PLL2X_3X"); - case CLK_TYPE_R8A779A0_PLL5: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + case CLK_TYPE_GEN4_PLL5: + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, pll_config->pll5_mult, pll_config->pll5_div, "V3U_PLL5"); case CLK_TYPE_FF: - return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core, + return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, 0, core->mult, core->div, "FIXED"); @@ -289,59 +285,82 @@ static u64 gen3_clk_get_rate64(struct clk *clk) div, rate); return rate; - case CLK_TYPE_GEN3_SD: /* FIXME */ + case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */ fallthrough; - case CLK_TYPE_R8A779A0_SD: - value = readl(priv->base + core->offset); - value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK; - - for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) { - if (cpg_sd_div_table[i].val != value) - continue; - - rate = gen3_clk_get_rate64(&parent) / - cpg_sd_div_table[i].div; - debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, cpg_sd_div_table[i].div, rate); - - return rate; + case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */ + return rcar_clk_get_rate64_sdh(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + core->offset); + + case CLK_TYPE_R8A77970_SD0H: + return rcar_clk_get_rate64_div_table(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + core->offset, + CPG_SDCKCR_SDHFC_MASK, + r8a77970_cpg_sd0h_div_table, "SDH"); + + case CLK_TYPE_GEN3_SD: + fallthrough; + case CLK_TYPE_GEN4_SD: + return rcar_clk_get_rate64_sd(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + core->offset); + + case CLK_TYPE_R8A77970_SD0: + return rcar_clk_get_rate64_div_table(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + core->offset, + CPG_SDCKCR_SD0FC_MASK, + r8a77970_cpg_sd0_div_table, "SD"); + + case CLK_TYPE_GEN3_RPCSRC: + return rcar_clk_get_rate64_div_table(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + CPG_RPCCKCR, + CPG_RPCCKCR_DIV_POST_MASK, + cpg_rpcsrc_div_table, "RPCSRC"); + + case CLK_TYPE_GEN3_D3_RPCSRC: + case CLK_TYPE_GEN3_E3_RPCSRC: + /* + * Register RPCSRC as fixed factor clock based on the + * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for + * which has been set prior to booting the kernel. + */ + value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3; + + switch (value) { + case 0: + div = 5; + break; + case 1: + div = 3; + break; + case 2: + div = core->div; + break; + case 3: + default: + div = 2; + break; } - return -EINVAL; - - case CLK_TYPE_GEN3_RPC: - case CLK_TYPE_GEN3_RPCD2: - rate = gen3_clk_get_rate64(&parent); - - value = readl(priv->base + core->offset); - - prediv = (value >> CPG_RPC_PREDIV_OFFSET) & - CPG_RPC_PREDIV_MASK; - if (prediv == 2) - rate /= 5; - else if (prediv == 3) - rate /= 6; - else - return -EINVAL; - - postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) & - CPG_RPC_POSTDIV_MASK; - - if (postdiv % 2 != 0) { - rate /= postdiv + 1; - - if (core->type == CLK_TYPE_GEN3_RPCD2) - rate /= 2; + rate = gen3_clk_get_rate64(&parent) / div; + debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n", + __func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate); - debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n", - __func__, __LINE__, - core->parent, prediv, postdiv, rate); + return rate; - return rate; - } + case CLK_TYPE_GEN3_RPC: + case CLK_TYPE_GEN4_RPC: + return rcar_clk_get_rate64_rpc(core->parent, + gen3_clk_get_rate64(&parent), + priv->base + CPG_RPCCKCR); - return -EINVAL; + case CLK_TYPE_GEN3_RPCD2: + case CLK_TYPE_GEN4_RPCD2: + return rcar_clk_get_rate64_rpcd2(core->parent, + gen3_clk_get_rate64(&parent)); } @@ -382,7 +401,7 @@ const struct clk_ops gen3_clk_ops = { .of_xlate = gen3_clk_of_xlate, }; -int gen3_clk_probe(struct udevice *dev) +static int gen3_clk_probe(struct udevice *dev) { struct gen3_clk_priv *priv = dev_get_priv(dev); struct cpg_mssr_info *info = @@ -440,9 +459,84 @@ int gen3_clk_probe(struct udevice *dev) return 0; } -int gen3_clk_remove(struct udevice *dev) +static int gen3_clk_remove(struct udevice *dev) { struct gen3_clk_priv *priv = dev_get_priv(dev); return renesas_clk_remove(priv->base, priv->info); } + +U_BOOT_DRIVER(clk_gen3) = { + .name = "clk_gen3", + .id = UCLASS_CLK, + .priv_auto = sizeof(struct gen3_clk_priv), + .ops = &gen3_clk_ops, + .probe = gen3_clk_probe, + .remove = gen3_clk_remove, +}; + +static int gen3_reset_assert(struct reset_ctl *reset_ctl) +{ + struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); + struct gen3_clk_priv *priv = dev_get_priv(cdev); + unsigned int reg = reset_ctl->id / 32; + unsigned int bit = reset_ctl->id % 32; + u32 bitmask = BIT(bit); + + writel(bitmask, priv->base + priv->info->reset_regs[reg]); + + return 0; +} + +static int gen3_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev); + struct gen3_clk_priv *priv = dev_get_priv(cdev); + unsigned int reg = reset_ctl->id / 32; + unsigned int bit = reset_ctl->id % 32; + u32 bitmask = BIT(bit); + + writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]); + + return 0; +} + +static const struct reset_ops rst_gen3_ops = { + .rst_assert = gen3_reset_assert, + .rst_deassert = gen3_reset_deassert, +}; + +U_BOOT_DRIVER(rst_gen3) = { + .name = "rst_gen3", + .id = UCLASS_RESET, + .ops = &rst_gen3_ops, +}; + +int gen3_cpg_bind(struct udevice *parent) +{ + struct cpg_mssr_info *info = + (struct cpg_mssr_info *)dev_get_driver_data(parent); + struct udevice *cdev, *rdev; + struct driver *drv; + int ret; + + drv = lists_driver_lookup_name("clk_gen3"); + if (!drv) + return -ENOENT; + + ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info, + dev_ofnode(parent), &cdev); + if (ret) + return ret; + + drv = lists_driver_lookup_name("rst_gen3"); + if (!drv) + return -ENOENT; + + ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev, + dev_ofnode(parent), &rdev); + if (ret) + device_unbind(cdev); + + return ret; +} diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 48da65cd3d..1f76d6b2c2 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -1,11 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0 /* - * Renesas R8A774A1 CPG MSSR driver + * r8a774a1 Clock Pulse Generator / Module Standby and Software Reset * - * Copyright (C) 2017-2019 Marek Vasut <marek.vasut@gmail.com> + * Copyright (C) 2018 Renesas Electronics Corp. * - * Based on the following driver from Linux kernel: - * r8a7796 Clock Pulse Generator / Module Standby and Software Reset + * Based on r8a7796-cpg-mssr.c * * Copyright (C) 2016 Glider bvba */ @@ -68,12 +67,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774A1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -100,10 +95,17 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_FIXED("s3d2", R8A774A1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774A1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774A1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A774A1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A774A1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A774A1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A774A1_CLK_SD0, R8A774A1_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, R8A774A1_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, R8A774A1_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, R8A774A1_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774A1_CLK_RPC), DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1), @@ -210,7 +212,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = { DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6), - DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP), + DEF_MOD("iic-pmic", 926, R8A774A1_CLK_CP), DEF_MOD("i2c4", 927, R8A774A1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774A1_CLK_S0D6), DEF_MOD("i2c2", 929, R8A774A1_CLK_S3D2), @@ -329,7 +331,7 @@ static const struct cpg_mssr_info r8a774a1_cpg_mssr_info = { .get_pll_config = r8a774a1_get_pll_config, }; -static const struct udevice_id r8a774a1_clk_ids[] = { +static const struct udevice_id r8a774a1_cpg_ids[] = { { .compatible = "renesas,r8a774a1-cpg-mssr", .data = (ulong)&r8a774a1_cpg_mssr_info, @@ -337,12 +339,9 @@ static const struct udevice_id r8a774a1_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a774a1) = { - .name = "clk_r8a774a1", - .id = UCLASS_CLK, - .of_match = r8a774a1_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a774a1) = { + .name = "cpg_r8a774a1", + .id = UCLASS_NOP, + .of_match = r8a774a1_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c index 418c393a20..b5927c7892 100644 --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c @@ -2,7 +2,7 @@ /* * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2019 Renesas Electronics Corp. * * Based on r8a7796-cpg-mssr.c * @@ -65,12 +65,8 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774B1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -96,10 +92,17 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = { DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774B1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A774B1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A774B1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A774B1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, R8A774B1_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, R8A774B1_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, R8A774B1_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, R8A774B1_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774B1_CLK_RPC), DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1), @@ -205,7 +208,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = { DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6), - DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP), + DEF_MOD("iic-pmic", 926, R8A774B1_CLK_CP), DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6), DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2), @@ -326,7 +329,7 @@ static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = { .get_pll_config = r8a774b1_get_pll_config, }; -static const struct udevice_id r8a774b1_clk_ids[] = { +static const struct udevice_id r8a774b1_cpg_ids[] = { { .compatible = "renesas,r8a774b1-cpg-mssr", .data = (ulong)&r8a774b1_cpg_mssr_info, @@ -334,12 +337,9 @@ static const struct udevice_id r8a774b1_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a774b1) = { - .name = "clk_r8a774b1", - .id = UCLASS_CLK, - .of_match = r8a774b1_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a774b1) = { + .name = "cpg_r8a774b1", + .id = UCLASS_NOP, + .of_match = r8a774b1_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c index c1283d2614..802a9c0b11 100644 --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c @@ -2,12 +2,12 @@ /* * r8a774c0 Clock Pulse Generator / Module Standby and Software Reset * - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a77990-cpg-mssr.c * * Copyright (C) 2015 Glider bvba - * Copyright (C) 2020 Renesas Electronics Corp. + * Copyright (C) 2015 Renesas Electronics Corp. */ #include <common.h> @@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = { DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), - DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774C0_CLK_RPC), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = { DEF_FIXED("s3d2", R8A774C0_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774C0_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, CLK_SDSRC, 0x0074), - DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, CLK_SDSRC, 0x0078), - DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774C0_CLK_RPC), + + DEF_GEN3_SDH("sd0h", R8A774C0_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SDH("sd1h", R8A774C0_CLK_SD1H, CLK_SDSRC, 0x0078), + DEF_GEN3_SDH("sd3h", R8A774C0_CLK_SD3H, CLK_SDSRC, 0x026c), + DEF_GEN3_SD("sd0", R8A774C0_CLK_SD0, R8A774C0_CLK_SD0H, 0x0074), + DEF_GEN3_SD("sd1", R8A774C0_CLK_SD1, R8A774C0_CLK_SD1H, 0x0078), + DEF_GEN3_SD("sd3", R8A774C0_CLK_SD3, R8A774C0_CLK_SD3H, 0x026c), DEF_FIXED("cl", R8A774C0_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cp", R8A774C0_CLK_CP, CLK_EXTAL, 2, 1), @@ -210,7 +211,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = { DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2), DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2), - DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP), + DEF_MOD("iic-pmic", 926, R8A774C0_CLK_CP), DEF_MOD("i2c4", 927, R8A774C0_CLK_S3D2), DEF_MOD("i2c3", 928, R8A774C0_CLK_S3D2), DEF_MOD("i2c2", 929, R8A774C0_CLK_S3D2), @@ -299,7 +300,7 @@ const struct cpg_mssr_info r8a774c0_cpg_mssr_info = { .get_pll_config = r8a774c0_get_pll_config, }; -static const struct udevice_id r8a774c0_clk_ids[] = { +static const struct udevice_id r8a774c0_cpg_ids[] = { { .compatible = "renesas,r8a774c0-cpg-mssr", .data = (ulong)&r8a774c0_cpg_mssr_info @@ -307,12 +308,9 @@ static const struct udevice_id r8a774c0_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a774c0) = { - .name = "clk_r8a774c0", - .id = UCLASS_CLK, - .of_match = r8a774c0_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a774c0) = { + .name = "cpg_r8a774c0", + .id = UCLASS_NOP, + .of_match = r8a774c0_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c index 0cacd8d0c8..617fa769dc 100644 --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c @@ -68,12 +68,8 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A774E1_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -100,10 +96,17 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = { DEF_FIXED("s3d2", R8A774E1_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A774E1_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A774E1_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A774E1_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A774E1_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A774E1_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A774E1_CLK_SD0, R8A774E1_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A774E1_CLK_SD1, R8A774E1_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A774E1_CLK_SD2, R8A774E1_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A774E1_CLK_SD3, R8A774E1_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A774E1_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A774E1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A774E1_CLK_RPC), DEF_FIXED("cl", R8A774E1_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A774E1_CLK_CR, CLK_PLL1_DIV4, 2, 1), @@ -219,7 +222,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = { DEF_MOD("i2c6", 918, R8A774E1_CLK_S0D6), DEF_MOD("i2c5", 919, R8A774E1_CLK_S0D6), DEF_MOD("adg", 922, R8A774E1_CLK_S0D1), - DEF_MOD("i2c-dvfs", 926, R8A774E1_CLK_CP), + DEF_MOD("iic-pmic", 926, R8A774E1_CLK_CP), DEF_MOD("i2c4", 927, R8A774E1_CLK_S0D6), DEF_MOD("i2c3", 928, R8A774E1_CLK_S0D6), DEF_MOD("i2c2", 929, R8A774E1_CLK_S3D2), @@ -340,7 +343,7 @@ static const struct cpg_mssr_info r8a774e1_cpg_mssr_info = { .get_pll_config = r8a774e1_get_pll_config, }; -static const struct udevice_id r8a774e1_clk_ids[] = { +static const struct udevice_id r8a774e1_cpg_ids[] = { { .compatible = "renesas,r8a774e1-cpg-mssr", .data = (ulong)&r8a774e1_cpg_mssr_info @@ -348,12 +351,9 @@ static const struct udevice_id r8a774e1_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a774e1) = { - .name = "clk_r8a774e1", - .id = UCLASS_CLK, - .of_match = r8a774e1_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a774e1) = { + .name = "cpg_r8a774e1", + .id = UCLASS_NOP, + .of_match = r8a774e1_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 6ba796b98c..005f6a9ecd 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7795 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015 Glider bvba + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * @@ -69,12 +70,8 @@ static const struct cpg_core_clk r8a7795_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A7795_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -102,10 +99,17 @@ static const struct cpg_core_clk r8a7795_core_clks[] = { DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A7795_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A7795_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A7795_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A7795_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, R8A7795_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, R8A7795_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, R8A7795_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, R8A7795_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7795_CLK_RPC), DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1), @@ -126,6 +130,11 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("fdp1-2", 117, R8A7795_CLK_S2D1), /* ES1.x */ DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1), DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1), + DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6), + DEF_MOD("tmu3", 122, R8A7795_CLK_S3D2), + DEF_MOD("tmu2", 123, R8A7795_CLK_S3D2), + DEF_MOD("tmu1", 124, R8A7795_CLK_S3D2), + DEF_MOD("tmu0", 125, R8A7795_CLK_CP), DEF_MOD("scif5", 202, R8A7795_CLK_S3D4), DEF_MOD("scif4", 203, R8A7795_CLK_S3D4), DEF_MOD("scif3", 204, R8A7795_CLK_S3D4), @@ -222,6 +231,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = { DEF_MOD("lvds", 727, R8A7795_CLK_S0D4), DEF_MOD("hdmi1", 728, R8A7795_CLK_HDMI), DEF_MOD("hdmi0", 729, R8A7795_CLK_HDMI), + DEF_MOD("mlp", 802, R8A7795_CLK_S2D1), DEF_MOD("vin7", 804, R8A7795_CLK_S0D2), DEF_MOD("vin6", 805, R8A7795_CLK_S0D2), DEF_MOD("vin5", 806, R8A7795_CLK_S0D2), @@ -370,7 +380,7 @@ static const struct cpg_mssr_info r8a7795_cpg_mssr_info = { .get_pll_config = r8a7795_get_pll_config, }; -static const struct udevice_id r8a7795_clk_ids[] = { +static const struct udevice_id r8a7795_cpg_ids[] = { { .compatible = "renesas,r8a7795-cpg-mssr", .data = (ulong)&r8a7795_cpg_mssr_info @@ -378,12 +388,9 @@ static const struct udevice_id r8a7795_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a7795) = { - .name = "clk_r8a7795", - .id = UCLASS_CLK, - .of_match = r8a7795_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a7795) = { + .name = "cpg_r8a7795", + .id = UCLASS_NOP, + .of_match = r8a7795_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index e318719033..27cf62e021 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -1,13 +1,10 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Renesas R8A7796 CPG MSSR driver + * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software + * Reset * - * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com> - * - * Based on the following driver from Linux kernel: - * r8a7796 Clock Pulse Generator / Module Standby and Software Reset - * - * Copyright (C) 2016 Glider bvba + * Copyright (C) 2016-2019 Glider bvba + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -75,12 +72,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A7796_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -108,10 +101,17 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A7796_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A7796_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A7796_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A7796_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, R8A7796_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, R8A7796_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, R8A7796_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, R8A7796_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A7796_CLK_RPC), DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1), @@ -209,6 +209,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { DEF_MOD("du0", 724, R8A7796_CLK_S2D1), DEF_MOD("lvds", 727, R8A7796_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A7796_CLK_HDMI), + DEF_MOD("mlp", 802, R8A7796_CLK_S2D1), DEF_MOD("vin7", 804, R8A7796_CLK_S0D2), DEF_MOD("vin6", 805, R8A7796_CLK_S0D2), DEF_MOD("vin5", 806, R8A7796_CLK_S0D2), @@ -354,20 +355,36 @@ static const struct cpg_mssr_info r8a7796_cpg_mssr_info = { .get_pll_config = r8a7796_get_pll_config, }; -static const struct udevice_id r8a7796_clk_ids[] = { +static const struct cpg_mssr_info r8a77961_cpg_mssr_info = { + .core_clk = r8a7796_core_clks, + .core_clk_size = ARRAY_SIZE(r8a7796_core_clks), + .mod_clk = r8a7796_mod_clks, + .mod_clk_size = ARRAY_SIZE(r8a7796_mod_clks), + .mstp_table = r8a7796_mstp_table, + .mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table), + .reset_node = "renesas,r8a77961-rst", + .extalr_node = "extalr", + .mod_clk_base = MOD_CLK_BASE, + .clk_extal_id = CLK_EXTAL, + .clk_extalr_id = CLK_EXTALR, + .get_pll_config = r8a7796_get_pll_config, +}; + +static const struct udevice_id r8a7796_cpg_ids[] = { { .compatible = "renesas,r8a7796-cpg-mssr", .data = (ulong)&r8a7796_cpg_mssr_info, }, + { + .compatible = "renesas,r8a77961-cpg-mssr", + .data = (ulong)&r8a77961_cpg_mssr_info, + }, { } }; -U_BOOT_DRIVER(clk_r8a7796) = { - .name = "clk_r8a7796", - .id = UCLASS_CLK, - .of_match = r8a7796_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a7796) = { + .name = "cpg_r8a7796", + .id = UCLASS_NOP, + .of_match = r8a7796_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index 0a15617da8..58e557a95f 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a77965 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org> + * Copyright (C) 2019 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -68,12 +69,8 @@ static const struct cpg_core_clk r8a77965_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), - DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77965_CLK_RPC), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), @@ -100,10 +97,17 @@ static const struct cpg_core_clk r8a77965_core_clks[] = { DEF_FIXED("s3d2", R8A77965_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77965_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, CLK_SDSRC, 0x074), - DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, CLK_SDSRC, 0x078), - DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268), - DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c), + DEF_GEN3_SDH("sd0h", R8A77965_CLK_SD0H, CLK_SDSRC, 0x074), + DEF_GEN3_SDH("sd1h", R8A77965_CLK_SD1H, CLK_SDSRC, 0x078), + DEF_GEN3_SDH("sd2h", R8A77965_CLK_SD2H, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd3h", R8A77965_CLK_SD3H, CLK_SDSRC, 0x26c), + DEF_GEN3_SD("sd0", R8A77965_CLK_SD0, R8A77965_CLK_SD0H, 0x074), + DEF_GEN3_SD("sd1", R8A77965_CLK_SD1, R8A77965_CLK_SD1H, 0x078), + DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, R8A77965_CLK_SD2H, 0x268), + DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, R8A77965_CLK_SD3H, 0x26c), + + DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77965_CLK_RPC), DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1), @@ -204,6 +208,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("lvds", 727, R8A77965_CLK_S2D1), DEF_MOD("hdmi0", 729, R8A77965_CLK_HDMI), + DEF_MOD("mlp", 802, R8A77965_CLK_S2D1), DEF_MOD("vin7", 804, R8A77965_CLK_S0D2), DEF_MOD("vin6", 805, R8A77965_CLK_S0D2), DEF_MOD("vin5", 806, R8A77965_CLK_S0D2), @@ -249,6 +254,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = { DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("dab", 1016, R8A77965_CLK_S0D6), DEF_MOD("scu-all", 1017, R8A77965_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), @@ -352,7 +358,7 @@ static const struct cpg_mssr_info r8a77965_cpg_mssr_info = { .get_pll_config = r8a77965_get_pll_config, }; -static const struct udevice_id r8a77965_clk_ids[] = { +static const struct udevice_id r8a77965_cpg_ids[] = { { .compatible = "renesas,r8a77965-cpg-mssr", .data = (ulong)&r8a77965_cpg_mssr_info, @@ -360,12 +366,9 @@ static const struct udevice_id r8a77965_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a77965) = { - .name = "clk_r8a77965", - .id = UCLASS_CLK, - .of_match = r8a77965_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a77965) = { + .name = "cpg_r8a77965", + .id = UCLASS_NOP, + .of_match = r8a77965_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c index a85bed6192..f5d77df423 100644 --- a/drivers/clk/renesas/r8a77970-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c @@ -22,11 +22,6 @@ #define CPG_SD0CKCR 0x0074 -enum r8a77970_clk_types { - CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE, - CLK_TYPE_R8A77970_SD0, -}; - enum clk_ids { /* Core Clock Outputs exported to DT */ LAST_DT_CORE_CLK = R8A77970_CLK_OSC, @@ -219,7 +214,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = { .get_pll_config = r8a77970_get_pll_config, }; -static const struct udevice_id r8a77970_clk_ids[] = { +static const struct udevice_id r8a77970_cpg_ids[] = { { .compatible = "renesas,r8a77970-cpg-mssr", .data = (ulong)&r8a77970_cpg_mssr_info @@ -227,12 +222,9 @@ static const struct udevice_id r8a77970_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a77970) = { - .name = "clk_r8a77970", - .id = UCLASS_CLK, - .of_match = r8a77970_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a77970) = { + .name = "cpg_r8a77970", + .id = UCLASS_NOP, + .of_match = r8a77970_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c index bd9d7c9be5..f29727ddb9 100644 --- a/drivers/clk/renesas/r8a77980-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c @@ -65,13 +65,10 @@ static const struct cpg_core_clk r8a77980_core_clks[] = { DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1), - DEF_RATE(".oco", CLK_OCO, 32768), - DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77980_CLK_RPC), + DEF_RATE(".oco", CLK_OCO, 32768), /* Core Clock Outputs */ DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), @@ -95,7 +92,11 @@ static const struct cpg_core_clk r8a77980_core_clks[] = { DEF_FIXED("s3d2", R8A77980_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77980_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, CLK_SDSRC, 0x0074), + DEF_GEN3_SDH("sd0h", R8A77980_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SD("sd0", R8A77980_CLK_SD0, R8A77980_CLK_SD0H, 0x0074), + + DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77980_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77980_CLK_RPC), DEF_FIXED("cl", R8A77980_CLK_CL, CLK_PLL1_DIV2, 48, 1), DEF_FIXED("cp", R8A77980_CLK_CP, CLK_EXTAL, 2, 1), @@ -238,7 +239,7 @@ static const struct cpg_mssr_info r8a77980_cpg_mssr_info = { .get_pll_config = r8a77980_get_pll_config, }; -static const struct udevice_id r8a77980_clk_ids[] = { +static const struct udevice_id r8a77980_cpg_ids[] = { { .compatible = "renesas,r8a77980-cpg-mssr", .data = (ulong)&r8a77980_cpg_mssr_info @@ -246,12 +247,9 @@ static const struct udevice_id r8a77980_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a77980) = { - .name = "clk_r8a77980", - .id = UCLASS_CLK, - .of_match = r8a77980_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a77980) = { + .name = "cpg_r8a77980", + .id = UCLASS_NOP, + .of_match = r8a77980_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 67a1f586e2..1864af30c8 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -2,7 +2,7 @@ /* * r8a77990 Clock Pulse Generator / Module Standby and Software Reset * - * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018-2019 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -77,11 +77,6 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), - DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77990_CLK_RPC), - DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), @@ -108,9 +103,15 @@ static const struct cpg_core_clk r8a77990_core_clks[] = { DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), - DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), - DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078), + DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c), + DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074), + DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), + DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), + + DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77990_CLK_RPC), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), @@ -205,6 +206,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("du0", 724, R8A77990_CLK_S1D1), DEF_MOD("lvds", 727, R8A77990_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77990_CLK_S2D1), DEF_MOD("vin5", 806, R8A77990_CLK_S1D2), DEF_MOD("vin4", 807, R8A77990_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77990_CLK_S3D2), @@ -219,7 +221,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77990_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77990_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77990_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77990_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77990_CLK_RPCD2), DEF_MOD("i2c6", 918, R8A77990_CLK_S3D2), DEF_MOD("i2c5", 919, R8A77990_CLK_S3D2), DEF_MOD("i2c-dvfs", 926, R8A77990_CLK_CP), @@ -241,6 +243,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = { DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)), DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)), DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)), + DEF_MOD("dab", 1016, R8A77990_CLK_S3D1), DEF_MOD("scu-all", 1017, R8A77990_CLK_S3D4), DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)), DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)), @@ -311,7 +314,7 @@ static const struct cpg_mssr_info r8a77990_cpg_mssr_info = { .get_pll_config = r8a77990_get_pll_config, }; -static const struct udevice_id r8a77990_clk_ids[] = { +static const struct udevice_id r8a77990_cpg_ids[] = { { .compatible = "renesas,r8a77990-cpg-mssr", .data = (ulong)&r8a77990_cpg_mssr_info @@ -319,12 +322,9 @@ static const struct udevice_id r8a77990_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a77990) = { - .name = "clk_r8a77990", - .id = UCLASS_CLK, - .of_match = r8a77990_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a77990) = { + .name = "cpg_r8a77990", + .id = UCLASS_NOP, + .of_match = r8a77990_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 83e8e9bfaa..03ae863c8b 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -71,18 +71,14 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), - DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), - - DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77995_CLK_RPC), + DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), /* Core Clock Outputs */ + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1), DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), @@ -110,7 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), - DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), + + DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC), DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), @@ -166,6 +166,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("du1", 723, R8A77995_CLK_S1D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), @@ -179,7 +180,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77995_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), @@ -249,7 +250,7 @@ static const struct cpg_mssr_info r8a77995_cpg_mssr_info = { .get_pll_config = r8a77995_get_pll_config, }; -static const struct udevice_id r8a77995_clk_ids[] = { +static const struct udevice_id r8a77995_cpg_ids[] = { { .compatible = "renesas,r8a77995-cpg-mssr", .data = (ulong)&r8a77995_cpg_mssr_info @@ -257,12 +258,9 @@ static const struct udevice_id r8a77995_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a77995) = { - .name = "clk_r8a77995", - .id = UCLASS_CLK, - .of_match = r8a77995_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a77995) = { + .name = "cpg_r8a77995", + .id = UCLASS_NOP, + .of_match = r8a77995_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c index bda6995236..a9c941b6db 100644 --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c @@ -53,29 +53,18 @@ enum clk_ids { }; #define DEF_PLL(_name, _id, _offset) \ - DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_PLL2X_3X, CLK_MAIN, \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \ .offset = _offset) -#define DEF_SD(_name, _id, _parent, _offset) \ - DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_SD, _parent, .offset = _offset) - -#define DEF_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ - DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_MDSEL, \ - (_parent0) << 16 | (_parent1), \ - .div = (_div0) << 16 | (_div1), .offset = _md) - -#define DEF_OSC(_name, _id, _parent, _div) \ - DEF_BASE(_name, _id, CLK_TYPE_R8A779A0_OSC, _parent, .div = _div) - static const struct cpg_core_clk r8a779a0_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), /* Internal Core Clocks */ - DEF_BASE(".main", CLK_MAIN, CLK_TYPE_R8A779A0_MAIN, CLK_EXTAL), - DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_R8A779A0_PLL1, CLK_MAIN), - DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_R8A779A0_PLL5, CLK_MAIN), + DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN4_MAIN, CLK_EXTAL), + DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN4_PLL1, CLK_MAIN), + DEF_BASE(".pll5", CLK_PLL5, CLK_TYPE_GEN4_PLL5, CLK_MAIN), DEF_PLL(".pll20", CLK_PLL20, 0x0834), DEF_PLL(".pll21", CLK_PLL21, 0x0838), DEF_PLL(".pll30", CLK_PLL30, 0x083c), @@ -91,9 +80,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = { DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 2, 1), DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 4, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL5_DIV4, 1, 1), + DEF_RATE(".oco", CLK_OCO, 32768), + DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5), + /* Core Clock Outputs */ + DEF_GEN4_Z("z0", R8A779A0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL20, 2, 0), + DEF_GEN4_Z("z1", R8A779A0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL21, 2, 8), DEF_FIXED("zx", R8A779A0_CLK_ZX, CLK_PLL20_DIV2, 2, 1), DEF_FIXED("s1d1", R8A779A0_CLK_S1D1, CLK_S1, 1, 1), DEF_FIXED("s1d2", R8A779A0_CLK_S1D2, CLK_S1, 2, 1), @@ -107,7 +101,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = { DEF_FIXED("zt", R8A779A0_CLK_ZT, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("ztr", R8A779A0_CLK_ZTR, CLK_PLL1_DIV2, 2, 1), DEF_FIXED("zr", R8A779A0_CLK_ZR, CLK_PLL1_DIV2, 1, 1), - DEF_FIXED("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 1, 1), DEF_FIXED("cnndsp", R8A779A0_CLK_CNNDSP, CLK_PLL5_DIV4, 1, 1), DEF_FIXED("vip", R8A779A0_CLK_VIP, CLK_PLL5, 5, 1), DEF_FIXED("adgh", R8A779A0_CLK_ADGH, CLK_PLL5_DIV4, 1, 1), @@ -116,15 +109,22 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = { DEF_FIXED("vcbus", R8A779A0_CLK_VCBUS, CLK_PLL5_DIV4, 1, 1), DEF_FIXED("cbfusa", R8A779A0_CLK_CBFUSA, CLK_EXTAL, 2, 1), DEF_FIXED("cp", R8A779A0_CLK_CP, CLK_EXTAL, 2, 1), + DEF_FIXED("cl16mck", R8A779A0_CLK_CL16MCK, CLK_PLL1_DIV2, 64, 1), + + DEF_GEN4_SDH("sd0h", R8A779A0_CLK_SD0H, CLK_SDSRC, 0x870), + DEF_GEN4_SD("sd0", R8A779A0_CLK_SD0, R8A779A0_CLK_SD0H, 0x870), - DEF_SD("sd0", R8A779A0_CLK_SD0, CLK_SDSRC, 0x870), + DEF_BASE("rpc", R8A779A0_CLK_RPC, CLK_TYPE_GEN4_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A779A0_CLK_RPCD2, CLK_TYPE_GEN4_RPCD2, + R8A779A0_CLK_RPC), DEF_DIV6P1("mso", R8A779A0_CLK_MSO, CLK_PLL5_DIV4, 0x87c), DEF_DIV6P1("canfd", R8A779A0_CLK_CANFD, CLK_PLL5_DIV4, 0x878), DEF_DIV6P1("csi0", R8A779A0_CLK_CSI0, CLK_PLL5_DIV4, 0x880), + DEF_DIV6P1("dsi", R8A779A0_CLK_DSI, CLK_PLL5_DIV4, 0x884), - DEF_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), - DEF_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), + DEF_GEN4_OSC("osc", R8A779A0_CLK_OSC, CLK_EXTAL, 8), + DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1), }; static const struct mssr_mod_clk r8a779a0_mod_clks[] = { @@ -134,10 +134,14 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { DEF_MOD("avb3", 214, R8A779A0_CLK_S3D2), DEF_MOD("avb4", 215, R8A779A0_CLK_S3D2), DEF_MOD("avb5", 216, R8A779A0_CLK_S3D2), + DEF_MOD("canfd0", 328, R8A779A0_CLK_CANFD), DEF_MOD("csi40", 331, R8A779A0_CLK_CSI0), DEF_MOD("csi41", 400, R8A779A0_CLK_CSI0), DEF_MOD("csi42", 401, R8A779A0_CLK_CSI0), DEF_MOD("csi43", 402, R8A779A0_CLK_CSI0), + DEF_MOD("du", 411, R8A779A0_CLK_S3D1), + DEF_MOD("dsi0", 415, R8A779A0_CLK_DSI), + DEF_MOD("dsi1", 416, R8A779A0_CLK_DSI), DEF_MOD("fcpvd0", 508, R8A779A0_CLK_S3D1), DEF_MOD("fcpvd1", 509, R8A779A0_CLK_S3D1), DEF_MOD("hscif0", 514, R8A779A0_CLK_S1D2), @@ -151,12 +155,17 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { DEF_MOD("i2c4", 522, R8A779A0_CLK_S1D4), DEF_MOD("i2c5", 523, R8A779A0_CLK_S1D4), DEF_MOD("i2c6", 524, R8A779A0_CLK_S1D4), + DEF_MOD("ispcs0", 612, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs1", 613, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs2", 614, R8A779A0_CLK_S1D1), + DEF_MOD("ispcs3", 615, R8A779A0_CLK_S1D1), DEF_MOD("msi0", 618, R8A779A0_CLK_MSO), DEF_MOD("msi1", 619, R8A779A0_CLK_MSO), DEF_MOD("msi2", 620, R8A779A0_CLK_MSO), DEF_MOD("msi3", 621, R8A779A0_CLK_MSO), DEF_MOD("msi4", 622, R8A779A0_CLK_MSO), DEF_MOD("msi5", 623, R8A779A0_CLK_MSO), + DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2), DEF_MOD("scif0", 702, R8A779A0_CLK_S1D8), DEF_MOD("scif1", 703, R8A779A0_CLK_S1D8), DEF_MOD("scif3", 704, R8A779A0_CLK_S1D8), @@ -164,6 +173,12 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { DEF_MOD("sdhi0", 706, R8A779A0_CLK_SD0), DEF_MOD("sydm1", 709, R8A779A0_CLK_S1D2), DEF_MOD("sydm2", 710, R8A779A0_CLK_S1D2), + DEF_MOD("tmu0", 713, R8A779A0_CLK_CL16MCK), + DEF_MOD("tmu1", 714, R8A779A0_CLK_S1D4), + DEF_MOD("tmu2", 715, R8A779A0_CLK_S1D4), + DEF_MOD("tmu3", 716, R8A779A0_CLK_S1D4), + DEF_MOD("tmu4", 717, R8A779A0_CLK_S1D4), + DEF_MOD("tpu0", 718, R8A779A0_CLK_S1D8), DEF_MOD("vin00", 730, R8A779A0_CLK_S1D1), DEF_MOD("vin01", 731, R8A779A0_CLK_S1D1), DEF_MOD("vin02", 800, R8A779A0_CLK_S1D1), @@ -199,10 +214,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = { DEF_MOD("vspd0", 830, R8A779A0_CLK_S3D1), DEF_MOD("vspd1", 831, R8A779A0_CLK_S3D1), DEF_MOD("rwdt", 907, R8A779A0_CLK_R), + DEF_MOD("cmt0", 910, R8A779A0_CLK_R), + DEF_MOD("cmt1", 911, R8A779A0_CLK_R), + DEF_MOD("cmt2", 912, R8A779A0_CLK_R), + DEF_MOD("cmt3", 913, R8A779A0_CLK_R), DEF_MOD("pfc0", 915, R8A779A0_CLK_CP), DEF_MOD("pfc1", 916, R8A779A0_CLK_CP), DEF_MOD("pfc2", 917, R8A779A0_CLK_CP), DEF_MOD("pfc3", 918, R8A779A0_CLK_CP), + DEF_MOD("tsc", 919, R8A779A0_CLK_CL16MCK), DEF_MOD("vspx0", 1028, R8A779A0_CLK_S1D1), DEF_MOD("vspx1", 1029, R8A779A0_CLK_S1D1), DEF_MOD("vspx2", 1030, R8A779A0_CLK_S1D1), @@ -281,7 +301,7 @@ static const struct cpg_mssr_info r8a779a0_cpg_mssr_info = { .reg_layout = CLK_REG_LAYOUT_RCAR_V3U, }; -static const struct udevice_id r8a779a0_clk_ids[] = { +static const struct udevice_id r8a779a0_cpg_ids[] = { { .compatible = "renesas,r8a779a0-cpg-mssr", .data = (ulong)&r8a779a0_cpg_mssr_info @@ -289,12 +309,9 @@ static const struct udevice_id r8a779a0_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_r8a779a0) = { - .name = "clk_r8a779a0", - .id = UCLASS_CLK, - .of_match = r8a779a0_clk_ids, - .priv_auto = sizeof(struct gen3_clk_priv), - .ops = &gen3_clk_ops, - .probe = gen3_clk_probe, - .remove = gen3_clk_remove, +U_BOOT_DRIVER(cpg_r8a779a0) = { + .name = "cpg_r8a779a0", + .id = UCLASS_NOP, + .of_match = r8a779a0_cpg_ids, + .bind = gen3_cpg_bind, }; diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c new file mode 100644 index 0000000000..a2fca660a8 --- /dev/null +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Renesas RCar Gen3 CPG MSSR driver + * + * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com> + * + * Based on the following driver from Linux kernel: + * r8a7796 Clock Pulse Generator / Module Standby and Software Reset + * + * Copyright (C) 2016 Glider bvba + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wait_bit.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +#include "renesas-cpg-mssr.h" +#include "rcar-gen3-cpg.h" +#include "rcar-cpg-lib.h" + +#define SDnSRCFC_SHIFT 2 +#define STPnHCK_TABLE (CPG_SDCKCR_STPnHCK >> SDnSRCFC_SHIFT) + +/* Non-constant mask variant of FIELD_GET/FIELD_PREP */ +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +static const struct clk_div_table cpg_sdh_div_table[] = { + { 0, 1 }, { 1, 2 }, { STPnHCK_TABLE | 2, 4 }, { STPnHCK_TABLE | 3, 8 }, + { STPnHCK_TABLE | 4, 16 }, { 0, 0 }, +}; + +static const struct clk_div_table cpg_sd_div_table[] = { + { 0, 2 }, { 1, 4 }, { 0, 0 }, +}; + +static const struct clk_div_table cpg_rpc_div_table[] = { + { 1, 2 }, { 3, 4 }, { 5, 6 }, { 7, 8 }, { 0, 0 }, +}; + +static unsigned int rcar_clk_get_table_div(const struct clk_div_table *table, + const u32 value) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->val == value) + return clkt->div; + return 0; +} + +static int rcar_clk_get_table_val(const struct clk_div_table *table, + unsigned int div) +{ + const struct clk_div_table *clkt; + + for (clkt = table; clkt->div; clkt++) + if (clkt->div == div) + return clkt->val; + return -EINVAL; +} + +s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate, + void __iomem *reg, const u32 mask, + const struct clk_div_table *table, char *name) +{ + u32 value, div; + u64 rate; + + value = field_get(mask, readl(reg)); + div = rcar_clk_get_table_div(table, value); + if (!div) + return -EINVAL; + + rate = parent_rate / div; + debug("%s[%i] %s clk: parent=%i div=%u => rate=%llu\n", + __func__, __LINE__, name, parent, div, rate); + + return rate; +} + +int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg, const u32 mask, + const struct clk_div_table *table, char *name) +{ + u32 value = 0, div = 0; + + div = DIV_ROUND_CLOSEST(parent_rate, rate); + value = rcar_clk_get_table_val(table, div); + if (value < 0) + return value; + + clrsetbits_le32(reg, mask, field_prep(mask, value)); + + debug("%s[%i] %s clk: parent=%i div=%u rate=%lu => val=%u\n", + __func__, __LINE__, name, parent, div, rate, value); + + return 0; +} + +s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg) +{ + return rcar_clk_get_rate64_div_table(parent, parent_rate, reg, + CPG_RPCCKCR_DIV_PRE_MASK, + cpg_rpc_div_table, "RPC"); +} + +u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate) +{ + u64 rate = 0; + + rate = parent_rate / 2; + debug("%s[%i] RPCD2 clk: parent=%i => rate=%llu\n", + __func__, __LINE__, parent, rate); + + return rate; +} + +s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg) +{ + /* + * This takes STPnHCK and STPnCK bits into consideration + * in the table look up too, hence the inobvious GENMASK + * below. Bits [7:5] always read zero, so this is OKish. + */ + return rcar_clk_get_rate64_div_table(parent, parent_rate, reg, + CPG_SDCKCR_SRCFC_MASK | + GENMASK(9, 5), + cpg_sdh_div_table, "SDH"); +} + +s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg) +{ + return rcar_clk_get_rate64_div_table(parent, parent_rate, reg, + CPG_SDCKCR_FC_MASK, + cpg_sd_div_table, "SD"); +} + +int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg) +{ + /* + * This takes STPnHCK and STPnCK bits into consideration + * in the table look up too, hence the inobvious GENMASK + * below. Bits [7:5] always read zero, so this is OKish. + */ + return rcar_clk_set_rate64_div_table(parent, parent_rate, rate, reg, + CPG_SDCKCR_SRCFC_MASK | + GENMASK(9, 5), + cpg_sdh_div_table, "SDH"); +} + +int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg) +{ + return rcar_clk_set_rate64_div_table(parent, parent_rate, rate, reg, + CPG_SDCKCR_FC_MASK, + cpg_sd_div_table, "SD"); +} diff --git a/drivers/clk/renesas/rcar-cpg-lib.h b/drivers/clk/renesas/rcar-cpg-lib.h new file mode 100644 index 0000000000..09b3e50918 --- /dev/null +++ b/drivers/clk/renesas/rcar-cpg-lib.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R-Car Gen3 Clock Pulse Generator Library + * + * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2019 Renesas Electronics Corp. + * + * Based on clk-rcar-gen3.c + * + * Copyright (C) 2015 Renesas Electronics Corp. + */ + +#ifndef __CLK_RENESAS_RCAR_CPG_LIB_H__ +#define __CLK_RENESAS_RCAR_CPG_LIB_H__ + +s64 rcar_clk_get_rate64_div_table(unsigned int parent, u64 parent_rate, + void __iomem *reg, const u32 mask, + const struct clk_div_table *table, char *name); + +int rcar_clk_set_rate64_div_table(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg, const u32 mask, + const struct clk_div_table *table, char *name); + +s64 rcar_clk_get_rate64_sdh(unsigned int parent, u64 parent_rate, void __iomem *reg); +s64 rcar_clk_get_rate64_sd(unsigned int parent, u64 parent_rate, void __iomem *reg); +s64 rcar_clk_get_rate64_rpc(unsigned int parent, u64 parent_rate, void __iomem *reg); +u64 rcar_clk_get_rate64_rpcd2(unsigned int parent, u64 parent_rate); +int rcar_clk_set_rate64_sdh(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg); +int rcar_clk_set_rate64_sd(unsigned int parent, u64 parent_rate, ulong rate, + void __iomem *reg); + +#endif diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 7bf5701361..200e4adb90 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -17,35 +17,44 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_PLL2, CLK_TYPE_GEN3_PLL3, CLK_TYPE_GEN3_PLL4, + CLK_TYPE_GEN3_SDH, + CLK_TYPE_R8A77970_SD0H, CLK_TYPE_GEN3_SD, + CLK_TYPE_R8A77970_SD0, CLK_TYPE_GEN3_R, CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ CLK_TYPE_GEN3_Z, CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_D3_RPCSRC, CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, - CLK_TYPE_R8A779A0_MAIN, - CLK_TYPE_R8A779A0_PLL1, - CLK_TYPE_R8A779A0_PLL2X_3X, /* PLL[23][01] */ - CLK_TYPE_R8A779A0_PLL5, - CLK_TYPE_R8A779A0_SD, - CLK_TYPE_R8A779A0_MDSEL, /* Select parent/divider using mode pin */ - CLK_TYPE_R8A779A0_OSC, /* OSC EXTAL predivider and fixed divider */ + CLK_TYPE_GEN4_MAIN, + CLK_TYPE_GEN4_PLL1, + CLK_TYPE_GEN4_PLL2X_3X, /* PLL[23][01] */ + CLK_TYPE_GEN4_PLL5, + CLK_TYPE_GEN4_SDH, + CLK_TYPE_GEN4_SD, + CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ + CLK_TYPE_GEN4_Z, + CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ + CLK_TYPE_GEN4_RPCSRC, + CLK_TYPE_GEN4_RPC, + CLK_TYPE_GEN4_RPCD2, /* SoC specific definitions start here */ CLK_TYPE_GEN3_SOC_BASE, }; +#define DEF_GEN3_SDH(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_SDH, _parent, .offset = _offset) + #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) -#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \ - DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset) - #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \ (_parent0) << 16 | (_parent1), \ @@ -66,10 +75,31 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) +#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \ + (_parent0) << 16 | (_parent1), .div = 5) + #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ (_parent0) << 16 | (_parent1), .div = 8) +#define DEF_GEN4_SDH(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SDH, _parent, .offset = _offset) + +#define DEF_GEN4_SD(_name, _id, _parent, _offset) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_SD, _parent, .offset = _offset) + +#define DEF_GEN4_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_MDSEL, \ + (_parent0) << 16 | (_parent1), \ + .div = (_div0) << 16 | (_div1), .offset = _md) + +#define DEF_GEN4_OSC(_name, _id, _parent, _div) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_OSC, _parent, .div = _div) + +#define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult; @@ -83,7 +113,18 @@ struct rcar_gen3_cpg_pll_config { #define CPG_RST_MODEMR 0x060 +#define CPG_SDCKCR_STPnHCK BIT(9) +#define CPG_SDCKCR_STPnCK BIT(8) +#define CPG_SDCKCR_SRCFC_MASK GENMASK(4, 2) +#define CPG_SDCKCR_FC_MASK GENMASK(1, 0) +/* V3M specifics */ +#define CPG_SDCKCR_SDHFC_MASK GENMASK(11, 8) +#define CPG_SDCKCR_SD0FC_MASK GENMASK(7, 4) + #define CPG_RPCCKCR 0x238 +#define CPG_RPCCKCR_DIV_POST_MASK GENMASK(4, 3) +#define CPG_RPCCKCR_DIV_PRE_MASK GENMASK(2, 0) + #define CPG_RCKCR 0x240 struct gen3_clk_priv { @@ -95,8 +136,7 @@ struct gen3_clk_priv { const struct rcar_gen3_cpg_pll_config *cpg_pll_config; }; -int gen3_clk_probe(struct udevice *dev); -int gen3_clk_remove(struct udevice *dev); +int gen3_cpg_bind(struct udevice *parent); extern const struct clk_ops gen3_clk_ops; diff --git a/drivers/core/device.c b/drivers/core/device.c index d9ce546c0c..6e26b64fb8 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -654,7 +654,8 @@ void *dev_get_priv(const struct udevice *dev) return dm_priv_to_rw(dev->priv_); } -void *dev_get_uclass_priv(const struct udevice *dev) +/* notrace is needed as this is called by timer_get_rate() */ +notrace void *dev_get_uclass_priv(const struct udevice *dev) { if (!dev) { dm_warn("%s: null device\n", __func__); diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index 4d56b1a767..d08578e9c4 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -991,6 +991,53 @@ int ofnode_decode_display_timing(ofnode parent, int index, return ret; } +int ofnode_decode_panel_timing(ofnode parent, + struct display_timing *dt) +{ + ofnode timings; + u32 val = 0; + int ret = 0; + + timings = ofnode_find_subnode(parent, "panel-timings"); + if (!ofnode_valid(timings)) + return -EINVAL; + memset(dt, 0, sizeof(*dt)); + ret |= decode_timing_property(timings, "hback-porch", &dt->hback_porch); + ret |= decode_timing_property(timings, "hfront-porch", &dt->hfront_porch); + ret |= decode_timing_property(timings, "hactive", &dt->hactive); + ret |= decode_timing_property(timings, "hsync-len", &dt->hsync_len); + ret |= decode_timing_property(timings, "vback-porch", &dt->vback_porch); + ret |= decode_timing_property(timings, "vfront-porch", &dt->vfront_porch); + ret |= decode_timing_property(timings, "vactive", &dt->vactive); + ret |= decode_timing_property(timings, "vsync-len", &dt->vsync_len); + ret |= decode_timing_property(timings, "clock-frequency", &dt->pixelclock); + dt->flags = 0; + if (!ofnode_read_u32(timings, "vsync-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_VSYNC_HIGH : + DISPLAY_FLAGS_VSYNC_LOW; + } + if (!ofnode_read_u32(timings, "hsync-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_HSYNC_HIGH : + DISPLAY_FLAGS_HSYNC_LOW; + } + if (!ofnode_read_u32(timings, "de-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_DE_HIGH : + DISPLAY_FLAGS_DE_LOW; + } + if (!ofnode_read_u32(timings, "pixelclk-active", &val)) { + dt->flags |= val ? DISPLAY_FLAGS_PIXDATA_POSEDGE : + DISPLAY_FLAGS_PIXDATA_NEGEDGE; + } + if (ofnode_read_bool(timings, "interlaced")) + dt->flags |= DISPLAY_FLAGS_INTERLACED; + if (ofnode_read_bool(timings, "doublescan")) + dt->flags |= DISPLAY_FLAGS_DOUBLESCAN; + if (ofnode_read_bool(timings, "doubleclk")) + dt->flags |= DISPLAY_FLAGS_DOUBLECLK; + + return ret; +} + const void *ofnode_get_property(ofnode node, const char *propname, int *lenp) { if (ofnode_is_np(node)) diff --git a/drivers/core/read.c b/drivers/core/read.c index 3e5fea87d8..e0543bbad5 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -420,6 +420,12 @@ int dev_decode_display_timing(const struct udevice *dev, int index, return ofnode_decode_display_timing(dev_ofnode(dev), index, config); } +int dev_decode_panel_timing(const struct udevice *dev, + struct display_timing *config) +{ + return ofnode_decode_panel_timing(dev_ofnode(dev), config); +} + ofnode dev_get_phy_node(const struct udevice *dev) { return ofnode_get_phy_node(dev_ofnode(dev)); diff --git a/drivers/crypto/aspeed/aspeed_hace.c b/drivers/crypto/aspeed/aspeed_hace.c index a1b0b9f564..6b6c8fa658 100644 --- a/drivers/crypto/aspeed/aspeed_hace.c +++ b/drivers/crypto/aspeed/aspeed_hace.c @@ -288,7 +288,7 @@ static int aspeed_hace_digest_wd(struct udevice *dev, enum HASH_ALGO algo, if (rc) return rc; - if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { + if (IS_ENABLED(CONFIG_HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { cur = ibuf; end = ibuf + ilen; diff --git a/drivers/crypto/hash/hash_sw.c b/drivers/crypto/hash/hash_sw.c index 553c068010..d8065d68ea 100644 --- a/drivers/crypto/hash/hash_sw.c +++ b/drivers/crypto/hash/hash_sw.c @@ -244,7 +244,7 @@ static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo, if (rc) return rc; - if (CONFIG_IS_ENABLED(HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { + if (IS_ENABLED(CONFIG_HW_WATCHDOG) || CONFIG_IS_ENABLED(WATCHDOG)) { cur = ibuf; end = ibuf + ilen; diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index b852c870f9..6a8b6be42b 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -112,6 +112,7 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_disable_bypass(); break; case 3733: + case 3732: dram_pll_init(MHZ(933)); dram_disable_bypass(); break; diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c index 67a9479828..71cfaec6e9 100644 --- a/drivers/fastboot/fb_command.c +++ b/drivers/fastboot/fb_command.c @@ -295,11 +295,11 @@ void fastboot_data_complete(char *response) */ static void __maybe_unused flash(char *cmd_parameter, char *response) { - if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)) + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr, image_size, response); - if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)) + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size, response); } @@ -315,10 +315,10 @@ static void __maybe_unused flash(char *cmd_parameter, char *response) */ static void __maybe_unused erase(char *cmd_parameter, char *response) { - if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)) + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) fastboot_mmc_erase(cmd_parameter, response); - if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)) + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) fastboot_nand_erase(cmd_parameter, response); } diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 7563650d07..57b6182c46 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -99,7 +99,7 @@ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) const int mmc_dev = config_opt_enabled(CONFIG_FASTBOOT_FLASH_MMC, CONFIG_FASTBOOT_FLASH_MMC_DEV, -1); - if (!CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)) + if (!IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) return -EINVAL; if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c index 2fbd285db3..dd3475e0a8 100644 --- a/drivers/fastboot/fb_getvar.c +++ b/drivers/fastboot/fb_getvar.c @@ -57,17 +57,17 @@ static const struct { }, { .variable = "current-slot", .dispatch = getvar_current_slot -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) +#if IS_ENABLED(CONFIG_FASTBOOT_FLASH) }, { .variable = "has-slot", .dispatch = getvar_has_slot #endif -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC) +#if IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC) }, { .variable = "partition-type", .dispatch = getvar_partition_type #endif -#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) +#if IS_ENABLED(CONFIG_FASTBOOT_FLASH) }, { .variable = "partition-size", .dispatch = getvar_partition_size @@ -99,12 +99,12 @@ static int getvar_get_part_info(const char *part_name, char *response, struct disk_partition disk_part; struct part_info *part_info; - if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)) { + if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_MMC)) { r = fastboot_mmc_get_part_info(part_name, &dev_desc, &disk_part, response); if (r >= 0 && size) *size = disk_part.size * disk_part.blksz; - } else if (CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)) { + } else if (IS_ENABLED(CONFIG_FASTBOOT_FLASH_NAND)) { r = fastboot_nand_get_part_info(part_name, &part_info, response); if (r >= 0 && size) *size = part_info->size; diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 033c510bc0..a06c590234 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -588,7 +588,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, } #endif -#if CONFIG_IS_ENABLED(FASTBOOT_MMC_USER_SUPPORT) +#if IS_ENABLED(CONFIG_FASTBOOT_MMC_USER_SUPPORT) if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { dev_desc = fastboot_mmc_get_dev(response); if (!dev_desc) diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 4113de230c..61490d6d8d 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -21,6 +21,12 @@ config FPGA_SOCFPGA This provides common functionality for Gen5 and Arria10 devices. +config FPGA_STRATIX_II + bool "Enable Stratix II FPGA drivers" + depends on FPGA_ALTERA + help + Say Y here to enable the Altera Stratix II FPGA-specific driver. + config FPGA_STRATIX_V bool "Enable Stratix V FPGA drivers" depends on FPGA_ALTERA @@ -54,6 +60,12 @@ config FPGA_INTEL_SDM_MAILBOX Enable FPGA driver for writing full bitstream into Intel FPGA devices through SDM (Secure Device Manager) Mailbox. +config FPGA_LATTICE + bool "Enable Lattice FPGA driver" + help + This is used for the lattice FPGAs. Please check the source code as + there is no documentation for this at present. + config FPGA_XILINX bool "Enable Xilinx FPGA drivers" select FPGA diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index baceb54d31..1e81e36962 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -23,13 +23,11 @@ obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_INTEL_BROADWELL_GPIO) += intel_broadwell_gpio.o obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o -obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_NPCM_GPIO) += npcm_gpio.o obj-$(CONFIG_PCA953X) += pca953x.o -obj-$(CONFIG_PCA9698) += pca9698.o obj-$(CONFIG_ROCKCHIP_GPIO) += rk_gpio.o obj-$(CONFIG_RCAR_GPIO) += gpio-rcar.o obj-$(CONFIG_RZA1_GPIO) += gpio-rza1.o @@ -38,9 +36,7 @@ obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o sandbox_test.o obj-$(CONFIG_TEGRA_GPIO) += tegra_gpio.o obj-$(CONFIG_TEGRA186_GPIO) += tegra186_gpio.o obj-$(CONFIG_DA8XX_GPIO) += da8xx_gpio.o -obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o -obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o obj-$(CONFIG_MPC8XX_GPIO) += mpc8xx_gpio.o obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o @@ -48,7 +44,6 @@ obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o obj-$(CONFIG_XILINX_GPIO) += xilinx_gpio.o -obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o diff --git a/drivers/gpio/adi_gpio2.c b/drivers/gpio/adi_gpio2.c deleted file mode 100644 index d0849c85c3..0000000000 --- a/drivers/gpio/adi_gpio2.c +++ /dev/null @@ -1,425 +0,0 @@ -/* - * ADI GPIO2 Abstraction Layer - * Support BF54x, BF60x and future processors. - * - * Copyright 2008-2013 Analog Devices Inc. - * - * Licensed under the GPL-2 or later - */ - -#include <common.h> -#include <malloc.h> -#include <linux/bug.h> -#include <linux/errno.h> -#include <asm/gpio.h> - -#define RESOURCE_LABEL_SIZE 16 - -static struct str_ident { - char name[RESOURCE_LABEL_SIZE]; -} str_ident[MAX_RESOURCES]; - -static void gpio_error(unsigned gpio) -{ - printf("adi_gpio2: GPIO %d wasn't requested!\n", gpio); -} - -static void set_label(unsigned short ident, const char *label) -{ - if (label) { - strncpy(str_ident[ident].name, label, - RESOURCE_LABEL_SIZE); - str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0; - } -} - -static char *get_label(unsigned short ident) -{ - return *str_ident[ident].name ? str_ident[ident].name : "UNKNOWN"; -} - -static int cmp_label(unsigned short ident, const char *label) -{ - if (label == NULL) - printf("adi_gpio2: please provide none-null label\n"); - - if (label) - return strcmp(str_ident[ident].name, label); - else - return -EINVAL; -} - -#define map_entry(m, i) reserved_##m##_map[gpio_bank(i)] -#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i)) -#define reserve(m, i) (map_entry(m, i) |= gpio_bit(i)) -#define unreserve(m, i) (map_entry(m, i) &= ~gpio_bit(i)) -#define DECLARE_RESERVED_MAP(m, c) unsigned short reserved_##m##_map[c] - -static DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM); -static DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES)); - -inline int check_gpio(unsigned gpio) -{ -#if defined(CONFIG_BF54x) - if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 || - gpio == GPIO_PH14 || gpio == GPIO_PH15 || - gpio == GPIO_PJ14 || gpio == GPIO_PJ15) - return -EINVAL; -#endif - if (gpio >= MAX_GPIOS) - return -EINVAL; - return 0; -} - -static void port_setup(unsigned gpio, unsigned short usage) -{ -#if defined(CONFIG_BF54x) - if (usage == GPIO_USAGE) - gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->port_fer |= gpio_bit(gpio); -#else - if (usage == GPIO_USAGE) - gpio_array[gpio_bank(gpio)]->port_fer_clear = gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->port_fer_set = gpio_bit(gpio); -#endif -} - -inline void portmux_setup(unsigned short per) -{ - u32 pmux; - u16 ident = P_IDENT(per); - u16 function = P_FUNCT2MUX(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - - pmux &= ~(0x3 << (2 * gpio_sub_n(ident))); - pmux |= (function & 0x3) << (2 * gpio_sub_n(ident)); - - gpio_array[gpio_bank(ident)]->port_mux = pmux; -} - -inline u16 get_portmux(unsigned short per) -{ - u32 pmux; - u16 ident = P_IDENT(per); - - pmux = gpio_array[gpio_bank(ident)]->port_mux; - - return pmux >> (2 * gpio_sub_n(ident)) & 0x3; -} - -unsigned short get_gpio_dir(unsigned gpio) -{ - return 0x01 & - (gpio_array[gpio_bank(gpio)]->dir_clear >> gpio_sub_n(gpio)); -} - -/*********************************************************** -* -* FUNCTIONS: Peripheral Resource Allocation -* and PortMux Setup -* -* INPUTS/OUTPUTS: -* per Peripheral Identifier -* label String -* -* DESCRIPTION: Peripheral Resource Allocation and Setup API -**************************************************************/ - -int peripheral_request(unsigned short per, const char *label) -{ - unsigned short ident = P_IDENT(per); - - /* - * Don't cares are pins with only one dedicated function - */ - - if (per & P_DONTCARE) - return 0; - - if (!(per & P_DEFINED)) - return -EINVAL; - - BUG_ON(ident >= MAX_RESOURCES); - - /* If a pin can be muxed as either GPIO or peripheral, make - * sure it is not already a GPIO pin when we request it. - */ - if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) { - printf("%s: Peripheral %d is already reserved as GPIO by %s!\n", - __func__, ident, get_label(ident)); - return -EBUSY; - } - - if (unlikely(is_reserved(peri, ident, 1))) { - /* - * Pin functions like AMC address strobes my - * be requested and used by several drivers - */ - - if (!((per & P_MAYSHARE) && - get_portmux(per) == P_FUNCT2MUX(per))) { - /* - * Allow that the identical pin function can - * be requested from the same driver twice - */ - - if (cmp_label(ident, label) == 0) - goto anyway; - - printf("%s: Peripheral %d function %d is already " - "reserved by %s!\n", __func__, ident, - P_FUNCT2MUX(per), get_label(ident)); - return -EBUSY; - } - } - - anyway: - reserve(peri, ident); - - portmux_setup(per); - port_setup(ident, PERIPHERAL_USAGE); - - set_label(ident, label); - - return 0; -} - -int peripheral_request_list(const unsigned short per[], const char *label) -{ - u16 cnt; - int ret; - - for (cnt = 0; per[cnt] != 0; cnt++) { - ret = peripheral_request(per[cnt], label); - - if (ret < 0) { - for (; cnt > 0; cnt--) - peripheral_free(per[cnt - 1]); - - return ret; - } - } - - return 0; -} - -void peripheral_free(unsigned short per) -{ - unsigned short ident = P_IDENT(per); - - if (per & P_DONTCARE) - return; - - if (!(per & P_DEFINED)) - return; - - if (unlikely(!is_reserved(peri, ident, 0))) - return; - - if (!(per & P_MAYSHARE)) - port_setup(ident, GPIO_USAGE); - - unreserve(peri, ident); - - set_label(ident, "free"); -} - -void peripheral_free_list(const unsigned short per[]) -{ - u16 cnt; - for (cnt = 0; per[cnt] != 0; cnt++) - peripheral_free(per[cnt]); -} - -/*********************************************************** -* -* FUNCTIONS: GPIO Driver -* -* INPUTS/OUTPUTS: -* gpio PIO Number between 0 and MAX_GPIOS -* label String -* -* DESCRIPTION: GPIO Driver API -**************************************************************/ - -int gpio_request(unsigned gpio, const char *label) -{ - if (check_gpio(gpio) < 0) - return -EINVAL; - - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) - return 0; - - if (unlikely(is_reserved(gpio, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved by %s!\n", - gpio, get_label(gpio)); - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved as Peripheral " - "by %s!\n", gpio, get_label(gpio)); - return -EBUSY; - } - - reserve(gpio, gpio); - set_label(gpio, label); - - port_setup(gpio, GPIO_USAGE); - - return 0; -} - -int gpio_free(unsigned gpio) -{ - if (check_gpio(gpio) < 0) - return -1; - - if (unlikely(!is_reserved(gpio, gpio, 0))) { - gpio_error(gpio); - return -1; - } - - unreserve(gpio, gpio); - - set_label(gpio, "free"); - - return 0; -} - -#ifdef ADI_SPECIAL_GPIO_BANKS -static DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES)); - -int special_gpio_request(unsigned gpio, const char *label) -{ - /* - * Allow that the identical GPIO can - * be requested from the same driver twice - * Do nothing and return - - */ - - if (cmp_label(gpio, label) == 0) - return 0; - - if (unlikely(is_reserved(special_gpio, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved by %s!\n", - gpio, get_label(gpio)); - return -EBUSY; - } - if (unlikely(is_reserved(peri, gpio, 1))) { - printf("adi_gpio2: GPIO %d is already reserved as Peripheral " - "by %s!\n", gpio, get_label(gpio)); - - return -EBUSY; - } - - reserve(special_gpio, gpio); - reserve(peri, gpio); - - set_label(gpio, label); - port_setup(gpio, GPIO_USAGE); - - return 0; -} - -void special_gpio_free(unsigned gpio) -{ - if (unlikely(!is_reserved(special_gpio, gpio, 0))) { - gpio_error(gpio); - return; - } - - unreserve(special_gpio, gpio); - unreserve(peri, gpio); - set_label(gpio, "free"); -} -#endif - -static inline void __gpio_direction_input(unsigned gpio) -{ - gpio_array[gpio_bank(gpio)]->dir_clear = gpio_bit(gpio); -#if defined(CONFIG_BF54x) - gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio); -#else - gpio_array[gpio_bank(gpio)]->inen_set = gpio_bit(gpio); -#endif -} - -int gpio_direction_input(unsigned gpio) -{ - unsigned long flags; - - if (!is_reserved(gpio, gpio, 0)) { - gpio_error(gpio); - return -EINVAL; - } - - local_irq_save(flags); - __gpio_direction_input(gpio); - local_irq_restore(flags); - - return 0; -} - -int gpio_set_value(unsigned gpio, int arg) -{ - if (arg) - gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio); - else - gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - unsigned long flags; - - if (!is_reserved(gpio, gpio, 0)) { - gpio_error(gpio); - return -EINVAL; - } - - local_irq_save(flags); - -#if defined(CONFIG_BF54x) - gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio); -#else - gpio_array[gpio_bank(gpio)]->inen_clear = gpio_bit(gpio); -#endif - gpio_set_value(gpio, value); - gpio_array[gpio_bank(gpio)]->dir_set = gpio_bit(gpio); - - local_irq_restore(flags); - - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - return 1 & (gpio_array[gpio_bank(gpio)]->data >> gpio_sub_n(gpio)); -} - -void gpio_labels(void) -{ - int c, gpio; - - for (c = 0; c < MAX_RESOURCES; c++) { - gpio = is_reserved(gpio, c, 1); - if (!check_gpio(c) && gpio) - printf("GPIO_%d:\t%s\tGPIO %s\n", c, get_label(c), - get_gpio_dir(c) ? "OUTPUT" : "INPUT"); - else if (is_reserved(peri, c, 1)) - printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c)); - else - continue; - } -} diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c deleted file mode 100644 index 29791882a3..0000000000 --- a/drivers/gpio/kona_gpio.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#include <common.h> -#include <malloc.h> -#include <asm/io.h> -#include <asm/arch/sysmap.h> - -#define GPIO_BASE (void *)GPIO2_BASE_ADDR - -#define GPIO_PASSWD 0x00a5a501 -#define GPIO_PER_BANK 32 -#define GPIO_MAX_BANK_NUM 8 - -#define GPIO_BANK(gpio) ((gpio) >> 5) -#define GPIO_BITMASK(gpio) \ - (1UL << ((gpio) & (GPIO_PER_BANK - 1))) - -#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) -#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) -#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) -#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) -#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) -#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) -#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) -#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) -#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) - -#define GPIO_GPPWR_OFFSET 0x00000520 - -#define GPIO_GPCTR0_DBR_SHIFT 5 -#define GPIO_GPCTR0_DBR_MASK 0x000001e0 - -#define GPIO_GPCTR0_ITR_SHIFT 3 -#define GPIO_GPCTR0_ITR_MASK 0x00000018 -#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 -#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 -#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 - -#define GPIO_GPCTR0_IOTR_MASK 0x00000001 -#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 -#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 - -int gpio_request(unsigned gpio, const char *label) -{ - unsigned int value, off; - - writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); - off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); - value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); - writel(value, GPIO_BASE + off); - - return 0; -} - -int gpio_free(unsigned gpio) -{ - unsigned int value, off; - - writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); - off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); - value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); - writel(value, GPIO_BASE + off); - - return 0; -} - -int gpio_direction_input(unsigned gpio) -{ - u32 val; - - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= ~GPIO_GPCTR0_IOTR_MASK; - val |= GPIO_GPCTR0_IOTR_CMD_INPUT; - writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); - - return 0; -} - -int gpio_direction_output(unsigned gpio, int value) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= ~GPIO_GPCTR0_IOTR_MASK; - val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; - writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); - off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); - - val = readl(GPIO_BASE + off); - val |= bitmask; - writel(val, GPIO_BASE + off); - - return 0; -} - -int gpio_get_value(unsigned gpio) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - /* determine the GPIO pin direction */ - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= GPIO_GPCTR0_IOTR_MASK; - - /* read the GPIO bank status */ - off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? - GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); - val = readl(GPIO_BASE + off); - - /* return the specified bit status */ - return !!(val & bitmask); -} - -void gpio_set_value(unsigned gpio, int value) -{ - int bank_id = GPIO_BANK(gpio); - int bitmask = GPIO_BITMASK(gpio); - u32 val, off; - - /* determine the GPIO pin direction */ - val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); - val &= GPIO_GPCTR0_IOTR_MASK; - - /* this function only applies to output pin */ - if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { - printf("%s: Cannot set an input pin %d\n", __func__, gpio); - return; - } - - off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); - - val = readl(GPIO_BASE + off); - val |= bitmask; - writel(val, GPIO_BASE + off); -} diff --git a/drivers/gpio/mpc83xx_gpio.c b/drivers/gpio/mpc83xx_gpio.c deleted file mode 100644 index bf693c8d45..0000000000 --- a/drivers/gpio/mpc83xx_gpio.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale MPC83xx GPIO handling. - */ - -#include <common.h> -#include <malloc.h> -#include <mpc83xx.h> -#include <asm/gpio.h> -#include <asm/io.h> - -#ifndef CFG_MPC83XX_GPIO_0_INIT_DIRECTION -#define CFG_MPC83XX_GPIO_0_INIT_DIRECTION 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_DIRECTION -#define CFG_MPC83XX_GPIO_1_INIT_DIRECTION 0 -#endif -#ifndef CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN -#define CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN -#define CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN 0 -#endif -#ifndef CFG_MPC83XX_GPIO_0_INIT_VALUE -#define CFG_MPC83XX_GPIO_0_INIT_VALUE 0 -#endif -#ifndef CFG_MPC83XX_GPIO_1_INIT_VALUE -#define CFG_MPC83XX_GPIO_1_INIT_VALUE 0 -#endif - -static unsigned int gpio_output_value[MPC83XX_GPIO_CTRLRS]; - -/* - * Generic_GPIO primitives. - */ - -int gpio_request(unsigned gpio, const char *label) -{ - if (gpio >= MAX_NUM_GPIOS) - return -1; - - return 0; -} - -int gpio_free(unsigned gpio) -{ - /* Do not set to input */ - return 0; -} - -/* set GPIO pin 'gpio' as an input */ -int gpio_direction_input(unsigned gpio) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - clrbits_be32(&im->gpio[ctrlr].dir, line_mask); - - return 0; -} - -/* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gpio, int value) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - if (value != 0 && value != 1) { - printf("Error: Value parameter must be 0 or 1.\n"); - return -1; - } - - gpio_set_value(gpio, value); - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Make the line output */ - setbits_be32(&im->gpio[ctrlr].dir, line_mask); - - return 0; -} - -/* read GPIO IN value of pin 'gpio' */ -int gpio_get_value(unsigned gpio) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Read the value and mask off the bit */ - return (in_be32(&im->gpio[ctrlr].dat) & line_mask) != 0; -} - -/* write GPIO OUT value to pin 'gpio' */ -int gpio_set_value(unsigned gpio, int value) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - unsigned int ctrlr; - unsigned int line; - unsigned int line_mask; - - if (value != 0 && value != 1) { - printf("Error: Value parameter must be 0 or 1.\n"); - return -1; - } - - /* 32-bits per controller */ - ctrlr = gpio >> 5; - line = gpio & (0x1F); - - /* Big endian */ - line_mask = 1 << (31 - line); - - /* Update the local output buffer soft copy */ - gpio_output_value[ctrlr] = - (gpio_output_value[ctrlr] & ~line_mask) | \ - (value ? line_mask : 0); - - /* Write the output */ - out_be32(&im->gpio[ctrlr].dat, gpio_output_value[ctrlr]); - - return 0; -} - -/* Configure GPIO registers early */ -void mpc83xx_gpio_init_f(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - -#if MPC83XX_GPIO_CTRLRS >= 1 - out_be32(&im->gpio[0].dir, CFG_MPC83XX_GPIO_0_INIT_DIRECTION); - out_be32(&im->gpio[0].odr, CFG_MPC83XX_GPIO_0_INIT_OPEN_DRAIN); - out_be32(&im->gpio[0].dat, CFG_MPC83XX_GPIO_0_INIT_VALUE); - out_be32(&im->gpio[0].ier, 0xFFFFFFFF); /* Clear all events */ - out_be32(&im->gpio[0].imr, 0); - out_be32(&im->gpio[0].icr, 0); -#endif - -#if MPC83XX_GPIO_CTRLRS >= 2 - out_be32(&im->gpio[1].dir, CFG_MPC83XX_GPIO_1_INIT_DIRECTION); - out_be32(&im->gpio[1].odr, CFG_MPC83XX_GPIO_1_INIT_OPEN_DRAIN); - out_be32(&im->gpio[1].dat, CFG_MPC83XX_GPIO_1_INIT_VALUE); - out_be32(&im->gpio[1].ier, 0xFFFFFFFF); /* Clear all events */ - out_be32(&im->gpio[1].imr, 0); - out_be32(&im->gpio[1].icr, 0); -#endif -} - -/* Initialize GPIO soft-copies */ -void mpc83xx_gpio_init_r(void) -{ -#if MPC83XX_GPIO_CTRLRS >= 1 - gpio_output_value[0] = CFG_MPC83XX_GPIO_0_INIT_VALUE; -#endif - -#if MPC83XX_GPIO_CTRLRS >= 2 - gpio_output_value[1] = CFG_MPC83XX_GPIO_1_INIT_VALUE; -#endif -} diff --git a/drivers/gpio/pca9698.c b/drivers/gpio/pca9698.c deleted file mode 100644 index 11274c7810..0000000000 --- a/drivers/gpio/pca9698.c +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2011 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - */ - -/* - * Driver for NXP's pca9698 40 bit I2C gpio expander - */ - -#include <common.h> -#include <i2c.h> -#include <malloc.h> -#include <linux/errno.h> -#include <pca9698.h> - -/* - * The pca9698 registers - */ - -#define PCA9698_REG_INPUT 0x00 -#define PCA9698_REG_OUTPUT 0x08 -#define PCA9698_REG_POLARITY 0x10 -#define PCA9698_REG_CONFIG 0x18 - -#define PCA9698_BUFFER_SIZE 5 -#define PCA9698_GPIO_COUNT 40 - -static int pca9698_read40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_read(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static int pca9698_write40(u8 addr, u8 offset, u8 *buffer) -{ - u8 command = offset | 0x80; /* autoincrement */ - - return i2c_write(addr, command, 1, buffer, PCA9698_BUFFER_SIZE); -} - -static void pca9698_set_bit(unsigned gpio, u8 *buffer, unsigned value) -{ - unsigned byte = gpio / 8; - unsigned bit = gpio % 8; - - if (value) - buffer[byte] |= (1 << bit); - else - buffer[byte] &= ~(1 << bit); -} - -int pca9698_request(unsigned gpio, const char *label) -{ - if (gpio >= PCA9698_GPIO_COUNT) - return -EINVAL; - - return 0; -} - -void pca9698_free(unsigned gpio) -{ -} - -int pca9698_direction_input(u8 addr, unsigned gpio) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 1); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_direction_output(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_set_value(addr, gpio, value); - if (res) - return res; - - res = pca9698_read40(addr, PCA9698_REG_CONFIG, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, 0); - - return pca9698_write40(addr, PCA9698_REG_CONFIG, data); -} - -int pca9698_get_value(u8 addr, unsigned gpio) -{ - unsigned config_byte = gpio / 8; - unsigned config_bit = gpio % 8; - unsigned value; - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_INPUT, data); - if (res) - return -1; - - value = data[config_byte] & (1 << config_bit); - - return !!value; -} - -int pca9698_set_value(u8 addr, unsigned gpio, int value) -{ - u8 data[PCA9698_BUFFER_SIZE]; - int res; - - res = pca9698_read40(addr, PCA9698_REG_OUTPUT, data); - if (res) - return res; - - pca9698_set_bit(gpio, data, value); - - return pca9698_write40(addr, PCA9698_REG_OUTPUT, data); -} diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 3be1be8692..65feb453eb 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -303,9 +303,25 @@ static int qcom_pwrkey_get_value(struct udevice *dev, unsigned offset) } } +/* + * Since pmic buttons modelled as GPIO, we need empty direction functions + * to trick u-boot button driver + */ +static int qcom_pwrkey_direction_input(struct udevice *dev, unsigned int offset) +{ + return 0; +} + +static int qcom_pwrkey_direction_output(struct udevice *dev, unsigned int offset, int value) +{ + return -EOPNOTSUPP; +} + static const struct dm_gpio_ops qcom_pwrkey_ops = { .get_value = qcom_pwrkey_get_value, .get_function = qcom_pwrkey_get_function, + .direction_input = qcom_pwrkey_direction_input, + .direction_output = qcom_pwrkey_direction_output, }; static int qcom_pwrkey_probe(struct udevice *dev) diff --git a/drivers/gpio/sh_pfc.c b/drivers/gpio/sh_pfc.c index 0653171af4..988f7e9bba 100644 --- a/drivers/gpio/sh_pfc.c +++ b/drivers/gpio/sh_pfc.c @@ -125,7 +125,7 @@ static void config_reg_helper(struct pinmux_info *gpioc, *maskp = (1 << crp->var_field_width[in_pos]) - 1; *posp = crp->reg_width; for (k = 0; k <= in_pos; k++) - *posp -= crp->var_field_width[k]; + *posp -= abs(crp->var_field_width[k]); } } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 76e19918aa..427074bff8 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -580,6 +580,18 @@ config SYS_I2C_OCTEON chips have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_QUP + bool "Qualcomm QUP I2C controller" + depends on ARCH_SNAPDRAGON + help + Support for Qualcomm QUP I2C controller based on Qualcomm Universal + Peripherals (QUP) engine. The QUP engine is an advanced high + performance slave port that provides a common data path (an output + FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP + controller is publicly documented in the Snapdragon 410E (APQ8016E) + Technical Reference Manual, chapter "6.1 Qualcomm Universal + Peripherals Engine (QUP)". + config SYS_I2C_S3C24X0 bool "Samsung I2C driver" depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 920aafb91c..8a70b5ba88 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,7 +25,6 @@ obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o -obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o @@ -38,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_NPCM) += npcm_i2c.o obj-$(CONFIG_SYS_I2C_OCORES) += ocores_i2c.o obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o +obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c deleted file mode 100644 index b9b0ff1c39..0000000000 --- a/drivers/i2c/kona_i2c.c +++ /dev/null @@ -1,728 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Broadcom Corporation. - * - * NOTE: This driver should be converted to driver model before June 2017. - * Please see doc/driver-model/i2c-howto.rst for instructions. - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <asm/arch/sysmap.h> -#include <asm/kona-common/clk.h> -#include <i2c.h> - -/* Hardware register offsets and field defintions */ -#define CS_OFFSET 0x00000020 -#define CS_ACK_SHIFT 3 -#define CS_ACK_MASK 0x00000008 -#define CS_ACK_CMD_GEN_START 0x00000000 -#define CS_ACK_CMD_GEN_RESTART 0x00000001 -#define CS_CMD_SHIFT 1 -#define CS_CMD_CMD_NO_ACTION 0x00000000 -#define CS_CMD_CMD_START_RESTART 0x00000001 -#define CS_CMD_CMD_STOP 0x00000002 -#define CS_EN_SHIFT 0 -#define CS_EN_CMD_ENABLE_BSC 0x00000001 - -#define TIM_OFFSET 0x00000024 -#define TIM_PRESCALE_SHIFT 6 -#define TIM_P_SHIFT 3 -#define TIM_NO_DIV_SHIFT 2 -#define TIM_DIV_SHIFT 0 - -#define DAT_OFFSET 0x00000028 - -#define TOUT_OFFSET 0x0000002c - -#define TXFCR_OFFSET 0x0000003c -#define TXFCR_FIFO_FLUSH_MASK 0x00000080 -#define TXFCR_FIFO_EN_MASK 0x00000040 - -#define IER_OFFSET 0x00000044 -#define IER_READ_COMPLETE_INT_MASK 0x00000010 -#define IER_I2C_INT_EN_MASK 0x00000008 -#define IER_FIFO_INT_EN_MASK 0x00000002 -#define IER_NOACK_EN_MASK 0x00000001 - -#define ISR_OFFSET 0x00000048 -#define ISR_RESERVED_MASK 0xffffff60 -#define ISR_CMDBUSY_MASK 0x00000080 -#define ISR_READ_COMPLETE_MASK 0x00000010 -#define ISR_SES_DONE_MASK 0x00000008 -#define ISR_ERR_MASK 0x00000004 -#define ISR_TXFIFOEMPTY_MASK 0x00000002 -#define ISR_NOACK_MASK 0x00000001 - -#define CLKEN_OFFSET 0x0000004c -#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 -#define CLKEN_M_SHIFT 4 -#define CLKEN_N_SHIFT 1 -#define CLKEN_CLKEN_MASK 0x00000001 - -#define FIFO_STATUS_OFFSET 0x00000054 -#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 -#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 - -#define HSTIM_OFFSET 0x00000058 -#define HSTIM_HS_MODE_MASK 0x00008000 -#define HSTIM_HS_HOLD_SHIFT 10 -#define HSTIM_HS_HIGH_PHASE_SHIFT 5 -#define HSTIM_HS_SETUP_SHIFT 0 - -#define PADCTL_OFFSET 0x0000005c -#define PADCTL_PAD_OUT_EN_MASK 0x00000004 - -#define RXFCR_OFFSET 0x00000068 -#define RXFCR_NACK_EN_SHIFT 7 -#define RXFCR_READ_COUNT_SHIFT 0 -#define RXFIFORDOUT_OFFSET 0x0000006c - -/* Locally used constants */ -#define MAX_RX_FIFO_SIZE 64U /* bytes */ -#define MAX_TX_FIFO_SIZE 64U /* bytes */ - -#define I2C_TIMEOUT 100000 /* usecs */ - -#define WAIT_INT_CHK 100 /* usecs */ -#if I2C_TIMEOUT % WAIT_INT_CHK -#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK -#endif - -/* Operations that can be commanded to the controller */ -enum bcm_kona_cmd_t { - BCM_CMD_NOACTION = 0, - BCM_CMD_START, - BCM_CMD_RESTART, - BCM_CMD_STOP, -}; - -/* Internal divider settings for standard mode, fast mode and fast mode plus */ -struct bus_speed_cfg { - uint8_t time_m; /* Number of cycles for setup time */ - uint8_t time_n; /* Number of cycles for hold time */ - uint8_t prescale; /* Prescale divider */ - uint8_t time_p; /* Timing coefficient */ - uint8_t no_div; /* Disable clock divider */ - uint8_t time_div; /* Post-prescale divider */ -}; - -static const struct bus_speed_cfg std_cfg_table[] = { - [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, - [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, - [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, -}; - -struct bcm_kona_i2c_dev { - void *base; - uint speed; - const struct bus_speed_cfg *std_cfg; -}; - -/* Keep these two defines in sync */ -#define DEF_SPD I2C_SPEED_STANDARD_RATE -#define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD - -#define DEF_DEVICE(num) \ -{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} - -static struct bcm_kona_i2c_dev g_i2c_devs[CFG_SYS_MAX_I2C_BUS] = { -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_DEVICE(0), -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_DEVICE(1), -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_DEVICE(2), -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_DEVICE(3), -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_DEVICE(4), -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_DEVICE(5), -#endif -}; - -#define I2C_M_TEN 0x0010 /* ten bit address */ -#define I2C_M_RD 0x0001 /* read data */ -#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ - -struct kona_i2c_msg { - uint16_t addr; - uint16_t flags; - uint16_t len; - uint8_t *buf; -}; - -static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - debug("%s, %d\n", __func__, cmd); - - switch (cmd) { - case BCM_CMD_NOACTION: - writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_START: - writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_RESTART: - writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | - (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - case BCM_CMD_STOP: - writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | - (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), - dev->base + CS_OFFSET); - break; - - default: - printf("Unknown command %d\n", cmd); - } -} - -static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, - dev->base + CLKEN_OFFSET); -} - -/* Wait until at least one of the mask bit(s) are set */ -static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, - unsigned long time_left, - uint32_t mask) -{ - uint32_t status; - - while (time_left) { - status = readl(dev->base + ISR_OFFSET); - - if ((status & ~ISR_RESERVED_MASK) == 0) { - debug("Bogus I2C interrupt 0x%x\n", status); - continue; - } - - /* Must flush the TX FIFO when NAK detected */ - if (status & ISR_NOACK_MASK) - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); - - if (status & mask) { - /* We are done since one of the mask bits are set */ - return time_left; - } - udelay(WAIT_INT_CHK); - time_left -= WAIT_INT_CHK; - } - return 0; -} - -/* Send command to I2C bus */ -static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, - enum bcm_kona_cmd_t cmd) -{ - int rc = 0; - unsigned long time_left = I2C_TIMEOUT; - - /* Send the command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); - - /* Wait for transaction to finish or timeout */ - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - printf("controller timed out\n"); - rc = -ETIMEDOUT; - } - - /* Clear command */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - return rc; -} - -/* Read a single RX FIFO worth of data from the i2c bus */ -static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len, - unsigned int last_byte_nak) -{ - unsigned long time_left = I2C_TIMEOUT; - - /* Start the RX FIFO */ - writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | - (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); - - /* Wait for FIFO read to complete */ - time_left = - wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); - - if (!time_left) { - printf("RX FIFO time out\n"); - return -EREMOTEIO; - } - - /* Read data from FIFO */ - for (; len > 0; len--, buf++) - *buf = readl(dev->base + RXFIFORDOUT_OFFSET); - - return 0; -} - -/* Read any amount of data using the RX FIFO from the i2c bus */ -static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; - unsigned int last_byte_nak = 0; - unsigned int bytes_read = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_read < msg->len) { - if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { - last_byte_nak = 1; /* NAK last byte of transfer */ - bytes_to_read = msg->len - bytes_read; - } - - rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, - last_byte_nak); - if (rc < 0) - return -EREMOTEIO; - - bytes_read += bytes_to_read; - tmp_buf += bytes_to_read; - } - - return 0; -} - -/* Write a single byte of data to the i2c bus */ -static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, - unsigned int nak_expected) -{ - unsigned long time_left = I2C_TIMEOUT; - unsigned int nak_received; - - /* Clear pending session done interrupt */ - writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); - - /* Send one byte of data */ - writel(data, dev->base + DAT_OFFSET); - - time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); - - if (!time_left) { - debug("controller timed out\n"); - return -ETIMEDOUT; - } - - nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; - - if (nak_received ^ nak_expected) { - debug("unexpected NAK/ACK\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write a single TX FIFO worth of data to the i2c bus */ -static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, - uint8_t *buf, unsigned int len) -{ - int k; - unsigned long time_left = I2C_TIMEOUT; - unsigned int fifo_status; - - /* Write data into FIFO */ - for (k = 0; k < len; k++) - writel(buf[k], (dev->base + DAT_OFFSET)); - - /* Wait for FIFO to empty */ - do { - time_left = - wait_for_int_timeout(dev, time_left, - (IER_FIFO_INT_EN_MASK | - IER_NOACK_EN_MASK)); - fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); - } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); - - /* Check if there was a NAK */ - if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { - printf("unexpected NAK\n"); - return -EREMOTEIO; - } - - /* Check if a timeout occurred */ - if (!time_left) { - printf("completion timed out\n"); - return -EREMOTEIO; - } - - return 0; -} - -/* Write any amount of data using TX FIFO to the i2c bus */ -static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; - unsigned int bytes_written = 0; - int rc; - - uint8_t *tmp_buf = msg->buf; - - while (bytes_written < msg->len) { - if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) - bytes_to_write = msg->len - bytes_written; - - rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, - bytes_to_write); - if (rc < 0) - return -EREMOTEIO; - - bytes_written += bytes_to_write; - tmp_buf += bytes_to_write; - } - - return 0; -} - -/* Send i2c address */ -static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg *msg) -{ - unsigned char addr; - - if (msg->flags & I2C_M_TEN) { - /* First byte is 11110XX0 where XX is upper 2 bits */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7); - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - /* Second byte is the remaining 8 bits */ - addr = msg->addr & 0xff; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - - if (msg->flags & I2C_M_RD) { - /* For read, send restart command */ - if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) - return -EREMOTEIO; - - /* Then re-send the first byte with the read bit set */ - addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - } else { - addr = msg->addr << 1; - - if (msg->flags & I2C_M_RD) - addr |= 1; - - if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) - return -EREMOTEIO; - } - - return 0; -} - -static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, - dev->base + CLKEN_OFFSET); -} - -static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) -{ - writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, - dev->base + HSTIM_OFFSET); - - writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | - (dev->std_cfg->time_p << TIM_P_SHIFT) | - (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | - (dev->std_cfg->time_div << TIM_DIV_SHIFT), - dev->base + TIM_OFFSET); - - writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | - (dev->std_cfg->time_n << CLKEN_N_SHIFT) | - CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); -} - -/* Master transfer function */ -static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, - struct kona_i2c_msg msgs[], int num) -{ - struct kona_i2c_msg *pmsg; - int rc = 0; - int i; - - /* Enable pad output */ - writel(0, dev->base + PADCTL_OFFSET); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Send start command */ - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); - if (rc < 0) { - printf("Start command failed rc = %d\n", rc); - goto xfer_disable_pad; - } - - /* Loop through all messages */ - for (i = 0; i < num; i++) { - pmsg = &msgs[i]; - - /* Send restart for subsequent messages */ - if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { - rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); - if (rc < 0) { - printf("restart cmd failed rc = %d\n", rc); - goto xfer_send_stop; - } - } - - /* Send slave address */ - if (!(pmsg->flags & I2C_M_NOSTART)) { - rc = bcm_kona_i2c_do_addr(dev, pmsg); - if (rc < 0) { - debug("NAK from addr %2.2x msg#%d rc = %d\n", - pmsg->addr, i, rc); - goto xfer_send_stop; - } - } - - /* Perform data transfer */ - if (pmsg->flags & I2C_M_RD) { - rc = bcm_kona_i2c_read_fifo(dev, pmsg); - if (rc < 0) { - printf("read failure\n"); - goto xfer_send_stop; - } - } else { - rc = bcm_kona_i2c_write_fifo(dev, pmsg); - if (rc < 0) { - printf("write failure"); - goto xfer_send_stop; - } - } - } - - rc = num; - -xfer_send_stop: - /* Send a STOP command */ - bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); - -xfer_disable_pad: - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); - - /* Stop internal clock */ - bcm_kona_i2c_disable_clock(dev); - - return rc; -} - -static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, - uint speed) -{ - switch (speed) { - case I2C_SPEED_STANDARD_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD]; - break; - case I2C_SPEED_FAST_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST]; - break; - case I2C_SPEED_FAST_PLUS_RATE: - dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS]; - break; - default: - printf("%d hz bus speed not supported\n", speed); - return -EINVAL; - } - dev->speed = speed; - return 0; -} - -static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) -{ - /* Parse bus speed */ - bcm_kona_i2c_assign_bus_speed(dev, dev->speed); - - /* Enable internal clocks */ - bcm_kona_i2c_enable_clock(dev); - - /* Configure internal dividers */ - bcm_kona_i2c_config_timing(dev); - - /* Disable timeout */ - writel(0, dev->base + TOUT_OFFSET); - - /* Enable autosense */ - bcm_kona_i2c_enable_autosense(dev); - - /* Enable TX FIFO */ - writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, - dev->base + TXFCR_OFFSET); - - /* Mask all interrupts */ - writel(0, dev->base + IER_OFFSET); - - /* Clear all pending interrupts */ - writel(ISR_CMDBUSY_MASK | - ISR_READ_COMPLETE_MASK | - ISR_SES_DONE_MASK | - ISR_ERR_MASK | - ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); - - /* Enable the controller but leave it idle */ - bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); - - /* Disable pad output */ - writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); -} - -/* - * uboot layer - */ -struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) -{ - return &g_i2c_devs[adap->hwadapnr]; -} - -static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - if (clk_bsc_enable(dev->base)) - return; - - bcm_kona_i2c_init(dev); -} - -static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - /* msg[0] writes the addr, msg[1] reads the data */ - struct kona_i2c_msg msg[2]; - unsigned char msgbuf0[64]; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 1; - msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ - - msg[1].addr = chip; - msg[1].flags = I2C_M_RD; - /* msg[1].buf dest ptr increments each read */ - - msgbuf0[0] = (unsigned char)addr; - msg[1].buf = buffer; - msg[1].len = len; - if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { - /* Sending 2 i2c messages */ - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C read: I/O error\n"); - return -EIO; - } - return 0; -} - -static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) -{ - struct kona_i2c_msg msg[1]; - unsigned char msgbuf0[64]; - unsigned int i; - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - - msg[0].addr = chip; - msg[0].flags = 0; - msg[0].len = 2; /* addr byte plus data */ - msg[0].buf = msgbuf0; - - for (i = 0; i < len; i++) { - msgbuf0[0] = addr++; - msgbuf0[1] = buffer[i]; - if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { - kona_i2c_init(adap, adap->speed, adap->slaveaddr); - debug("I2C write: I/O error\n"); - return -EIO; - } - } - return 0; -} - -static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) -{ - uchar tmp; - - /* - * read addr 0x0 of the given chip. - */ - return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); -} - -static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) -{ - struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); - return bcm_kona_i2c_assign_bus_speed(dev, speed); -} - -/* - * Register kona i2c adapters. Keep the order below so - * that the bus number matches the adapter number. - */ -#define DEF_ADAPTER(num) \ -U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ - kona_i2c_read, kona_i2c_write, \ - kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) - -#ifdef CONFIG_SYS_I2C_BASE0 - DEF_ADAPTER(0) -#endif -#ifdef CONFIG_SYS_I2C_BASE1 - DEF_ADAPTER(1) -#endif -#ifdef CONFIG_SYS_I2C_BASE2 - DEF_ADAPTER(2) -#endif -#ifdef CONFIG_SYS_I2C_BASE3 - DEF_ADAPTER(3) -#endif -#ifdef CONFIG_SYS_I2C_BASE4 - DEF_ADAPTER(4) -#endif -#ifdef CONFIG_SYS_I2C_BASE5 - DEF_ADAPTER(5) -#endif diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 9a1599dcd9..86b9fb57c8 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -744,7 +744,7 @@ void bus_i2c_init(int index, int speed, int unused, return; } - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (i2c_fused((ulong)mxc_i2c_buses[index].base)) { printf("SoC fuse indicates I2C@0x%lx is unavailable.\n", (ulong)mxc_i2c_buses[index].base); @@ -878,7 +878,7 @@ static int mxc_i2c_probe(struct udevice *bus) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (i2c_fused((ulong)addr)) { printf("SoC fuse indicates I2C@0x%lx is unavailable.\n", (ulong)addr); diff --git a/drivers/i2c/qup_i2c.c b/drivers/i2c/qup_i2c.c new file mode 100644 index 0000000000..5ae3cccd4a --- /dev/null +++ b/drivers/i2c/qup_i2c.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, Sony Mobile Communications AB. + * Copyright (c) 2022-2023, Sumit Garg <sumit.garg@linaro.org> + * + * Inspired by corresponding driver in Linux: drivers/i2c/busses/i2c-qup.c + */ + +#include <init.h> +#include <env.h> +#include <common.h> +#include <log.h> +#include <dm/device_compat.h> +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/compat.h> +#include <linux/bitops.h> +#include <asm/io.h> +#include <i2c.h> +#include <watchdog.h> +#include <fdtdec.h> +#include <clk.h> +#include <reset.h> +#include <asm/arch/gpio.h> +#include <cpu_func.h> +#include <asm/system.h> +#include <asm/gpio.h> +#include <dm.h> +#include <dm/pinctrl.h> + +/* QUP Registers */ +#define QUP_CONFIG 0x000 +#define QUP_STATE 0x004 +#define QUP_IO_MODE 0x008 +#define QUP_SW_RESET 0x00c +#define QUP_OPERATIONAL 0x018 +#define QUP_ERROR_FLAGS 0x01c /* NOT USED */ +#define QUP_ERROR_FLAGS_EN 0x020 /* NOT USED */ +#define QUP_TEST_CTRL 0x024 /* NOT USED */ +#define QUP_OPERATIONAL_MASK 0x028 /* NOT USED */ +#define QUP_HW_VERSION 0x030 +#define QUP_MX_OUTPUT_CNT 0x100 +#define QUP_OUT_DEBUG 0x108 /* NOT USED */ +#define QUP_OUT_FIFO_CNT 0x10C /* NOT USED */ +#define QUP_OUT_FIFO_BASE 0x110 +#define QUP_MX_WRITE_CNT 0x150 +#define QUP_MX_INPUT_CNT 0x200 +#define QUP_MX_READ_CNT 0x208 +#define QUP_IN_READ_CUR 0x20C /* NOT USED */ +#define QUP_IN_DEBUG 0x210 /* NOT USED */ +#define QUP_IN_FIFO_CNT 0x214 /* NOT USED */ +#define QUP_IN_FIFO_BASE 0x218 +#define QUP_I2C_CLK_CTL 0x400 +#define QUP_I2C_STATUS 0x404 /* NOT USED */ +#define QUP_I2C_MASTER_GEN 0x408 +#define QUP_I2C_MASTER_BUS_CLR 0x40C /* NOT USED */ + +/* QUP States and reset values */ +#define QUP_RESET_STATE 0 +#define QUP_RUN_STATE 1 +#define QUP_PAUSE_STATE 3 +#define QUP_STATE_MASK 3 + +#define QUP_STATE_VALID BIT(2) +#define QUP_I2C_MAST_GEN BIT(4) +#define QUP_I2C_FLUSH BIT(6) + +#define QUP_OPERATIONAL_RESET 0x000ff0 +#define QUP_I2C_STATUS_RESET 0xfffffc + +/* QUP OPERATIONAL FLAGS */ +#define QUP_I2C_NACK_FLAG BIT(3) +#define QUP_OUT_NOT_EMPTY BIT(4) +#define QUP_IN_NOT_EMPTY BIT(5) +#define QUP_OUT_FULL BIT(6) +#define QUP_OUT_SVC_FLAG BIT(8) +#define QUP_IN_SVC_FLAG BIT(9) +#define QUP_MX_OUTPUT_DONE BIT(10) +#define QUP_MX_INPUT_DONE BIT(11) +#define OUT_BLOCK_WRITE_REQ BIT(12) +#define IN_BLOCK_READ_REQ BIT(13) + +/* + * QUP engine acting as I2C controller is referred to as + * I2C mini core, following are related macros. + */ +#define QUP_NO_OUTPUT BIT(6) +#define QUP_NO_INPUT BIT(7) +#define QUP_CLOCK_AUTO_GATE BIT(13) +#define QUP_I2C_MINI_CORE (2 << 8) +#define QUP_I2C_N_VAL_V2 7 + +/* Packing/Unpacking words in FIFOs, and IO modes */ +#define QUP_OUTPUT_BLK_MODE BIT(10) +#define QUP_OUTPUT_BAM_MODE (BIT(10) | BIT(11)) +#define QUP_INPUT_BLK_MODE BIT(12) +#define QUP_INPUT_BAM_MODE (BIT(12) | BIT(13)) +#define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE) +#define QUP_BLK_MODE (QUP_OUTPUT_BLK_MODE | QUP_INPUT_BLK_MODE) +#define QUP_UNPACK_EN BIT(14) +#define QUP_PACK_EN BIT(15) + +#define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN) +#define QUP_V2_TAGS_EN 1 + +#define QUP_OUTPUT_BLOCK_SIZE(x) (((x) >> 0) & 0x03) +#define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07) +#define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03) +#define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07) + +/* QUP v2 tags */ +#define QUP_TAG_V2_START 0x81 +#define QUP_TAG_V2_DATAWR 0x82 +#define QUP_TAG_V2_DATAWR_STOP 0x83 +#define QUP_TAG_V2_DATARD 0x85 +#define QUP_TAG_V2_DATARD_NACK 0x86 +#define QUP_TAG_V2_DATARD_STOP 0x87 + +#define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31) + +/* Minimum transfer timeout for i2c transfers in micro seconds */ +#define TOUT_CNT (2 * 1000 * 1000) + +/* Default values. Use these if FW query fails */ +#define DEFAULT_CLK_FREQ I2C_SPEED_STANDARD_RATE +#define DEFAULT_SRC_CLK 19200000 + +/* + * Max tags length (start, stop and maximum 2 bytes address) for each QUP + * data transfer + */ +#define QUP_MAX_TAGS_LEN 4 +/* Max data length for each DATARD tags */ +#define RECV_MAX_DATA_LEN 254 +/* TAG length for DATA READ in RX FIFO */ +#define READ_RX_TAGS_LEN 2 + +struct qup_i2c_priv { + phys_addr_t base; + struct clk core; + struct clk iface; + u32 in_fifo_sz; + u32 out_fifo_sz; + u32 clk_ctl; + u32 config_run; +}; + +static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg) +{ + return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0); +} + +static int qup_i2c_poll_state_mask(struct qup_i2c_priv *qup, + u32 req_state, u32 req_mask) +{ + int retries = 1; + u32 state; + + /* + * State transition takes 3 AHB clocks cycles + 3 I2C master clock + * cycles. So retry once after a 1uS delay. + */ + do { + state = readl(qup->base + QUP_STATE); + + if (state & QUP_STATE_VALID && + (state & req_mask) == req_state) + return 0; + + udelay(1); + } while (retries--); + + return -ETIMEDOUT; +} + +static int qup_i2c_poll_state(struct qup_i2c_priv *qup, u32 req_state) +{ + return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); +} + +static int qup_i2c_poll_state_valid(struct qup_i2c_priv *qup) +{ + return qup_i2c_poll_state_mask(qup, 0, 0); +} + +static int qup_i2c_poll_state_i2c_master(struct qup_i2c_priv *qup) +{ + return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); +} + +static int qup_i2c_change_state(struct qup_i2c_priv *qup, u32 state) +{ + if (qup_i2c_poll_state_valid(qup) != 0) + return -EIO; + + writel(state, qup->base + QUP_STATE); + + if (qup_i2c_poll_state(qup, state) != 0) + return -EIO; + return 0; +} + +/* + * Function to check wheather Input or Output FIFO + * has data to be serviced + */ +static int qup_i2c_check_fifo_status(struct qup_i2c_priv *qup, u32 reg_addr, + u32 flags) +{ + unsigned long count = TOUT_CNT; + u32 val, status_flag; + int ret = 0; + + do { + val = readl(qup->base + reg_addr); + status_flag = val & flags; + + if (!count) { + printf("%s, timeout\n", __func__); + ret = -ETIMEDOUT; + break; + } + + count--; + udelay(1); + } while (!status_flag); + + return ret; +} + +/* + * Function to configure Input and Output enable/disable + */ +static void qup_i2c_enable_io_config(struct qup_i2c_priv *qup, u32 write_cnt, + u32 read_cnt) +{ + u32 qup_config = QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2; + + writel(qup->config_run | write_cnt, qup->base + QUP_MX_WRITE_CNT); + + if (read_cnt) + writel(qup->config_run | read_cnt, qup->base + QUP_MX_READ_CNT); + else + qup_config |= QUP_NO_INPUT; + + writel(qup_config, qup->base + QUP_CONFIG); +} + +static unsigned int qup_i2c_read_word(struct qup_i2c_priv *qup) +{ + return readl(qup->base + QUP_IN_FIFO_BASE); +} + +static void qup_i2c_write_word(struct qup_i2c_priv *qup, u32 word) +{ + writel(word, qup->base + QUP_OUT_FIFO_BASE); +} + +static int qup_i2c_blsp_read(struct qup_i2c_priv *qup, unsigned int addr, + bool last, u8 *buffer, unsigned int bytes) +{ + unsigned int i, j, word; + int ret = 0; + + /* FIFO mode size limitation, for larger size implement block mode */ + if (bytes > (qup->in_fifo_sz - READ_RX_TAGS_LEN)) + return -EINVAL; + + qup_i2c_enable_io_config(qup, QUP_MAX_TAGS_LEN, + bytes + READ_RX_TAGS_LEN); + + if (last) + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATARD_STOP << 16 | + bytes << 24); + else + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATARD << 16 | bytes << 24); + + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG); + if (ret) + return ret; + writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_IN_SVC_FLAG); + if (ret) + return ret; + writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + word = qup_i2c_read_word(qup); + *(buffer++) = (word >> (8 * READ_RX_TAGS_LEN)) & 0xff; + if (bytes > 1) + *(buffer++) = (word >> (8 * (READ_RX_TAGS_LEN + 1))) & 0xff; + + for (i = 2; i < bytes; i += 4) { + word = qup_i2c_read_word(qup); + + for (j = 0; j < 4; j++) { + if ((i + j) == bytes) + break; + *buffer = (word >> (j * 8)) & 0xff; + buffer++; + } + } + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + return ret; +} + +static int qup_i2c_blsp_write(struct qup_i2c_priv *qup, unsigned int addr, + bool first, bool last, const u8 *buffer, + unsigned int bytes) +{ + unsigned int i; + u32 word = 0; + int ret = 0; + + /* FIFO mode size limitation, for larger size implement block mode */ + if (bytes > (qup->out_fifo_sz - QUP_MAX_TAGS_LEN)) + return -EINVAL; + + qup_i2c_enable_io_config(qup, bytes + QUP_MAX_TAGS_LEN, 0); + + if (first) { + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + if (ret) + return ret; + } + + if (last) + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATAWR_STOP << 16 | + bytes << 24); + else + qup_i2c_write_word(qup, QUP_TAG_V2_START | addr << 8 | + QUP_TAG_V2_DATAWR << 16 | bytes << 24); + + for (i = 0; i < bytes; i++) { + /* Write the byte of data */ + word |= *buffer << ((i % 4) * 8); + if ((i % 4) == 3) { + qup_i2c_write_word(qup, word); + word = 0; + } + buffer++; + } + + if ((i % 4) != 0) + qup_i2c_write_word(qup, word); + + ret = qup_i2c_change_state(qup, QUP_RUN_STATE); + if (ret) + return ret; + + ret = qup_i2c_check_fifo_status(qup, QUP_OPERATIONAL, QUP_OUT_SVC_FLAG); + if (ret) + return ret; + writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); + + ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); + return ret; +} + +static void qup_i2c_conf_mode_v2(struct qup_i2c_priv *qup) +{ + u32 io_mode = QUP_REPACK_EN; + + writel(0, qup->base + QUP_MX_OUTPUT_CNT); + writel(0, qup->base + QUP_MX_INPUT_CNT); + + writel(io_mode, qup->base + QUP_IO_MODE); +} + +static int qup_i2c_xfer_v2(struct udevice *bus, struct i2c_msg msgs[], int num) +{ + struct qup_i2c_priv *qup = dev_get_priv(bus); + int ret, idx = 0; + u32 i2c_addr; + + writel(1, qup->base + QUP_SW_RESET); + ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); + if (ret) + goto out; + + /* Configure QUP as I2C mini core */ + writel(QUP_I2C_MINI_CORE | QUP_I2C_N_VAL_V2 | QUP_NO_INPUT, + qup->base + QUP_CONFIG); + writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); + + if (qup_i2c_poll_state_i2c_master(qup)) { + ret = -EIO; + goto out; + } + + qup_i2c_conf_mode_v2(qup); + + for (idx = 0; idx < num; idx++) { + struct i2c_msg *m = &msgs[idx]; + + qup->config_run = !idx ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; + i2c_addr = i2c_8bit_addr_from_msg(m); + + if (m->flags & I2C_M_RD) + ret = qup_i2c_blsp_read(qup, i2c_addr, idx == (num - 1), + m->buf, m->len); + else + ret = qup_i2c_blsp_write(qup, i2c_addr, idx == 0, + idx == (num - 1), m->buf, + m->len); + if (ret) + break; + } +out: + qup_i2c_change_state(qup, QUP_RESET_STATE); + return ret; +} + +static int qup_i2c_enable_clocks(struct udevice *dev, struct qup_i2c_priv *qup) +{ + int ret; + + ret = clk_enable(&qup->core); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + ret = clk_enable(&qup->iface); + if (ret) { + dev_err(dev, "clk_enable failed %d\n", ret); + return ret; + } + + return 0; +} + +static int qup_i2c_probe(struct udevice *dev) +{ + static const int blk_sizes[] = {4, 16, 32}; + struct qup_i2c_priv *qup = dev_get_priv(dev); + u32 io_mode, hw_ver, size, size_idx; + int ret; + + qup->base = (phys_addr_t)dev_read_addr_ptr(dev); + if (!qup->base) + return -EINVAL; + + ret = clk_get_by_name(dev, "core", &qup->core); + if (ret) { + pr_err("clk_get_by_name(core) failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(dev, "iface", &qup->iface); + if (ret) { + pr_err("clk_get_by_name(iface) failed: %d\n", ret); + return ret; + } + qup_i2c_enable_clocks(dev, qup); + + writel(1, qup->base + QUP_SW_RESET); + ret = qup_i2c_poll_state_valid(qup); + if (ret) + return ret; + + hw_ver = readl(qup->base + QUP_HW_VERSION); + dev_dbg(dev, "Revision %x\n", hw_ver); + + io_mode = readl(qup->base + QUP_IO_MODE); + + /* + * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag' + * associated with each byte written/received + */ + size_idx = QUP_OUTPUT_BLOCK_SIZE(io_mode); + if (size_idx >= ARRAY_SIZE(blk_sizes)) { + ret = -EIO; + return ret; + } + size = QUP_OUTPUT_FIFO_SIZE(io_mode); + qup->out_fifo_sz = blk_sizes[size_idx] * (2 << size); + + size_idx = QUP_INPUT_BLOCK_SIZE(io_mode); + if (size_idx >= ARRAY_SIZE(blk_sizes)) { + ret = -EIO; + return ret; + } + size = QUP_INPUT_FIFO_SIZE(io_mode); + qup->in_fifo_sz = blk_sizes[size_idx] * (2 << size); + + dev_dbg(dev, "IN:fifo:%d, OUT:fifo:%d\n", qup->in_fifo_sz, + qup->out_fifo_sz); + + return 0; +} + +static int qup_i2c_set_bus_speed(struct udevice *dev, unsigned int clk_freq) +{ + struct qup_i2c_priv *qup = dev_get_priv(dev); + unsigned int src_clk_freq; + int fs_div, hs_div; + + /* We support frequencies up to FAST Mode Plus (1MHz) */ + if (!clk_freq || clk_freq > I2C_SPEED_FAST_PLUS_RATE) { + dev_err(dev, "clock frequency not supported %d\n", clk_freq); + return -EINVAL; + } + + src_clk_freq = clk_get_rate(&qup->iface); + if ((int)src_clk_freq < 0) { + src_clk_freq = DEFAULT_SRC_CLK; + dev_dbg(dev, "using default core freq %d\n", src_clk_freq); + } + + dev_dbg(dev, "src_clk_freq %u\n", src_clk_freq); + dev_dbg(dev, "clk_freq %u\n", clk_freq); + + hs_div = 3; + if (clk_freq <= I2C_SPEED_STANDARD_RATE) { + fs_div = ((src_clk_freq / clk_freq) / 2) - 3; + qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); + } else { + /* 33%/66% duty cycle */ + fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; + qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); + } + + dev_dbg(dev, "clk_ctl %u\n", qup->clk_ctl); + + return 0; +} + +/* Probe to see if a chip is present. */ +static int qup_i2c_probe_chip(struct udevice *dev, uint chip_addr, + uint chip_flags) +{ + struct qup_i2c_priv *qup = dev_get_priv(dev); + u32 hw_ver = readl(qup->base + QUP_HW_VERSION); + + return hw_ver ? 0 : -1; +} + +static const struct dm_i2c_ops qup_i2c_ops = { + .xfer = qup_i2c_xfer_v2, + .probe_chip = qup_i2c_probe_chip, + .set_bus_speed = qup_i2c_set_bus_speed, +}; + +/* + * Currently this driver only supports v2.x of QUP I2C controller, hence + * functions above are named with a _v2 suffix. So when we have the + * v1.1.1 support added as per the Linux counterpart then it should be easy + * to add corresponding functions named with a _v1 suffix. + */ +static const struct udevice_id qup_i2c_ids[] = { + { .compatible = "qcom,i2c-qup-v2.1.1" }, + { .compatible = "qcom,i2c-qup-v2.2.1" }, + {} +}; + +U_BOOT_DRIVER(i2c_qup) = { + .name = "i2c_qup", + .id = UCLASS_I2C, + .of_match = qup_i2c_ids, + .probe = qup_i2c_probe, + .priv_auto = sizeof(struct qup_i2c_priv), + .ops = &qup_i2c_ops, +}; diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 6cecec4145..3335d9482a 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -172,14 +172,9 @@ static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) { int ret = -1; -#if defined(CONFIG_SH73A0) - if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) - goto exit0; -#else if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) goto exit0; udelay(100); -#endif writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); sh_irq_dte(dev); diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 1c534be005..32360d94c0 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -46,6 +46,15 @@ config APPLE_SPI_KEYB laptops based on Apple SoCs. These keyboards use an Apple-specific HID-over-SPI protocol. +config BUTTON_KEYBOARD + bool "Buttons as keyboard" + depends on BUTTON_GPIO + depends on DM_KEYBOARD + help + Enable support for mapping buttons to keycode events. Use linux,code button driver + dt node to define button-event mapping. + For example, an arrows and enter may be implemented to navigate boot menu. + config CROS_EC_KEYB bool "Enable Chrome OS EC keyboard support" depends on INPUT diff --git a/drivers/input/Makefile b/drivers/input/Makefile index ded76bddb2..14c0ea7325 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_$(SPL_TPL_)CROS_EC_KEYB) += cros_ec_keyb.o obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += key_matrix.o obj-$(CONFIG_$(SPL_TPL_)DM_KEYBOARD) += input.o keyboard-uclass.o +obj-$(CONFIG_BUTTON_KEYBOARD) += button_kbd.o ifndef CONFIG_SPL_BUILD diff --git a/drivers/input/button_kbd.c b/drivers/input/button_kbd.c new file mode 100644 index 0000000000..99e65f12f0 --- /dev/null +++ b/drivers/input/button_kbd.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Dzmitry Sankouski <dsankouski@gmail.com> + */ + +#include <stdlib.h> +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <input.h> +#include <keyboard.h> +#include <button.h> +#include <dm/device-internal.h> +#include <log.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/delay.h> +#include <linux/input.h> + +/** + * struct button_kbd_priv - driver private data + * + * @input: input configuration + * @button_size: number of buttons found + * @old_state: a pointer to old button states array. Used to determine button state change. + */ +struct button_kbd_priv { + struct input_config *input; + u32 button_size; + u32 *old_state; +}; + +static int button_kbd_start(struct udevice *dev) +{ + struct button_kbd_priv *priv = dev_get_priv(dev); + int i = 0; + struct udevice *button_gpio_devp; + + uclass_foreach_dev_probe(UCLASS_BUTTON, button_gpio_devp) { + struct button_uc_plat *uc_plat = dev_get_uclass_plat(button_gpio_devp); + /* Ignore the top-level button node */ + if (!uc_plat->label) + continue; + debug("Found button %s #%d - %s, probing...\n", + uc_plat->label, i, button_gpio_devp->name); + i++; + } + + priv->button_size = i; + priv->old_state = calloc(i, sizeof(int)); + + return 0; +} + +int button_read_keys(struct input_config *input) +{ + struct button_kbd_priv *priv = dev_get_priv(input->dev); + struct udevice *button_gpio_devp; + struct uclass *uc; + int i = 0; + u32 code, state, state_changed = 0; + + uclass_id_foreach_dev(UCLASS_BUTTON, button_gpio_devp, uc) { + struct button_uc_plat *uc_plat = dev_get_uclass_plat(button_gpio_devp); + /* Ignore the top-level button node */ + if (!uc_plat->label) + continue; + code = button_get_code(button_gpio_devp); + if (!code) + continue; + + state = button_get_state(button_gpio_devp); + state_changed = state != priv->old_state[i]; + + if (state_changed) { + debug("%s: %d\n", uc_plat->label, code); + priv->old_state[i] = state; + input_add_keycode(input, code, state); + } + i++; + } + return 0; +} + +static const struct keyboard_ops button_kbd_ops = { + .start = button_kbd_start, +}; + +static int button_kbd_probe(struct udevice *dev) +{ + struct button_kbd_priv *priv = dev_get_priv(dev); + struct keyboard_priv *uc_priv = dev_get_uclass_priv(dev); + struct stdio_dev *sdev = &uc_priv->sdev; + struct input_config *input = &uc_priv->input; + int ret = 0; + + input_init(input, false); + input_add_tables(input, false); + + /* Register the device. */ + priv->input = input; + input->dev = dev; + input->read_keys = button_read_keys; + strcpy(sdev->name, "button-kbd"); + ret = input_stdio_register(sdev); + if (ret) { + debug("%s: input_stdio_register() failed\n", __func__); + return ret; + } + + return 0; +} + +static const struct udevice_id button_kbd_ids[] = { + { .compatible = "button-kbd" }, + { } +}; + +U_BOOT_DRIVER(button_kbd) = { + .name = "button_kbd", + .id = UCLASS_KEYBOARD, + .of_match = button_kbd_ids, + .ops = &button_kbd_ops, + .priv_auto = sizeof(struct button_kbd_priv), + .probe = button_kbd_probe, +}; diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index d494639cd9..3b792f2a14 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -29,7 +29,6 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += spltest_sandbox.o endif endif -obj-$(CONFIG_ALI152X) += ali512x.o obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o @@ -37,7 +36,6 @@ obj-$(CONFIG_DS4510) += ds4510.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_IIM) += fsl_iim.o -obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_$(SPL_)FS_LOADER) += fs_loader.o obj-$(CONFIG_GATEWORKS_SC) += gsc.o diff --git a/drivers/misc/ali512x.c b/drivers/misc/ali512x.c deleted file mode 100644 index e714e28bdc..0000000000 --- a/drivers/misc/ali512x.c +++ /dev/null @@ -1,401 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - */ - -/* - * Based on sc520cdp.c from rolo 1.6: - *---------------------------------------------------------------------- - * (C) Copyright 2000 - * Sysgo Real-Time Solutions GmbH - * Klein-Winternheim, Germany - *---------------------------------------------------------------------- - */ - -#include <config.h> - -#include <common.h> -#include <asm/io.h> -#include <ali512x.h> - - -/* ALI M5123 Logical device numbers: - * 0 FDC - * 1 unused? - * 2 unused? - * 3 lpt - * 4 UART1 - * 5 UART2 - * 6 RTC - * 7 mouse/kbd - * 8 CIO - */ - -/* - ************************************************************ - * Some access primitives for the ALi chip: * - ************************************************************ - */ - -static void ali_write(u8 index, u8 value) -{ - /* write an arbirary register */ - outb(index, ALI_INDEX); - outb(value, ALI_DATA); -} - -#if 0 -static int ali_read(u8 index) -{ - outb(index, ALI_INDEX); - return inb(ALI_DATA); -} -#endif - -#define ALI_OPEN() \ - outb(0x51, ALI_INDEX); \ - outb(0x23, ALI_INDEX) - - -#define ALI_CLOSE() \ - outb(0xbb, ALI_INDEX) - -/* Select a logical device */ -#define ALI_SELDEV(dev) \ - ali_write(0x07, dev) - - -void ali512x_init(void) -{ - ALI_OPEN(); - - ali_write(0x02, 0x01); /* soft reset */ - ali_write(0x03, 0x03); /* disable access to CIOs */ - ali_write(0x22, 0x00); /* disable direct powerdown */ - ali_write(0x23, 0x00); /* disable auto powerdown */ - ali_write(0x24, 0x00); /* IR 8 is active hi, pin26 is PDIR */ - - ALI_CLOSE(); -} - -void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) -{ - ALI_OPEN(); - ALI_SELDEV(0); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - ali_write(0x74, dma_channel); - - /* AT mode, no drive swap */ - ali_write(0xf0, 0x08); - ali_write(0xf1, 0x00); - ali_write(0xf2, 0xff); - ali_write(0xf4, 0x00); - } - ALI_CLOSE(); -} - - -void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) -{ - ALI_OPEN(); - ALI_SELDEV(3); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - ali_write(0x74, dma_channel); - - /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */ - ali_write(0xf0, 0xbc); - /* 12 MHz, Burst DMA in ECP */ - ali_write(0xf1, 0x05); - } - ALI_CLOSE(); - -} - -void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) -{ - ALI_OPEN(); - ALI_SELDEV(index?5:4); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - - ali_write(0xf0, 0x00); - ali_write(0xf1, 0x00); - - /* huh? write 0xf2 twice - a typo in rolo - * or some secret ali errata? Who knows? - */ - if (index) { - ali_write(0xf2, 0x00); - } - ali_write(0xf2, 0x0c); - } - ALI_CLOSE(); - -} - -void ali512x_set_uart2_irda(int enabled) -{ - ALI_OPEN(); - ALI_SELDEV(5); - - ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */ - ALI_CLOSE(); - -} - -void ali512x_set_rtc(int enabled, u16 io, u8 irq) -{ - ALI_OPEN(); - ALI_SELDEV(6); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x60, io >> 8); - ali_write(0x61, io & 0xff); - ali_write(0x70, irq); - - ali_write(0xf0, 0x00); - } - ALI_CLOSE(); -} - -void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) -{ - ALI_OPEN(); - ALI_SELDEV(7); - - ali_write(0x30, enabled?1:0); - if (enabled) { - ali_write(0x70, kbc_irq); - ali_write(0x72, mouse_irq); - - ali_write(0xf0, 0x00); - } - ALI_CLOSE(); -} - - -/* Common I/O - * - * (This descripotsion is base on several incompete sources - * since I have not been able to obtain any datasheet for the device - * there may be some mis-understandings burried in here. - * -- Daniel daniel@omicron.se) - * - * There are 22 CIO pins numbered - * 10-17 - * 20-25 - * 30-37 - * - * 20-24 are dedicated CIO pins, the other 17 are muliplexed with - * other functions. - * - * Secondary - * CIO Pin Function Decription - * ======================================================= - * CIO10 IRQIN1 Interrupt input 1? - * CIO11 IRQIN2 Interrupt input 2? - * CIO12 IRRX IrDa Receive - * CIO13 IRTX IrDa Transmit - * CIO14 P21 KBC P21 fucntion - * CIO15 P20 KBC P21 fucntion - * CIO16 I2C_CLK I2C Clock - * CIO17 I2C_DAT I2C Data - * - * CIO20 - - * CIO21 - - * CIO22 - - * CIO23 - - * CIO24 - - * CIO25 LOCK Keylock - * - * CIO30 KBC_CLK Keybaord Clock - * CIO31 CS0J General Chip Select decoder CS0J - * CIO32 CS1J General Chip Select decoder CS1J - * CIO33 ALT_KCLK Alternative Keyboard Clock - * CIO34 ALT_KDAT Alternative Keyboard Data - * CIO35 ALT_MCLK Alternative Mouse Clock - * CIO36 ALT_MDAT Alternative Mouse Data - * CIO37 ALT_KBC Alternative KBC select - * - * The CIO use an indirect address scheme. - * - * Reigster 3 in the SIO is used to select the index and data - * port addresses where the CIO I/O registers show up. - * The function selection registers are accessible under - * function SIO 8. - * - * SIO reigster 3 (CIO Address Selection) bit definitions: - * bit 7 CIO index and data registers enabled - * bit 1-0 CIO indirect registers port address select - * 0 index = 0xE0 data = 0xE1 - * 1 index = 0xE2 data = 0xE3 - * 2 index = 0xE4 data = 0xE5 - * 3 index = 0xEA data = 0xEB - * - * There are three CIO I/O register accessed via CIO index port and CIO data port - * 0x01 CIO 10-17 data - * 0x02 CIO 20-25 data (bits 7-6 unused) - * 0x03 CIO 30-37 data - * - * - * The pin function is accessed through normal - * SIO registers, each register have the same format: - * - * Bit Function Value - * 0 Input/output 1=input - * 1 Polarity of signal 1=inverted - * 2 Unused ?? - * 3 Function (normal or special) 1=special - * 7-4 Unused - * - * SIO REG - * 0xe0 CIO 10 Config - * 0xe1 CIO 11 Config - * 0xe2 CIO 12 Config - * 0xe3 CIO 13 Config - * 0xe4 CIO 14 Config - * 0xe5 CIO 15 Config - * 0xe6 CIO 16 Config - * 0xe7 CIO 16 Config - * - * 0xe8 CIO 20 Config - * 0xe9 CIO 21 Config - * 0xea CIO 22 Config - * 0xeb CIO 23 Config - * 0xec CIO 24 Config - * 0xed CIO 25 Config - * - * 0xf5 CIO 30 Config - * 0xf6 CIO 31 Config - * 0xf7 CIO 32 Config - * 0xf8 CIO 33 Config - * 0xf9 CIO 34 Config - * 0xfa CIO 35 Config - * 0xfb CIO 36 Config - * 0xfc CIO 37 Config - * - */ - -#define ALI_CIO_PORT_SEL 0x83 -#define ALI_CIO_INDEX 0xea -#define ALI_CIO_DATA 0xeb - -void ali512x_set_cio(int enabled) -{ - int i; - - ALI_OPEN(); - - if (enabled) { - ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */ - } else { - ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80); - } - - ALI_SELDEV(8); - - ali_write(0x30, enabled?1:0); - - /* set all pins to input to start with */ - for (i=0xe0;i<0xee;i++) { - ali_write(i, 1); - } - - for (i=0xf5;i<0xfe;i++) { - ali_write(i, 1); - } - - ALI_CLOSE(); -} - - -void ali512x_cio_function(int pin, int special, int inv, int input) -{ - u8 data; - u8 addr; - - /* valid pins are 10-17, 20-25 and 30-37 */ - if (pin >= 10 && pin <= 17) { - addr = 0xe0+(pin&7); - } else if (pin >= 20 && pin <= 25) { - addr = 0xe8+(pin&7); - } else if (pin >= 30 && pin <= 37) { - addr = 0xf5+(pin&7); - } else { - return; - } - - ALI_OPEN(); - - ALI_SELDEV(8); - - - data=0xf4; - if (special) { - data |= 0x08; - } else { - if (inv) { - data |= 0x02; - } - if (input) { - data |= 0x01; - } - } - - ali_write(addr, data); - - ALI_CLOSE(); -} - -void ali512x_cio_out(int pin, int value) -{ - u8 reg; - u8 data; - u8 bit; - - reg = pin/10; - bit = 1 << (pin%10); - - - outb(reg, ALI_CIO_INDEX); /* select I/O register */ - data = inb(ALI_CIO_DATA); - if (value) { - data |= bit; - } else { - data &= ~bit; - } - outb(data, ALI_CIO_DATA); -} - -int ali512x_cio_in(int pin) -{ - u8 reg; - u8 data; - u8 bit; - - /* valid pins are 10-17, 20-25 and 30-37 */ - reg = pin/10; - bit = 1 << (pin%10); - - - outb(reg, ALI_CIO_INDEX); /* select I/O register */ - data = inb(ALI_CIO_DATA); - - return data & bit; -} diff --git a/drivers/misc/fsl_ifc.c b/drivers/misc/fsl_ifc.c index 58b0058736..f165b8c36b 100644 --- a/drivers/misc/fsl_ifc.c +++ b/drivers/misc/fsl_ifc.c @@ -371,7 +371,7 @@ void init_early_memctl_regs(void) for (i = 0 ; i < regs_info.cs_size; i++) { if (regs[i].pr && (regs[i].pr & CSPR_V)) { /* skip setting cspr/csor_ext in below condition */ - if (!(CONFIG_IS_ENABLED(A003399_NOR_WORKAROUND) && + if (!(IS_ENABLED(CONFIG_A003399_NOR_WORKAROUND) && i == 0 && ((regs[0].pr & CSPR_MSEL) == CSPR_MSEL_NOR))) { if (regs[i].pr_ext) diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 27ecce710f..8f546e9b3f 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -788,7 +788,7 @@ sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) RPC_VER(&msg) = SC_RPC_VERSION; RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED; - RPC_U8(&msg, 0U) = (u8)pad; + RPC_U16(&msg, 0U) = (u16)pad; RPC_SIZE(&msg) = 2U; ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c index dd104962c2..2a81bc7de5 100644 --- a/drivers/misc/ls2_sfp.c +++ b/drivers/misc/ls2_sfp.c @@ -229,7 +229,7 @@ static int ls2_sfp_probe(struct udevice *dev) return -EINVAL; } - ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply); + ret = device_get_supply_regulator(dev, "ta-sfp-prog-supply", &priv->supply); if (ret && ret != -ENODEV && ret != -ENOSYS) { dev_dbg(dev, "problem getting supply (err %d)\n", ret); return ret; diff --git a/drivers/misc/mc9sdz60.c b/drivers/misc/mc9sdz60.c deleted file mode 100644 index e68a056a55..0000000000 --- a/drivers/misc/mc9sdz60.c +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 Stefano Babic <sbabic@denx.de> - */ - - -#include <config.h> -#include <common.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <i2c.h> -#include <mc9sdz60.h> - -#ifndef CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR -#error "You have to configure I2C address for MC9SDZ60" -#endif - - -u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg) -{ - u8 val; - - if (i2c_read(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1)) { - puts("Error reading MC9SDZ60 register\n"); - return -1; - } - - return val; -} - -void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val) -{ - i2c_write(CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR, reg, 1, &val, 1); -} diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index 1d54b7542b..9ef95caa89 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -7,6 +7,9 @@ #define LOG_CATEGORY UCLASS_QFW #include <common.h> +#include <bootdev.h> +#include <bootflow.h> +#include <bootmeth.h> #include <command.h> #include <errno.h> #include <log.h> @@ -310,8 +313,92 @@ int qfw_register(struct udevice *dev) return 0; } +static int qfw_post_bind(struct udevice *dev) +{ + int ret; + + ret = bootdev_setup_for_dev(dev, "qfw_bootdev"); + if (ret) + return log_msg_ret("dev", ret); + + return 0; +} + +static int qfw_get_bootflow(struct udevice *dev, struct bootflow_iter *iter, + struct bootflow *bflow) +{ + const struct udevice *media = dev_get_parent(dev); + int ret; + + if (!CONFIG_IS_ENABLED(BOOTSTD)) + return -ENOSYS; + + log_debug("media=%s\n", media->name); + ret = bootmeth_check(bflow->method, iter); + if (ret) + return log_msg_ret("check", ret); + + log_debug("iter->part=%d\n", iter->part); + + /* We only support the whole device, not partitions */ + if (iter->part) + return log_msg_ret("max", -ESHUTDOWN); + + log_debug("reading bootflow with method: %s\n", bflow->method->name); + ret = bootmeth_read_bootflow(bflow->method, bflow); + if (ret) + return log_msg_ret("method", ret); + + return 0; +} + +static int qfw_bootdev_bind(struct udevice *dev) +{ + struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev); + + ucp->prio = BOOTDEVP_4_SCAN_FAST; + + return 0; +} + +static int qfw_bootdev_hunt(struct bootdev_hunter *info, bool show) +{ + int ret; + + ret = uclass_probe_all(UCLASS_QFW); + if (ret && ret != -ENOENT) + return log_msg_ret("vir", ret); + + return 0; +} + UCLASS_DRIVER(qfw) = { .id = UCLASS_QFW, .name = "qfw", + .post_bind = qfw_post_bind, .per_device_auto = sizeof(struct qfw_dev), }; + +struct bootdev_ops qfw_bootdev_ops = { + .get_bootflow = qfw_get_bootflow, +}; + +static const struct udevice_id qfw_bootdev_ids[] = { + { .compatible = "u-boot,bootdev-qfw" }, + { } +}; + +U_BOOT_DRIVER(qfw_bootdev) = { + .name = "qfw_bootdev", + .id = UCLASS_BOOTDEV, + .ops = &qfw_bootdev_ops, + .bind = qfw_bootdev_bind, + .of_match = qfw_bootdev_ids, +}; + +BOOTDEV_HUNTER(qfw_bootdev_hunter) = { + .prio = BOOTDEVP_4_SCAN_FAST, + .uclass = UCLASS_QFW, + .hunt = qfw_bootdev_hunt, + .drv = DM_DRIVER_REF(qfw_bootdev), +}; diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3a664c2ebb..3dc757108d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -46,7 +46,7 @@ obj-$(CONFIG_MMC_MXS) += mxsmmc.o obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o obj-$(CONFIG_MMC_OWL) += owl_mmc.o obj-$(CONFIG_MMC_PCI) += pci_mmc.o -obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o +obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o obj-$(CONFIG_MMC_SANDBOX) += sandbox_mmc.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SH_SDHI) += sh_sdhi.o diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 210703ea46..dde251c87b 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -247,7 +247,7 @@ static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd, static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data, u32 quirk, uint retries) { - if (CONFIG_IS_ENABLED(MMC_QUIRKS) && mmc->quirks & quirk) + if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk) return mmc_send_cmd_retry(mmc, cmd, data, retries); else return mmc_send_cmd(mmc, cmd, data); @@ -3127,9 +3127,10 @@ int mmc_init_device(int num) #endif #ifdef CONFIG_CMD_BKOPS_ENABLE -int mmc_set_bkops_enable(struct mmc *mmc) +int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable) { int err; + u32 bit = autobkops ? BIT(1) : BIT(0); ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); err = mmc_send_ext_csd(mmc, ext_csd); @@ -3143,18 +3144,21 @@ int mmc_set_bkops_enable(struct mmc *mmc) return -EMEDIUMTYPE; } - if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { + if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) { puts("Background operations already enabled\n"); return 0; } - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, + enable ? bit : 0); if (err) { - puts("Failed to enable manual background operations\n"); + printf("Failed to %sable manual background operations\n", + enable ? "en" : "dis"); return err; } - puts("Enabled manual background operations\n"); + printf("%sabled %s background operations\n", + enable ? "En" : "Dis", autobkops ? "auto" : "manual"); return 0; } diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 9ad92648a3..4a1accebfc 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -71,39 +71,25 @@ #define CALIB_TABLE_MAX (RENESAS_SDHI_SCC_TMPPORT_CALIB_CODE_MASK + 1) -static const u8 r8a7795_calib_table[2][CALIB_TABLE_MAX] = { - { 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 5, 6, 6, 7, 11, - 15, 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 21 }, - { 3, 3, 4, 4, 5, 6, 6, 7, 8, 8, 9, 9, 10, 11, 12, 15, - 16, 16, 17, 17, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 22 } -}; - -static const u8 r8a7796_rev1_calib_table[2][CALIB_TABLE_MAX] = { - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 2, 3, 4, 9, - 15, 15, 15, 16, 16, 16, 16, 16, 17, 18, 19, 20, 21, 21, 22, 22 }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, - 2, 9, 16, 17, 17, 17, 18, 18, 18, 18, 19, 20, 21, 22, 23, 24} -}; - -static const u8 r8a7796_rev3_calib_table[2][CALIB_TABLE_MAX] = { - { 0, 0, 0, 0, 2, 3, 4, 4, 5, 6, 7, 7, 8, 9, 9, 10, - 11, 12, 13, 15, 16, 17, 17, 18, 19, 19, 20, 21, 21, 22, 23, 23 }, - { 1, 2, 2, 3, 4, 4, 5, 6, 6, 7, 8, 9, 9, 10, 11, 12, - 13, 14, 15, 16, 17, 17, 18, 19, 20, 20, 21, 22, 22, 23, 24, 24 } +static const u8 r8a7796_rev13_calib_table[2][CALIB_TABLE_MAX] = { + { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, + 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, + { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, + 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } }; static const u8 r8a77965_calib_table[2][CALIB_TABLE_MAX] = { - { 0, 1, 2, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, - 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 29 }, - { 0, 1, 2, 2, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15, - 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 31 } + { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, + { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, + 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } }; static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { 0, 0, 1, 2, 3, 4, 4, 4, 4, 5, 5, 6, 7, 8, 10, 11, - 12, 13, 14, 16, 17, 18, 18, 18, 19, 19, 20, 24, 26, 26, 26, 26 } + { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, + 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } }; static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) @@ -372,13 +358,21 @@ static int renesas_sdhi_hs400(struct udevice *dev) struct mmc *mmc = mmc_get_mmc_dev(dev); bool hs400 = (mmc->selected_mode == MMC_HS_400); int ret, taps = hs400 ? priv->nrtaps : 8; + const u32 sdn_rate = 200000000; + u32 sdnh_rate = 800000000; unsigned long new_tap; u32 reg; - if (taps == 4) /* HS400 on 4tap SoC needs different clock */ - ret = clk_set_rate(&priv->clk, 400000000); - else - ret = clk_set_rate(&priv->clk, 200000000); + if (clk_valid(&priv->clkh) && !priv->needs_clkh_fallback) { + /* HS400 on 4tap SoC => SDnH=400 MHz, SDn=200 MHz */ + if (taps == 4) + sdnh_rate /= 2; + ret = clk_set_rate(&priv->clkh, sdnh_rate); + if (ret < 0) + return ret; + } + + ret = clk_set_rate(&priv->clk, sdn_rate); if (ret < 0) return ret; @@ -843,6 +837,7 @@ static const struct udevice_id renesas_sdhi_match[] = { { .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS }, { .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS }, + { .compatible = "renesas,sdhi-r8a77961", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,rcar-gen3-sdhi", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS }, { .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS }, @@ -871,12 +866,16 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) struct tmio_sd_plat *plat = dev_get_plat(dev); - /* HS400 is not supported on H3 ES1.x and M3W ES1.0, ES1.1 */ + /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 1)) || ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() < 2))) + (rmobile_get_cpu_rev_fraction() <= 2)) || + (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) || + ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) && + (rmobile_get_cpu_rev_integer() <= 1)) || + (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) plat->cfg.host_caps &= ~MMC_MODE_HS400; /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */ @@ -888,35 +887,21 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965)) priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7); - /* H3 ES3.0 can use HS400 with manual adjustment */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() >= 3)) { - priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; - priv->adjust_hs400_calib_table = - r8a7795_calib_table[!rmobile_is_gen3_mmc0(priv)]; - } - - /* M3W ES1.2 can use HS400 with manual adjustment */ + /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() == 2)) { + (rmobile_get_cpu_rev_fraction() > 2)) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 3; + priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); priv->adjust_hs400_calib_table = - r8a7796_rev1_calib_table[!rmobile_is_gen3_mmc0(priv)]; + r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)]; } - /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */ + /* M3W+ bad taps */ if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() > 2)) { - priv->adjust_hs400_enable = true; - priv->adjust_hs400_offset = 0; + (rmobile_get_cpu_rev_integer() == 3)) priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); - priv->adjust_hs400_calib_table = - r8a7796_rev3_calib_table[!rmobile_is_gen3_mmc0(priv)]; - } /* M3N can use HS400 with manual adjustment */ if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) { @@ -934,12 +919,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)]; } - /* H3 ES1.x, ES2.0 and M3W ES1.0, ES1.1, ES1.2 uses 4 tuning taps */ + /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */ if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && (rmobile_get_cpu_rev_integer() <= 2)) || ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 2))) + (rmobile_get_cpu_rev_fraction() <= 3))) priv->nrtaps = 4; else priv->nrtaps = 8; @@ -953,6 +938,12 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD; else priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; + + /* V3M handles SD0H differently than other Gen3 SoCs */ + if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) + priv->needs_clkh_fallback = true; + else + priv->needs_clkh_fallback = false; } static int renesas_sdhi_probe(struct udevice *dev) @@ -984,6 +975,11 @@ static int renesas_sdhi_probe(struct udevice *dev) return ret; } + /* optional SDnH clock */ + ret = clk_get_by_name(dev, "clkh", &priv->clkh); + if (ret < 0) + dev_dbg(dev, "failed to get clkh\n"); + /* set to max rate */ ret = clk_set_rate(&priv->clk, 200000000); if (ret < 0) { diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index a80ad8329a..c6b250b9a1 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -396,6 +396,14 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } } + if (host->ops && host->ops->config_dll) { + ret = host->ops->config_dll(host, clock, false); + if (ret) { + printf("%s: Error while configuring dll\n", __func__); + return ret; + } + } + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { /* * Check if the Host Controller supports Programmable Clock @@ -439,6 +447,14 @@ int sdhci_set_clock(struct mmc *mmc, unsigned int clock) if (host->ops && host->ops->set_clock) host->ops->set_clock(host, div); + if (host->ops && host->ops->config_dll) { + ret = host->ops->config_dll(host, clock, true); + if (ret) { + printf("%s: Error while configuring dll\n", __func__); + return ret; + } + } + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; @@ -979,6 +995,10 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps |= MMC_CAP(UHS_SDR50); } + if ((host->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_HS400) && + (caps_1 & SDHCI_SUPPORT_HS400)) + cfg->host_caps |= MMC_CAP(MMC_HS_400); + if (caps_1 & SDHCI_SUPPORT_DDR50) cfg->host_caps |= MMC_CAP(UHS_DDR50); diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h index 59d5a0e22e..4d717d85de 100644 --- a/drivers/mmc/tmio-common.h +++ b/drivers/mmc/tmio-common.h @@ -138,8 +138,9 @@ struct tmio_sd_priv { #endif #if CONFIG_IS_ENABLED(CLK) struct clk clk; + struct clk clkh; #endif -#if CONFIG_IS_ENABLED(RENESAS_SDHI) +#if IS_ENABLED(CONFIG_RENESAS_SDHI) unsigned int smpcmp; u8 tap_set; u8 tap_num; @@ -151,6 +152,7 @@ struct tmio_sd_priv { u8 hs400_bad_tap; const u8 *adjust_hs400_calib_table; u32 quirks; + bool needs_clkh_fallback; #endif ulong (*clk_get_rate)(struct tmio_sd_priv *); }; diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index be4075c97a..91e309d275 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2013 - 2015 Xilinx, Inc. + * (C) Copyright 2013 - 2022, Xilinx, Inc. + * (C) Copyright 2022, Advanced Micro Devices, Inc. * * Xilinx Zynq SD Host Controller Interface */ @@ -16,6 +17,7 @@ #include <dm/device_compat.h> #include <linux/err.h> #include <linux/libfdt.h> +#include <linux/iopoll.h> #include <asm/types.h> #include <linux/math64.h> #include <asm/cache.h> @@ -48,6 +50,41 @@ #define SD0_OTAPDLYSEL_MASK GENMASK(5, 0) #define SD1_OTAPDLYSEL_MASK GENMASK(21, 16) +#define MIN_PHY_CLK_HZ 50000000 + +#define PHY_CTRL_REG1 0x270 +#define PHY_CTRL_ITAPDLY_ENA_MASK BIT(0) +#define PHY_CTRL_ITAPDLY_SEL_MASK GENMASK(5, 1) +#define PHY_CTRL_ITAPDLY_SEL_SHIFT 1 +#define PHY_CTRL_ITAP_CHG_WIN_MASK BIT(6) +#define PHY_CTRL_OTAPDLY_ENA_MASK BIT(8) +#define PHY_CTRL_OTAPDLY_SEL_MASK GENMASK(15, 12) +#define PHY_CTRL_OTAPDLY_SEL_SHIFT 12 +#define PHY_CTRL_STRB_SEL_MASK GENMASK(23, 16) +#define PHY_CTRL_STRB_SEL_SHIFT 16 +#define PHY_CTRL_TEST_CTRL_MASK GENMASK(31, 24) + +#define PHY_CTRL_REG2 0x274 +#define PHY_CTRL_EN_DLL_MASK BIT(0) +#define PHY_CTRL_DLL_RDY_MASK BIT(1) +#define PHY_CTRL_FREQ_SEL_MASK GENMASK(6, 4) +#define PHY_CTRL_FREQ_SEL_SHIFT 4 +#define PHY_CTRL_SEL_DLY_TX_MASK BIT(16) +#define PHY_CTRL_SEL_DLY_RX_MASK BIT(17) +#define FREQSEL_200M_170M 0x0 +#define FREQSEL_170M_140M 0x1 +#define FREQSEL_140M_110M 0x2 +#define FREQSEL_110M_80M 0x3 +#define FREQSEL_80M_50M 0x4 +#define FREQSEL_275M_250M 0x5 +#define FREQSEL_250M_225M 0x6 +#define FREQSEL_225M_200M 0x7 +#define PHY_DLL_TIMEOUT_MS 100 + +#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN 39 +#define VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL 146 +#define VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL 0X77 + struct arasan_sdhci_clk_data { int clk_phase_in[MMC_TIMING_MMC_HS400 + 1]; int clk_phase_out[MMC_TIMING_MMC_HS400 + 1]; @@ -64,6 +101,7 @@ struct arasan_sdhci_priv { u32 node_id; u8 bank; u8 no_1p8; + bool internal_phy_reg; struct reset_ctl_bulk resets; }; @@ -84,7 +122,7 @@ __weak int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) return 1; } -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) /* Default settings for ZynqMP Clock Phases */ static const u32 zynqmp_iclk_phases[] = {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}; @@ -97,6 +135,12 @@ static const u32 versal_iclk_phases[] = {0, 132, 132, 0, 132, static const u32 versal_oclk_phases[] = {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}; +/* Default settings for versal-net eMMC Clock Phases */ +static const u32 versal_net_emmc_iclk_phases[] = {0, 0, 0, 0, 0, 0, 0, 0, 39, + 0, 0}; +static const u32 versal_net_emmc_oclk_phases[] = {0, 113, 0, 0, 0, 0, 0, 0, + 113, 79, 45}; + static const u8 mode2timing[] = { [MMC_LEGACY] = MMC_TIMING_LEGACY, [MMC_HS] = MMC_TIMING_MMC_HS, @@ -109,8 +153,124 @@ static const u8 mode2timing[] = { [UHS_DDR50] = MMC_TIMING_UHS_DDR50, [UHS_SDR104] = MMC_TIMING_UHS_SDR104, [MMC_HS_200] = MMC_TIMING_MMC_HS200, + [MMC_HS_400] = MMC_TIMING_MMC_HS400, }; +#if defined(CONFIG_ARCH_VERSAL_NET) +/** + * arasan_phy_set_delaychain - Set eMMC delay chain based Input/Output clock + * + * @host: Pointer to the sdhci_host structure + * @enable: Enable or disable Delay chain based Tx and Rx clock + * Return: None + * + * Enable or disable eMMC delay chain based Input and Output clock in + * PHY_CTRL_REG2 + */ +static void arasan_phy_set_delaychain(struct sdhci_host *host, bool enable) +{ + u32 reg; + + reg = sdhci_readw(host, PHY_CTRL_REG2); + if (enable) + reg |= PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK; + else + reg &= ~(PHY_CTRL_SEL_DLY_TX_MASK | PHY_CTRL_SEL_DLY_RX_MASK); + + sdhci_writew(host, reg, PHY_CTRL_REG2); +} + +/** + * arasan_phy_set_dll - Set eMMC DLL clock + * + * @host: Pointer to the sdhci_host structure + * @enable: Enable or disable DLL clock + * Return: 0 if success or timeout error + * + * Enable or disable eMMC DLL clock in PHY_CTRL_REG2. When DLL enable is + * set, wait till DLL is locked + */ +static int arasan_phy_set_dll(struct sdhci_host *host, bool enable) +{ + u32 reg; + + reg = sdhci_readw(host, PHY_CTRL_REG2); + if (enable) + reg |= PHY_CTRL_EN_DLL_MASK; + else + reg &= ~PHY_CTRL_EN_DLL_MASK; + + sdhci_writew(host, reg, PHY_CTRL_REG2); + + /* If DLL is disabled return success */ + if (!enable) + return 0; + + /* If DLL is enabled wait till DLL loop is locked, which is + * indicated by dll_rdy bit(bit1) in PHY_CTRL_REG2 + */ + return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg, + (reg & PHY_CTRL_DLL_RDY_MASK), + 1000 * PHY_DLL_TIMEOUT_MS); +} + +/** + * arasan_phy_dll_set_freq - Select frequency range of DLL for eMMC + * + * @host: Pointer to the sdhci_host structure + * @clock: clock value + * Return: None + * + * Set frequency range bits based on the selected clock for eMMC + */ +static void arasan_phy_dll_set_freq(struct sdhci_host *host, int clock) +{ + u32 reg, freq_sel, freq; + + freq = DIV_ROUND_CLOSEST(clock, 1000000); + if (freq <= 200 && freq > 170) + freq_sel = FREQSEL_200M_170M; + else if (freq <= 170 && freq > 140) + freq_sel = FREQSEL_170M_140M; + else if (freq <= 140 && freq > 110) + freq_sel = FREQSEL_140M_110M; + else if (freq <= 110 && freq > 80) + freq_sel = FREQSEL_110M_80M; + else + freq_sel = FREQSEL_80M_50M; + + reg = sdhci_readw(host, PHY_CTRL_REG2); + reg &= ~PHY_CTRL_FREQ_SEL_MASK; + reg |= (freq_sel << PHY_CTRL_FREQ_SEL_SHIFT); + sdhci_writew(host, reg, PHY_CTRL_REG2); +} + +static int arasan_sdhci_config_dll(struct sdhci_host *host, unsigned int clock, bool enable) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev); + + if (enable) { + if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ && enable) + arasan_phy_set_dll(host, 1); + return 0; + } + + if (priv->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) { + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + arasan_phy_set_dll(host, 0); + arasan_phy_set_delaychain(host, 0); + arasan_phy_dll_set_freq(host, clock); + return 0; + } + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + arasan_phy_set_delaychain(host, 1); + + return 0; +} +#endif + static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay) { int ret; @@ -585,6 +745,101 @@ static int sdhci_versal_sampleclk_set_phase(struct sdhci_host *host, return 0; } +/** + * sdhci_versal_net_emmc_sdcardclk_set_phase - Set eMMC Output Clock Tap Delays + * + * @host: Pointer to the sdhci_host structure. + * @degrees: The clock phase shift between 0 - 359. + * Return: 0 + * + * Set eMMC Output Clock Tap Delays for Output path + */ +static int sdhci_versal_net_emmc_sdcardclk_set_phase(struct sdhci_host *host, int degrees) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + int timing = mode2timing[mmc->selected_mode]; + u8 tap_delay, tap_max = 0; + u32 regval; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_MMC_DDR52: + tap_max = 16; + break; + case MMC_TIMING_MMC_HS200: + case MMC_TIMING_MMC_HS400: + /* For 200MHz clock, 32 Taps are available */ + tap_max = 32; + break; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + /* Set the Clock Phase */ + if (tap_delay) { + regval = sdhci_readl(host, PHY_CTRL_REG1); + regval |= PHY_CTRL_OTAPDLY_ENA_MASK; + sdhci_writel(host, regval, PHY_CTRL_REG1); + regval &= ~PHY_CTRL_OTAPDLY_SEL_MASK; + regval |= tap_delay << PHY_CTRL_OTAPDLY_SEL_SHIFT; + sdhci_writel(host, regval, PHY_CTRL_REG1); + } + + return 0; +} + +/** + * sdhci_versal_net_emmc_sampleclk_set_phase - Set eMMC Input Clock Tap Delays + * + * @host: Pointer to the sdhci_host structure. + * @degrees: The clock phase shift between 0 - 359. + * Return: 0 + * + * Set eMMC Input Clock Tap Delays for Input path. If HS400 is selected, + * set strobe90 and strobe180 in PHY_CTRL_REG1. + */ +static int sdhci_versal_net_emmc_sampleclk_set_phase(struct sdhci_host *host, int degrees) +{ + struct mmc *mmc = (struct mmc *)host->mmc; + int timing = mode2timing[mmc->selected_mode]; + u8 tap_delay, tap_max = 0; + u32 regval; + + switch (timing) { + case MMC_TIMING_MMC_HS: + case MMC_TIMING_MMC_DDR52: + tap_max = 32; + break; + case MMC_TIMING_MMC_HS400: + /* Strobe select tap point for strb90 and strb180 */ + regval = sdhci_readl(host, PHY_CTRL_REG1); + regval &= ~PHY_CTRL_STRB_SEL_MASK; + regval |= VERSAL_NET_PHY_CTRL_STRB90_STRB180_VAL << PHY_CTRL_STRB_SEL_SHIFT; + sdhci_writel(host, regval, PHY_CTRL_REG1); + break; + default: + break; + } + + tap_delay = (degrees * tap_max) / 360; + /* Set the Clock Phase */ + if (tap_delay) { + regval = sdhci_readl(host, PHY_CTRL_REG1); + regval |= PHY_CTRL_ITAP_CHG_WIN_MASK; + sdhci_writel(host, regval, PHY_CTRL_REG1); + regval |= PHY_CTRL_ITAPDLY_ENA_MASK; + sdhci_writel(host, regval, PHY_CTRL_REG1); + regval &= ~PHY_CTRL_ITAPDLY_SEL_MASK; + regval |= tap_delay << PHY_CTRL_ITAPDLY_SEL_SHIFT; + sdhci_writel(host, regval, PHY_CTRL_REG1); + regval &= ~PHY_CTRL_ITAP_CHG_WIN_MASK; + sdhci_writel(host, regval, PHY_CTRL_REG1); + } + + return 0; +} + static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) { struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev); @@ -616,6 +871,19 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) ret = sdhci_versal_sdcardclk_set_phase(host, oclk_phase); if (ret) return ret; + } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { + if (mmc->clock >= MIN_PHY_CLK_HZ) + if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) + iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL; + + ret = sdhci_versal_net_emmc_sampleclk_set_phase(host, iclk_phase); + if (ret) + return ret; + + ret = sdhci_versal_net_emmc_sdcardclk_set_phase(host, oclk_phase); + if (ret) + return ret; } return 0; @@ -678,6 +946,14 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } } + if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && + device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { + for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { + clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; + clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i]; + } + } + arasan_dt_read_clk_phase(dev, MMC_TIMING_LEGACY, "clk-phase-legacy"); arasan_dt_read_clk_phase(dev, MMC_TIMING_MMC_HS, @@ -706,6 +982,9 @@ static const struct sdhci_ops arasan_ops = { .platform_execute_tuning = &arasan_sdhci_execute_tuning, .set_delay = &arasan_sdhci_set_tapdelay, .set_control_reg = &sdhci_set_control_reg, +#if defined(CONFIG_ARCH_VERSAL_NET) + .config_dll = &arasan_sdhci_config_dll, +#endif }; #endif @@ -822,6 +1101,8 @@ static int arasan_sdhci_probe(struct udevice *dev) } } #endif + if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) + priv->internal_phy_reg = true; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) { @@ -853,6 +1134,10 @@ static int arasan_sdhci_probe(struct udevice *dev) if (priv->no_1p8) host->quirks |= SDHCI_QUIRK_NO_1_8_V; + if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) && + device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) + host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400; + plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; ret = mmc_of_parse(dev, &plat->cfg); @@ -905,7 +1190,7 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev) priv->host->name = dev->name; -#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) +#if defined(CONFIG_ARCH_ZYNQMP) || defined(CONFIG_ARCH_VERSAL) || defined(CONFIG_ARCH_VERSAL_NET) priv->host->ops = &arasan_ops; arasan_dt_parse_clk_phases(dev); #endif @@ -933,6 +1218,7 @@ static int arasan_sdhci_bind(struct udevice *dev) static const struct udevice_id arasan_sdhci_ids[] = { { .compatible = "arasan,sdhci-8.9a" }, + { .compatible = "xlnx,versal-net-5.1-emmc" }, { } }; diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index 7320d581e2..666323e221 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -56,8 +56,6 @@ obj-$(CONFIG_NAND_DENALI) += denali.o obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o -obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o -obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o @@ -70,11 +68,9 @@ obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o obj-$(CONFIG_NAND_OCTEONTX) += octeontx_nand.o obj-$(CONFIG_NAND_OCTEONTX_HW_ECC) += octeontx_bch.o obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o -obj-$(CONFIG_NAND_SPEAR) += spr_nand.o obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o -obj-$(CONFIG_NAND_PLAT) += nand_plat.o obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o obj-$(CONFIG_NAND_MXIC) += mxic_nand.o obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c deleted file mode 100644 index 91cc133953..0000000000 --- a/drivers/mtd/nand/raw/fsl_upm.c +++ /dev/null @@ -1,187 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * FSL UPM NAND driver - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov <avorontsov@ru.mvista.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/fsl_upm.h> -#include <nand.h> - -static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) -{ - clrsetbits_be32(upm->mxmr, MxMR_MAD_MSK, MxMR_OP_RUNP | pat_offset); - (void)in_be32(upm->mxmr); -} - -static void fsl_upm_end_pattern(struct fsl_upm *upm) -{ - clrbits_be32(upm->mxmr, MxMR_OP_RUNP); - - while (in_be32(upm->mxmr) & MxMR_OP_RUNP) - eieio(); -} - -static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, - void __iomem *io_addr, u32 mar) -{ - out_be32(upm->mar, mar); - (void)in_be32(upm->mar); - switch (width) { - case 8: - out_8(io_addr, 0x0); - break; - case 16: - out_be16(io_addr, 0x0); - break; - case 32: - out_be32(io_addr, 0x0); - break; - } -} - -static void fun_wait(struct fsl_upm_nand *fun) -{ - if (fun->dev_ready) { - while (!fun->dev_ready(fun->chip_nr)) - debug("unexpected busy state\n"); - } else { - /* - * If the R/B pin is not connected, - * a short delay is necessary. - */ - udelay(1); - } -} - -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 -static void fun_select_chip(struct mtd_info *mtd, int chip_nr) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - if (chip_nr >= 0) { - fun->chip_nr = chip_nr; - chip->IO_ADDR_R = chip->IO_ADDR_W = - fun->upm.io_addr + fun->chip_offset * chip_nr; - } else if (chip_nr == -1) { - chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); - } -} -#endif - -static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - void __iomem *io_addr; - u32 mar; - - if (!(ctrl & fun->last_ctrl)) { - fsl_upm_end_pattern(&fun->upm); - - if (cmd == NAND_CMD_NONE) - return; - - fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE); - } - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_ALE) - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - else if (ctrl & NAND_CLE) - fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - } - - mar = cmd << (32 - fun->width); - io_addr = fun->upm.io_addr; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - if (fun->chip_nr > 0) { - io_addr += fun->chip_offset * fun->chip_nr; - if (fun->upm_mar_chip_offset) - mar |= fun->upm_mar_chip_offset * fun->chip_nr; - } -#endif - fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar); - - /* - * Some boards/chips needs this. At least the MPC8360E-RDK - * needs it. Probably weird chip, because I don't see any - * need for this on MPC8555E + Samsung K9F1G08U0A. Usually - * here are 0-2 unexpected busy states per block read. - */ - if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN) - fun_wait(fun); -} - -static u8 upm_nand_read_byte(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - - return in_8(chip->IO_ADDR_R); -} - -static void upm_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - for (i = 0; i < len; i++) { - out_8(chip->IO_ADDR_W, buf[i]); - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE) - fun_wait(fun); - } - - if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER) - fun_wait(fun); -} - -static void upm_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - struct nand_chip *chip = mtd_to_nand(mtd); - - for (i = 0; i < len; i++) - buf[i] = in_8(chip->IO_ADDR_R); -} - -static int nand_dev_ready(struct mtd_info *mtd) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct fsl_upm_nand *fun = nand_get_controller_data(chip); - - return fun->dev_ready(fun->chip_nr); -} - -int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) -{ - if (fun->width != 8 && fun->width != 16 && fun->width != 32) - return -ENOSYS; - - fun->last_ctrl = NAND_CLE; - - nand_set_controller_data(chip, fun); - chip->chip_delay = fun->chip_delay; - chip->ecc.mode = NAND_ECC_SOFT; - chip->cmd_ctrl = fun_cmd_ctrl; -#if CONFIG_SYS_NAND_MAX_CHIPS > 1 - chip->select_chip = fun_select_chip; -#endif - chip->read_byte = upm_nand_read_byte; - chip->read_buf = upm_nand_read_buf; - chip->write_buf = upm_nand_write_buf; - if (fun->dev_ready) - chip->dev_ready = nand_dev_ready; - - return 0; -} diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c deleted file mode 100644 index d795864949..0000000000 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ /dev/null @@ -1,470 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. - * - * (C) Copyright 2012 - * Amit Virdi, STMicroelectronics, amit.virdi@st.com. - */ - -#include <common.h> -#include <nand.h> -#include <asm/io.h> -#include <linux/bitops.h> -#include <linux/err.h> -#include <linux/mtd/nand_ecc.h> -#include <linux/mtd/rawnand.h> -#include <linux/mtd/fsmc_nand.h> -#include <asm/arch/hardware.h> - -static u32 fsmc_version; -static struct fsmc_regs *const fsmc_regs_p = (struct fsmc_regs *) - CONFIG_SYS_FSMC_BASE; - -/* - * ECC4 and ECC1 have 13 bytes and 3 bytes of ecc respectively for 512 bytes of - * data. ECC4 can correct up to 8 bits in 512 bytes of data while ECC1 can - * correct 1 bit in 512 bytes - */ - -static struct nand_ecclayout fsmc_ecc4_lp_layout = { - .eccbytes = 104, - .eccpos = { 2, 3, 4, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, - 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, - 34, 35, 36, 37, 38, 39, 40, - 41, 42, 43, 44, 45, 46, - 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, - 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, - 82, 83, 84, 85, 86, 87, 88, - 89, 90, 91, 92, 93, 94, - 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, - 114, 115, 116, 117, 118, 119, 120, - 121, 122, 123, 124, 125, 126 - }, - .oobfree = { - {.offset = 15, .length = 3}, - {.offset = 31, .length = 3}, - {.offset = 47, .length = 3}, - {.offset = 63, .length = 3}, - {.offset = 79, .length = 3}, - {.offset = 95, .length = 3}, - {.offset = 111, .length = 3}, - {.offset = 127, .length = 1} - } -}; - -/* - * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes - * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118 - * bytes are free for use. - */ -static struct nand_ecclayout fsmc_ecc4_224_layout = { - .eccbytes = 104, - .eccpos = { 2, 3, 4, 5, 6, 7, 8, - 9, 10, 11, 12, 13, 14, - 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, - 34, 35, 36, 37, 38, 39, 40, - 41, 42, 43, 44, 45, 46, - 50, 51, 52, 53, 54, 55, 56, - 57, 58, 59, 60, 61, 62, - 66, 67, 68, 69, 70, 71, 72, - 73, 74, 75, 76, 77, 78, - 82, 83, 84, 85, 86, 87, 88, - 89, 90, 91, 92, 93, 94, - 98, 99, 100, 101, 102, 103, 104, - 105, 106, 107, 108, 109, 110, - 114, 115, 116, 117, 118, 119, 120, - 121, 122, 123, 124, 125, 126 - }, - .oobfree = { - {.offset = 15, .length = 3}, - {.offset = 31, .length = 3}, - {.offset = 47, .length = 3}, - {.offset = 63, .length = 3}, - {.offset = 79, .length = 3}, - {.offset = 95, .length = 3}, - {.offset = 111, .length = 3}, - {.offset = 127, .length = 97} - } -}; - -/* - * ECC placement definitions in oobfree type format - * There are 13 bytes of ecc for every 512 byte block and it has to be read - * consecutively and immediately after the 512 byte data block for hardware to - * generate the error bit offsets in 512 byte data - * Managing the ecc bytes in the following way makes it easier for software to - * read ecc bytes consecutive to data bytes. This way is similar to - * oobfree structure maintained already in u-boot nand driver - */ -static struct fsmc_eccplace fsmc_eccpl_lp = { - .eccplace = { - {.offset = 2, .length = 13}, - {.offset = 18, .length = 13}, - {.offset = 34, .length = 13}, - {.offset = 50, .length = 13}, - {.offset = 66, .length = 13}, - {.offset = 82, .length = 13}, - {.offset = 98, .length = 13}, - {.offset = 114, .length = 13} - } -}; - -static struct nand_ecclayout fsmc_ecc4_sp_layout = { - .eccbytes = 13, - .eccpos = { 0, 1, 2, 3, 6, 7, 8, - 9, 10, 11, 12, 13, 14 - }, - .oobfree = { - {.offset = 15, .length = 1}, - } -}; - -static struct fsmc_eccplace fsmc_eccpl_sp = { - .eccplace = { - {.offset = 0, .length = 4}, - {.offset = 6, .length = 9} - } -}; - -static struct nand_ecclayout fsmc_ecc1_layout = { - .eccbytes = 24, - .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52, - 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116}, - .oobfree = { - {.offset = 8, .length = 8}, - {.offset = 24, .length = 8}, - {.offset = 40, .length = 8}, - {.offset = 56, .length = 8}, - {.offset = 72, .length = 8}, - {.offset = 88, .length = 8}, - {.offset = 104, .length = 8}, - {.offset = 120, .length = 8} - } -}; - -/* Count the number of 0's in buff upto a max of max_bits */ -static int count_written_bits(uint8_t *buff, int size, int max_bits) -{ - int k, written_bits = 0; - - for (k = 0; k < size; k++) { - written_bits += hweight8(~buff[k]); - if (written_bits > max_bits) - break; - } - - return written_bits; -} - -static void fsmc_nand_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - ulong IO_ADDR_W; - - if (ctrl & NAND_CTRL_CHANGE) { - IO_ADDR_W = (ulong)this->IO_ADDR_W; - - IO_ADDR_W &= ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE); - if (ctrl & NAND_CLE) - IO_ADDR_W |= CONFIG_SYS_NAND_CLE; - if (ctrl & NAND_ALE) - IO_ADDR_W |= CONFIG_SYS_NAND_ALE; - - if (ctrl & NAND_NCE) { - writel(readl(&fsmc_regs_p->pc) | - FSMC_ENABLE, &fsmc_regs_p->pc); - } else { - writel(readl(&fsmc_regs_p->pc) & - ~FSMC_ENABLE, &fsmc_regs_p->pc); - } - this->IO_ADDR_W = (void *)IO_ADDR_W; - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -static int fsmc_bch8_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - /* The calculated ecc is actually the correction index in data */ - u32 err_idx[8]; - u32 num_err, i; - u32 ecc1, ecc2, ecc3, ecc4; - - num_err = (readl(&fsmc_regs_p->sts) >> 10) & 0xF; - - if (likely(num_err == 0)) - return 0; - - if (unlikely(num_err > 8)) { - /* - * This is a temporary erase check. A newly erased page read - * would result in an ecc error because the oob data is also - * erased to FF and the calculated ecc for an FF data is not - * FF..FF. - * This is a workaround to skip performing correction in case - * data is FF..FF - * - * Logic: - * For every page, each bit written as 0 is counted until these - * number of bits are greater than 8 (the maximum correction - * capability of FSMC for each 512 + 13 bytes) - */ - - int bits_ecc = count_written_bits(read_ecc, 13, 8); - int bits_data = count_written_bits(dat, 512, 8); - - if ((bits_ecc + bits_data) <= 8) { - if (bits_data) - memset(dat, 0xff, 512); - return bits_data + bits_ecc; - } - - return -EBADMSG; - } - - ecc1 = readl(&fsmc_regs_p->ecc1); - ecc2 = readl(&fsmc_regs_p->ecc2); - ecc3 = readl(&fsmc_regs_p->ecc3); - ecc4 = readl(&fsmc_regs_p->sts); - - err_idx[0] = (ecc1 >> 0) & 0x1FFF; - err_idx[1] = (ecc1 >> 13) & 0x1FFF; - err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); - err_idx[3] = (ecc2 >> 7) & 0x1FFF; - err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); - err_idx[5] = (ecc3 >> 1) & 0x1FFF; - err_idx[6] = (ecc3 >> 14) & 0x1FFF; - err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); - - i = 0; - while (i < num_err) { - err_idx[i] ^= 3; - - if (err_idx[i] < 512 * 8) - __change_bit(err_idx[i], dat); - - i++; - } - - return num_err; -} - -static int fsmc_read_hwecc(struct mtd_info *mtd, - const u_char *data, u_char *ecc) -{ - u_int ecc_tmp; - int timeout = CONFIG_SYS_HZ; - ulong start; - - switch (fsmc_version) { - case FSMC_VER8: - start = get_timer(0); - while (get_timer(start) < timeout) { - /* - * Busy waiting for ecc computation - * to finish for 512 bytes - */ - if (readl(&fsmc_regs_p->sts) & FSMC_CODE_RDY) - break; - } - - ecc_tmp = readl(&fsmc_regs_p->ecc1); - ecc[0] = (u_char) (ecc_tmp >> 0); - ecc[1] = (u_char) (ecc_tmp >> 8); - ecc[2] = (u_char) (ecc_tmp >> 16); - ecc[3] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->ecc2); - ecc[4] = (u_char) (ecc_tmp >> 0); - ecc[5] = (u_char) (ecc_tmp >> 8); - ecc[6] = (u_char) (ecc_tmp >> 16); - ecc[7] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->ecc3); - ecc[8] = (u_char) (ecc_tmp >> 0); - ecc[9] = (u_char) (ecc_tmp >> 8); - ecc[10] = (u_char) (ecc_tmp >> 16); - ecc[11] = (u_char) (ecc_tmp >> 24); - - ecc_tmp = readl(&fsmc_regs_p->sts); - ecc[12] = (u_char) (ecc_tmp >> 16); - break; - - default: - ecc_tmp = readl(&fsmc_regs_p->ecc1); - ecc[0] = (u_char) (ecc_tmp >> 0); - ecc[1] = (u_char) (ecc_tmp >> 8); - ecc[2] = (u_char) (ecc_tmp >> 16); - break; - } - - return 0; -} - -void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) -{ - writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCPLEN_256, - &fsmc_regs_p->pc); - writel(readl(&fsmc_regs_p->pc) & ~FSMC_ECCEN, - &fsmc_regs_p->pc); - writel(readl(&fsmc_regs_p->pc) | FSMC_ECCEN, - &fsmc_regs_p->pc); -} - -/* - * fsmc_read_page_hwecc - * @mtd: mtd info structure - * @chip: nand chip info structure - * @buf: buffer to store read data - * @oob_required: caller expects OOB data read to chip->oob_poi - * @page: page number to read - * - * This routine is needed for fsmc verison 8 as reading from NAND chip has to be - * performed in a strict sequence as follows: - * data(512 byte) -> ecc(13 byte) - * After this read, fsmc hardware generates and reports error data bits(upto a - * max of 8 bits) - */ -static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, - uint8_t *buf, int oob_required, int page) -{ - struct fsmc_eccplace *fsmc_eccpl; - int i, j, s, stat, eccsize = chip->ecc.size; - int eccbytes = chip->ecc.bytes; - int eccsteps = chip->ecc.steps; - uint8_t *p = buf; - uint8_t *ecc_calc = chip->buffers->ecccalc; - uint8_t *ecc_code = chip->buffers->ecccode; - int off, len, group = 0; - uint8_t oob[13] __attribute__ ((aligned (2))); - - /* Differentiate between small and large page ecc place definitions */ - if (mtd->writesize == 512) - fsmc_eccpl = &fsmc_eccpl_sp; - else - fsmc_eccpl = &fsmc_eccpl_lp; - - for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { - - chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); - chip->ecc.hwctl(mtd, NAND_ECC_READ); - chip->read_buf(mtd, p, eccsize); - - for (j = 0; j < eccbytes;) { - off = fsmc_eccpl->eccplace[group].offset; - len = fsmc_eccpl->eccplace[group].length; - group++; - - /* - * length is intentionally kept a higher multiple of 2 - * to read at least 13 bytes even in case of 16 bit NAND - * devices - */ - if (chip->options & NAND_BUSWIDTH_16) - len = roundup(len, 2); - chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); - chip->read_buf(mtd, oob + j, len); - j += len; - } - - memcpy(&ecc_code[i], oob, 13); - chip->ecc.calculate(mtd, p, &ecc_calc[i]); - - stat = chip->ecc.correct(mtd, p, &ecc_code[i], - &ecc_calc[i]); - if (stat < 0) - mtd->ecc_stats.failed++; - else - mtd->ecc_stats.corrected += stat; - } - - return 0; -} - -int fsmc_nand_init(struct nand_chip *nand) -{ - static int chip_nr; - struct mtd_info *mtd; - u32 peripid2 = readl(&fsmc_regs_p->peripid2); - - fsmc_version = (peripid2 >> FSMC_REVISION_SHFT) & - FSMC_REVISION_MSK; - - writel(readl(&fsmc_regs_p->ctrl) | FSMC_WP, &fsmc_regs_p->ctrl); - -#if defined(CONFIG_SYS_FSMC_NAND_16BIT) - writel(FSMC_DEVWID_16 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->pc); -#elif defined(CONFIG_SYS_FSMC_NAND_8BIT) - writel(FSMC_DEVWID_8 | FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON, - &fsmc_regs_p->pc); -#else -#error Please define CONFIG_SYS_FSMC_NAND_16BIT or CONFIG_SYS_FSMC_NAND_8BIT -#endif - writel(readl(&fsmc_regs_p->pc) | FSMC_TCLR_1 | FSMC_TAR_1, - &fsmc_regs_p->pc); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->comm); - writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0, - &fsmc_regs_p->attrib); - - nand->options = 0; -#if defined(CONFIG_SYS_FSMC_NAND_16BIT) - nand->options |= NAND_BUSWIDTH_16; -#endif - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = 512; - nand->ecc.calculate = fsmc_read_hwecc; - nand->ecc.hwctl = fsmc_enable_hwecc; - nand->cmd_ctrl = fsmc_nand_hwcontrol; - nand->IO_ADDR_R = nand->IO_ADDR_W = - (void __iomem *)CFG_SYS_NAND_BASE; - nand->badblockbits = 7; - - mtd = nand_to_mtd(nand); - - switch (fsmc_version) { - case FSMC_VER8: - nand->ecc.bytes = 13; - nand->ecc.strength = 8; - nand->ecc.correct = fsmc_bch8_correct_data; - nand->ecc.read_page = fsmc_read_page_hwecc; - if (mtd->writesize == 512) - nand->ecc.layout = &fsmc_ecc4_sp_layout; - else { - if (mtd->oobsize == 224) - nand->ecc.layout = &fsmc_ecc4_224_layout; - else - nand->ecc.layout = &fsmc_ecc4_lp_layout; - } - - break; - default: - nand->ecc.bytes = 3; - nand->ecc.strength = 1; - nand->ecc.layout = &fsmc_ecc1_layout; - nand->ecc.correct = nand_correct_data; - break; - } - - /* Detect NAND chips */ - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) - return -ENXIO; - - if (nand_scan_tail(mtd)) - return -ENXIO; - - if (nand_register(chip_nr++, mtd)) - return -ENXIO; - - return 0; -} diff --git a/drivers/mtd/nand/raw/nand_plat.c b/drivers/mtd/nand/raw/nand_plat.c deleted file mode 100644 index 81e7aa218d..0000000000 --- a/drivers/mtd/nand/raw/nand_plat.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Genericish driver for memory mapped NAND devices - * - * Copyright (c) 2006-2009 Analog Devices Inc. - * Licensed under the GPL-2 or later. - */ - -/* Your board must implement the following macros: - * NAND_PLAT_WRITE_CMD(chip, cmd) - * NAND_PLAT_WRITE_ADR(chip, cmd) - * NAND_PLAT_INIT() - * - * It may also implement the following: - * NAND_PLAT_DEV_READY(chip) - */ - -#include <common.h> -#include <linux/mtd/rawnand.h> -#include <asm/io.h> -#ifdef NAND_PLAT_GPIO_DEV_READY -# include <asm/gpio.h> -# define NAND_PLAT_DEV_READY(chip) gpio_get_value(NAND_PLAT_GPIO_DEV_READY) -#endif - -#include <nand.h> - -static void plat_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd_to_nand(mtd); - - if (cmd == NAND_CMD_NONE) - return; - - if (ctrl & NAND_CLE) - NAND_PLAT_WRITE_CMD(this, cmd); - else - NAND_PLAT_WRITE_ADR(this, cmd); -} - -#ifdef NAND_PLAT_DEV_READY -static int plat_dev_ready(struct mtd_info *mtd) -{ - return NAND_PLAT_DEV_READY((struct nand_chip *)mtd_to_nand(mtd)); -} -#else -# define plat_dev_ready NULL -#endif - -int board_nand_init(struct nand_chip *nand) -{ -#ifdef NAND_PLAT_GPIO_DEV_READY - gpio_request(NAND_PLAT_GPIO_DEV_READY, "nand-plat"); - gpio_direction_input(NAND_PLAT_GPIO_DEV_READY); -#endif - -#ifdef NAND_PLAT_INIT - NAND_PLAT_INIT(); -#endif - - nand->cmd_ctrl = plat_cmd_ctrl; - nand->dev_ready = plat_dev_ready; - nand->ecc.mode = NAND_ECC_SOFT; - - return 0; -} diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7873538cc2..ceadee98a1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -242,6 +242,13 @@ config DWC_ETH_QOS_TEGRA186 The Synopsys Designware Ethernet QOS IP block with specific configuration used in NVIDIA's Tegra186 chip. +config DWC_ETH_QOS_QCOM + bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs" + depends on DWC_ETH_QOS + help + The Synopsys Designware Ethernet QOS IP block with specific + configuration used in Qcom QCS404 SoC. + config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" depends on PCI @@ -406,6 +413,7 @@ config FSL_FM_10GEC_REGULAR_NOTATION config FTMAC100 bool "Ftmac100 Ethernet Support" + select MII help This MAC is present in Andestech SoCs. @@ -473,6 +481,13 @@ config LITEETH help Driver for the LiteEth Ethernet MAC from LiteX. +config MV88E6XXX + bool "Marvell MV88E6xxx Ethernet switch DSA driver" + depends on DM_DSA && DM_MDIO + help + This driver implements a DSA switch driver for the MV88E6xxx family + of Ethernet switches using the MDIO interface + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 5b4e60eea3..75daa5e694 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o +obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o @@ -60,6 +61,7 @@ obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o obj-$(CONFIG_MT7620_ETH) += mt7620-eth.o obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o +obj-$(CONFIG_MV88E6XXX) += mv88e6xxx.o obj-$(CONFIG_MVGBE) += mvgbe.o obj-$(CONFIG_MVMDIO) += mvmdio.o obj-$(CONFIG_MVNETA) += mvneta.o diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index afc47b56ff..112deb546d 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -774,10 +774,13 @@ static int eqos_start(struct udevice *dev) pr_err("eqos_calibrate_pads() failed: %d", ret); goto err_stop_resets; } - rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); - val = (rate / 1000000) - 1; - writel(val, &eqos->mac_regs->us_tic_counter); + if (eqos->config->ops->eqos_get_tick_clk_rate) { + rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); + + val = (rate / 1000000) - 1; + writel(val, &eqos->mac_regs->us_tic_counter); + } /* * if PHY was already connected and configured, @@ -849,12 +852,19 @@ static int eqos_start(struct udevice *dev) rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; - /* - * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting. - * r/tqs is encoded as (n / 256) - 1. - */ - tqs = (128 << tx_fifo_sz) / 256 - 1; - rqs = (128 << rx_fifo_sz) / 256 - 1; + /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */ + tx_fifo_sz = 128 << tx_fifo_sz; + rx_fifo_sz = 128 << rx_fifo_sz; + + /* Allow platform to override TX/RX fifo size */ + if (eqos->tx_fifo_sz) + tx_fifo_sz = eqos->tx_fifo_sz; + if (eqos->rx_fifo_sz) + rx_fifo_sz = eqos->rx_fifo_sz; + + /* r/tqs is encoded as (n / 256) - 1 */ + tqs = tx_fifo_sz / 256 - 1; + rqs = rx_fifo_sz / 256 - 1; clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << @@ -1702,6 +1712,13 @@ static const struct udevice_id eqos_ids[] = { }, #endif +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) + { + .compatible = "qcom,qcs404-ethqos", + .data = (ulong)&eqos_qcom_config + }, +#endif + { } }; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index 8fccd6f057..fddbe9336c 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -253,6 +253,7 @@ struct eqos_priv { struct eqos_mtl_regs *mtl_regs; struct eqos_dma_regs *dma_regs; struct eqos_tegra186_regs *tegra186_regs; + void *eqos_qcom_rgmii_regs; struct reset_ctl reset_ctl; struct gpio_desc phy_reset_gpio; struct clk clk_master_bus; @@ -276,6 +277,8 @@ struct eqos_priv { bool started; bool reg_access_ok; bool clk_ck_enabled; + unsigned int tx_fifo_sz, rx_fifo_sz; + u32 reset_delays[3]; }; void eqos_inval_desc_generic(void *desc); @@ -285,3 +288,4 @@ void eqos_flush_buffer_generic(void *buf, size_t size); int eqos_null_ops(struct udevice *dev); extern struct eqos_config eqos_imx_config; +extern struct eqos_config eqos_qcom_config; diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c new file mode 100644 index 0000000000..df83f1c5f9 --- /dev/null +++ b/drivers/net/dwc_eth_qos_qcom.c @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022-2023 Sumit Garg <sumit.garg@linaro.org> + * + * Qcom DWMAC specific glue layer + */ + +#include <common.h> +#include <asm/global_data.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <phy.h> +#include <reset.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <linux/delay.h> + +#include "dwc_eth_qos.h" + +/* RGMII_IO_MACRO_CONFIG fields */ +#define RGMII_CONFIG_FUNC_CLK_EN BIT(30) +#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23) +#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20) +#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17) +#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8) +#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6) +#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4) +#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3) +#define RGMII_CONFIG_LOOPBACK_EN BIT(2) +#define RGMII_CONFIG_PROG_SWAP BIT(1) +#define RGMII_CONFIG_DDR_MODE BIT(0) + +/* SDCC_HC_REG_DLL_CONFIG fields */ +#define SDCC_DLL_CONFIG_DLL_RST BIT(30) +#define SDCC_DLL_CONFIG_PDN BIT(29) +#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24) +#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20) +#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19) +#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18) +#define SDCC_DLL_CONFIG_CDR_EN BIT(17) +#define SDCC_DLL_CONFIG_DLL_EN BIT(16) +#define SDCC_DLL_MCLK_GATING_EN BIT(5) +#define SDCC_DLL_CDR_FINE_PHASE GENMASK(3, 2) + +/* SDCC_HC_REG_DDR_CONFIG fields */ +#define SDCC_DDR_CONFIG_PRG_DLY_EN BIT(31) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY GENMASK(26, 21) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE GENMASK(29, 27) +#define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN BIT(30) +#define SDCC_DDR_CONFIG_PRG_RCLK_DLY GENMASK(8, 0) + +/* SDCC_HC_REG_DLL_CONFIG2 fields */ +#define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS BIT(21) +#define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC GENMASK(17, 10) +#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL GENMASK(3, 2) +#define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW BIT(1) +#define SDCC_DLL_CONFIG2_DDR_CAL_EN BIT(0) + +/* SDC4_STATUS bits */ +#define SDC4_STATUS_DLL_LOCK BIT(7) + +/* RGMII_IO_MACRO_CONFIG2 fields */ +#define RGMII_CONFIG2_RSVD_CONFIG15 GENMASK(31, 17) +#define RGMII_CONFIG2_RGMII_CLK_SEL_CFG BIT(16) +#define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN BIT(13) +#define RGMII_CONFIG2_CLK_DIVIDE_SEL BIT(12) +#define RGMII_CONFIG2_RX_PROG_SWAP BIT(7) +#define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL BIT(6) +#define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN BIT(5) + +struct dwmac_rgmii_regs { + u32 io_macro_config; /* 0x00 */ + u32 sdcc_hc_dll_config; /* 0x04 */ + u32 reserved_1; /* 0x08 */ + u32 sdcc_hc_ddr_config; /* 0x0c */ + u32 sdcc_hc_dll_config2; /* 0x10 */ + u32 sdc4_status; /* 0x14 */ + u32 sdcc_usr_ctl; /* 0x18 */ + u32 io_macro_config2; /* 0x1c */ + u32 io_macro_debug1; /* 0x20 */ + u32 reserved_2; /* 0x24 */ + u32 emac_sys_low_power_dbg; /* 0x28 */ + u32 reserved_3[53]; /* upto 0x100 */ +}; + +static struct dwmac_rgmii_regs emac_v2_3_0_por = { + .io_macro_config = 0x00C01343, + .sdcc_hc_dll_config = 0x2004642C, + .sdcc_hc_ddr_config = 0x00000000, + .sdcc_hc_dll_config2 = 0x00200000, + .sdcc_usr_ctl = 0x00010800, + .io_macro_config2 = 0x00002060 +}; + +static void ethqos_set_func_clk_en(struct dwmac_rgmii_regs *regs) +{ + setbits_le32(®s->io_macro_config, RGMII_CONFIG_FUNC_CLK_EN); +} + +static int ethqos_dll_configure(struct udevice *dev, + struct dwmac_rgmii_regs *regs) +{ + unsigned int val; + int retry = 1000; + + /* Set CDR_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EN); + + /* Set CDR_EXT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CDR_EXT_EN); + + /* Clear CK_OUT_EN */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Set DLL_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN); + + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_MCLK_GATING_EN); + + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CDR_FINE_PHASE); + + /* Wait for CK_OUT_EN clear */ + do { + val = readl(®s->sdcc_hc_dll_config); + val &= SDCC_DLL_CONFIG_CK_OUT_EN; + if (!val) + break; + mdelay(1); + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Clear CK_OUT_EN timedout\n"); + + /* Set CK_OUT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Wait for CK_OUT_EN set */ + retry = 1000; + do { + val = readl(®s->sdcc_hc_dll_config); + val &= SDCC_DLL_CONFIG_CK_OUT_EN; + if (val) + break; + mdelay(1); + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Set CK_OUT_EN timedout\n"); + + /* Set DDR_CAL_EN */ + setbits_le32(®s->sdcc_hc_dll_config2, SDCC_DLL_CONFIG2_DDR_CAL_EN); + + clrbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DLL_CLOCK_DIS); + + clrsetbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_MCLK_FREQ_CALC, 0x1A << 10); + + clrsetbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL, BIT(2)); + + setbits_le32(®s->sdcc_hc_dll_config2, + SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW); + + return 0; +} + +static int ethqos_rgmii_macro_init(struct udevice *dev, + struct dwmac_rgmii_regs *regs, + unsigned long speed) +{ + /* Disable loopback mode */ + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN); + + /* Select RGMII, write 0 to interface select */ + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_INTF_SEL); + + switch (speed) { + case SPEED_1000: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + setbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_PRG_RCLK_DLY, 57); + setbits_le32(®s->sdcc_hc_ddr_config, SDCC_DDR_CONFIG_PRG_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + case SPEED_100: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + clrsetbits_le32(®s->io_macro_config, + RGMII_CONFIG_MAX_SPD_PRG_2, BIT(6)); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + setbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Write 0x5 to PRG_RCLK_DLY_CODE */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, + (BIT(29) | BIT(27))); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + case SPEED_10: + setbits_le32(®s->io_macro_config, RGMII_CONFIG_DDR_MODE); + setbits_le32(®s->io_macro_config, + RGMII_CONFIG_BYPASS_TX_ID_EN); + clrbits_le32(®s->io_macro_config, + RGMII_CONFIG_POS_NEG_DATA_SEL); + clrbits_le32(®s->io_macro_config, RGMII_CONFIG_PROG_SWAP); + clrsetbits_le32(®s->io_macro_config, + RGMII_CONFIG_MAX_SPD_PRG_9, + BIT(12) | GENMASK(9, 8)); + + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RSVD_CONFIG15); + clrbits_le32(®s->io_macro_config2, + RGMII_CONFIG2_RX_PROG_SWAP); + + /* Write 0x5 to PRG_RCLK_DLY_CODE */ + clrsetbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE, + (BIT(29) | BIT(27))); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY); + setbits_le32(®s->sdcc_hc_ddr_config, + SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN); + + setbits_le32(®s->io_macro_config, RGMII_CONFIG_LOOPBACK_EN); + break; + + default: + dev_err(dev, "Invalid speed %ld\n", speed); + return -EINVAL; + } + + return 0; +} + +static int ethqos_configure(struct udevice *dev, + struct dwmac_rgmii_regs *regs, + unsigned long speed) +{ + unsigned int retry = 1000; + + /* Reset to POR values and enable clk */ + writel(emac_v2_3_0_por.io_macro_config, ®s->io_macro_config); + writel(emac_v2_3_0_por.sdcc_hc_dll_config, ®s->sdcc_hc_dll_config); + writel(emac_v2_3_0_por.sdcc_hc_ddr_config, ®s->sdcc_hc_ddr_config); + writel(emac_v2_3_0_por.sdcc_hc_dll_config2, ®s->sdcc_hc_dll_config2); + writel(emac_v2_3_0_por.sdcc_usr_ctl, ®s->sdcc_usr_ctl); + writel(emac_v2_3_0_por.io_macro_config2, ®s->io_macro_config2); + + ethqos_set_func_clk_en(regs); + + /* Initialize the DLL first */ + + /* Set DLL_RST */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST); + + /* Set PDN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN); + + /* Clear DLL_RST */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_RST); + + /* Clear PDN */ + clrbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_PDN); + + if (speed == SPEED_1000) { + /* Set DLL_EN */ + setbits_le32(®s->sdcc_hc_dll_config, SDCC_DLL_CONFIG_DLL_EN); + + /* Set CK_OUT_EN */ + setbits_le32(®s->sdcc_hc_dll_config, + SDCC_DLL_CONFIG_CK_OUT_EN); + + /* Set USR_CTL bit 26 with mask of 3 bits */ + clrsetbits_le32(®s->sdcc_usr_ctl, GENMASK(26, 24), BIT(26)); + + /* wait for DLL LOCK */ + do { + mdelay(1); + if (readl(®s->sdc4_status) & SDC4_STATUS_DLL_LOCK) + break; + retry--; + } while (retry > 0); + if (!retry) + dev_err(dev, "Timeout while waiting for DLL lock\n"); + + ethqos_dll_configure(dev, regs); + } + + ethqos_rgmii_macro_init(dev, regs, speed); + + return 0; +} + +static void ethqos_rgmii_dump(struct udevice *dev, + struct dwmac_rgmii_regs *regs) +{ + dev_dbg(dev, "Rgmii register dump\n"); + dev_dbg(dev, "RGMII_IO_MACRO_CONFIG: %08x\n", + readl(®s->io_macro_config)); + dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG: %08x\n", + readl(®s->sdcc_hc_dll_config)); + dev_dbg(dev, "SDCC_HC_REG_DDR_CONFIG: %08x\n", + readl(®s->sdcc_hc_ddr_config)); + dev_dbg(dev, "SDCC_HC_REG_DLL_CONFIG2: %08x\n", + readl(®s->sdcc_hc_dll_config2)); + dev_dbg(dev, "SDC4_STATUS: %08x\n", + readl(®s->sdc4_status)); + dev_dbg(dev, "SDCC_USR_CTL: %08x\n", + readl(®s->sdcc_usr_ctl)); + dev_dbg(dev, "RGMII_IO_MACRO_CONFIG2: %08x\n", + readl(®s->io_macro_config2)); + dev_dbg(dev, "RGMII_IO_MACRO_DEBUG1: %08x\n", + readl(®s->io_macro_debug1)); + dev_dbg(dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %08x\n", + readl(®s->emac_sys_low_power_dbg)); +} + +static int qcom_eqos_rgmii_set_speed(struct udevice *dev, + void *rgmii_regs, + unsigned long speed) +{ + int ret; + + ethqos_rgmii_dump(dev, rgmii_regs); + + ret = ethqos_configure(dev, rgmii_regs, speed); + if (ret) + return ret; + + ethqos_rgmii_dump(dev, rgmii_regs); + + return 0; +} + +static int qcom_eqos_rgmii_reset(struct udevice *dev, void *rgmii_regs) +{ + ethqos_set_func_clk_en(rgmii_regs); + + return 0; +} + +static int eqos_start_clks_qcom(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_CLK)) { + struct clk_bulk clocks; + int ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_stop_clks_qcom(struct udevice *dev) +{ + if (IS_ENABLED(CONFIG_CLK)) { + struct clk_bulk clocks; + int ret; + + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_disable_bulk(&clocks); + if (ret) + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_start_resets_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + if (!eqos->phy) { + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[0]); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[1]); + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + return ret; + } + + udelay(eqos->reset_delays[2]); + } + + ret = reset_deassert(&eqos->reset_ctl); + if (ret < 0) { + pr_err("reset_deassert() failed: %d", ret); + return ret; + } + + ret = qcom_eqos_rgmii_reset(dev, eqos->eqos_qcom_rgmii_regs); + if (ret < 0) { + pr_err("qcom rgmii_reset failed: %d", ret); + return ret; + } + + debug("%s: OK\n", __func__); + return 0; +} + +/* Clock rates */ +#define RGMII_1000_NOM_CLK_FREQ (250 * 1000 * 1000UL) +#define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ (50 * 1000 * 1000UL) +#define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ (5 * 1000 * 1000UL) + +static int eqos_set_tx_clk_speed_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + ulong rate; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + switch (eqos->phy->speed) { + case SPEED_1000: + rate = RGMII_1000_NOM_CLK_FREQ; + break; + case SPEED_100: + rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ; + break; + case SPEED_10: + rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ; + break; + default: + pr_err("invalid speed %d", eqos->phy->speed); + return -EINVAL; + } + + ret = clk_set_rate(&eqos->clk_tx, rate); + if (ret < 0) { + pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret); + return ret; + } + + ret = qcom_eqos_rgmii_set_speed(dev, eqos->eqos_qcom_rgmii_regs, + eqos->phy->speed); + if (ret < 0) { + pr_err("qcom set_speed: %d, failed: %d", eqos->phy->speed, ret); + return ret; + } + + return 0; +} + +static int eqos_probe_resources_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + phy_interface_t interface; + int reset_flags = GPIOD_IS_OUT; + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + interface = eqos->config->interface(dev); + + if (interface == PHY_INTERFACE_MODE_NA) { + pr_err("Invalid PHY interface\n"); + return -EINVAL; + } + + eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); + + eqos->tx_fifo_sz = dev_read_u32_default(dev, "tx-fifo-depth", 0); + eqos->rx_fifo_sz = dev_read_u32_default(dev, "rx-fifo-depth", 0); + + ret = reset_get_by_name(dev, "emac", &eqos->reset_ctl); + if (ret) { + pr_err("reset_get_by_name(rst) failed: %d", ret); + return ret; + } + + if (dev_read_bool(dev, "snps,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, + &eqos->phy_reset_gpio, reset_flags); + if (ret == 0) { + ret = dev_read_u32_array(dev, "snps,reset-delays-us", + eqos->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } + + eqos->eqos_qcom_rgmii_regs = (void *)dev_read_addr_name(dev, "rgmii"); + if ((fdt_addr_t)eqos->eqos_qcom_rgmii_regs == FDT_ADDR_T_NONE) { + pr_err("Invalid RGMII address\n"); + return -EINVAL; + } + + ret = clk_get_by_name(dev, "rgmii", &eqos->clk_tx); + if (ret) { + pr_err("clk_get_by_name(tx) failed: %d", ret); + return -EINVAL; + } + + debug("%s: OK\n", __func__); + return 0; +} + +static int eqos_remove_resources_qcom(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_free(&eqos->clk_tx); + dm_gpio_free(dev, &eqos->phy_reset_gpio); + reset_free(&eqos->reset_ctl); + + debug("%s: OK\n", __func__); + return 0; +} + +static struct eqos_ops eqos_qcom_ops = { + .eqos_inval_desc = eqos_inval_desc_generic, + .eqos_flush_desc = eqos_flush_desc_generic, + .eqos_inval_buffer = eqos_inval_buffer_generic, + .eqos_flush_buffer = eqos_flush_buffer_generic, + .eqos_probe_resources = eqos_probe_resources_qcom, + .eqos_remove_resources = eqos_remove_resources_qcom, + .eqos_stop_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_qcom, + .eqos_stop_clks = eqos_stop_clks_qcom, + .eqos_start_clks = eqos_start_clks_qcom, + .eqos_calibrate_pads = eqos_null_ops, + .eqos_disable_calibration = eqos_null_ops, + .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_qcom, + .eqos_get_enetaddr = eqos_null_ops, +}; + +struct eqos_config __maybe_unused eqos_qcom_config = { + .reg_access_always_ok = false, + .mdio_wait = 10, + .swr_wait = 50, + .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, + .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300, + .axi_bus_width = EQOS_AXI_WIDTH_64, + .interface = dev_read_phy_mode, + .ops = &eqos_qcom_ops +}; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 006d27051e..1a6c18a441 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -30,6 +30,8 @@ #include <asm/arch/imx-regs.h> #include <asm/mach-imx/sys_proto.h> #include <asm-generic/gpio.h> +#include <dm/device_compat.h> +#include <dm/lists.h> #include "fec_mxc.h" #include <eth_phy.h> @@ -1019,6 +1021,81 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) return bus; } +#ifdef CONFIG_DM_MDIO +struct dm_fec_mdio_priv { + struct ethernet_regs *regs; +}; + +static int dm_fec_mdio_read(struct udevice *dev, int addr, int devad, int reg) +{ + struct dm_fec_mdio_priv *priv = dev_get_priv(dev); + + return fec_mdio_read(priv->regs, addr, reg); +} + +static int dm_fec_mdio_write(struct udevice *dev, int addr, int devad, int reg, u16 data) +{ + struct dm_fec_mdio_priv *priv = dev_get_priv(dev); + + return fec_mdio_write(priv->regs, addr, reg, data); +} + +static const struct mdio_ops dm_fec_mdio_ops = { + .read = dm_fec_mdio_read, + .write = dm_fec_mdio_write, +}; + +static int dm_fec_mdio_probe(struct udevice *dev) +{ + struct dm_fec_mdio_priv *priv = dev_get_priv(dev); + + priv->regs = (struct ethernet_regs *)ofnode_get_addr(dev_ofnode(dev->parent)); + + return 0; +} + +U_BOOT_DRIVER(fec_mdio) = { + .name = "fec_mdio", + .id = UCLASS_MDIO, + .probe = dm_fec_mdio_probe, + .ops = &dm_fec_mdio_ops, + .priv_auto = sizeof(struct dm_fec_mdio_priv), +}; + +static int dm_fec_bind_mdio(struct udevice *dev) +{ + struct udevice *mdiodev; + const char *name; + ofnode mdio; + int ret = -ENODEV; + + /* for a UCLASS_MDIO driver we need to bind and probe manually + * for an internal MDIO bus that has no dt compatible of its own + */ + ofnode_for_each_subnode(mdio, dev_ofnode(dev)) { + name = ofnode_get_name(mdio); + + if (strcmp(name, "mdio")) + continue; + + ret = device_bind_driver_to_node(dev, "fec_mdio", + name, mdio, &mdiodev); + if (ret) { + printf("%s bind %s failed: %d\n", __func__, name, ret); + break; + } + + /* need to probe it as there is no compatible to do so */ + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio, &mdiodev); + if (!ret) + return 0; + printf("%s probe %s failed: %d\n", __func__, name, ret); + } + + return ret; +} +#endif + static int fecmxc_read_rom_hwaddr(struct udevice *dev) { struct fec_priv *priv = dev_get_priv(dev); @@ -1082,7 +1159,7 @@ static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev) static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) { - struct phy_device *phydev; + struct phy_device *phydev = NULL; int addr; addr = device_get_phy_addr(priv, dev); @@ -1090,7 +1167,10 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) addr = CFG_FEC_MXC_PHYADDR; #endif - phydev = phy_connect(priv->bus, addr, dev, priv->interface); + if (IS_ENABLED(CONFIG_DM_MDIO)) + phydev = dm_eth_phy_connect(dev); + if (!phydev) + phydev = phy_connect(priv->bus, addr, dev, priv->interface); if (!phydev) return -ENODEV; @@ -1125,7 +1205,7 @@ static int fecmxc_probe(struct udevice *dev) uint32_t start; int ret; - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (enet_fused((ulong)priv->eth)) { printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth); return -ENODEV; @@ -1221,6 +1301,12 @@ static int fecmxc_probe(struct udevice *dev) priv->dev_id = dev_seq(dev); +#ifdef CONFIG_DM_MDIO + ret = dm_fec_bind_mdio(dev); + if (ret && ret != -ENODEV) + return ret; +#endif + #ifdef CONFIG_DM_ETH_PHY bus = eth_phy_get_mdio_bus(dev); #endif diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 6b36860187..4f84403d95 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -356,8 +356,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, if (noff < 0) { err = fdt_increase_size(blob, 200); if (err) { - printf("fdt_increase_size: err=%s\n", - fdt_strerror(err)); + printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); return err; } @@ -373,7 +372,7 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id, "link_type", link_type_mode); if (err) { printf("fdt_appendprop_string: err=%s\n", - fdt_strerror(err)); + fdt_strerror(err)); return err; } } @@ -527,7 +526,6 @@ static int load_mc_dpc(u64 mc_ram_addr, size_t mc_ram_size, u64 mc_dpc_addr) return 0; } - static int mc_fixup_dpl(u64 dpl_addr) { void *blob = (void *)dpl_addr; @@ -699,7 +697,6 @@ static int wait_for_mc(bool booting_mc, u32 *final_reg_gsr) printf("SUCCESS\n"); } - *final_reg_gsr = reg_gsr; return 0; } @@ -812,7 +809,7 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr) * Initialize the global default MC portal * And check that the MC firmware is responding portal commands: */ - root_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1); + root_mc_io = calloc(sizeof(struct fsl_mc_io), 1); if (!root_mc_io) { printf(" No memory: calloc() failed\n"); return -ENOMEM; @@ -979,8 +976,7 @@ static int dpio_init(void) int err = 0; uint16_t major_ver, minor_ver; - dflt_dpio = (struct fsl_dpio_obj *)calloc( - sizeof(struct fsl_dpio_obj), 1); + dflt_dpio = calloc(sizeof(struct fsl_dpio_obj), 1); if (!dflt_dpio) { printf("No memory: calloc() failed\n"); err = -ENOMEM; @@ -1038,7 +1034,7 @@ static int dpio_init(void) } #ifdef DEBUG - printf("Init: DPIO id=0x%d\n", dflt_dpio->dpio_id); + printf("Init: DPIO.%d\n", dflt_dpio->dpio_id); #endif err = dpio_enable(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpio->dpio_handle); if (err < 0) { @@ -1107,7 +1103,7 @@ static int dpio_exit(void) } #ifdef DEBUG - printf("Exit: DPIO id=0x%d\n", dflt_dpio->dpio_id); + printf("Exit: DPIO.%d\n", dflt_dpio->dpio_id); #endif if (dflt_dpio) @@ -1159,16 +1155,15 @@ static int dprc_init(void) cfg.icid = DPRC_GET_ICID_FROM_POOL; cfg.portal_id = DPRC_GET_PORTAL_ID_FROM_POOL; err = dprc_create_container(root_mc_io, MC_CMD_NO_FLAGS, - root_dprc_handle, - &cfg, - &child_dprc_id, - &mc_portal_offset); + root_dprc_handle, &cfg, + &child_dprc_id, + &mc_portal_offset); if (err < 0) { printf("dprc_create_container() failed: %d\n", err); goto err_create; } - dflt_mc_io = (struct fsl_mc_io *)calloc(sizeof(struct fsl_mc_io), 1); + dflt_mc_io = calloc(sizeof(struct fsl_mc_io), 1); if (!dflt_mc_io) { err = -ENOMEM; printf(" No memory: calloc() failed\n"); @@ -1250,8 +1245,7 @@ static int dpbp_init(void) struct dpbp_cfg dpbp_cfg; uint16_t major_ver, minor_ver; - dflt_dpbp = (struct fsl_dpbp_obj *)calloc( - sizeof(struct fsl_dpbp_obj), 1); + dflt_dpbp = calloc(sizeof(struct fsl_dpbp_obj), 1); if (!dflt_dpbp) { printf("No memory: calloc() failed\n"); err = -ENOMEM; @@ -1312,7 +1306,7 @@ static int dpbp_init(void) } #ifdef DEBUG - printf("Init: DPBP id=0x%x\n", dflt_dpbp->dpbp_attr.id); + printf("Init: DPBP.%d\n", dflt_dpbp->dpbp_attr.id); #endif err = dpbp_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpbp->dpbp_handle); @@ -1351,7 +1345,7 @@ static int dpbp_exit(void) } #ifdef DEBUG - printf("Exit: DPBP id=0x%d\n", dflt_dpbp->dpbp_attr.id); + printf("Exit: DPBP.%d\n", dflt_dpbp->dpbp_attr.id); #endif if (dflt_dpbp) @@ -1369,8 +1363,7 @@ static int dpni_init(void) struct dpni_cfg dpni_cfg; uint16_t major_ver, minor_ver; - dflt_dpni = (struct fsl_dpni_obj *)calloc( - sizeof(struct fsl_dpni_obj), 1); + dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1); if (!dflt_dpni) { printf("No memory: calloc() failed\n"); err = -ENOMEM; @@ -1422,7 +1415,7 @@ static int dpni_init(void) } #ifdef DEBUG - printf("Init: DPNI id=0x%d\n", dflt_dpni->dpni_id); + printf("Init: DPNI.%d\n", dflt_dpni->dpni_id); #endif err = dpni_close(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle); if (err < 0) { @@ -1459,7 +1452,7 @@ static int dpni_exit(void) } #ifdef DEBUG - printf("Exit: DPNI id=0x%d\n", dflt_dpni->dpni_id); + printf("Exit: DPNI.%d\n", dflt_dpni->dpni_id); #endif if (dflt_dpni) @@ -1796,7 +1789,6 @@ static void mc_dump_log(void) if (size > bytes_end) { print_k_bytes(cur_ptr, &bytes_end); - cur_ptr = buf; size -= bytes_end; } @@ -1962,7 +1954,6 @@ static int do_fsl_mc(struct cmd_tbl *cmdtp, int flag, int argc, default: printf("Invalid option: %s\n", argv[1]); goto usage; - break; } return err; usage: diff --git a/drivers/net/fsl_ls_mdio.c b/drivers/net/fsl_ls_mdio.c index f213e0dd85..fce7393750 100644 --- a/drivers/net/fsl_ls_mdio.c +++ b/drivers/net/fsl_ls_mdio.c @@ -124,6 +124,9 @@ static int fsl_ls_mdio_probe(struct udevice *dev) struct memac_mdio_controller *regs; priv->regs_base = dev_read_addr_ptr(dev); + if (!priv->regs_base) + return -ENODEV; + regs = (struct memac_mdio_controller *)(priv->regs_base); memac_setbits_32(®s->mdio_stat, diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index f710c271c6..fae3adc3de 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -12,9 +12,13 @@ #include <env.h> #include <malloc.h> #include <net.h> +#include <phy.h> +#include <miiphy.h> +#include <dm/device_compat.h> #include <asm/global_data.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/iopoll.h> #include "ftmac100.h" #include <dm.h> @@ -23,12 +27,16 @@ DECLARE_GLOBAL_DATA_PTR; #define ETH_ZLEN 60 +/* Timeout for a mdio read/write operation */ +#define FTMAC100_MDIO_TIMEOUT_USEC 10000 + struct ftmac100_data { struct ftmac100_txdes txdes[1]; struct ftmac100_rxdes rxdes[PKTBUFSRX]; int rx_index; const char *name; - phys_addr_t iobase; + struct ftmac100 *ftmac100; + struct mii_dev *bus; }; /* @@ -36,7 +44,7 @@ struct ftmac100_data { */ static void ftmac100_reset(struct ftmac100_data *priv) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase; + struct ftmac100 *ftmac100 = priv->ftmac100; debug ("%s()\n", __func__); @@ -57,7 +65,7 @@ static void ftmac100_reset(struct ftmac100_data *priv) static void ftmac100_set_mac(struct ftmac100_data *priv , const unsigned char *mac) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase; + struct ftmac100 *ftmac100 = priv->ftmac100; unsigned int maddr = mac[0] << 8 | mac[1]; unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; @@ -72,7 +80,7 @@ static void ftmac100_set_mac(struct ftmac100_data *priv , */ static void _ftmac100_halt(struct ftmac100_data *priv) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase; + struct ftmac100 *ftmac100 = priv->ftmac100; debug ("%s()\n", __func__); writel (0, &ftmac100->maccr); } @@ -82,7 +90,7 @@ static void _ftmac100_halt(struct ftmac100_data *priv) */ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6]) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase; + struct ftmac100 *ftmac100 = priv->ftmac100; struct ftmac100_txdes *txdes = priv->txdes; struct ftmac100_rxdes *rxdes = priv->rxdes; unsigned int maccr; @@ -187,7 +195,7 @@ static int __ftmac100_recv(struct ftmac100_data *priv) */ static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length) { - struct ftmac100 *ftmac100 = (struct ftmac100 *)(uintptr_t)priv->iobase; + struct ftmac100 *ftmac100 = priv->ftmac100; struct ftmac100_txdes *curr_des = priv->txdes; ulong start; @@ -314,7 +322,7 @@ static int ftmac100_of_to_plat(struct udevice *dev) struct eth_pdata *pdata = dev_get_plat(dev); const char *mac; pdata->iobase = dev_read_addr(dev); - priv->iobase = pdata->iobase; + priv->ftmac100 = phys_to_virt(pdata->iobase); mac = dtbmacaddr(0); if (mac) memcpy(pdata->enetaddr , mac , 6); @@ -322,10 +330,104 @@ static int ftmac100_of_to_plat(struct udevice *dev) return 0; } +/* + * struct mii_bus functions + */ +static int ftmac100_mdio_read(struct mii_dev *bus, int addr, int devad, + int reg) +{ + struct ftmac100_data *priv = bus->priv; + struct ftmac100 *ftmac100 = priv->ftmac100; + int phycr = FTMAC100_PHYCR_PHYAD(addr) | + FTMAC100_PHYCR_REGAD(reg) | + FTMAC100_PHYCR_MIIRD; + int ret; + + writel(phycr, &ftmac100->phycr); + + ret = readl_poll_timeout(&ftmac100->phycr, phycr, + !(phycr & FTMAC100_PHYCR_MIIRD), + FTMAC100_MDIO_TIMEOUT_USEC); + if (ret) + pr_err("%s: mdio read failed (addr=0x%x reg=0x%x)\n", + bus->name, addr, reg); + else + ret = phycr & FTMAC100_PHYCR_MIIRDATA; + + return ret; +} + +static int ftmac100_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) +{ + struct ftmac100_data *priv = bus->priv; + struct ftmac100 *ftmac100 = priv->ftmac100; + int phycr = FTMAC100_PHYCR_PHYAD(addr) | + FTMAC100_PHYCR_REGAD(reg) | + FTMAC100_PHYCR_MIIWR; + int ret; + + writel(value, &ftmac100->phywdata); + writel(phycr, &ftmac100->phycr); + + ret = readl_poll_timeout(&ftmac100->phycr, phycr, + !(phycr & FTMAC100_PHYCR_MIIWR), + FTMAC100_MDIO_TIMEOUT_USEC); + if (ret) + pr_err("%s: mdio write failed (addr=0x%x reg=0x%x)\n", + bus->name, addr, reg); + + return ret; +} + +static int ftmac100_mdio_init(struct udevice *dev) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + struct mii_dev *bus; + int ret; + + bus = mdio_alloc(); + if (!bus) + return -ENOMEM; + + bus->read = ftmac100_mdio_read; + bus->write = ftmac100_mdio_write; + bus->priv = priv; + + ret = mdio_register_seq(bus, dev_seq(dev)); + if (ret) { + mdio_free(bus); + return ret; + } + + priv->bus = bus; + + return 0; +} + static int ftmac100_probe(struct udevice *dev) { struct ftmac100_data *priv = dev_get_priv(dev); priv->name = dev->name; + int ret = 0; + + ret = ftmac100_mdio_init(dev); + if (ret) { + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret); + goto out; + } + +out: + return ret; +} + +static int ftmac100_remove(struct udevice *dev) +{ + struct ftmac100_data *priv = dev_get_priv(dev); + + mdio_unregister(priv->bus); + mdio_free(priv->bus); + return 0; } @@ -348,12 +450,13 @@ static const struct udevice_id ftmac100_ids[] = { }; U_BOOT_DRIVER(ftmac100) = { - .name = "nds32_mac", + .name = "ftmac100", .id = UCLASS_ETH, .of_match = ftmac100_ids, .bind = ftmac100_bind, .of_to_plat = ftmac100_of_to_plat, .probe = ftmac100_probe, + .remove = ftmac100_remove, .ops = &ftmac100_ops, .priv_auto = sizeof(struct ftmac100_data), .plat_auto = sizeof(struct eth_pdata), diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h index 75a49f628a..21d339f835 100644 --- a/drivers/net/ftmac100.h +++ b/drivers/net/ftmac100.h @@ -93,6 +93,15 @@ struct ftmac100 { #define FTMAC100_MACCR_RX_BROADPKT (1 << 17) /* + * PHY control register + */ +#define FTMAC100_PHYCR_MIIRDATA 0xffff +#define FTMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) +#define FTMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) +#define FTMAC100_PHYCR_MIIWR BIT(27) +#define FTMAC100_PHYCR_MIIRD BIT(26) + +/* * Transmit descriptor, aligned to 16 bytes */ struct ftmac100_txdes { diff --git a/drivers/net/ksz9477.c b/drivers/net/ksz9477.c index ed8f1895cb..fb5c76c600 100644 --- a/drivers/net/ksz9477.c +++ b/drivers/net/ksz9477.c @@ -62,7 +62,6 @@ struct ksz_dsa_priv { struct udevice *dev; - int active_port; }; static inline int ksz_read8(struct udevice *dev, u32 reg, u8 *val) @@ -382,9 +381,6 @@ static int ksz_port_enable(struct udevice *dev, int port, struct phy_device *phy data8 |= SW_START; ksz_write8(priv->dev, REG_SW_OPERATION, data8); - /* keep track of current enabled non-cpu port */ - priv->active_port = port; - return 0; } @@ -413,28 +409,9 @@ static void ksz_port_disable(struct udevice *dev, int port, struct phy_device *p */ } -static int ksz_xmit(struct udevice *dev, int port, void *packet, int length) -{ - dev_dbg(dev, "%s P%d %d\n", __func__, port + 1, length); - - return 0; -} - -static int ksz_recv(struct udevice *dev, int *port, void *packet, int length) -{ - struct ksz_dsa_priv *priv = dev_get_priv(dev); - - dev_dbg(dev, "%s P%d %d\n", __func__, priv->active_port + 1, length); - *port = priv->active_port; - - return 0; -}; - static const struct dsa_ops ksz_dsa_ops = { .port_enable = ksz_port_enable, .port_disable = ksz_port_disable, - .xmit = ksz_xmit, - .rcv = ksz_recv, }; static int ksz_probe_mdio(struct udevice *dev) diff --git a/drivers/net/mv88e6xxx.c b/drivers/net/mv88e6xxx.c new file mode 100644 index 0000000000..64e860e324 --- /dev/null +++ b/drivers/net/mv88e6xxx.c @@ -0,0 +1,755 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2022 + * Gateworks Corporation <www.gateworks.com> + * Tim Harvey <tharvey@gateworks.com> + * + * (C) Copyright 2015 + * Elecsys Corporation <www.elecsyscorp.com> + * Kevin Smith <kevin.smith@elecsyscorp.com> + * + * Original driver: + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla@marvell.com> + */ + +/* + * DSA driver for mv88e6xxx ethernet switches. + * + * This driver configures the mv88e6xxx for basic use as a DSA switch. + * + * This driver was adapted from drivers/net/phy/mv88e61xx and tested + * on the mv88e6176 via an SGMII interface. + */ + +#include <common.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/of_extra.h> +#include <linux/delay.h> +#include <miiphy.h> +#include <net/dsa.h> + +/* Device addresses */ +#define DEVADDR_PHY(p) (p) +#define DEVADDR_SERDES 0x0F + +/* SMI indirection registers for multichip addressing mode */ +#define SMI_CMD_REG 0x00 +#define SMI_DATA_REG 0x01 + +/* Global registers */ +#define GLOBAL1_STATUS 0x00 +#define GLOBAL1_CTRL 0x04 + +/* Global 2 registers */ +#define GLOBAL2_REG_PHY_CMD 0x18 +#define GLOBAL2_REG_PHY_DATA 0x19 +#define GLOBAL2_REG_SCRATCH 0x1A + +/* Port registers */ +#define PORT_REG_STATUS 0x00 +#define PORT_REG_PHYS_CTRL 0x01 +#define PORT_REG_SWITCH_ID 0x03 +#define PORT_REG_CTRL 0x04 + +/* Phy registers */ +#define PHY_REG_PAGE 0x16 + +/* Phy page numbers */ +#define PHY_PAGE_COPPER 0 +#define PHY_PAGE_SERDES 1 + +/* Register fields */ +#define GLOBAL1_CTRL_SWRESET BIT(15) + +#define PORT_REG_STATUS_SPEED_SHIFT 8 +#define PORT_REG_STATUS_SPEED_10 0 +#define PORT_REG_STATUS_SPEED_100 1 +#define PORT_REG_STATUS_SPEED_1000 2 + +#define PORT_REG_STATUS_CMODE_MASK 0xF +#define PORT_REG_STATUS_CMODE_SGMII 0xa +#define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 +#define PORT_REG_STATUS_CMODE_100BASE_X 0x8 +#define PORT_REG_STATUS_CMODE_RGMII 0x7 +#define PORT_REG_STATUS_CMODE_RMII 0x5 +#define PORT_REG_STATUS_CMODE_RMII_PHY 0x4 +#define PORT_REG_STATUS_CMODE_GMII 0x3 +#define PORT_REG_STATUS_CMODE_MII 0x2 +#define PORT_REG_STATUS_CMODE_MIIPHY 0x1 + +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK BIT(15) +#define PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK BIT(14) +#define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) +#define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) +#define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) +#define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6) +#define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) +#define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) +#define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3) +#define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2) +#define PORT_REG_PHYS_CTRL_SPD1000 BIT(1) +#define PORT_REG_PHYS_CTRL_SPD100 BIT(0) +#define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0)) + +#define PORT_REG_CTRL_PSTATE_SHIFT 0 +#define PORT_REG_CTRL_PSTATE_MASK 3 + +/* Field values */ +#define PORT_REG_CTRL_PSTATE_DISABLED 0 +#define PORT_REG_CTRL_PSTATE_FORWARD 3 + +/* + * Macros for building commands for indirect addressing modes. These are valid + * for both the indirect multichip addressing mode and the PHY indirection + * required for the writes to any PHY register. + */ +#define SMI_BUSY BIT(15) +#define SMI_CMD_CLAUSE_22 BIT(12) +#define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) +#define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) +#define SMI_CMD_ADDR_SHIFT 5 +#define SMI_CMD_ADDR_MASK 0x1f +#define SMI_CMD_REG_SHIFT 0 +#define SMI_CMD_REG_MASK 0x1f +#define SMI_CMD_READ(addr, reg) \ + (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_READ) | \ + (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ + (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) +#define SMI_CMD_WRITE(addr, reg) \ + (SMI_BUSY | SMI_CMD_CLAUSE_22 | SMI_CMD_CLAUSE_22_OP_WRITE) | \ + (((addr) & SMI_CMD_ADDR_MASK) << SMI_CMD_ADDR_SHIFT) | \ + (((reg) & SMI_CMD_REG_MASK) << SMI_CMD_REG_SHIFT) + +/* ID register values for different switch models */ +#define PORT_SWITCH_ID_6020 0x0200 +#define PORT_SWITCH_ID_6070 0x0700 +#define PORT_SWITCH_ID_6071 0x0710 +#define PORT_SWITCH_ID_6096 0x0980 +#define PORT_SWITCH_ID_6097 0x0990 +#define PORT_SWITCH_ID_6172 0x1720 +#define PORT_SWITCH_ID_6176 0x1760 +#define PORT_SWITCH_ID_6220 0x2200 +#define PORT_SWITCH_ID_6240 0x2400 +#define PORT_SWITCH_ID_6250 0x2500 +#define PORT_SWITCH_ID_6320 0x1150 +#define PORT_SWITCH_ID_6352 0x3520 + +struct mv88e6xxx_priv { + int smi_addr; + int id; + int port_count; /* Number of switch ports */ + int port_reg_base; /* Base of the switch port registers */ + u8 global1; /* Offset of Switch Global 1 registers */ + u8 global2; /* Offset of Switch Global 2 registers */ +}; + +/* Wait for the current SMI indirect command to complete */ +static int mv88e6xxx_smi_wait(struct udevice *dev, int smi_addr) +{ + int val; + u32 timeout = 100; + + do { + val = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + dev_err(dev, "SMI busy timeout\n"); + return -ETIMEDOUT; +} + +/* + * The mv88e6xxx has three types of addresses: the smi bus address, the device + * address, and the register address. The smi bus address distinguishes it on + * the smi bus from other PHYs or switches. The device address determines + * which on-chip register set you are reading/writing (the various PHYs, their + * associated ports, or global configuration registers). The register address + * is the offset of the register you are reading/writing. + * + * When the mv88e6xxx is hardware configured to have address zero, it behaves in + * single-chip addressing mode, where it responds to all SMI addresses, using + * the smi address as its device address. This obviously only works when this + * is the only chip on the SMI bus. This allows the driver to access device + * registers without using indirection. When the chip is configured to a + * non-zero address, it only responds to that SMI address and requires indirect + * writes to access the different device addresses. + */ +static int mv88e6xxx_reg_read(struct udevice *dev, int addr, int reg) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) + return dm_mdio_read(dev->parent, addr, MDIO_DEVAD_NONE, reg); + + /* Wait for the bus to become free */ + res = mv88e6xxx_smi_wait(dev, smi_addr); + if (res < 0) + return res; + + /* Issue the read command */ + res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + SMI_CMD_READ(addr, reg)); + if (res < 0) + return res; + + /* Wait for the read command to complete */ + res = mv88e6xxx_smi_wait(dev, smi_addr); + if (res < 0) + return res; + + /* Read the data */ + res = dm_mdio_read(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG); + if (res < 0) + return res; + + return res & 0xffff; +} + +/* See the comment above mv88e6xxx_reg_read */ +static int mv88e6xxx_reg_write(struct udevice *dev, int addr, int reg, u16 val) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int smi_addr = priv->smi_addr; + int res; + + /* In single-chip mode, the device can be addressed directly */ + if (smi_addr == 0) + return dm_mdio_write(dev->parent, addr, MDIO_DEVAD_NONE, reg, val); + + /* Wait for the bus to become free */ + res = mv88e6xxx_smi_wait(dev, smi_addr); + if (res < 0) + return res; + + /* Set the data to write */ + res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, + SMI_DATA_REG, val); + if (res < 0) + return res; + + /* Issue the write command */ + res = dm_mdio_write(dev->parent, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, + SMI_CMD_WRITE(addr, reg)); + if (res < 0) + return res; + + /* Wait for the write command to complete */ + res = mv88e6xxx_smi_wait(dev, smi_addr); + if (res < 0) + return res; + + return 0; +} + +static int mv88e6xxx_phy_wait(struct udevice *dev) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int val; + u32 timeout = 100; + + do { + val = mv88e6xxx_reg_read(dev, priv->global2, GLOBAL2_REG_PHY_CMD); + if (val >= 0 && (val & SMI_BUSY) == 0) + return 0; + + mdelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int mv88e6xxx_phy_read_indirect(struct udevice *dev, int phyad, int devad, int reg) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int res; + + /* Issue command to read */ + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_CMD, + SMI_CMD_READ(phyad, reg)); + + /* Wait for data to be read */ + res = mv88e6xxx_phy_wait(dev); + if (res < 0) + return res; + + /* Read retrieved data */ + return mv88e6xxx_reg_read(dev, priv->global2, + GLOBAL2_REG_PHY_DATA); +} + +static int mv88e6xxx_phy_write_indirect(struct udevice *dev, int phyad, + int devad, int reg, u16 data) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int res; + + /* Set the data to write */ + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_DATA, data); + if (res < 0) + return res; + /* Issue the write command */ + res = mv88e6xxx_reg_write(dev, priv->global2, + GLOBAL2_REG_PHY_CMD, + SMI_CMD_WRITE(phyad, reg)); + if (res < 0) + return res; + + /* Wait for command to complete */ + return mv88e6xxx_phy_wait(dev); +} + +/* Wrapper function to make calls to phy_read_indirect simpler */ +static int mv88e6xxx_phy_read(struct udevice *dev, int phy, int reg) +{ + return mv88e6xxx_phy_read_indirect(dev, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg); +} + +/* Wrapper function to make calls to phy_write_indirect simpler */ +static int mv88e6xxx_phy_write(struct udevice *dev, int phy, int reg, u16 val) +{ + return mv88e6xxx_phy_write_indirect(dev, DEVADDR_PHY(phy), + MDIO_DEVAD_NONE, reg, val); +} + +static int mv88e6xxx_port_read(struct udevice *dev, u8 port, u8 reg) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + + return mv88e6xxx_reg_read(dev, priv->port_reg_base + port, reg); +} + +static int mv88e6xxx_port_write(struct udevice *dev, u8 port, u8 reg, u16 val) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + + return mv88e6xxx_reg_write(dev, priv->port_reg_base + port, reg, val); +} + +static int mv88e6xxx_set_page(struct udevice *dev, u8 phy, u8 page) +{ + return mv88e6xxx_phy_write(dev, phy, PHY_REG_PAGE, page); +} + +static int mv88e6xxx_get_switch_id(struct udevice *dev) +{ + int res; + + res = mv88e6xxx_port_read(dev, 0, PORT_REG_SWITCH_ID); + if (res < 0) { + dev_err(dev, "Failed to read switch ID: %d\n", res); + return res; + } + return res & 0xfff0; +} + +static bool mv88e6xxx_6352_family(struct udevice *dev) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + + switch (priv->id) { + case PORT_SWITCH_ID_6172: + case PORT_SWITCH_ID_6176: + case PORT_SWITCH_ID_6240: + case PORT_SWITCH_ID_6352: + return true; + } + return false; +} + +static int mv88e6xxx_get_cmode(struct udevice *dev, u8 port) +{ + int res; + + res = mv88e6xxx_port_read(dev, port, PORT_REG_STATUS); + if (res < 0) + return res; + return res & PORT_REG_STATUS_CMODE_MASK; +} + +static int mv88e6xxx_switch_reset(struct udevice *dev) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int time_ms; + int val; + u8 port; + + /* Disable all ports */ + for (port = 0; port < priv->port_count; port++) { + val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT); + val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT); + val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + } + + /* Wait 2 ms for queues to drain */ + udelay(2000); + + /* Reset switch */ + val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL); + if (val < 0) + return val; + val |= GLOBAL1_CTRL_SWRESET; + val = mv88e6xxx_reg_write(dev, priv->global1, GLOBAL1_CTRL, val); + if (val < 0) + return val; + + /* Wait up to 1 second for switch to reset complete */ + for (time_ms = 1000; time_ms; time_ms--) { + val = mv88e6xxx_reg_read(dev, priv->global1, GLOBAL1_CTRL); + if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0)) + break; + udelay(1000); + } + if (!time_ms) + return -ETIMEDOUT; + + return 0; +} + +static int mv88e6xxx_serdes_init(struct udevice *dev) +{ + int val; + + val = mv88e6xxx_set_page(dev, DEVADDR_SERDES, PHY_PAGE_SERDES); + if (val < 0) + return val; + + /* Power up serdes module */ + val = mv88e6xxx_phy_read(dev, DEVADDR_SERDES, MII_BMCR); + if (val < 0) + return val; + val &= ~(BMCR_PDOWN); + val = mv88e6xxx_phy_write(dev, DEVADDR_SERDES, MII_BMCR, val); + if (val < 0) + return val; + + return 0; +} + +/* + * This function is used to pre-configure the required register + * offsets, so that the indirect register access to the PHY registers + * is possible. This is necessary to be able to read the PHY ID + * while driver probing or in get_phy_id(). The globalN register + * offsets must be initialized correctly for a detected switch, + * otherwise detection of the PHY ID won't work! + */ +static int mv88e6xxx_priv_reg_offs_pre_init(struct udevice *dev) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + + /* + * Initial 'port_reg_base' value must be an offset of existing + * port register, then reading the ID should succeed. First, try + * to read via port registers with device address 0x10 (88E6096 + * and compatible switches). + */ + priv->port_reg_base = 0x10; + priv->id = mv88e6xxx_get_switch_id(dev); + if (priv->id != 0xfff0) { + priv->global1 = 0x1B; + priv->global2 = 0x1C; + return 0; + } + + /* + * Now try via port registers with device address 0x08 + * (88E6020 and compatible switches). + */ + priv->port_reg_base = 0x08; + priv->id = mv88e6xxx_get_switch_id(dev); + if (priv->id != 0xfff0) { + priv->global1 = 0x0F; + priv->global2 = 0x07; + return 0; + } + + dev_warn(dev, "%s Unknown ID 0x%x\n", __func__, priv->id); + + return -ENODEV; +} + +static int mv88e6xxx_mdio_read(struct udevice *dev, int addr, int devad, int reg) +{ + return mv88e6xxx_phy_read_indirect(dev->parent, DEVADDR_PHY(addr), + MDIO_DEVAD_NONE, reg); +} + +static int mv88e6xxx_mdio_write(struct udevice *dev, int addr, int devad, + int reg, u16 val) +{ + return mv88e6xxx_phy_write_indirect(dev->parent, DEVADDR_PHY(addr), + MDIO_DEVAD_NONE, reg, val); +} + +static const struct mdio_ops mv88e6xxx_mdio_ops = { + .read = mv88e6xxx_mdio_read, + .write = mv88e6xxx_mdio_write, +}; + +static int mv88e6xxx_mdio_bind(struct udevice *dev) +{ + char name[32]; + static int num_devices; + + sprintf(name, "mv88e6xxx-mdio-%d", num_devices++); + device_set_name(dev, name); + + return 0; +} + +U_BOOT_DRIVER(mv88e6xxx_mdio) = { + .name = "mv88e6xxx_mdio", + .id = UCLASS_MDIO, + .ops = &mv88e6xxx_mdio_ops, + .bind = mv88e6xxx_mdio_bind, + .plat_auto = sizeof(struct mdio_perdev_priv), +}; + +static int mv88e6xxx_port_probe(struct udevice *dev, int port, struct phy_device *phy) +{ + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int supported; + + switch (priv->id) { + case PORT_SWITCH_ID_6020: + case PORT_SWITCH_ID_6070: + case PORT_SWITCH_ID_6071: + supported = PHY_BASIC_FEATURES | SUPPORTED_MII; + break; + default: + supported = PHY_GBIT_FEATURES; + break; + } + + phy->supported &= supported; + phy->advertising &= supported; + + return phy_config(phy); +} + +static int mv88e6xxx_port_enable(struct udevice *dev, int port, struct phy_device *phy) +{ + int val, ret; + + dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port, + phy->phy_id, phy_string_for_interface(phy->interface)); + + if (phy->phy_id == PHY_FIXED_ID) { + /* Physical Control register: Table 62 */ + val = mv88e6xxx_port_read(dev, port, PORT_REG_PHYS_CTRL); + + /* configure RGMII delays for fixed link */ + switch (phy->interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + dev_dbg(dev, "configure internal RGMII delays\n"); + + /* RGMII delays */ + val &= ~(PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK || + PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK); + if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID || + phy->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_RXCLK; + if (phy->interface == PHY_INTERFACE_MODE_RGMII_ID || + phy->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= PORT_REG_PHYS_CTRL_RGMII_DELAY_TXCLK; + break; + default: + break; + } + + /* Force Link */ + val |= PORT_REG_PHYS_CTRL_LINK_VALUE | + PORT_REG_PHYS_CTRL_LINK_FORCE; + + ret = mv88e6xxx_port_write(dev, port, PORT_REG_PHYS_CTRL, val); + if (ret < 0) + return ret; + + if (mv88e6xxx_6352_family(dev)) { + /* validate interface type */ + dev_dbg(dev, "validate interface type\n"); + val = mv88e6xxx_get_cmode(dev, port); + if (val < 0) + return val; + switch (phy->interface) { + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + case PHY_INTERFACE_MODE_RGMII_ID: + if (val != PORT_REG_STATUS_CMODE_RGMII) + goto mismatch; + break; + case PHY_INTERFACE_MODE_1000BASEX: + if (val != PORT_REG_STATUS_CMODE_1000BASE_X) + goto mismatch; + break; +mismatch: + default: + dev_err(dev, "Mismatched PHY mode %s on port %d!\n", + phy_string_for_interface(phy->interface), port); + break; + } + } + } + + /* enable port */ + val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL); + if (val < 0) + return val; + val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT); + val |= (PORT_REG_CTRL_PSTATE_FORWARD << PORT_REG_CTRL_PSTATE_SHIFT); + val = mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val); + if (val < 0) + return val; + + return phy_startup(phy); +} + +static void mv88e6xxx_port_disable(struct udevice *dev, int port, struct phy_device *phy) +{ + int val; + + dev_dbg(dev, "%s P%d phy:0x%08x %s\n", __func__, port, + phy->phy_id, phy_string_for_interface(phy->interface)); + + val = mv88e6xxx_port_read(dev, port, PORT_REG_CTRL); + val &= ~(PORT_REG_CTRL_PSTATE_MASK << PORT_REG_CTRL_PSTATE_SHIFT); + val |= (PORT_REG_CTRL_PSTATE_DISABLED << PORT_REG_CTRL_PSTATE_SHIFT); + mv88e6xxx_port_write(dev, port, PORT_REG_CTRL, val); +} + +static const struct dsa_ops mv88e6xxx_dsa_ops = { + .port_probe = mv88e6xxx_port_probe, + .port_enable = mv88e6xxx_port_enable, + .port_disable = mv88e6xxx_port_disable, +}; + +/* bind and probe the switch mdios */ +static int mv88e6xxx_probe_mdio(struct udevice *dev) +{ + struct udevice *mdev; + const char *name; + ofnode node; + int ret; + + /* bind phy ports of mdio child node to mv88e6xxx_mdio device */ + node = dev_read_subnode(dev, "mdio"); + if (!ofnode_valid(node)) + return 0; + + name = ofnode_get_name(node); + ret = device_bind_driver_to_node(dev, + "mv88e6xxx_mdio", + name, node, NULL); + if (ret) { + dev_err(dev, "failed to bind %s: %d\n", name, ret); + } else { + /* need to probe it as there is no compatible to do so */ + ret = uclass_get_device_by_ofnode(UCLASS_MDIO, node, &mdev); + if (ret) + dev_err(dev, "failed to probe %s: %d\n", name, ret); + } + + return ret; +} + +static int mv88e6xxx_probe(struct udevice *dev) +{ + struct dsa_pdata *dsa_pdata = dev_get_uclass_plat(dev); + struct mv88e6xxx_priv *priv = dev_get_priv(dev); + int val, ret; + + if (ofnode_valid(dev_ofnode(dev)) && + !ofnode_is_enabled(dev_ofnode(dev))) { + dev_dbg(dev, "switch disabled\n"); + return -ENODEV; + } + + /* probe internal mdio bus */ + ret = mv88e6xxx_probe_mdio(dev); + if (ret) + return ret; + + ret = mv88e6xxx_priv_reg_offs_pre_init(dev); + if (ret) + return ret; + + dev_dbg(dev, "ID=0x%x PORT_BASE=0x%02x GLOBAL1=0x%02x GLOBAL2=0x%02x\n", + priv->id, priv->port_reg_base, priv->global1, priv->global2); + switch (priv->id) { + case PORT_SWITCH_ID_6096: + case PORT_SWITCH_ID_6097: + case PORT_SWITCH_ID_6172: + case PORT_SWITCH_ID_6176: + case PORT_SWITCH_ID_6240: + case PORT_SWITCH_ID_6352: + priv->port_count = 11; + break; + case PORT_SWITCH_ID_6020: + case PORT_SWITCH_ID_6070: + case PORT_SWITCH_ID_6071: + case PORT_SWITCH_ID_6220: + case PORT_SWITCH_ID_6250: + case PORT_SWITCH_ID_6320: + priv->port_count = 7; + break; + default: + return -ENODEV; + } + + ret = mv88e6xxx_switch_reset(dev); + if (ret < 0) + return ret; + + if (mv88e6xxx_6352_family(dev)) { + val = mv88e6xxx_get_cmode(dev, dsa_pdata->cpu_port); + if (val < 0) + return val; + /* initialize serdes */ + if (val == PORT_REG_STATUS_CMODE_100BASE_X || + val == PORT_REG_STATUS_CMODE_1000BASE_X || + val == PORT_REG_STATUS_CMODE_SGMII) { + ret = mv88e6xxx_serdes_init(dev); + if (ret < 0) + return ret; + } + } + + return 0; +} + +static const struct udevice_id mv88e6xxx_ids[] = { + { .compatible = "marvell,mv88e6085" }, + { } +}; + +U_BOOT_DRIVER(mv88e6xxx) = { + .name = "mv88e6xxx", + .id = UCLASS_DSA, + .of_match = mv88e6xxx_ids, + .probe = mv88e6xxx_probe, + .ops = &mv88e6xxx_dsa_ops, + .priv_auto = sizeof(struct mv88e6xxx_priv), +}; diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index c28680565f..5a835cc06f 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -693,12 +693,6 @@ int ravb_of_to_plat(struct udevice *dev) } static const struct udevice_id ravb_ids[] = { - { .compatible = "renesas,etheravb-r8a7795" }, - { .compatible = "renesas,etheravb-r8a7796" }, - { .compatible = "renesas,etheravb-r8a77965" }, - { .compatible = "renesas,etheravb-r8a77970" }, - { .compatible = "renesas,etheravb-r8a77990" }, - { .compatible = "renesas,etheravb-r8a77995" }, { .compatible = "renesas,etheravb-rcar-gen3" }, { } }; diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index d393f1ba03..49506e7ba5 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o -obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_PCI_TEGRA) += pci_tegra.o obj-$(CONFIG_PCIE_IPROC) += pcie_iproc.o obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o diff --git a/drivers/pci/pci_sh7780.c b/drivers/pci/pci_sh7780.c deleted file mode 100644 index 7533286c01..0000000000 --- a/drivers/pci/pci_sh7780.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * SH7780 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - */ - -#include <common.h> -#include <linux/delay.h> - -#include <pci.h> -#include <asm/processor.h> -#include <asm/pci.h> -#include <asm/io.h> - -#define SH7780_VENDOR_ID 0x1912 -#define SH7780_DEVICE_ID 0x0002 -#define SH7780_PCICR_PREFIX 0xA5000000 -#define SH7780_PCICR_PFCS 0x00000800 -#define SH7780_PCICR_FTO 0x00000400 -#define SH7780_PCICR_PFE 0x00000200 -#define SH7780_PCICR_TBS 0x00000100 -#define SH7780_PCICR_ARBM 0x00000040 -#define SH7780_PCICR_IOCS 0x00000004 -#define SH7780_PCICR_PRST 0x00000002 -#define SH7780_PCICR_CFIN 0x00000001 - -#define p4_in(addr) (*(vu_long *)addr) -#define p4_out(data, addr) (*(vu_long *)addr) = (data) -#define p4_inw(addr) (*(vu_short *)addr) -#define p4_outw(data, addr) (*(vu_short *)addr) = (data) - -int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 *value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - *value = p4_in(SH7780_PCIPDR); - - return 0; -} - -int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value) -{ - u32 par_data = PCI_CONF1_ADDRESS(PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), offset); - - p4_out(par_data, SH7780_PCIPAR); - p4_out(value, SH7780_PCIPDR); - return 0; -} - -int pci_sh7780_init(struct pci_controller *hose) -{ - p4_out(0x01, SH7780_PCIECR); - - if (p4_inw(SH7780_PCIVID) != SH7780_VENDOR_ID - && p4_inw(SH7780_PCIDID) != SH7780_DEVICE_ID) { - printf("PCI: Unknown PCI host bridge.\n"); - return -1; - } - printf("PCI: SH7780 PCI host bridge found.\n"); - - /* Toggle PCI reset pin */ - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_PRST), SH7780_PCICR); - udelay(100000); - p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR); - p4_outw(0x0047, SH7780_PCICMD); - - p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0); - p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0); - p4_out(0x00000000, SH7780_PCILSR1); - p4_out(0, SH7780_PCILAR1); - p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0); - p4_out(0x00000000, SH7780_PCIMBAR1); - - p4_out(0xFD000000, SH7780_PCIMBR0); - p4_out(0x00FC0000, SH7780_PCIMBMR0); - - /* if use Operand Cache then enable PCICSCR Soonp bits. */ - p4_out(0x08000000, SH7780_PCICSAR0); - p4_out(0x0000001B, SH7780_PCICSCR0); /* Snoop bit :On */ - - p4_out((SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | SH7780_PCICR_ARBM - | SH7780_PCICR_FTO | SH7780_PCICR_PFCS | SH7780_PCICR_PFE), - SH7780_PCICR); - - pci_sh4_init(hose); - return 0; -} diff --git a/drivers/phy/phy-ab8500-usb.c b/drivers/phy/phy-ab8500-usb.c index 0e04595717..3d3d48c973 100644 --- a/drivers/phy/phy-ab8500-usb.c +++ b/drivers/phy/phy-ab8500-usb.c @@ -19,7 +19,7 @@ static int ab8500_usb_phy_power_on(struct phy *phy) struct udevice *dev = phy->dev; uint set = AB8500_BIT_PHY_CTRL_DEVICE_EN; - if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) + if (IS_ENABLED(CONFIG_USB_MUSB_HOST)) set = AB8500_BIT_PHY_CTRL_HOST_EN; return pmic_clrsetbits(dev->parent, AB8500_USB_PHY_CTRL_REG, diff --git a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c index 44a310f83d..e949cb7090 100644 --- a/drivers/pinctrl/broadcom/pinctrl-bcm283x.c +++ b/drivers/pinctrl/broadcom/pinctrl-bcm283x.c @@ -153,7 +153,7 @@ U_BOOT_DRIVER(pinctrl_bcm283x) = { .priv_auto = sizeof(struct bcm283x_pinctrl_priv), .ops = &bcm283x_pinctrl_ops, .probe = bcm283x_pinctl_probe, -#if CONFIG_IS_ENABLED(OF_BOARD) +#if IS_ENABLED(CONFIG_OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif }; diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 50e3dd449a..84b398619c 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -271,7 +271,7 @@ static int atmel_pinctrl_bind(struct udevice *dev) ofnode node = dev_ofnode(dev); struct atmel_pinctrl_data *priv = (struct atmel_pinctrl_data *)dev_get_driver_data(dev); - if (!CONFIG_IS_ENABLED(ATMEL_PIO4)) + if (!IS_ENABLED(CONFIG_ATMEL_PIO4)) return 0; /* Obtain a handle to the GPIO driver */ diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index bc9c17bce8..d80281fd3d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -541,7 +541,7 @@ static int single_probe(struct udevice *dev) INIT_LIST_HEAD(&priv->gpiofuncs); size = pdata->offset + pdata->width / BITS_PER_BYTE; - #if (CONFIG_IS_ENABLED(SANDBOX)) + #if (IS_ENABLED(CONFIG_SANDBOX)) priv->sandbox_regs = devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs), GFP_KERNEL); diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 1fedf63252..8f994d8d76 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -65,17 +65,23 @@ config PINCTRL_PFC_R8A774E1 help Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs. -config PINCTRL_PFC_R8A7795 +config PINCTRL_PFC_R8A77951 bool "Renesas RCar Gen3 R8A7795 pin control driver" depends on PINCTRL_PFC help Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs. -config PINCTRL_PFC_R8A7796 - bool "Renesas RCar Gen3 R8A7796 pin control driver" +config PINCTRL_PFC_R8A77960 + bool "Renesas RCar Gen3 R8A77960 pin control driver" depends on PINCTRL_PFC help - Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs. + Support pin multiplexing control on Renesas RCar Gen3 R8A77960 SoCs. + +config PINCTRL_PFC_R8A77961 + bool "Renesas RCar Gen3 R8A77961 pin control driver" + depends on PINCTRL_PFC + help + Support pin multiplexing control on Renesas RCar Gen3 R8A77961 SoCs. config PINCTRL_PFC_R8A77965 bool "Renesas RCar Gen3 R8A77965 pin control driver" diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index 1c65505eff..1198c86855 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -8,8 +8,9 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o -obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o -obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o +obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o +obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o +obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o obj-$(CONFIG_PINCTRL_PFC_R8A77980) += pfc-r8a77980.o diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index 1793000ab5..432895ac55 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -21,18 +21,23 @@ * which case they support both 3.3V and 1.8V signalling. */ #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_30(1, fn, sfx), \ - PORT_GP_30(2, fn, sfx), \ - PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) #define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ PIN_NOGP(IIC0_SDA, "AF15", fn), \ PIN_NOGP(IIC0_SCL, "AG15", fn), \ PIN_NOGP(IIC3_SDA, "AH15", fn), \ - PIN_NOGP(IIC3_SCL, "AJ15", fn) + PIN_NOGP(IIC3_SCL, "AJ15", fn), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -189,24 +194,24 @@ enum { FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, + FN_WE0_N, FN_IECLK, FN_CAN_CLK, FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, - FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, + FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, /* IPSR6 */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, + FN_DACK0, FN_IRQ0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, - FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, + FN_SSI_WS6_B, FN_SSI_SDATA8_C, FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, - FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, + FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, @@ -563,23 +568,23 @@ enum { CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, - INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, + WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, - IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, + IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, SSI_WS78_B_MARK, - DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, + DACK0_MARK, IRQ0_MARK, SSI_SCK6_B_MARK, VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, - INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, + SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, - MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, + MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, @@ -1089,7 +1094,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), - PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), @@ -1106,7 +1110,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), - PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), @@ -1120,7 +1123,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP6_2_0, DACK0), PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), - PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), @@ -1132,7 +1134,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), PINMUX_IPSR_GPSR(IP6_8_6, DACK1), PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), - PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), @@ -1141,7 +1142,6 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), PINMUX_IPSR_GPSR(IP6_13_11, DACK2), PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), - PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), @@ -2405,29 +2405,14 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7790 */ /* - MMCIF0 ----------------------------------------------------------------- */ -static const unsigned int mmc0_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int mmc0_data1_mux[] = { - MMC0_D0_MARK, -}; -static const unsigned int mmc0_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), - RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), -}; -static const unsigned int mmc0_data4_mux[] = { - MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, -}; -static const unsigned int mmc0_data8_pins[] = { +static const unsigned int mmc0_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), }; -static const unsigned int mmc0_data8_mux[] = { +static const unsigned int mmc0_data_mux[] = { MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, }; @@ -2439,29 +2424,14 @@ static const unsigned int mmc0_ctrl_mux[] = { MMC0_CLK_MARK, MMC0_CMD_MARK, }; /* - MMCIF1 ----------------------------------------------------------------- */ -static const unsigned int mmc1_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int mmc1_data1_mux[] = { - MMC1_D0_MARK, -}; -static const unsigned int mmc1_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), - RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), -}; -static const unsigned int mmc1_data4_mux[] = { - MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, -}; -static const unsigned int mmc1_data8_pins[] = { +static const unsigned int mmc1_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const unsigned int mmc1_data8_mux[] = { +static const unsigned int mmc1_data_mux[] = { MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, }; @@ -2808,19 +2778,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3317,18 +3280,11 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3353,18 +3309,11 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3389,18 +3338,11 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3425,18 +3367,11 @@ static const unsigned int sdhi2_wp_mux[] = { SD2_WP_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 26), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), }; -static const unsigned int sdhi3_data4_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, }; static const unsigned int sdhi3_ctrl_pins[] = { @@ -3674,18 +3609,11 @@ static const unsigned int tpu0_to3_mux[] = { }; /* - USB0 ------------------------------------------------------------------- */ static const unsigned int usb0_pins[] = { - /* PWEN, OVC/VBUS */ - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + /* OVC/VBUS, PWEN */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 18), }; static const unsigned int usb0_mux[] = { - USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, -}; -static const unsigned int usb0_ovc_vbus_pins[] = { - /* OVC/VBUS */ - RCAR_GP_PIN(5, 19), -}; -static const unsigned int usb0_ovc_vbus_mux[] = { - USB0_OVC_VBUS_MARK, + USB0_OVC_VBUS_MARK, USB0_PWEN_MARK, }; /* - USB1 ------------------------------------------------------------------- */ static const unsigned int usb1_pins[] = { @@ -3695,13 +3623,6 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; -static const unsigned int usb1_pwen_pins[] = { - /* PWEN */ - RCAR_GP_PIN(5, 20), -}; -static const unsigned int usb1_pwen_mux[] = { - USB1_PWEN_MARK, -}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3711,43 +3632,39 @@ static const unsigned int usb2_mux[] = { USB2_PWEN_MARK, USB2_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - /* G */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - /* R */ - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), - RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + /* G */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + /* R */ + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), + RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3804,43 +3721,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, - VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, - VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, - VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, - /* G */ - VI1_G0_MARK, VI1_G1_MARK, - VI1_G2_MARK, VI1_G3_MARK, - VI1_G4_MARK, VI1_G5_MARK, - VI1_G6_MARK, VI1_G7_MARK, - /* R */ - VI1_R0_MARK, VI1_R1_MARK, - VI1_R2_MARK, VI1_R3_MARK, - VI1_R4_MARK, VI1_R5_MARK, - VI1_R6_MARK, VI1_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, + VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, + VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, + VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, + /* G */ + VI1_G0_MARK, VI1_G1_MARK, + VI1_G2_MARK, VI1_G3_MARK, + VI1_G4_MARK, VI1_G5_MARK, + VI1_G6_MARK, VI1_G7_MARK, + /* R */ + VI1_R0_MARK, VI1_R1_MARK, + VI1_R2_MARK, VI1_R3_MARK, + VI1_R4_MARK, VI1_R5_MARK, + VI1_R6_MARK, VI1_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -3870,43 +3783,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_R4_MARK, VI1_R5_MARK, VI1_R6_MARK, VI1_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - /* G */ - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + /* G */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), + RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), + RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, - VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, - VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, - VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_VI1_B0_B_MARK, VI1_DATA1_VI1_B1_B_MARK, + VI1_DATA2_VI1_B2_B_MARK, VI1_DATA3_VI1_B3_B_MARK, + VI1_DATA4_VI1_B4_B_MARK, VI1_DATA5_VI1_B5_B_MARK, + VI1_DATA6_VI1_B6_B_MARK, VI1_DATA7_VI1_B7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -3989,83 +3898,67 @@ static const unsigned int vin1_clk_b_mux[] = { VI1_CLK_B_MARK, }; /* - VIN2 ----------------------------------------------------------------- */ -static const union vin_data vin2_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - /* G */ - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), - RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - /* R */ - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), - RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), - }, -}; -static const union vin_data vin2_data_mux = { - .data24 = { - /* B */ - VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, - VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, - VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, - VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, - /* G */ - VI2_G0_MARK, VI2_G1_MARK, - VI2_G2_MARK, VI2_G3_MARK, - VI2_G4_MARK, VI2_G5_MARK, - VI2_G6_MARK, VI2_G7_MARK, - /* R */ - VI2_R0_MARK, VI2_R1_MARK, - VI2_R2_MARK, VI2_R3_MARK, - VI2_R4_MARK, VI2_R5_MARK, - VI2_R6_MARK, VI2_R7_MARK, - }, -}; -static const unsigned int vin2_data18_pins[] = { +static const unsigned int vin2_data_pins[] = { /* B */ + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), /* G */ + RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), /* R */ + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), }; -static const unsigned int vin2_data18_mux[] = { +static const unsigned int vin2_data_mux[] = { /* B */ + VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, /* G */ + VI2_G0_MARK, VI2_G1_MARK, VI2_G2_MARK, VI2_G3_MARK, VI2_G4_MARK, VI2_G5_MARK, VI2_G6_MARK, VI2_G7_MARK, /* R */ + VI2_R0_MARK, VI2_R1_MARK, VI2_R2_MARK, VI2_R3_MARK, VI2_R4_MARK, VI2_R5_MARK, VI2_R6_MARK, VI2_R7_MARK, }; -static const unsigned int vin2_g8_pins[] = { - RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), +static const unsigned int vin2_data18_pins[] = { + /* B */ + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + /* G */ RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + /* R */ + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), + RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), }; -static const unsigned int vin2_g8_mux[] = { - VI2_G0_MARK, VI2_G1_MARK, +static const unsigned int vin2_data18_mux[] = { + /* B */ + VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, + VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, + VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, + /* G */ VI2_G2_MARK, VI2_G3_MARK, VI2_G4_MARK, VI2_G5_MARK, VI2_G6_MARK, VI2_G7_MARK, + /* R */ + VI2_R2_MARK, VI2_R3_MARK, + VI2_R4_MARK, VI2_R5_MARK, + VI2_R6_MARK, VI2_R7_MARK, }; static const unsigned int vin2_sync_pins[] = { RCAR_GP_PIN(1, 16), /* HSYNC */ @@ -4218,13 +4111,13 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), + BUS_DATA_PIN_GROUP(mmc0_data, 1), + BUS_DATA_PIN_GROUP(mmc0_data, 4), + BUS_DATA_PIN_GROUP(mmc0_data, 8), SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), + BUS_DATA_PIN_GROUP(mmc1_data, 1), + BUS_DATA_PIN_GROUP(mmc1_data, 4), + BUS_DATA_PIN_GROUP(mmc1_data, 8), SH_PFC_PIN_GROUP(mmc1_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4274,8 +4167,8 @@ static const struct { SH_PFC_PIN_GROUP(pwm5), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4345,23 +4238,23 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_c), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4396,38 +4289,38 @@ static const struct { SH_PFC_PIN_GROUP(tpu0_to2), SH_PFC_PIN_GROUP(tpu0_to3), SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP_SUBSET(usb0_ovc_vbus, usb0, 0, 1), SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb1_pwen), + SH_PFC_PIN_GROUP_SUBSET(usb1_pwen, usb1, 0, 1), SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 4), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 4), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), - VIN_DATA_PIN_GROUP(vin1_data, 4, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 4, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field), @@ -4436,12 +4329,12 @@ static const struct { SH_PFC_PIN_GROUP(vin1_clkenb_b), SH_PFC_PIN_GROUP(vin1_clk), SH_PFC_PIN_GROUP(vin1_clk_b), - VIN_DATA_PIN_GROUP(vin2_data, 24), + BUS_DATA_PIN_GROUP(vin2_data, 24), SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_g8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP_SUBSET(vin2_g8, vin2_data, 8, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), @@ -4959,10 +4852,10 @@ static const struct { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), SH_PFC_FUNCTION(can_clk), + SH_PFC_FUNCTION(du), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), @@ -5229,10 +5122,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_0_FN, FN_IP14_21_19 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3), + GROUP(-1, 4, 4, 3, 4, 4, 3, 3, 3, 3), GROUP( - /* IP0_31 [1] */ - 0, 0, + /* IP0_31 [1] RESERVED */ /* IP0_30_27 [4] */ FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, @@ -5266,10 +5158,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4), + GROUP(-2, 2, 2, 4, 4, 3, 3, 4, 4, 4), GROUP( - /* IP1_31_30 [2] */ - 0, 0, 0, 0, + /* IP1_31_30 [2] RESERVED */ /* IP1_29_28 [2] */ FN_A1, FN_PWM4, 0, 0, /* IP1_27_26 [2] */ @@ -5304,10 +5195,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3), + GROUP(-3, 3, 4, 4, 3, 3, 3, 3, 3, 3), GROUP( - /* IP2_31_29 [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_31_29 [3] RESERVED */ /* IP2_28_26 [3] */ FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, @@ -5368,10 +5258,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), GROUP( - /* IP4_31_30 [2] */ - 0, 0, 0, 0, + /* IP4_31_30 [2] RESERVED */ /* IP4_29_27 [3] */ FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, @@ -5402,17 +5291,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, - GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), + GROUP(-2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3), GROUP( - /* IP5_31_30 [2] */ - 0, 0, 0, 0, + /* IP5_31_30 [2] RESERVED */ /* IP5_29_27 [3] */ FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, /* IP5_26_24 [3] */ - FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, - FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, - FN_MSIOF0_SCK_B, 0, + FN_EX_WAIT0, FN_IRQ3, 0, FN_VI3_CLK, FN_SCIFA0_RTS_N_B, + FN_HRX0_B, FN_MSIOF0_SCK_B, 0, /* IP5_23_21 [3] */ FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, @@ -5421,7 +5308,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, /* IP5_17_15 [3] */ FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, - FN_INTC_IRQ4_N, 0, 0, + 0, 0, 0, /* IP5_14_13 [2] */ FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, /* IP5_12_10 [3] */ @@ -5462,25 +5349,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, FN_I2C2_SCL_E, 0, /* IP6_13_11 [3] */ - FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, - FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, + FN_DACK2, FN_IRQ2, 0, FN_SSI_SDATA6_B, FN_HRTS0_N_B, + FN_MSIOF0_RXD_B, 0, 0, /* IP6_10_9 [2] */ FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, /* IP6_8_6 [3] */ - FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, - FN_SSI_SDATA8_C, 0, 0, 0, + FN_DACK1, FN_IRQ1, 0, FN_SSI_WS6_B, FN_SSI_SDATA8_C, 0, 0, 0, /* IP6_5_3 [3] */ FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, /* IP6_2_0 [3] */ - FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, - FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) + FN_DACK0, FN_IRQ0, 0, FN_SSI_SCK6_B, FN_VI1_VSYNC_N, + FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), + GROUP(-1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3), GROUP( - /* IP7_31 [1] */ - 0, 0, + /* IP7_31 [1] RESERVED */ /* IP7_30_29 [2] */ FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, /* IP7_28_27 [2] */ @@ -5513,11 +5398,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, + GROUP(-1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2), GROUP( - /* IP8_31 [1] */ - 0, 0, + /* IP8_31 [1] RESERVED */ /* IP8_30_29 [2] */ FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, /* IP8_28 [1] */ @@ -5591,10 +5475,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, - GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4), + GROUP(-2, 4, 3, 4, 4, 4, 4, 3, 4), GROUP( - /* IP10_31_30 [2] */ - 0, 0, 0, 0, + /* IP10_31_30 [2] RESERVED */ /* IP10_29_26 [4] */ FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, @@ -5667,10 +5550,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), + GROUP(-1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2), GROUP( - /* IP12_31 [1] */ - 0, 0, + /* IP12_31 [1] RESERVED */ /* IP12_30_28 [3] */ FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, @@ -5707,10 +5589,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), + GROUP(-1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3), GROUP( - /* IP13_31 [1] */ - 0, 0, + /* IP13_31 [1] RESERVED */ /* IP13_30_29 [2] */ FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, /* IP13_28_26 [3] */ @@ -5744,10 +5625,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, - GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), + GROUP(-1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3), GROUP( - /* IP14_30 [1] */ - 0, 0, + /* IP14_30 [1] RESERVED */ /* IP14_30_28 [3] */ FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, @@ -5783,10 +5663,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_REMOCON, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP(-2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3), GROUP( - /* IP15_31_30 [2] */ - 0, 0, 0, 0, + /* IP15_31_30 [2] RESERVED */ /* IP15_29_28 [2] */ FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, /* IP15_27_26 [2] */ @@ -5819,26 +5698,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_LCDOUT15, FN_SCIF_CLK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3), + GROUP(-24, 1, 1, 3, 3), GROUP( - /* IP16_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_19_16 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_15_12 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_11_8 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, + /* IP16_31_8 [24] RESERVED */ /* IP16_7 [1] */ FN_USB1_OVC, FN_TCLK1_B, /* IP16_6 [1] */ @@ -5852,7 +5714,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1, - 1, 1, 1, 2, 1, 1, 2, 1, 1), + 1, 1, 1, 2, -1, 1, 2, 1, 1), GROUP( /* SEL_SCIF1 [3] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, @@ -5891,7 +5753,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_TSIF1 [2] */ FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, /* RESERVED [1] */ - 0, 0, /* SEL_LBS [1] */ FN_SEL_LBS_0, FN_SEL_LBS_1, /* SEL_TSIF0 [2] */ @@ -5902,11 +5763,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SOF0_0, FN_SEL_SOF0_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1, - 3, 3, 2, 3, 2, 2), + GROUP(-3, 1, 1, 1, 2, 1, 2, 1, -2, 1, 1, 1, + 3, 3, 2, -3, 2, 2), GROUP( /* RESERVED [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_TMU1 [1] */ FN_SEL_TMU1_0, FN_SEL_TMU1_1, /* SEL_HSCIF1 [1] */ @@ -5922,7 +5782,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_CAN1 [1] */ FN_SEL_CAN1_0, FN_SEL_CAN1_1, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_SCIF2 [1] */ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, /* SEL_ADI [1] */ @@ -5938,36 +5797,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_GPS [2] */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, /* RESERVED [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_SIM [2] */ FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, /* SEL_SSI8 [2] */ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2), + GROUP(1, 1, -12, 2, -6, 3, 2, 3, 2), GROUP( /* SEL_IICDVFS [1] */ FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, /* SEL_IIC0 [1] */ FN_SEL_IIC0_0, FN_SEL_IIC0_1, - /* RESERVED [2] */ - 0, 0, 0, 0, - /* RESERVED [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, + /* RESERVED [12] */ /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, - /* RESERVED [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, + /* RESERVED [6] */ /* SEL_IIC2 [3] */ FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, FN_SEL_IIC2_4, 0, 0, 0, @@ -5982,7 +5827,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; -static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31)) return -EINVAL; @@ -5992,6 +5837,284 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return 31 - (pin & 0x1f); } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 16), /* A0 */ + [ 1] = RCAR_GP_PIN(0, 17), /* A1 */ + [ 2] = RCAR_GP_PIN(0, 18), /* A2 */ + [ 3] = RCAR_GP_PIN(0, 19), /* A3 */ + [ 4] = RCAR_GP_PIN(0, 20), /* A4 */ + [ 5] = RCAR_GP_PIN(0, 21), /* A5 */ + [ 6] = RCAR_GP_PIN(0, 22), /* A6 */ + [ 7] = RCAR_GP_PIN(0, 23), /* A7 */ + [ 8] = RCAR_GP_PIN(0, 24), /* A8 */ + [ 9] = RCAR_GP_PIN(0, 25), /* A9 */ + [10] = RCAR_GP_PIN(0, 26), /* A10 */ + [11] = RCAR_GP_PIN(0, 27), /* A11 */ + [12] = RCAR_GP_PIN(0, 28), /* A12 */ + [13] = RCAR_GP_PIN(0, 29), /* A13 */ + [14] = RCAR_GP_PIN(0, 30), /* A14 */ + [15] = RCAR_GP_PIN(0, 31), /* A15 */ + [16] = RCAR_GP_PIN(1, 0), /* A16 */ + [17] = RCAR_GP_PIN(1, 1), /* A17 */ + [18] = RCAR_GP_PIN(1, 2), /* A18 */ + [19] = RCAR_GP_PIN(1, 3), /* A19 */ + [20] = RCAR_GP_PIN(1, 4), /* A20 */ + [21] = RCAR_GP_PIN(1, 5), /* A21 */ + [22] = RCAR_GP_PIN(1, 6), /* A22 */ + [23] = RCAR_GP_PIN(1, 7), /* A23 */ + [24] = RCAR_GP_PIN(1, 8), /* A24 */ + [25] = RCAR_GP_PIN(1, 9), /* A25 */ + [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + /* PUPR1 pull-up pins */ + [ 0] = RCAR_GP_PIN(1, 18), /* BS# */ + [ 1] = RCAR_GP_PIN(1, 19), /* RD# */ + [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */ + [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */ + [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */ + [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */ + [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */ + [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [10] = PIN_TRST_N, /* TRST# */ + [11] = PIN_TCK, /* TCK */ + [12] = PIN_TMS, /* TMS */ + [13] = PIN_TDI, /* TDI */ + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = RCAR_GP_PIN(0, 0), /* D0 */ + [17] = RCAR_GP_PIN(0, 1), /* D1 */ + [18] = RCAR_GP_PIN(0, 2), /* D2 */ + [19] = RCAR_GP_PIN(0, 3), /* D3 */ + [20] = RCAR_GP_PIN(0, 4), /* D4 */ + [21] = RCAR_GP_PIN(0, 5), /* D5 */ + [22] = RCAR_GP_PIN(0, 6), /* D6 */ + [23] = RCAR_GP_PIN(0, 7), /* D7 */ + [24] = RCAR_GP_PIN(0, 8), /* D8 */ + [25] = RCAR_GP_PIN(0, 9), /* D9 */ + [26] = RCAR_GP_PIN(0, 10), /* D10 */ + [27] = RCAR_GP_PIN(0, 11), /* D11 */ + [28] = RCAR_GP_PIN(0, 12), /* D12 */ + [29] = RCAR_GP_PIN(0, 13), /* D13 */ + [30] = RCAR_GP_PIN(0, 14), /* D14 */ + [31] = RCAR_GP_PIN(0, 15), /* D15 */ + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { + /* PUPR1 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */ + [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */ + [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */ + [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */ + [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */ + [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */ + [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */ + [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */ + [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */ + [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */ + [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */ + [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */ + [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */ + [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */ + [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */ + [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */ + [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */ + [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */ + [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */ + [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */ + [30] = SH_PFC_PIN_NONE, + [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */ + [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */ + [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */ + [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */ + [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */ + [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */ + [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */ + [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */ + [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */ + [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */ + [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */ + [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */ + [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */ + [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */ + [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */ + [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */ + [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */ + [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */ + [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */ + [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */ + [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */ + [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */ + [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */ + [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */ + [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */ + [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */ + [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */ + [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */ + [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */ + [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */ + [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */ + [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */ + [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */ + [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */ + [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */ + [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */ + [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */ + [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */ + [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */ + [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */ + [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */ + [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */ + [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */ + [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */ + [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */ + [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */ + [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */ + [25] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */ + [27] = RCAR_GP_PIN(1, 27), /* DACK1 */ + [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */ + [29] = RCAR_GP_PIN(1, 29), /* DACK2 */ + [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */ + [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */ + [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */ + [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */ + [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */ + [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */ + [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */ + [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */ + [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */ + [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */ + [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */ + [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */ + [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */ + [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */ + [13] = RCAR_GP_PIN(5, 8), /* HRX0 */ + [14] = RCAR_GP_PIN(5, 9), /* HTX0 */ + [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */ + [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */ + [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */ + [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ + [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ + [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */ + [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */ + [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */ + [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */ + [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */ + [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */ + [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */ + [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */ + [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */ + [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */ + [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */ + [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */ + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */ + [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */ + [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */ + [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */ + [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */ + [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */ + [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */ + [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */ + [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */ + [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */ + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) { /* Initialize TDSEL on old revisions */ @@ -6002,15 +6125,40 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7790_pfc_ops = { .init = r8a7790_pinmux_soc_init, .pin_to_pocctrl = r8a7790_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + +#ifdef CONFIG_PINCTRL_PFC_R8A7742 +const struct sh_pfc_soc_info r8a7742_pinmux_info = { + .name = "r8a77420_pfc", + .ops = &r8a7790_pfc_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", - .ops = &r8a7790_pinmux_ops, + .ops = &r8a7790_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6025,6 +6173,7 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c index 7c8db5dc2c..219333106f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7791.c +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c @@ -19,22 +19,50 @@ * which case they support both 3.3V and 1.8V signalling. */ #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx), \ - PORT_GP_1(6, 26, fn, sfx), \ - PORT_GP_1(6, 27, fn, sfx), \ - PORT_GP_1(6, 28, fn, sfx), \ - PORT_GP_1(6, 29, fn, sfx), \ - PORT_GP_1(6, 30, fn, sfx), \ - PORT_GP_1(6, 31, fn, sfx), \ - PORT_GP_26(7, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 30, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 31, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(7, 7, fn, sfx), \ + PORT_GP_1(7, 8, fn, sfx), \ + PORT_GP_1(7, 9, fn, sfx), \ + PORT_GP_CFG_1(7, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(7, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(AVS1, "AVS1", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(AVS2, "AVS2", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -209,11 +237,11 @@ enum { FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2, FN_SCIFA2_RXD, FN_FMIN_E, FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ0, FN_SCIFB1_RXD_D, + FN_IRQ1, FN_SCIFB1_SCK_C, + FN_IRQ2, FN_SCIFB1_TXD_D, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, @@ -581,12 +609,12 @@ enum { AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK, SCIFA2_RXD_MARK, FMIN_E_MARK, AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK, - IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, - IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, - IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ0_MARK, SCIFB1_RXD_D_MARK, + IRQ1_MARK, SCIFB1_SCK_C_MARK, + IRQ2_MARK, SCIFB1_TXD_D_MARK, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, - MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, + MSIOF2_RXD_E_MARK, IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, @@ -1115,22 +1143,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_GPSR(IP6_9_8, IRQ0), PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N), PINMUX_IPSR_GPSR(IP6_11_10, IRQ1), PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2), - PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N), PINMUX_IPSR_GPSR(IP6_13_12, IRQ2), PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), - PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), - PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), @@ -1699,8 +1722,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793) @@ -2269,13 +2301,6 @@ static const unsigned int hscif1_data_d_pins[] = { static const unsigned int hscif1_data_d_mux[] = { HRX1_D_MARK, HTX1_D_MARK, }; -static const unsigned int hscif1_data_e_pins[] = { - /* RX, TX */ - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), -}; -static const unsigned int hscif1_data_e_mux[] = { - HRX1_C_MARK, HTX1_C_MARK, -}; static const unsigned int hscif1_clk_e_pins[] = { /* SCK */ RCAR_GP_PIN(2, 6), @@ -2570,40 +2595,25 @@ static const unsigned int mlb_3pin_mux[] = { #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */ /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; -static const unsigned int mmc_data8_b_pins[] = { +static const unsigned int mmc_data_b_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), }; -static const unsigned int mmc_data8_b_mux[] = { +static const unsigned int mmc_data_b_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK, }; @@ -3191,19 +3201,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; @@ -3214,19 +3217,12 @@ static const unsigned int qspi_ctrl_b_pins[] = { static const unsigned int qspi_ctrl_b_mux[] = { SPCLK_B_MARK, SSL_B_MARK, }; -static const unsigned int qspi_data2_b_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), -}; -static const unsigned int qspi_data2_b_mux[] = { - MOSI_IO0_B_MARK, MISO_IO1_B_MARK, -}; -static const unsigned int qspi_data4_b_pins[] = { +static const unsigned int qspi_data_b_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), }; -static const unsigned int qspi_data4_b_mux[] = { +static const unsigned int qspi_data_b_mux[] = { MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3787,19 +3783,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3824,19 +3813,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3861,19 +3843,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -4196,43 +4171,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), - RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), - /* G */ - RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), - RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), - RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), - RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), - /* R */ - RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), - RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), - RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), - RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), + RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), + RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), + RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), + /* G */ + RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), + RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), + RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), + RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), + /* R */ + RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), + RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), + RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), + RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -4327,43 +4298,39 @@ static const unsigned int vin1_clk_pins[] = { static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - /* G */ - RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), - RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), - RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), - RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), - /* R */ - RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + /* G */ + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), + RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22), + /* R */ + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, - VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, - VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, - VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, - /* G */ - VI1_G0_B_MARK, VI1_G1_B_MARK, - VI1_G2_B_MARK, VI1_G3_B_MARK, - VI1_G4_B_MARK, VI1_G5_B_MARK, - VI1_G6_B_MARK, VI1_G7_B_MARK, - /* R */ - VI1_R0_B_MARK, VI1_R1_B_MARK, - VI1_R2_B_MARK, VI1_R3_B_MARK, - VI1_R4_B_MARK, VI1_R5_B_MARK, - VI1_R6_B_MARK, VI1_R7_B_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_DATA0_B_MARK, VI1_DATA1_B_MARK, + VI1_DATA2_B_MARK, VI1_DATA3_B_MARK, + VI1_DATA4_B_MARK, VI1_DATA5_B_MARK, + VI1_DATA6_B_MARK, VI1_DATA7_B_MARK, + /* G */ + VI1_G0_B_MARK, VI1_G1_B_MARK, + VI1_G2_B_MARK, VI1_G3_B_MARK, + VI1_G4_B_MARK, VI1_G5_B_MARK, + VI1_G6_B_MARK, VI1_G7_B_MARK, + /* R */ + VI1_R0_B_MARK, VI1_R1_B_MARK, + VI1_R2_B_MARK, VI1_R3_B_MARK, + VI1_R4_B_MARK, VI1_R5_B_MARK, + VI1_R6_B_MARK, VI1_R7_B_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -4522,7 +4489,7 @@ static const struct { SH_PFC_PIN_GROUP(hscif1_clk_c), SH_PFC_PIN_GROUP(hscif1_ctrl_c), SH_PFC_PIN_GROUP(hscif1_data_d), - SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP_ALIAS(hscif1_data_e, hscif1_data_c), SH_PFC_PIN_GROUP(hscif1_clk_e), SH_PFC_PIN_GROUP(hscif1_ctrl_e), SH_PFC_PIN_GROUP(hscif2_data), @@ -4562,10 +4529,10 @@ static const struct { SH_PFC_PIN_GROUP(intc_irq1), SH_PFC_PIN_GROUP(intc_irq2), SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_data8_b), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), + BUS_DATA_PIN_GROUP(mmc_data, 8, _b), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -4649,11 +4616,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm5_b), SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(qspi_ctrl_b), - SH_PFC_PIN_GROUP(qspi_data2_b), - SH_PFC_PIN_GROUP(qspi_data4_b), + BUS_DATA_PIN_GROUP(qspi_data, 2, _b), + BUS_DATA_PIN_GROUP(qspi_data, 4, _b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -4731,18 +4698,18 @@ static const struct { SH_PFC_PIN_GROUP(scifb2_data_d), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4780,13 +4747,13 @@ static const struct { SH_PFC_PIN_GROUP(tpu_to3), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), @@ -4796,13 +4763,13 @@ static const struct { SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), - VIN_DATA_PIN_GROUP(vin1_data, 12, _b), - VIN_DATA_PIN_GROUP(vin1_data, 10, _b), - VIN_DATA_PIN_GROUP(vin1_data, 8, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 12, _b), + BUS_DATA_PIN_GROUP(vin1_data, 10, _b), + BUS_DATA_PIN_GROUP(vin1_data, 8, _b), SH_PFC_PIN_GROUP(vin1_sync_b), SH_PFC_PIN_GROUP(vin1_field_b), SH_PFC_PIN_GROUP(vin1_clkenb_b), @@ -5722,11 +5689,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_0_FN, FN_IP15_17_15 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, - GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, + GROUP(-1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP0_31 [1] */ - 0, 0, + /* IP0_31 [1] RESERVED */ /* IP0_30_29 [2] */ FN_A6, FN_MSIOF1_SCK, 0, 0, @@ -5819,10 +5785,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, - GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), + GROUP(-2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3), GROUP( - /* IP2_31_30 [2] */ - 0, 0, 0, 0, + /* IP2_31_30 [2] RESERVED */ /* IP2_29_27 [3] */ FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, 0, FN_EX_WAIT1, @@ -5856,10 +5821,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, - GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), + GROUP(-1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3), GROUP( - /* IP3_31 [1] */ - 0, 0, + /* IP3_31 [1] RESERVED */ /* IP3_30_28 [3] */ FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, @@ -5895,11 +5859,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, - GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, + GROUP(-1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2), GROUP( - /* IP4_31 [1] */ - 0, 0, + /* IP4_31 [1] RESERVED */ /* IP4_30_28 [3] */ FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0, FN_MSIOF2_SYNC_D, FN_VI1_R2_B, @@ -5979,10 +5942,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, - GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), + GROUP(-2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3), GROUP( - /* IP6_31_30 [2] */ - 0, 0, 0, 0, + /* IP6_31_30 [2] RESERVED */ /* IP6_29_27 [3] */ FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, @@ -5999,15 +5961,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, /* IP6_18_16 [3] */ FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, - FN_INTC_IRQ4_N, 0, 0, 0, + 0, 0, 0, 0, /* IP6_15_14 [2] */ - FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, 0, /* IP6_13_12 [2] */ - FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, + FN_IRQ2, FN_SCIFB1_TXD_D, 0, 0, /* IP6_11_10 [2] */ - FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0, + FN_IRQ1, FN_SCIFB1_SCK_C, 0, 0, /* IP6_9_8 [2] */ - FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0, + FN_IRQ0, FN_SCIFB1_RXD_D, 0, 0, /* IP6_7_6 [2] */ FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD, /* IP6_5_3 [3] */ @@ -6020,10 +5982,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), + GROUP(-2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3), GROUP( - /* IP7_31_30 [2] */ - 0, 0, 0, 0, + /* IP7_31_30 [2] RESERVED */ /* IP7_29_27 [3] */ FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B, FN_SCIFA1_SCK, FN_SSI_SCK78_B, @@ -6062,10 +6023,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, - GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP(-1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3), GROUP( - /* IP8_31 [1] */ - 0, 0, + /* IP8_31 [1] RESERVED */ /* IP8_30_28 [3] */ FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, 0, 0, 0, @@ -6237,10 +6197,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_I2C1_SDA_D, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), + GROUP(-2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2), GROUP( - /* IP12_31_30 [2] */ - 0, 0, 0, 0, + /* IP12_31_30 [2] RESERVED */ /* IP12_29_27 [3] */ FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D, FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C, @@ -6279,11 +6238,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, + GROUP(-1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, 3, 2, 2, 3), GROUP( - /* IP13_31 [1] */ - 0, 0, + /* IP13_31 [1] RESERVED */ /* IP13_30_28 [3] */ FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 0, 0, 0, 0, @@ -6376,10 +6334,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, - GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), + GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2), GROUP( - /* IP15_31_30 [2] */ - 0, 0, 0, 0, + /* IP15_31_30 [2] RESERVED */ /* IP15_29_27 [3] */ FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C, @@ -6418,23 +6375,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, - GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3), + GROUP(-20, 2, 2, 2, 3, 3), GROUP( - /* IP16_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_19_16 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* IP16_15_12 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED [20] */ /* IP16_11_10 [2] */ FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B, /* IP16_9_8 [2] */ @@ -6451,11 +6394,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2, - 2, 2, 1, 2, 2, 2), + GROUP(-1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, -2, + 2, -2, 1, 2, 2, 2), GROUP( /* RESERVED [1] */ - 0, 0, /* SEL_SCIF1 [2] */ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, /* SEL_SCIFB [2] */ @@ -6482,11 +6424,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_VI1 [2] */ FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU1_0, FN_SEL_TMU1_1, /* SEL_LBS [2] */ @@ -6497,15 +6437,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, - GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2, - 1, 2, 2, 2, 1, 1, 1), + GROUP(3, -1, 1, 3, 2, -1, 1, 2, -2, 1, 3, 2, + -1, 2, 2, 2, 1, -1, 1), GROUP( /* SEL_SCIF0 [3] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, FN_SEL_SCIF0_4, 0, 0, 0, /* RESERVED [1] */ - 0, 0, /* SEL_SCIF [1] */ FN_SEL_SCIF_0, FN_SEL_SCIF_1, /* SEL_CAN0 [3] */ @@ -6515,13 +6454,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_CAN1 [2] */ FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, /* RESERVED [1] */ - 0, 0, /* SEL_SCIFA2 [1] */ FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, /* SEL_SCIF4 [2] */ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_ADG [1] */ FN_SEL_ADG_0, FN_SEL_ADG_1, /* SEL_FM [3] */ @@ -6531,7 +6468,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIFA5 [2] */ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0, /* RESERVED [1] */ - 0, 0, /* SEL_GPS [2] */ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3, /* SEL_SCIFA4 [2] */ @@ -6541,13 +6477,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SIM [1] */ FN_SEL_SIM_0, FN_SEL_SIM_1, /* RESERVED [1] */ - 0, 0, /* SEL_SSI8 [1] */ FN_SEL_SSI8_0, FN_SEL_SSI8_1, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, - GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2, - 3, 2, 2, 2, 1), + GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, -2, 2, + 3, 2, -5), GROUP( /* SEL_HSCIF2 [2] */ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, @@ -6572,7 +6507,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF5 [1] */ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_I2C2 [2] */ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, /* SEL_I2C1 [3] */ @@ -6581,16 +6515,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* SEL_I2C0 [2] */ FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, - /* RESERVED [1] */ - 0, 0, )) + /* RESERVED [5] */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32, - GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1, - 1, 1, 2, 2, 2, 2), + GROUP(3, 2, 2, -1, 1, 1, 1, 3, -4, 3, -1, + 1, 1, 2, -6), GROUP( /* SEL_SOF1 [3] */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, @@ -6601,7 +6530,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_DIS [2] */ FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0, /* RESERVED [1] */ - 0, 0, /* SEL_RAD [1] */ FN_SEL_RAD_0, FN_SEL_RAD_1, /* SEL_RCN [1] */ @@ -6613,32 +6541,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF2_3, FN_SEL_SCIF2_4, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, /* RESERVED [2] */ - 0, 0, 0, 0, /* SEL_SOF2 [3] */ FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3, FN_SEL_SOF2_4, 0, 0, 0, /* RESERVED [1] */ - 0, 0, /* SEL_SSI1 [1] */ FN_SEL_SSI1_0, FN_SEL_SSI1_1, /* SEL_SSI0 [1] */ FN_SEL_SSI0_0, FN_SEL_SSI0_1, /* SEL_SSP [2] */ FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, - /* RESERVED [2] */ - 0, 0, 0, 0, )) + /* RESERVED [6] */ )) }, { }, }; -static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) return -EINVAL; @@ -6648,14 +6568,328 @@ static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return 31 - (pin & 0x1f); } -static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 4), /* A20 */ + [ 1] = RCAR_GP_PIN(1, 5), /* A21 */ + [ 2] = RCAR_GP_PIN(1, 6), /* A22 */ + [ 3] = RCAR_GP_PIN(1, 7), /* A23 */ + [ 4] = RCAR_GP_PIN(1, 8), /* A24 */ + [ 5] = RCAR_GP_PIN(6, 31), /* DU0_DOTCLKIN */ + [ 6] = RCAR_GP_PIN(0, 0), /* D0 */ + [ 7] = RCAR_GP_PIN(0, 1), /* D1 */ + [ 8] = RCAR_GP_PIN(0, 2), /* D2 */ + [ 9] = RCAR_GP_PIN(0, 3), /* D3 */ + [10] = RCAR_GP_PIN(0, 4), /* D4 */ + [11] = RCAR_GP_PIN(0, 5), /* D5 */ + [12] = RCAR_GP_PIN(0, 6), /* D6 */ + [13] = RCAR_GP_PIN(0, 7), /* D7 */ + [14] = RCAR_GP_PIN(0, 8), /* D8 */ + [15] = RCAR_GP_PIN(0, 9), /* D9 */ + [16] = RCAR_GP_PIN(0, 10), /* D10 */ + [17] = RCAR_GP_PIN(0, 11), /* D11 */ + [18] = RCAR_GP_PIN(0, 12), /* D12 */ + [19] = RCAR_GP_PIN(0, 13), /* D13 */ + [20] = RCAR_GP_PIN(0, 14), /* D14 */ + [21] = RCAR_GP_PIN(0, 15), /* D15 */ + [22] = RCAR_GP_PIN(0, 16), /* A0 */ + [23] = RCAR_GP_PIN(0, 17), /* A1 */ + [24] = RCAR_GP_PIN(0, 18), /* A2 */ + [25] = RCAR_GP_PIN(0, 19), /* A3 */ + [26] = RCAR_GP_PIN(0, 20), /* A4 */ + [27] = RCAR_GP_PIN(0, 21), /* A5 */ + [28] = RCAR_GP_PIN(0, 22), /* A6 */ + [29] = RCAR_GP_PIN(0, 23), /* A7 */ + [30] = RCAR_GP_PIN(0, 24), /* A8 */ + [31] = RCAR_GP_PIN(0, 25), /* A9 */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 26), /* A10 */ + [ 1] = RCAR_GP_PIN(0, 27), /* A11 */ + [ 2] = RCAR_GP_PIN(0, 28), /* A12 */ + [ 3] = RCAR_GP_PIN(0, 29), /* A13 */ + [ 4] = RCAR_GP_PIN(0, 30), /* A14 */ + [ 5] = RCAR_GP_PIN(0, 31), /* A15 */ + [ 6] = RCAR_GP_PIN(1, 0), /* A16 */ + [ 7] = RCAR_GP_PIN(1, 1), /* A17 */ + [ 8] = RCAR_GP_PIN(1, 2), /* A18 */ + [ 9] = RCAR_GP_PIN(1, 3), /* A19 */ + [10] = PIN_TRST_N, /* TRST# */ + [11] = PIN_TCK, /* TCK */ + [12] = PIN_TMS, /* TMS */ + [13] = PIN_TDI, /* TDI */ + [14] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [15] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [16] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [17] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [18] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [19] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [20] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + [21] = RCAR_GP_PIN(1, 18), /* BS# */ + [22] = RCAR_GP_PIN(1, 19), /* RD# */ + [23] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [24] = RCAR_GP_PIN(1, 21), /* WE0# */ + [25] = RCAR_GP_PIN(1, 22), /* WE1# */ + [26] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [27] = RCAR_GP_PIN(1, 24), /* DREQ0 */ + [28] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [29] = RCAR_GP_PIN(5, 31), /* SPEEDIN */ + [30] = RCAR_GP_PIN(2, 0), /* SSI_SCK0129 */ + [31] = RCAR_GP_PIN(2, 1), /* SSI_WS0129 */ + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 2), /* SSI_SDATA0 */ + [ 1] = RCAR_GP_PIN(2, 3), /* SSI_SCK1 */ + [ 2] = RCAR_GP_PIN(2, 4), /* SSI_WS1 */ + [ 3] = RCAR_GP_PIN(2, 5), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(2, 6), /* SSI_SCK2 */ + [ 5] = RCAR_GP_PIN(2, 7), /* SSI_WS2 */ + [ 6] = RCAR_GP_PIN(2, 8), /* SSI_SDATA2 */ + [ 7] = RCAR_GP_PIN(2, 9), /* SSI_SCK34 */ + [ 8] = RCAR_GP_PIN(2, 10), /* SSI_WS34 */ + [ 9] = RCAR_GP_PIN(2, 11), /* SSI_SDATA3 */ + [10] = RCAR_GP_PIN(2, 12), /* SSI_SCK4 */ + [11] = RCAR_GP_PIN(2, 13), /* SSI_WS4 */ + [12] = RCAR_GP_PIN(2, 14), /* SSI_SDATA4 */ + [13] = RCAR_GP_PIN(2, 15), /* SSI_SCK5 */ + [14] = RCAR_GP_PIN(2, 16), /* SSI_WS5 */ + [15] = RCAR_GP_PIN(2, 17), /* SSI_SDATA5 */ + [16] = RCAR_GP_PIN(2, 18), /* SSI_SCK6 */ + [17] = RCAR_GP_PIN(2, 19), /* SSI_WS6 */ + [18] = RCAR_GP_PIN(2, 20), /* SSI_SDATA6 */ + [19] = RCAR_GP_PIN(2, 21), /* SSI_SCK78 */ + [20] = RCAR_GP_PIN(2, 22), /* SSI_WS78 */ + [21] = RCAR_GP_PIN(2, 23), /* SSI_SDATA7 */ + [22] = RCAR_GP_PIN(2, 24), /* SSI_SDATA8 */ + [23] = RCAR_GP_PIN(2, 25), /* SSI_SCK9 */ + [24] = RCAR_GP_PIN(2, 26), /* SSI_WS9 */ + [25] = RCAR_GP_PIN(2, 27), /* SSI_SDATA9 */ + [26] = RCAR_GP_PIN(2, 28), /* AUDIO_CLKA */ + [27] = RCAR_GP_PIN(2, 29), /* AUDIO_CLKB */ + [28] = RCAR_GP_PIN(2, 30), /* AUDIO_CLKC */ + [29] = RCAR_GP_PIN(2, 31), /* AUDIO_CLKOUT */ + [30] = RCAR_GP_PIN(7, 10), /* IRQ0 */ + [31] = RCAR_GP_PIN(7, 11), /* IRQ1 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(7, 12), /* IRQ2 */ + [ 1] = RCAR_GP_PIN(7, 13), /* IRQ3 */ + [ 2] = RCAR_GP_PIN(7, 14), /* IRQ4 */ + [ 3] = RCAR_GP_PIN(7, 15), /* IRQ5 */ + [ 4] = RCAR_GP_PIN(7, 16), /* IRQ6 */ + [ 5] = RCAR_GP_PIN(7, 17), /* IRQ7 */ + [ 6] = RCAR_GP_PIN(7, 18), /* IRQ8 */ + [ 7] = RCAR_GP_PIN(7, 19), /* IRQ9 */ + [ 8] = RCAR_GP_PIN(3, 0), /* DU1_DR0 */ + [ 9] = RCAR_GP_PIN(3, 1), /* DU1_DR1 */ + [10] = RCAR_GP_PIN(3, 2), /* DU1_DR2 */ + [11] = RCAR_GP_PIN(3, 3), /* DU1_DR3 */ + [12] = RCAR_GP_PIN(3, 4), /* DU1_DR4 */ + [13] = RCAR_GP_PIN(3, 5), /* DU1_DR5 */ + [14] = RCAR_GP_PIN(3, 6), /* DU1_DR6 */ + [15] = RCAR_GP_PIN(3, 7), /* DU1_DR7 */ + [16] = RCAR_GP_PIN(3, 8), /* DU1_DG0 */ + [17] = RCAR_GP_PIN(3, 9), /* DU1_DG1 */ + [18] = RCAR_GP_PIN(3, 10), /* DU1_DG2 */ + [19] = RCAR_GP_PIN(3, 11), /* DU1_DG3 */ + [20] = RCAR_GP_PIN(3, 12), /* DU1_DG4 */ + [21] = RCAR_GP_PIN(3, 13), /* DU1_DG5 */ + [22] = RCAR_GP_PIN(3, 14), /* DU1_DG6 */ + [23] = RCAR_GP_PIN(3, 15), /* DU1_DG7 */ + [24] = RCAR_GP_PIN(3, 16), /* DU1_DB0 */ + [25] = RCAR_GP_PIN(3, 17), /* DU1_DB1 */ + [26] = RCAR_GP_PIN(3, 18), /* DU1_DB2 */ + [27] = RCAR_GP_PIN(3, 19), /* DU1_DB3 */ + [28] = RCAR_GP_PIN(3, 20), /* DU1_DB4 */ + [29] = RCAR_GP_PIN(3, 21), /* DU1_DB5 */ + [30] = RCAR_GP_PIN(3, 22), /* DU1_DB6 */ + [31] = RCAR_GP_PIN(3, 23), /* DU1_DB7 */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 24), /* DU1_DOTCLKIN */ + [ 1] = RCAR_GP_PIN(3, 25), /* DU1_DOTCLKOUT0 */ + [ 2] = RCAR_GP_PIN(3, 26), /* DU1_DOTCLKOUT1 */ + [ 3] = RCAR_GP_PIN(3, 27), /* DU1_EXHSYNC_DU1_HSYNC */ + [ 4] = RCAR_GP_PIN(3, 28), /* DU1_EXVSYNC_DU1_VSYNC */ + [ 5] = RCAR_GP_PIN(3, 29), /* DU1_EXODDF_DU1_ODDF_DISP_CDE */ + [ 6] = RCAR_GP_PIN(3, 30), /* DU1_DISP */ + [ 7] = RCAR_GP_PIN(3, 31), /* DU1_CDE */ + [ 8] = RCAR_GP_PIN(4, 0), /* VI0_CLK */ + [ 9] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */ + [10] = RCAR_GP_PIN(4, 2), /* VI0_FIELD */ + [11] = RCAR_GP_PIN(4, 3), /* VI0_HSYNC# */ + [12] = RCAR_GP_PIN(4, 4), /* VI0_VSYNC# */ + [13] = RCAR_GP_PIN(4, 5), /* VI0_DATA0_VI0_B0 */ + [14] = RCAR_GP_PIN(4, 6), /* VI0_DATA1_VI0_B1 */ + [15] = RCAR_GP_PIN(4, 7), /* VI0_DATA2_VI0_B2 */ + [16] = RCAR_GP_PIN(4, 8), /* VI0_DATA3_VI0_B3 */ + [17] = RCAR_GP_PIN(4, 9), /* VI0_DATA4_VI0_B4 */ + [18] = RCAR_GP_PIN(4, 10), /* VI0_DATA5_VI0_B5 */ + [19] = RCAR_GP_PIN(4, 11), /* VI0_DATA6_VI0_B6 */ + [20] = RCAR_GP_PIN(4, 12), /* VI0_DATA7_VI0_B7 */ + [21] = RCAR_GP_PIN(4, 13), /* VI0_G0 */ + [22] = RCAR_GP_PIN(4, 14), /* VI0_G1 */ + [23] = RCAR_GP_PIN(4, 15), /* VI0_G2 */ + [24] = RCAR_GP_PIN(4, 16), /* VI0_G3 */ + [25] = RCAR_GP_PIN(4, 17), /* VI0_G4 */ + [26] = RCAR_GP_PIN(4, 18), /* VI0_G5 */ + [27] = RCAR_GP_PIN(4, 19), /* VI0_G6 */ + [28] = RCAR_GP_PIN(4, 20), /* VI0_G7 */ + [29] = RCAR_GP_PIN(4, 21), /* VI0_R0 */ + [30] = RCAR_GP_PIN(4, 22), /* VI0_R1 */ + [31] = RCAR_GP_PIN(4, 23), /* VI0_R2 */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 24), /* VI0_R3 */ + [ 1] = RCAR_GP_PIN(4, 25), /* VI0_R4 */ + [ 2] = RCAR_GP_PIN(4, 26), /* VI0_R5 */ + [ 3] = RCAR_GP_PIN(4, 27), /* VI0_R6 */ + [ 4] = RCAR_GP_PIN(4, 28), /* VI0_R7 */ + [ 5] = RCAR_GP_PIN(5, 0), /* VI1_HSYNC# */ + [ 6] = RCAR_GP_PIN(5, 1), /* VI1_VSYNC# */ + [ 7] = RCAR_GP_PIN(5, 2), /* VI1_CLKENB */ + [ 8] = RCAR_GP_PIN(5, 3), /* VI1_FIELD */ + [ 9] = RCAR_GP_PIN(5, 4), /* VI1_CLK */ + [10] = RCAR_GP_PIN(5, 5), /* VI1_DATA0 */ + [11] = RCAR_GP_PIN(5, 6), /* VI1_DATA1 */ + [12] = RCAR_GP_PIN(5, 7), /* VI1_DATA2 */ + [13] = RCAR_GP_PIN(5, 8), /* VI1_DATA3 */ + [14] = RCAR_GP_PIN(5, 9), /* VI1_DATA4 */ + [15] = RCAR_GP_PIN(5, 10), /* VI1_DATA5 */ + [16] = RCAR_GP_PIN(5, 11), /* VI1_DATA6 */ + [17] = RCAR_GP_PIN(5, 12), /* VI1_DATA7 */ + [18] = RCAR_GP_PIN(5, 13), /* ETH_MDIO */ + [19] = RCAR_GP_PIN(5, 14), /* ETH_CRS_DV */ + [20] = RCAR_GP_PIN(5, 15), /* ETH_RX_ER */ + [21] = RCAR_GP_PIN(5, 16), /* ETH_RXD0 */ + [22] = RCAR_GP_PIN(5, 17), /* ETH_RXD1 */ + [23] = RCAR_GP_PIN(5, 18), /* ETH_LINK */ + [24] = RCAR_GP_PIN(5, 19), /* ETH_REFCLK */ + [25] = RCAR_GP_PIN(5, 20), /* ETH_TXD1 */ + [26] = RCAR_GP_PIN(5, 21), /* ETH_TX_EN */ + [27] = RCAR_GP_PIN(5, 22), /* ETH_MAGIC */ + [28] = RCAR_GP_PIN(5, 23), /* ETH_TXD0 */ + [29] = RCAR_GP_PIN(5, 24), /* ETH_MDC */ + [30] = RCAR_GP_PIN(5, 25), /* STP_IVCXO27_0 */ + [31] = RCAR_GP_PIN(5, 26), /* STP_ISCLK_0 */ + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 27), /* STP_ISD_0 */ + [ 1] = RCAR_GP_PIN(5, 28), /* STP_ISEN_0 */ + [ 2] = RCAR_GP_PIN(5, 29), /* STP_ISSYNC_0 */ + [ 3] = RCAR_GP_PIN(5, 30), /* STP_OPWM_0 */ + [ 4] = RCAR_GP_PIN(6, 0), /* SD0_CLK */ + [ 5] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ + [ 6] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ + [ 7] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ + [ 8] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ + [ 9] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ + [10] = RCAR_GP_PIN(6, 6), /* SD0_CD */ + [11] = RCAR_GP_PIN(6, 7), /* SD0_WP */ + [12] = RCAR_GP_PIN(6, 8), /* SD2_CLK */ + [13] = RCAR_GP_PIN(6, 9), /* SD2_CMD */ + [14] = RCAR_GP_PIN(6, 10), /* SD2_DATA0 */ + [15] = RCAR_GP_PIN(6, 11), /* SD2_DATA1 */ + [16] = RCAR_GP_PIN(6, 12), /* SD2_DATA2 */ + [17] = RCAR_GP_PIN(6, 13), /* SD2_DATA3 */ + [18] = RCAR_GP_PIN(6, 14), /* SD2_CD */ + [19] = RCAR_GP_PIN(6, 15), /* SD2_WP */ + [20] = RCAR_GP_PIN(6, 16), /* SD3_CLK */ + [21] = RCAR_GP_PIN(6, 17), /* SD3_CMD */ + [22] = RCAR_GP_PIN(6, 18), /* SD3_DATA0 */ + [23] = RCAR_GP_PIN(6, 19), /* SD3_DATA1 */ + [24] = RCAR_GP_PIN(6, 20), /* SD3_DATA2 */ + [25] = RCAR_GP_PIN(6, 21), /* SD3_DATA3 */ + [26] = RCAR_GP_PIN(6, 22), /* SD3_CD */ + [27] = RCAR_GP_PIN(6, 23), /* SD3_WP */ + [28] = RCAR_GP_PIN(6, 24), /* MSIOF0_SCK */ + [29] = RCAR_GP_PIN(6, 25), /* MSIOF0_SYNC */ + [30] = RCAR_GP_PIN(6, 26), /* MSIOF0_TXD */ + [31] = RCAR_GP_PIN(6, 27), /* MSIOF0_RXD */ + } }, + { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) { + /* PUPR7 pull-up pins */ + [ 0] = RCAR_GP_PIN(6, 28), /* MSIOF0_SS1 */ + [ 1] = RCAR_GP_PIN(6, 29), /* MSIOF0_SS2 */ + [ 2] = RCAR_GP_PIN(4, 29), /* SIM0_RST */ + [ 3] = RCAR_GP_PIN(4, 30), /* SIM0_CLK */ + [ 4] = RCAR_GP_PIN(4, 31), /* SIM0_D */ + [ 5] = RCAR_GP_PIN(7, 20), /* GPS_CLK */ + [ 6] = RCAR_GP_PIN(7, 21), /* GPS_SIGN */ + [ 7] = RCAR_GP_PIN(7, 22), /* GPS_MAG */ + [ 8] = RCAR_GP_PIN(7, 0), /* HCTS0# */ + [ 9] = RCAR_GP_PIN(7, 1), /* HRTS0# */ + [10] = RCAR_GP_PIN(7, 2), /* HSCK0 */ + [11] = RCAR_GP_PIN(7, 3), /* HRX0 */ + [12] = RCAR_GP_PIN(7, 4), /* HTX0 */ + [13] = RCAR_GP_PIN(7, 5), /* HRX1 */ + [14] = RCAR_GP_PIN(7, 6), /* HTX1 */ + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = RCAR_GP_PIN(1, 9), /* A25 */ + [19] = SH_PFC_PIN_NONE, + [20] = RCAR_GP_PIN(1, 10), /* CS0# */ + [21] = RCAR_GP_PIN(7, 23), /* USB0_PWEN */ + [22] = RCAR_GP_PIN(7, 24), /* USB0_OVC */ + [23] = RCAR_GP_PIN(7, 25), /* USB1_PWEN */ + [24] = RCAR_GP_PIN(6, 30), /* USB1_OVC */ + [25] = PIN_AVS1, /* AVS1 */ + [26] = PIN_AVS2, /* AVS2 */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR7", 0xe606011c) { + /* PUPR7 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ }, +}; + +static const struct sh_pfc_soc_operations r8a7791_pfc_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A7743 const struct sh_pfc_soc_info r8a7743_pinmux_info = { .name = "r8a77430_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6668,6 +6902,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6677,7 +6912,7 @@ const struct sh_pfc_soc_info r8a7743_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7744 const struct sh_pfc_soc_info r8a7744_pinmux_info = { .name = "r8a77440_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6690,6 +6925,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6699,7 +6935,7 @@ const struct sh_pfc_soc_info r8a7744_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6714,6 +6950,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6723,7 +6960,7 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7793 const struct sh_pfc_soc_info r8a7793_pinmux_info = { .name = "r8a77930_pfc", - .ops = &r8a7791_pinmux_ops, + .ops = &r8a7791_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6738,6 +6975,7 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index 054c02a4ae..81cfe81c7f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -15,18 +15,29 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_29(0, fn, sfx), \ - PORT_GP_23(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_28(3, fn, sfx), \ - PORT_GP_17(4, fn, sfx), \ - PORT_GP_17(5, fn, sfx), \ - PORT_GP_17(6, fn, sfx), \ - PORT_GP_17(7, fn, sfx), \ - PORT_GP_17(8, fn, sfx), \ - PORT_GP_17(9, fn, sfx), \ - PORT_GP_32(10, fn, sfx), \ - PORT_GP_30(11, fn, sfx) + PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -727,8 +738,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB -------------------------------------------------------------------- */ @@ -1100,19 +1120,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -1190,19 +1203,12 @@ static const unsigned int scif3_clk_mux[] = { SCK3_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* DAT0 */ - RCAR_GP_PIN(11, 7), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* DAT[0-3] */ RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8), RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -1227,43 +1233,39 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), - RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), - RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), - RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), - /* G */ - RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), - RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), - RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), - RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), - /* R */ - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), + RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), + RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), + RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), + /* G */ + RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), + RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2), + RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4), + /* R */ + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, - VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, - VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, - VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, - /* G */ - VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, - VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, - VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, - VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, - /* R */ - VI0_D16_R0_MARK, VI0_D17_R1_MARK, - VI0_D18_R2_MARK, VI0_D19_R3_MARK, - VI0_D20_R4_MARK, VI0_D21_R5_MARK, - VI0_D22_R6_MARK, VI0_D23_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, + VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK, + VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, + VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, + /* G */ + VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, + VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK, + VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK, + VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK, + /* R */ + VI0_D16_R0_MARK, VI0_D17_R1_MARK, + VI0_D18_R2_MARK, VI0_D19_R3_MARK, + VI0_D20_R4_MARK, VI0_D21_R5_MARK, + VI0_D22_R6_MARK, VI0_D23_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -1319,43 +1321,39 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data vin1_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), - RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6), + RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, - VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK, + VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_pins[] = { /* B */ @@ -1385,43 +1383,39 @@ static const unsigned int vin1_data18_mux[] = { VI1_D20_R4_MARK, VI1_D21_R5_MARK, VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; -static const union vin_data vin1_data_b_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), - RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), - RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), - RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), - /* G */ - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), - RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), - /* R */ - RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), - RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), - RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), - RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), - }, +static const unsigned int vin1_data_b_pins[] = { + /* B */ + RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), + RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), + RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), + RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), + /* G */ + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2), + RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4), + /* R */ + RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6), + RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8), + RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10), + RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12), }; -static const union vin_data vin1_data_b_mux = { - .data24 = { - /* B */ - VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, - VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, - VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, - VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, - /* G */ - VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, - VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, - VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, - VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, - /* R */ - VI1_D16_R0_MARK, VI1_D17_R1_MARK, - VI1_D18_R2_MARK, VI1_D19_R3_MARK, - VI1_D20_R4_MARK, VI1_D21_R5_MARK, - VI1_D22_R6_MARK, VI1_D23_R7_MARK, - }, +static const unsigned int vin1_data_b_mux[] = { + /* B */ + VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, + VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, + VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK, + VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, + /* G */ + VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, + VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK, + VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK, + VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK, + /* R */ + VI1_D16_R0_MARK, VI1_D17_R1_MARK, + VI1_D18_R2_MARK, VI1_D19_R3_MARK, + VI1_D20_R4_MARK, VI1_D21_R5_MARK, + VI1_D22_R6_MARK, VI1_D23_R7_MARK, }; static const unsigned int vin1_data18_b_pins[] = { /* B */ @@ -1477,29 +1471,25 @@ static const unsigned int vin1_clk_mux[] = { VI1_CLK_MARK, }; /* - VIN2 ------------------------------------------------------------------- */ -static const union vin_data16 vin2_data_pins = { - .data16 = { - RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), - RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), - RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), - RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), - RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), - RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), - RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), - RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), - }, +static const unsigned int vin2_data_pins[] = { + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7), + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), + RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), + RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), + RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10), + RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12), }; -static const union vin_data16 vin2_data_mux = { - .data16 = { - VI2_D0_C0_MARK, VI2_D1_C1_MARK, - VI2_D2_C2_MARK, VI2_D3_C3_MARK, - VI2_D4_C4_MARK, VI2_D5_C5_MARK, - VI2_D6_C6_MARK, VI2_D7_C7_MARK, - VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, - VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, - VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, - VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, - }, +static const unsigned int vin2_data_mux[] = { + VI2_D0_C0_MARK, VI2_D1_C1_MARK, + VI2_D2_C2_MARK, VI2_D3_C3_MARK, + VI2_D4_C4_MARK, VI2_D5_C5_MARK, + VI2_D6_C6_MARK, VI2_D7_C7_MARK, + VI2_D8_Y0_MARK, VI2_D9_Y1_MARK, + VI2_D10_Y2_MARK, VI2_D11_Y3_MARK, + VI2_D12_Y4_MARK, VI2_D13_Y5_MARK, + VI2_D14_Y6_MARK, VI2_D15_Y7_MARK, }; static const unsigned int vin2_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1527,29 +1517,25 @@ static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; /* - VIN3 ------------------------------------------------------------------- */ -static const union vin_data16 vin3_data_pins = { - .data16 = { - RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), - RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), - RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), - RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), - RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), - RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), - RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), - RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), - }, -}; -static const union vin_data16 vin3_data_mux = { - .data16 = { - VI3_D0_C0_MARK, VI3_D1_C1_MARK, - VI3_D2_C2_MARK, VI3_D3_C3_MARK, - VI3_D4_C4_MARK, VI3_D5_C5_MARK, - VI3_D6_C6_MARK, VI3_D7_C7_MARK, - VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, - VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, - VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, - VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, - }, +static const unsigned int vin3_data_pins[] = { + RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5), + RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7), + RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9), + RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11), + RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13), + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), + RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14), + RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16), +}; +static const unsigned int vin3_data_mux[] = { + VI3_D0_C0_MARK, VI3_D1_C1_MARK, + VI3_D2_C2_MARK, VI3_D3_C3_MARK, + VI3_D4_C4_MARK, VI3_D5_C5_MARK, + VI3_D6_C6_MARK, VI3_D7_C7_MARK, + VI3_D8_Y0_MARK, VI3_D9_Y1_MARK, + VI3_D10_Y2_MARK, VI3_D11_Y3_MARK, + VI3_D12_Y4_MARK, VI3_D13_Y5_MARK, + VI3_D14_Y6_MARK, VI3_D15_Y7_MARK, }; static const unsigned int vin3_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1577,25 +1563,21 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; /* - VIN4 ------------------------------------------------------------------- */ -static const union vin_data12 vin4_data_pins = { - .data12 = { - RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), - RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), - RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), - RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), - RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), - RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), - }, -}; -static const union vin_data12 vin4_data_mux = { - .data12 = { - VI4_D0_C0_MARK, VI4_D1_C1_MARK, - VI4_D2_C2_MARK, VI4_D3_C3_MARK, - VI4_D4_C4_MARK, VI4_D5_C5_MARK, - VI4_D6_C6_MARK, VI4_D7_C7_MARK, - VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, - VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5), + RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7), + RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9), + RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11), + RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13), + RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15), +}; +static const unsigned int vin4_data_mux[] = { + VI4_D0_C0_MARK, VI4_D1_C1_MARK, + VI4_D2_C2_MARK, VI4_D3_C3_MARK, + VI4_D4_C4_MARK, VI4_D5_C5_MARK, + VI4_D6_C6_MARK, VI4_D7_C7_MARK, + VI4_D8_Y0_MARK, VI4_D9_Y1_MARK, + VI4_D10_Y2_MARK, VI4_D11_Y3_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1623,25 +1605,21 @@ static const unsigned int vin4_clk_mux[] = { VI4_CLK_MARK, }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data12 vin5_data_pins = { - .data12 = { - RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), - RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), - RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), - RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), - RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), - RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), - }, -}; -static const union vin_data12 vin5_data_mux = { - .data12 = { - VI5_D0_C0_MARK, VI5_D1_C1_MARK, - VI5_D2_C2_MARK, VI5_D3_C3_MARK, - VI5_D4_C4_MARK, VI5_D5_C5_MARK, - VI5_D6_C6_MARK, VI5_D7_C7_MARK, - VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, - VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5), + RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7), + RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9), + RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11), + RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13), + RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15), +}; +static const unsigned int vin5_data_mux[] = { + VI5_D0_C0_MARK, VI5_D1_C1_MARK, + VI5_D2_C2_MARK, VI5_D3_C3_MARK, + VI5_D4_C4_MARK, VI5_D5_C5_MARK, + VI5_D6_C6_MARK, VI5_D7_C7_MARK, + VI5_D8_Y0_MARK, VI5_D9_Y1_MARK, + VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1712,8 +1690,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof1_rx), SH_PFC_PIN_GROUP(msiof1_tx), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1724,63 +1702,63 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif2_clk), SH_PFC_PIN_GROUP(scif3_data), SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), + BUS_DATA_PIN_GROUP(vin1_data, 24), + BUS_DATA_PIN_GROUP(vin1_data, 20), SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 24, _b), - VIN_DATA_PIN_GROUP(vin1_data, 20, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 24, _b), + BUS_DATA_PIN_GROUP(vin1_data, 20, _b), SH_PFC_PIN_GROUP(vin1_data18_b), - VIN_DATA_PIN_GROUP(vin1_data, 16, _b), + BUS_DATA_PIN_GROUP(vin1_data, 16, _b), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 12), - VIN_DATA_PIN_GROUP(vin2_data, 10), - VIN_DATA_PIN_GROUP(vin2_data, 8), + BUS_DATA_PIN_GROUP(vin2_data, 16), + BUS_DATA_PIN_GROUP(vin2_data, 12), + BUS_DATA_PIN_GROUP(vin2_data, 10), + BUS_DATA_PIN_GROUP(vin2_data, 8), SH_PFC_PIN_GROUP(vin2_sync), SH_PFC_PIN_GROUP(vin2_field), SH_PFC_PIN_GROUP(vin2_clkenb), SH_PFC_PIN_GROUP(vin2_clk), - VIN_DATA_PIN_GROUP(vin3_data, 16), - VIN_DATA_PIN_GROUP(vin3_data, 12), - VIN_DATA_PIN_GROUP(vin3_data, 10), - VIN_DATA_PIN_GROUP(vin3_data, 8), + BUS_DATA_PIN_GROUP(vin3_data, 16), + BUS_DATA_PIN_GROUP(vin3_data, 12), + BUS_DATA_PIN_GROUP(vin3_data, 10), + BUS_DATA_PIN_GROUP(vin3_data, 8), SH_PFC_PIN_GROUP(vin3_sync), SH_PFC_PIN_GROUP(vin3_field), SH_PFC_PIN_GROUP(vin3_clkenb), SH_PFC_PIN_GROUP(vin3_clk), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -2025,16 +2003,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_1_FN, FN_IP0_1, GP_0_0_FN, FN_IP0_0 )) }, - { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR1", 0xE6060008, 32, + GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP1_31_23 RESERVED */ GP_1_22_FN, FN_DU1_CDE, GP_1_21_FN, FN_DU1_DISP, GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, @@ -2127,22 +2100,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, FN_A17, GP_3_0_FN, FN_A16 )) }, - { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xE6060014, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_17 RESERVED */ GP_4_16_FN, FN_VI0_FIELD, GP_4_15_FN, FN_VI0_D11_G3_Y3, GP_4_14_FN, FN_VI0_D10_G2_Y2, @@ -2161,22 +2123,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, FN_VI0_CLKENB, GP_4_0_FN, FN_VI0_CLK )) }, - { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xE6060018, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_17 RESERVED */ GP_5_16_FN, FN_VI1_FIELD, GP_5_15_FN, FN_VI1_D11_G3_Y3, GP_5_14_FN, FN_VI1_D10_G2_Y2, @@ -2195,22 +2146,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_FN, FN_VI1_CLKENB, GP_5_0_FN, FN_VI1_CLK )) }, - { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR6", 0xE606001C, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP6_31_17 RESERVED */ GP_6_16_FN, FN_IP2_16, GP_6_15_FN, FN_IP2_15, GP_6_14_FN, FN_IP2_14, @@ -2229,22 +2169,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, FN_IP2_1, GP_6_0_FN, FN_IP2_0 )) }, - { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xE6060020, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP7_31_17 RESERVED */ GP_7_16_FN, FN_VI3_FIELD, GP_7_15_FN, FN_IP3_14, GP_7_14_FN, FN_VI3_D10_Y2, @@ -2263,22 +2192,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_1_FN, FN_IP3_1, GP_7_0_FN, FN_IP3_0 )) }, - { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR8", 0xE6060024, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP8_31_17 RESERVED */ GP_8_16_FN, FN_IP4_24, GP_8_15_FN, FN_IP4_23, GP_8_14_FN, FN_IP4_22, @@ -2297,22 +2215,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_1_FN, FN_IP4_0, GP_8_0_FN, FN_VI4_CLK )) }, - { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR9", 0xE6060028, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP9_31_17 RESERVED */ GP_9_16_FN, FN_VI5_FIELD, GP_9_15_FN, FN_VI5_D11_Y3, GP_9_14_FN, FN_VI5_D10_Y2, @@ -2400,15 +2307,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_11_0_FN, FN_IP7_1_0 )) }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, - GROUP(4, 4, + GROUP(-8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP0_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP0_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP0_31_24 [8] RESERVED */ /* IP0_23 [1] */ FN_DU0_DB7_C5, 0, /* IP0_22 [1] */ @@ -2459,17 +2363,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_DR0_DATA0, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, - GROUP(4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, + GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP1_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP1_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP1_23 [1] */ - 0, 0, + /* IP1_31_23 [9] RESERVED */ /* IP1_22 [1] */ FN_A25, FN_SSL, /* IP1_21 [1] */ @@ -2518,19 +2416,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_EXHSYNC_DU0_HSYNC, 0 )) }, { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, - GROUP(4, 4, - 4, 3, 1, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP2_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP2_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP2_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP2_19_17 [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* IP2_31_17 [15] RESERVED */ /* IP2_16 [1] */ FN_VI2_FIELD, FN_AVB_TXD2, /* IP2_15 [1] */ @@ -2567,21 +2457,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI2_CLK, FN_AVB_RX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, - GROUP(4, 4, - 4, 4, - 1, 1, 1, 1, 1, 1, 1, 1, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP3_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP3_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP3_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP3_19_16 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP3_15 [1] */ - 0, 0, + /* IP3_31_15 [17] RESERVED */ /* IP3_14 [1] */ FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH, /* IP3_13 [1] */ @@ -2614,14 +2493,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI3_CLK, FN_AVB_TX_CLK )) }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, - GROUP(4, 3, 1, - 1, 1, 1, 2, 2, 2, + GROUP(-7, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 1), GROUP( - /* IP4_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP4_27_25 [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* IP4_31_25 [7] RESERVED */ /* IP4_24 [1] */ FN_VI4_FIELD, FN_VI3_D15_Y7, /* IP4_23 [1] */ @@ -2656,21 +2531,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 )) }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, - GROUP(4, 4, - 4, 4, - 4, 1, 1, 1, 1, + GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP5_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP5_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP5_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP5_19_16 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP5_15_12 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP5_31_12 [20] RESERVED */ /* IP5_11 [1] */ FN_VI5_D8_Y0, FN_VI1_D23_R7, /* IP5_10 [1] */ @@ -2697,19 +2561,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B )) }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, - GROUP(4, 4, - 4, 1, 2, 1, - 2, 2, 2, 2, + GROUP(-13, 2, 1, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* IP6_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP6_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP6_23_20 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP6_19 [1] */ - 0, 0, + /* IP6_31_19 [13] RESERVED */ /* IP6_18_17 [2] */ FN_DREQ1_N, FN_RX3, 0, 0, /* IP6_16 [1] */ @@ -2740,17 +2595,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MSIOF0_SCK, FN_HSCK0 )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, - GROUP(4, 4, - 3, 1, 1, 1, 1, 1, + GROUP(-11, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 2, 2, 2), GROUP( - /* IP7_31_28 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP7_27_24 [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP7_23_21 [3] */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_31_21 [11] RESERVED */ /* IP7_20 [1] */ FN_AUDIO_CLKB, 0, /* IP7_19 [1] */ @@ -2783,8 +2632,496 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */ + [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */ + [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */ + [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */ + [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */ + [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */ + [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */ + [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */ + [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */ + [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */ + [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */ + [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */ + [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */ + [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */ + [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */ + [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ + [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */ + [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */ + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */ + [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */ + [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */ + [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */ + [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */ + [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */ + [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */ + [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */ + [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */ + [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */ + [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */ + [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */ + [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */ + [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */ + [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */ + [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */ + [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */ + [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */ + [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */ + [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */ + [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */ + [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */ + [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */ + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 0), /* D0 */ + [ 1] = RCAR_GP_PIN(2, 1), /* D1 */ + [ 2] = RCAR_GP_PIN(2, 2), /* D2 */ + [ 3] = RCAR_GP_PIN(2, 3), /* D3 */ + [ 4] = RCAR_GP_PIN(2, 4), /* D4 */ + [ 5] = RCAR_GP_PIN(2, 5), /* D5 */ + [ 6] = RCAR_GP_PIN(2, 6), /* D6 */ + [ 7] = RCAR_GP_PIN(2, 7), /* D7 */ + [ 8] = RCAR_GP_PIN(2, 8), /* D8 */ + [ 9] = RCAR_GP_PIN(2, 9), /* D9 */ + [10] = RCAR_GP_PIN(2, 10), /* D10 */ + [11] = RCAR_GP_PIN(2, 11), /* D11 */ + [12] = RCAR_GP_PIN(2, 12), /* D12 */ + [13] = RCAR_GP_PIN(2, 13), /* D13 */ + [14] = RCAR_GP_PIN(2, 14), /* D14 */ + [15] = RCAR_GP_PIN(2, 15), /* D15 */ + [16] = RCAR_GP_PIN(2, 16), /* A0 */ + [17] = RCAR_GP_PIN(2, 17), /* A1 */ + [18] = RCAR_GP_PIN(2, 18), /* A2 */ + [19] = RCAR_GP_PIN(2, 19), /* A3 */ + [20] = RCAR_GP_PIN(2, 20), /* A4 */ + [21] = RCAR_GP_PIN(2, 21), /* A5 */ + [22] = RCAR_GP_PIN(2, 22), /* A6 */ + [23] = RCAR_GP_PIN(2, 23), /* A7 */ + [24] = RCAR_GP_PIN(2, 24), /* A8 */ + [25] = RCAR_GP_PIN(2, 25), /* A9 */ + [26] = RCAR_GP_PIN(2, 26), /* A10 */ + [27] = RCAR_GP_PIN(2, 27), /* A11 */ + [28] = RCAR_GP_PIN(2, 28), /* A12 */ + [29] = RCAR_GP_PIN(2, 29), /* A13 */ + [30] = RCAR_GP_PIN(2, 30), /* A14 */ + [31] = RCAR_GP_PIN(2, 31), /* A15 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 0), /* A16 */ + [ 1] = RCAR_GP_PIN(3, 1), /* A17 */ + [ 2] = RCAR_GP_PIN(3, 2), /* A18 */ + [ 3] = RCAR_GP_PIN(3, 3), /* A19 */ + [ 4] = RCAR_GP_PIN(3, 4), /* A20 */ + [ 5] = RCAR_GP_PIN(3, 5), /* A21 */ + [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */ + [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */ + [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */ + [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */ + [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */ + [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */ + [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */ + [13] = RCAR_GP_PIN(3, 13), /* BS# */ + [14] = RCAR_GP_PIN(3, 14), /* RD# */ + [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */ + [16] = RCAR_GP_PIN(3, 16), /* WE0# */ + [17] = RCAR_GP_PIN(3, 17), /* WE1# */ + [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */ + [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */ + [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */ + [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */ + [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */ + [23] = RCAR_GP_PIN(3, 23), /* A22 */ + [24] = RCAR_GP_PIN(3, 24), /* A23 */ + [25] = RCAR_GP_PIN(3, 25), /* A24 */ + [26] = RCAR_GP_PIN(3, 26), /* A25 */ + [27] = RCAR_GP_PIN(3, 27), /* CS0# */ + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */ + [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */ + [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */ + [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */ + [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */ + [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */ + [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */ + [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */ + [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */ + [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */ + [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */ + [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */ + [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */ + [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */ + [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */ + [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */ + [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */ + [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */ + [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */ + [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */ + [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */ + [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */ + [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */ + [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */ + [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */ + [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */ + [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */ + [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */ + [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */ + [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */ + [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */ + [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */ + [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */ + [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */ + [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */ + [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */ + [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */ + [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */ + [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */ + [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */ + [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */ + [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */ + [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */ + [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */ + [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */ + [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */ + [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */ + [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */ + [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */ + [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */ + [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */ + [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */ + [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */ + [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */ + [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */ + [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */ + [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */ + [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */ + [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */ + [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */ + [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */ + [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */ + [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */ + [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */ + [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) { + [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */ + [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */ + [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */ + [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */ + [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */ + [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */ + [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */ + [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */ + [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */ + [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */ + [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */ + [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */ + [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */ + [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */ + [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */ + [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */ + [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) { + [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */ + [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */ + [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */ + [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */ + [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */ + [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */ + [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */ + [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */ + [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */ + [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */ + [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */ + [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */ + [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */ + [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */ + [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */ + [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */ + [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) { + [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */ + [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */ + [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */ + [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */ + [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */ + [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */ + [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */ + [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */ + [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */ + [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */ + [10] = RCAR_GP_PIN(10, 10), /* SCK0 */ + [11] = RCAR_GP_PIN(10, 11), /* CTS0# */ + [12] = RCAR_GP_PIN(10, 12), /* RTS0# */ + [13] = RCAR_GP_PIN(10, 13), /* TX0 */ + [14] = RCAR_GP_PIN(10, 14), /* RX0 */ + [15] = RCAR_GP_PIN(10, 15), /* SCK1 */ + [16] = RCAR_GP_PIN(10, 16), /* CTS1# */ + [17] = RCAR_GP_PIN(10, 17), /* RTS1# */ + [18] = RCAR_GP_PIN(10, 18), /* TX1 */ + [19] = RCAR_GP_PIN(10, 19), /* RX1 */ + [20] = RCAR_GP_PIN(10, 20), /* SCK2 */ + [21] = RCAR_GP_PIN(10, 21), /* TX2 */ + [22] = RCAR_GP_PIN(10, 22), /* RX2 */ + [23] = RCAR_GP_PIN(10, 23), /* SCK3 */ + [24] = RCAR_GP_PIN(10, 24), /* TX3 */ + [25] = RCAR_GP_PIN(10, 25), /* RX3 */ + [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */ + [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */ + [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */ + [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */ + [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */ + [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */ + } }, + { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */ + [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */ + [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */ + [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */ + [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */ + [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */ + [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */ + [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */ + [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */ + [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */ + [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */ + [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */ + [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */ + [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */ + [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */ + [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */ + [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */ + [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */ + [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */ + [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */ + [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */ + [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */ + [22] = RCAR_GP_PIN(11, 22), /* ADICLK */ + [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */ + [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */ + [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */ + [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */ + [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */ + [28] = RCAR_GP_PIN(11, 28), /* AVS1 */ + [29] = RCAR_GP_PIN(11, 29), /* AVS2 */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) { + /* PUPR12 pull-up pins */ + [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */ + [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */ + [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */ + [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) { + /* PUPR12 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = PIN_EDBGREQ, /* EDBGREQ */ + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + +static const struct sh_pfc_soc_operations r8a7792_pfc_ops = { + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + const struct sh_pfc_soc_info r8a7792_pinmux_info = { .name = "r8a77920_pfc", + .ops = &r8a7792_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2797,6 +3134,7 @@ const struct sh_pfc_soc_info r8a7792_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 9495603f7c..7ed54f0cff 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -16,15 +16,66 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_28(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 7, fn, sfx), \ + PORT_GP_1(5, 8, fn, sfx), \ + PORT_GP_1(5, 9, fn, sfx), \ + PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 24, fn, sfx), \ + PORT_GP_1(5, 25, fn, sfx), \ + PORT_GP_1(5, 26, fn, sfx), \ + PORT_GP_1(5, 27, fn, sfx), \ + PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -1437,8 +1488,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - Audio Clock ------------------------------------------------------------ */ @@ -2329,29 +2389,14 @@ static const unsigned int intc_irq9_mux[] = { IRQ9_MARK, }; /* - MMCIF ------------------------------------------------------------------ */ -static const unsigned int mmc_data1_pins[] = { - /* D[0] */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), - RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK, }; @@ -2686,19 +2731,12 @@ static const unsigned int qspi_ctrl_pins[] = { static const unsigned int qspi_ctrl_mux[] = { SPCLK_MARK, SSL_MARK, }; -static const unsigned int qspi_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), -}; -static const unsigned int qspi_data2_mux[] = { - MOSI_IO0_MARK, MISO_IO1_MARK, -}; -static const unsigned int qspi_data4_pins[] = { +static const unsigned int qspi_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), }; -static const unsigned int qspi_data4_mux[] = { +static const unsigned int qspi_data_mux[] = { MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, }; /* - SCIF0 ------------------------------------------------------------------ */ @@ -3173,19 +3211,12 @@ static const unsigned int scif_clk_b_mux[] = { SCIF_CLK_B_MARK, }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DATA0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, }; static const unsigned int sdhi0_ctrl_pins[] = { @@ -3210,19 +3241,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 10), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DATA0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, }; static const unsigned int sdhi1_ctrl_pins[] = { @@ -3247,19 +3271,12 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(6, 18), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DATA0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), }; -static const unsigned int sdhi2_data4_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, }; static const unsigned int sdhi2_ctrl_pins[] = { @@ -3614,43 +3631,39 @@ static const unsigned int usb1_mux[] = { USB1_OVC_MARK, }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - /* B */ - RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), - RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), - RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), - RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), - /* G */ - RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), - RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), - RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), - RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), - /* R */ - RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), - RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), - RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), - RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), - }, +static const unsigned int vin0_data_pins[] = { + /* B */ + RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), + RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), + RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), + RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), + /* G */ + RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), + RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), + RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), + RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), + /* R */ + RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), + RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24), + RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), + RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - /* B */ - VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, - VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, - VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, - VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, - /* G */ - VI0_G0_MARK, VI0_G1_MARK, - VI0_G2_MARK, VI0_G3_MARK, - VI0_G4_MARK, VI0_G5_MARK, - VI0_G6_MARK, VI0_G7_MARK, - /* R */ - VI0_R0_MARK, VI0_R1_MARK, - VI0_R2_MARK, VI0_R3_MARK, - VI0_R4_MARK, VI0_R5_MARK, - VI0_R6_MARK, VI0_R7_MARK, - }, +static const unsigned int vin0_data_mux[] = { + /* B */ + VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, + VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, + VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, + VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, + /* G */ + VI0_G0_MARK, VI0_G1_MARK, + VI0_G2_MARK, VI0_G3_MARK, + VI0_G4_MARK, VI0_G5_MARK, + VI0_G6_MARK, VI0_G7_MARK, + /* R */ + VI0_R0_MARK, VI0_R1_MARK, + VI0_R2_MARK, VI0_R3_MARK, + VI0_R4_MARK, VI0_R5_MARK, + VI0_R6_MARK, VI0_R7_MARK, }; static const unsigned int vin0_data18_pins[] = { /* B */ @@ -3707,25 +3720,21 @@ static const unsigned int vin0_clk_mux[] = { VI0_CLK_MARK, }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), - RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), - RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), - RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), - RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), + RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15), + RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), + RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), + RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { RCAR_GP_PIN(5, 22), /* HSYNC */ @@ -3864,9 +3873,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_irq7), SH_PFC_PIN_GROUP(intc_irq8), SH_PFC_PIN_GROUP(intc_irq9), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -3916,8 +3925,8 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm6), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), + BUS_DATA_PIN_GROUP(qspi_data, 2), + BUS_DATA_PIN_GROUP(qspi_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data_b), SH_PFC_PIN_GROUP(scif0_data_c), @@ -3983,18 +3992,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scifb2_ctrl), SH_PFC_PIN_GROUP(scif_clk), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd), SH_PFC_PIN_GROUP(sdhi2_wp), @@ -4046,20 +4055,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to3_c), SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 8), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 8), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -4859,7 +4868,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, - 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1), + 1, 1, 1, 1, 2, -7, 1), GROUP( /* IP0_31_30 [2] */ FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, @@ -4895,25 +4904,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_MMC_CLK, FN_SD2_CLK, /* IP0_9_8 [2] */ FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, - /* IP0_7 [1] */ - 0, 0, - /* IP0_6 [1] */ - 0, 0, - /* IP0_5 [1] */ - 0, 0, - /* IP0_4 [1] */ - 0, 0, - /* IP0_3 [1] */ - 0, 0, - /* IP0_2 [1] */ - 0, 0, - /* IP0_1 [1] */ - 0, 0, + /* IP0_7_1 [7] RESERVED */ /* IP0_0 [1] */ FN_SD1_CD, FN_CAN0_RX, )) }, { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, - GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, + GROUP(2, 2, 1, 1, -1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2, 2, 2), GROUP( /* IP1_31_30 [2] */ @@ -4924,8 +4920,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A4, FN_SCIFB0_TXD, /* IP1_26 [1] */ FN_A3, FN_SCIFB0_SCK, - /* IP1_25 [1] */ - 0, 0, + /* IP1_25 [1] RESERVED */ /* IP1_24 [1] */ FN_A1, FN_SCIFB1_TXD, /* IP1_23_22 [2] */ @@ -5152,12 +5147,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, - GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP(1, -1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3), GROUP( /* IP7_31 [1] */ FN_DREQ0_N, FN_SCIFB1_RXD, - /* IP7_30 [1] */ - 0, 0, + /* IP7_30 [1] RESERVED */ /* IP7_29_27 [3] */ FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, @@ -5226,10 +5220,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, - GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), + GROUP(-1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3), GROUP( - /* IP9_31 [1] */ - 0, 0, + /* IP9_31 [1] RESERVED */ /* IP9_30_28 [3] */ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B, 0, 0, 0, @@ -5299,10 +5292,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, - GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), + GROUP(-2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3), GROUP( - /* IP11_31_30 [2] */ - 0, 0, 0, 0, + /* IP11_31_30 [2] RESERVED */ /* IP11_29_27 [3] */ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, 0, 0, 0, 0, @@ -5335,10 +5327,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, - GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), + GROUP(-2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3), GROUP( - /* IP12_31_30 [2] */ - 0, 0, 0, 0, + /* IP12_31_30 [2] RESERVED */ /* IP12_29_27 [3] */ FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0, FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, @@ -5371,18 +5362,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_DREQ1_N_B, 0, 0, )) }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, - GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3), + GROUP(-5, 3, 3, 3, 3, 3, 3, 3, 3, 3), GROUP( - /* IP13_31 [1] */ - 0, 0, - /* IP13_30 [1] */ - 0, 0, - /* IP13_29 [1] */ - 0, 0, - /* IP13_28 [1] */ - 0, 0, - /* IP13_27 [1] */ - 0, 0, + /* IP13_31_27 [5] RESERVED */ /* IP13_26_24 [3] */ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0, @@ -5412,23 +5394,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, )) }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1), + GROUP(2, -1, 2, 3, -4, 1, -1, + 3, 3, 3, 3, 3, 2, -1), GROUP( /* SEL_ADG [2] */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, /* RESERVED [1] */ - 0, 0, /* SEL_CAN [2] */ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, /* SEL_DARC [3] */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, 0, 0, 0, /* RESERVED [4] */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_ETH [1] */ FN_SEL_ETH_0, FN_SEL_ETH_1, /* RESERVED [1] */ - 0, 0, /* SEL_IC200 [3] */ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, 0, 0, 0, @@ -5446,12 +5426,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_I2C04_4, 0, 0, 0, /* SEL_I2C05 [2] */ FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, - /* RESERVED [1] */ - 0, 0, )) + /* RESERVED [1] */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, - 2, 2, 1, 1, 2, 2, 2, 1, 1, 2), + 2, 2, -1, 1, 2, 2, 2, 1, 1, -2), GROUP( /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, @@ -5485,7 +5464,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, /* RESERVED [1] */ - 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU_0, FN_SEL_TMU_1, /* SEL_TSIF0 [2] */ @@ -5498,12 +5476,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, /* SEL_HSCIF1 [1] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* RESERVED [2] */ - 0, 0, 0, 0, )) + /* RESERVED [2] */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + 1, 1, -12), GROUP( /* SEL_SCIF0 [2] */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, @@ -5534,36 +5511,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SSI8_0, FN_SEL_SSI8_1, /* SEL_SSI9 [1] */ FN_SEL_SSI9_0, FN_SEL_SSI9_1, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, - /* RESERVED [1] */ - 0, 0, )) + /* RESERVED [12] */ )) }, { }, }; -static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7794_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { + if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23)) + return -EINVAL; + *pocctrl = 0xe606006c; switch (pin & 0x1f) { @@ -5581,6 +5538,284 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return -EINVAL; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 0), /* D0 */ + [ 1] = RCAR_GP_PIN(0, 1), /* D1 */ + [ 2] = RCAR_GP_PIN(0, 2), /* D2 */ + [ 3] = RCAR_GP_PIN(0, 3), /* D3 */ + [ 4] = RCAR_GP_PIN(0, 4), /* D4 */ + [ 5] = RCAR_GP_PIN(0, 5), /* D5 */ + [ 6] = RCAR_GP_PIN(0, 6), /* D6 */ + [ 7] = RCAR_GP_PIN(0, 7), /* D7 */ + [ 8] = RCAR_GP_PIN(0, 8), /* D8 */ + [ 9] = RCAR_GP_PIN(0, 9), /* D9 */ + [10] = RCAR_GP_PIN(0, 10), /* D10 */ + [11] = RCAR_GP_PIN(0, 11), /* D11 */ + [12] = RCAR_GP_PIN(0, 12), /* D12 */ + [13] = RCAR_GP_PIN(0, 13), /* D13 */ + [14] = RCAR_GP_PIN(0, 14), /* D14 */ + [15] = RCAR_GP_PIN(0, 15), /* D15 */ + [16] = RCAR_GP_PIN(0, 16), /* A0 */ + [17] = RCAR_GP_PIN(0, 17), /* A1 */ + [18] = RCAR_GP_PIN(0, 18), /* A2 */ + [19] = RCAR_GP_PIN(0, 19), /* A3 */ + [20] = RCAR_GP_PIN(0, 20), /* A4 */ + [21] = RCAR_GP_PIN(0, 21), /* A5 */ + [22] = RCAR_GP_PIN(0, 22), /* A6 */ + [23] = RCAR_GP_PIN(0, 23), /* A7 */ + [24] = RCAR_GP_PIN(0, 24), /* A8 */ + [25] = RCAR_GP_PIN(0, 25), /* A9 */ + [26] = RCAR_GP_PIN(0, 26), /* A10 */ + [27] = RCAR_GP_PIN(0, 27), /* A11 */ + [28] = RCAR_GP_PIN(0, 28), /* A12 */ + [29] = RCAR_GP_PIN(0, 29), /* A13 */ + [30] = RCAR_GP_PIN(0, 30), /* A14 */ + [31] = RCAR_GP_PIN(0, 31), /* A15 */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + /* PUPR1 pull-up pins */ + [ 0] = RCAR_GP_PIN(1, 0), /* A16 */ + [ 1] = RCAR_GP_PIN(1, 1), /* A17 */ + [ 2] = RCAR_GP_PIN(1, 2), /* A18 */ + [ 3] = RCAR_GP_PIN(1, 3), /* A19 */ + [ 4] = RCAR_GP_PIN(1, 4), /* A20 */ + [ 5] = RCAR_GP_PIN(1, 5), /* A21 */ + [ 6] = RCAR_GP_PIN(1, 6), /* A22 */ + [ 7] = RCAR_GP_PIN(1, 7), /* A23 */ + [ 8] = RCAR_GP_PIN(1, 8), /* A24 */ + [ 9] = RCAR_GP_PIN(1, 9), /* A25 */ + [10] = RCAR_GP_PIN(1, 10), /* CS0# */ + [11] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [12] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [13] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [14] = RCAR_GP_PIN(1, 18), /* BS# */ + [15] = RCAR_GP_PIN(1, 19), /* RD# */ + [16] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [17] = RCAR_GP_PIN(1, 21), /* WE0# */ + [18] = RCAR_GP_PIN(1, 22), /* WE1# */ + [19] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [20] = RCAR_GP_PIN(1, 24), /* DREQ0# */ + [21] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [22] = PIN_TRST_N, /* TRST# */ + [23] = PIN_TCK, /* TCK */ + [24] = PIN_TMS, /* TMS */ + [25] = PIN_TDI, /* TDI */ + [26] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [28] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [29] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { + /* PUPR1 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */ + [ 1] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */ + [ 2] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */ + [ 3] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */ + [ 4] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */ + [ 5] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */ + [ 6] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */ + [ 7] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */ + [ 8] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */ + [ 9] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */ + [10] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */ + [11] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */ + [12] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */ + [13] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */ + [14] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */ + [15] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */ + [16] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */ + [19] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */ + [20] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */ + [21] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */ + [22] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */ + [23] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */ + [24] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */ + [25] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */ + [26] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */ + [27] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */ + [28] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */ + [29] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ + [30] = RCAR_GP_PIN(2, 30), /* DU0_DISP */ + [31] = RCAR_GP_PIN(2, 31), /* DU0_CDE */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */ + [ 1] = RCAR_GP_PIN(3, 3), /* VI0_DATA2_VI0_B2 */ + [ 2] = RCAR_GP_PIN(3, 4), /* VI0_DATA3_VI0_B3 */ + [ 3] = RCAR_GP_PIN(3, 5), /* VI0_DATA4_VI0_B4 */ + [ 4] = RCAR_GP_PIN(3, 6), /* VI0_DATA5_VI0_B5 */ + [ 5] = RCAR_GP_PIN(3, 7), /* VI0_DATA6_VI0_B6 */ + [ 6] = RCAR_GP_PIN(3, 8), /* VI0_DATA7_VI0_B7 */ + [ 7] = RCAR_GP_PIN(3, 9), /* VI0_CLKENB */ + [ 8] = RCAR_GP_PIN(3, 10), /* VI0_FIELD */ + [ 9] = RCAR_GP_PIN(3, 11), /* VI0_HSYNC# */ + [10] = RCAR_GP_PIN(3, 12), /* VI0_VSYNC# */ + [11] = RCAR_GP_PIN(3, 13), /* ETH_MDIO */ + [12] = RCAR_GP_PIN(3, 14), /* ETH_CRS_DV */ + [13] = RCAR_GP_PIN(3, 15), /* ETH_RX_ER */ + [14] = RCAR_GP_PIN(3, 16), /* ETH_RXD0 */ + [15] = RCAR_GP_PIN(3, 17), /* ETH_RXD1 */ + [16] = RCAR_GP_PIN(3, 18), /* ETH_LINK */ + [17] = RCAR_GP_PIN(3, 19), /* ETH_REF_CLK */ + [18] = RCAR_GP_PIN(3, 20), /* ETH_TXD1 */ + [19] = RCAR_GP_PIN(3, 21), /* ETH_TX_EN */ + [20] = RCAR_GP_PIN(3, 22), /* ETH_MAGIC */ + [21] = RCAR_GP_PIN(3, 23), /* ETH_TXD0 */ + [22] = RCAR_GP_PIN(3, 24), /* ETH_MDC */ + [23] = RCAR_GP_PIN(3, 25), /* HSCIF0_HRX */ + [24] = RCAR_GP_PIN(3, 26), /* HSCIF0_HTX */ + [25] = RCAR_GP_PIN(3, 27), /* HSCIF0_HCTS# */ + [26] = RCAR_GP_PIN(3, 28), /* HSCIF0_HRTS# */ + [27] = RCAR_GP_PIN(3, 29), /* HSCIF0_HSCK */ + [28] = RCAR_GP_PIN(3, 30), /* I2C0_SCL */ + [29] = RCAR_GP_PIN(3, 31), /* I2C0_SDA */ + [30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */ + [31] = RCAR_GP_PIN(4, 1), /* I2C1_SDA */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */ + [ 1] = RCAR_GP_PIN(4, 3), /* MSIOF0_TXD */ + [ 2] = RCAR_GP_PIN(4, 4), /* MSIOF0_SCK */ + [ 3] = RCAR_GP_PIN(4, 5), /* MSIOF0_SYNC */ + [ 4] = RCAR_GP_PIN(4, 6), /* MSIOF0_SS1 */ + [ 5] = RCAR_GP_PIN(4, 7), /* MSIOF0_SS2 */ + [ 6] = RCAR_GP_PIN(4, 8), /* HSCIF1_HRX */ + [ 7] = RCAR_GP_PIN(4, 9), /* HSCIF1_HTX */ + [ 8] = RCAR_GP_PIN(4, 10), /* HSCIF1_HSCK */ + [ 9] = RCAR_GP_PIN(4, 11), /* HSCIF1_HCTS# */ + [10] = RCAR_GP_PIN(4, 12), /* HSCIF1_HRTS# */ + [11] = RCAR_GP_PIN(4, 13), /* SCIF1_SCK */ + [12] = RCAR_GP_PIN(4, 14), /* SCIF1_RXD */ + [13] = RCAR_GP_PIN(4, 15), /* SCIF1_TXD */ + [14] = RCAR_GP_PIN(4, 16), /* SCIF2_RXD */ + [15] = RCAR_GP_PIN(4, 17), /* SCIF2_TXD */ + [16] = RCAR_GP_PIN(4, 18), /* SCIF2_SCK */ + [17] = RCAR_GP_PIN(4, 19), /* SCIF3_SCK */ + [18] = RCAR_GP_PIN(4, 20), /* SCIF3_RXD */ + [19] = RCAR_GP_PIN(4, 21), /* SCIF3_TXD */ + [20] = RCAR_GP_PIN(4, 22), /* I2C2_SCL */ + [21] = RCAR_GP_PIN(4, 23), /* I2C2_SDA */ + [22] = RCAR_GP_PIN(4, 24), /* SSI_SCK5 */ + [23] = RCAR_GP_PIN(4, 25), /* SSI_WS5 */ + [24] = RCAR_GP_PIN(4, 26), /* SSI_SDATA5 */ + [25] = RCAR_GP_PIN(4, 27), /* SSI_SCK6 */ + [26] = RCAR_GP_PIN(4, 28), /* SSI_WS6 */ + [27] = RCAR_GP_PIN(4, 29), /* SSI_SDATA6 */ + [28] = RCAR_GP_PIN(4, 30), /* SSI_SCK78 */ + [29] = RCAR_GP_PIN(4, 31), /* SSI_WS78 */ + [30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */ + [31] = RCAR_GP_PIN(5, 1), /* SSI_SCK0129 */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */ + [ 1] = RCAR_GP_PIN(5, 3), /* SSI_SDATA0 */ + [ 2] = RCAR_GP_PIN(5, 4), /* SSI_SCK34 */ + [ 3] = RCAR_GP_PIN(5, 5), /* SSI_WS34 */ + [ 4] = RCAR_GP_PIN(5, 6), /* SSI_SDATA3 */ + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = RCAR_GP_PIN(5, 10), /* SSI_SDATA8 */ + [ 9] = RCAR_GP_PIN(5, 11), /* SSI_SCK1 */ + [10] = RCAR_GP_PIN(5, 12), /* SSI_WS1 */ + [11] = RCAR_GP_PIN(5, 13), /* SSI_SDATA1 */ + [12] = RCAR_GP_PIN(5, 14), /* SSI_SCK2 */ + [13] = RCAR_GP_PIN(5, 15), /* SSI_WS2 */ + [14] = RCAR_GP_PIN(5, 16), /* SSI_SDATA2 */ + [15] = RCAR_GP_PIN(5, 17), /* SSI_SCK9 */ + [16] = RCAR_GP_PIN(5, 18), /* SSI_WS9 */ + [17] = RCAR_GP_PIN(5, 19), /* SSI_SDATA9 */ + [18] = RCAR_GP_PIN(5, 20), /* AUDIO_CLKA */ + [19] = RCAR_GP_PIN(5, 21), /* AUDIO_CLKB */ + [20] = RCAR_GP_PIN(5, 22), /* AUDIO_CLKC */ + [21] = RCAR_GP_PIN(5, 23), /* AUDIO_CLKOUT */ + [22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */ + [23] = RCAR_GP_PIN(3, 1), /* VI0_DATA0_VI0_B0 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ + [ 1] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ + [ 2] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ + [ 3] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ + [ 4] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ + [ 5] = RCAR_GP_PIN(6, 6), /* SD0_CD */ + [ 6] = RCAR_GP_PIN(6, 7), /* SD0_WP */ + [ 7] = RCAR_GP_PIN(6, 9), /* SD1_CMD */ + [ 8] = RCAR_GP_PIN(6, 10), /* SD1_DATA0 */ + [ 9] = RCAR_GP_PIN(6, 11), /* SD1_DATA1 */ + [10] = RCAR_GP_PIN(6, 12), /* SD1_DATA2 */ + [11] = RCAR_GP_PIN(6, 13), /* SD1_DATA3 */ + [12] = RCAR_GP_PIN(6, 14), /* SD1_CD */ + [13] = RCAR_GP_PIN(6, 15), /* SD1_WP */ + [14] = SH_PFC_PIN_NONE, + [15] = RCAR_GP_PIN(6, 17), /* MMC_CMD */ + [16] = RCAR_GP_PIN(6, 18), /* MMC_D0 */ + [17] = RCAR_GP_PIN(6, 19), /* MMC_D1 */ + [18] = RCAR_GP_PIN(6, 20), /* MMC_D2 */ + [19] = RCAR_GP_PIN(6, 21), /* MMC_D3 */ + [20] = RCAR_GP_PIN(6, 22), /* MMC_D4 */ + [21] = RCAR_GP_PIN(6, 23), /* MMC_D5 */ + [22] = RCAR_GP_PIN(6, 24), /* MMC_D6 */ + [23] = RCAR_GP_PIN(6, 25), /* MMC_D7 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) { /* Initialize TDSEL on old revisions */ @@ -5591,15 +5826,17 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) return 0; } -static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7794_pfc_ops = { .init = r8a7794_pinmux_soc_init, .pin_to_pocctrl = r8a7794_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A7745 const struct sh_pfc_soc_info r8a7745_pinmux_info = { .name = "r8a77450_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5612,6 +5849,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -5621,7 +5859,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A7794 const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", - .ops = &r8a7794_pinmux_ops, + .ops = &r8a7794_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5634,6 +5872,7 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c b/drivers/pinctrl/renesas/pfc-r8a7795.c index 015a50f1de..d094bd7cc9 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7795.c +++ b/drivers/pinctrl/renesas/pfc-r8a7795.c @@ -243,7 +243,7 @@ #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) -#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) +#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ #define GPSR7_3 FM(GP7_03) @@ -670,7 +670,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), - PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), @@ -1827,7 +1827,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2042,7 +2042,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; -#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -2455,6 +2455,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3260,20 +3270,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3285,20 +3288,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3533,19 +3529,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3571,19 +3560,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3609,30 +3591,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3681,30 +3647,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4063,69 +4013,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4157,29 +4099,25 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4211,9 +4149,9 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[326]; -#ifdef CONFIG_PINCTRL_PFC_R8A7795 - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group common[328]; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4417,11 +4355,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4453,28 +4391,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4517,34 +4455,36 @@ static const struct { SH_PFC_PIN_GROUP(usb2), SH_PFC_PIN_GROUP(usb2_ch3), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4576,8 +4516,9 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } -#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; static const char * const audio_clk_groups[] = { @@ -4636,7 +4577,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4678,7 +4619,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; -#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ static const char * const du_groups[] = { "du_rgb666", @@ -4771,6 +4712,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5098,6 +5045,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5109,6 +5057,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", @@ -5117,8 +5066,8 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[55]; -#ifdef CONFIG_PINCTRL_PFC_R8A7795 - struct sh_pfc_function automotive[4]; +#ifdef CONFIG_PINCTRL_PFC_R8A77951 + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5178,36 +5127,25 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } -#endif /* CONFIG_PINCTRL_PFC_R8A7795 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77951 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_16 RESERVED */ GP_0_15_FN, GPSR0_15, GP_0_14_FN, GPSR0_14, GP_0_13_FN, GPSR0_13, @@ -5259,24 +5197,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP2_31_15 RESERVED */ GP_2_14_FN, GPSR2_14, GP_2_13_FN, GPSR2_13, GP_2_12_FN, GPSR2_12, @@ -5293,23 +5218,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_16 RESERVED */ GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, GP_3_13_FN, GPSR3_13, @@ -5327,21 +5240,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_18 RESERVED */ GP_4_17_FN, GPSR4_17, GP_4_16_FN, GPSR4_16, GP_4_15_FN, GPSR4_15, @@ -5429,35 +5332,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, GPSR6_1, GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, + GROUP(-28, 1, 1, 1, 1), + GROUP( + /* GP7_31_4 RESERVED */ GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, @@ -5538,12 +5416,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_7_4 IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( + { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, + GROUP(4, 4, 4, 4, -4, 4, 4, 4), + GROUP( IP7_31_28 IP7_27_24 IP7_23_20 IP7_19_16 - /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_15_12 RESERVED */ IP7_11_8 IP7_7_4 IP7_3_0 )) @@ -5648,13 +5528,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_7_4 IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( - /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, + GROUP(-24, 4, 4), + GROUP( + /* IP18_31_8 RESERVED */ IP18_7_4 IP18_3_0 )) }, @@ -5664,8 +5541,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, - 1, 1, 1, 2, 2, 1, 2, 3), + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2, + 1, 1, 1, 2, 2, 1, 2, -3), GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 @@ -5677,7 +5554,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_19 MOD_SEL0_18_17 MOD_SEL0_16 - 0, 0, /* RESERVED 15 */ + /* RESERVED 15 */ MOD_SEL0_14_13 MOD_SEL0_12 MOD_SEL0_11 @@ -5686,12 +5563,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_7_6 MOD_SEL0_5 MOD_SEL0_4_3 - /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 )) + /* RESERVED 2, 1, 0 */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, - 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 @@ -5708,7 +5584,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_11 MOD_SEL1_10 MOD_SEL1_9 - 0, 0, 0, 0, /* RESERVED 8, 7 */ + /* RESERVED 8, 7 */ MOD_SEL1_6 MOD_SEL1_5 MOD_SEL1_4 @@ -5718,8 +5594,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, - GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, - 1, 4, 4, 4, 3, 1), + GROUP(1, 1, 1, 2, 1, 3, -1, 1, 1, 1, 1, 1, + -16, 1), GROUP( MOD_SEL2_31 MOD_SEL2_30 @@ -5728,25 +5604,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL2_26 MOD_SEL2_25_24_23 /* RESERVED 22 */ - 0, 0, MOD_SEL2_21 MOD_SEL2_20 MOD_SEL2_19 MOD_SEL2_18 MOD_SEL2_17 - /* RESERVED 16 */ - 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 11, 10, 9, 8 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 7, 6, 5, 4 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 3, 2, 1 */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 16-1 */ MOD_SEL2_0 )) }, { }, @@ -5874,7 +5737,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ } }, { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) { -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ #endif { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ @@ -6014,8 +5877,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77951_pin_to_pocctrl(struct sh_pfc *pfc, - unsigned int pin, u32 *pocctrl) +static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6272,57 +6134,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - -static const struct sh_pfc_soc_operations r8a77951_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77951_pfc_ops = { .pin_to_pocctrl = r8a77951_pin_to_pocctrl, - .get_bias = r8a7795_pinmux_get_bias, - .set_bias = r8a7795_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774E1 const struct sh_pfc_soc_info r8a774e1_pinmux_info = { .name = "r8a774e1_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6344,10 +6165,10 @@ const struct sh_pfc_soc_info r8a774e1_pinmux_info = { }; #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7795 -const struct sh_pfc_soc_info r8a7795_pinmux_info = { +#ifdef CONFIG_PINCTRL_PFC_R8A77951 +const struct sh_pfc_soc_info r8a77951_pinmux_info = { .name = "r8a77951_pfc", - .ops = &r8a77951_pinmux_ops, + .ops = &r8a77951_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 06cae74fb5..3cc4a3b366 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -70,6 +70,7 @@ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ @@ -1551,7 +1552,7 @@ static const u16 pinmux_data[] = { * core will do the right thing and skip trying to mux the pin * while still applying configuration to it. */ -#define FM(x) PINMUX_DATA(x##_MARK, 0), +#define FM(x) PINMUX_DATA(x##_MARK, 0), PINMUX_STATIC #undef FM }; @@ -1832,7 +1833,7 @@ static const unsigned int canfd1_data_mux[] = { CANFD1_TX_MARK, CANFD1_RX_MARK, }; -#if defined(CONFIG_PINCTRL_PFC_R8A7796) +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) /* - DRIF0 --------------------------------------------------------------- */ static const unsigned int drif0_ctrl_a_pins[] = { /* CLK, SYNC */ @@ -2047,7 +2048,7 @@ static const unsigned int drif3_data1_b_pins[] = { static const unsigned int drif3_data1_b_mux[] = { RIF3_D1_B_MARK, }; -#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ /* - DU --------------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { @@ -2460,6 +2461,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3266,20 +3277,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3291,20 +3295,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3524,19 +3521,12 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3562,19 +3552,12 @@ static const unsigned int sdhi0_wp_mux[] = { SD0_WP_MARK, }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3600,30 +3583,14 @@ static const unsigned int sdhi1_wp_mux[] = { SD1_WP_MARK, }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3672,30 +3639,14 @@ static const unsigned int sdhi2_ds_mux[] = { SD2_DS_MARK, }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4038,69 +3989,61 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4132,29 +4075,25 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, }; static const unsigned int vin5_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -4186,9 +4125,9 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[322]; -#if defined(CONFIG_PINCTRL_PFC_R8A7796) - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group common[324]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4212,7 +4151,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), @@ -4392,11 +4331,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -4426,28 +4365,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4488,34 +4427,36 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), SH_PFC_PIN_GROUP(vin5_clk), }, -#if defined(CONFIG_PINCTRL_PFC_R8A7796) +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_PIN_GROUP(drif0_ctrl_a), SH_PFC_PIN_GROUP(drif0_data0_a), @@ -4547,8 +4488,9 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } -#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const char * const audio_clk_groups[] = { @@ -4607,7 +4549,7 @@ static const char * const canfd1_groups[] = { "canfd1_data", }; -#if defined(CONFIG_PINCTRL_PFC_R8A7796) +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) static const char * const drif0_groups[] = { "drif0_ctrl_a", "drif0_data0_a", @@ -4649,7 +4591,7 @@ static const char * const drif3_groups[] = { "drif3_data0_b", "drif3_data1_b", }; -#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ static const char * const du_groups[] = { "du_rgb666", @@ -4742,6 +4684,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5056,6 +5004,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5067,6 +5016,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", @@ -5075,8 +5025,8 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[52]; -#if defined(CONFIG_PINCTRL_PFC_R8A7796) - struct sh_pfc_function automotive[4]; +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5133,36 +5083,25 @@ static const struct { SH_PFC_FUNCTION(vin4), SH_PFC_FUNCTION(vin5), }, -#if defined(CONFIG_PINCTRL_PFC_R8A7796) +#if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961) .automotive = { SH_PFC_FUNCTION(drif0), SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } -#endif /* CONFIG_PINCTRL_PFC_R8A7796 */ +#endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */ }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_16 RESERVED */ GP_0_15_FN, GPSR0_15, GP_0_14_FN, GPSR0_14, GP_0_13_FN, GPSR0_13, @@ -5214,24 +5153,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP2_31_15 RESERVED */ GP_2_14_FN, GPSR2_14, GP_2_13_FN, GPSR2_13, GP_2_12_FN, GPSR2_12, @@ -5248,23 +5174,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_16 RESERVED */ GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, GP_3_13_FN, GPSR3_13, @@ -5282,21 +5196,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_18 RESERVED */ GP_4_17_FN, GPSR4_17, GP_4_16_FN, GPSR4_16, GP_4_15_FN, GPSR4_15, @@ -5384,35 +5288,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, GPSR6_1, GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, + GROUP(-28, 1, 1, 1, 1), + GROUP( + /* GP7_31_4 RESERVED */ GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, @@ -5493,12 +5372,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_7_4 IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( + { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, + GROUP(4, 4, 4, 4, -4, 4, 4, 4), + GROUP( IP7_31_28 IP7_27_24 IP7_23_20 IP7_19_16 - /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_15_12 RESERVED */ IP7_11_8 IP7_7_4 IP7_3_0 )) @@ -5603,13 +5484,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_7_4 IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( - /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, + GROUP(-24, 4, 4), + GROUP( + /* IP18_31_8 RESERVED */ IP18_7_4 IP18_3_0 )) }, @@ -5619,8 +5497,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, - 1, 1, 1, 2, 2, 1, 2, 3), + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2, + 1, 1, 1, 2, 2, 1, 2, -3), GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 @@ -5632,7 +5510,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_19 MOD_SEL0_18_17 MOD_SEL0_16 - 0, 0, /* RESERVED 15 */ + /* RESERVED 15 */ MOD_SEL0_14_13 MOD_SEL0_12 MOD_SEL0_11 @@ -5641,12 +5519,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_7_6 MOD_SEL0_5 MOD_SEL0_4_3 - /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 )) + /* RESERVED 2, 1, 0 */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, - 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 @@ -5663,7 +5540,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_11 MOD_SEL1_10 MOD_SEL1_9 - 0, 0, 0, 0, /* RESERVED 8, 7 */ + /* RESERVED 8, 7 */ MOD_SEL1_6 MOD_SEL1_5 MOD_SEL1_4 @@ -5674,7 +5551,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, - 1, 4, 4, 4, 3, 1), + -16, 1), GROUP( MOD_SEL2_31 MOD_SEL2_30 @@ -5688,19 +5565,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL2_19 MOD_SEL2_18 MOD_SEL2_17 - /* RESERVED 16 */ - 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 11, 10, 9, 8 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 7, 6, 5, 4 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 3, 2, 1 */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 16-1 */ MOD_SEL2_0 )) }, { }, @@ -5965,7 +5830,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6193,7 +6058,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = SH_PFC_PIN_NONE, + [ 7] = PIN_PRESET_N, /* PRESET# */ [ 8] = SH_PFC_PIN_NONE, [ 9] = SH_PFC_PIN_NONE, [10] = SH_PFC_PIN_NONE, @@ -6222,57 +6087,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - -static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a7796_pfc_ops = { .pin_to_pocctrl = r8a7796_pin_to_pocctrl, - .get_bias = r8a7796_pinmux_get_bias, - .set_bias = r8a7796_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774A1 const struct sh_pfc_soc_info r8a774a1_pinmux_info = { .name = "r8a774a1_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6294,10 +6118,37 @@ const struct sh_pfc_soc_info r8a774a1_pinmux_info = { }; #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7796 -const struct sh_pfc_soc_info r8a7796_pinmux_info = { +#ifdef CONFIG_PINCTRL_PFC_R8A77960 +const struct sh_pfc_soc_info r8a77960_pinmux_info = { .name = "r8a77960_pfc", - .ops = &r8a7796_pinmux_ops, + .ops = &r8a7796_pfc_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), + + .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, + .bias_regs = pinmux_bias_regs, + .ioctrl_regs = pinmux_ioctrl_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A77961 +const struct sh_pfc_soc_info r8a77961_pinmux_info = { + .name = "r8a77961_pfc", + .ops = &r8a7796_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index fae29d535c..04e8371f51 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -669,14 +669,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), @@ -730,16 +730,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1174,13 +1174,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), @@ -1556,7 +1556,7 @@ static const u16 pinmux_data[] = { * core will do the right thing and skip trying to mux the pin * while still applying configuration to it. */ -#define FM(x) PINMUX_DATA(x##_MARK, 0), +#define FM(x) PINMUX_DATA(x##_MARK, 0), PINMUX_STATIC #undef FM }; @@ -2612,6 +2612,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -3417,20 +3427,13 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, /* QSPI0_IO2, QSPI0_IO3 */ PIN_QSPI0_IO2, PIN_QSPI0_IO3, }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK, }; @@ -3442,20 +3445,13 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, /* QSPI1_IO2, QSPI1_IO3 */ PIN_QSPI1_IO2, PIN_QSPI1_IO3, }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; @@ -3691,22 +3687,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3739,22 +3726,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3787,27 +3765,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI2 ------------------------------------------------------------------ */ -static const unsigned int sdhi2_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi2_data1_mux[] = { - SD2_DAT0_MARK, -}; - -static const unsigned int sdhi2_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi2_data4_mux[] = { - SD2_DAT0_MARK, SD2_DAT1_MARK, - SD2_DAT2_MARK, SD2_DAT3_MARK, -}; - -static const unsigned int sdhi2_data8_pins[] = { +static const unsigned int sdhi2_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3815,7 +3773,7 @@ static const unsigned int sdhi2_data8_pins[] = { RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi2_data8_mux[] = { +static const unsigned int sdhi2_data_mux[] = { SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, SD2_DAT4_MARK, SD2_DAT5_MARK, @@ -3877,27 +3835,7 @@ static const unsigned int sdhi2_ds_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 9), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), - RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), @@ -3905,7 +3843,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -4227,118 +4165,110 @@ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), +}; + +static const unsigned int vin4_data18_a_mux[] = { + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, +}; + +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), + RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const unsigned int vin4_data18_a_mux[] = { +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, VI4_DATA18_MARK, VI4_DATA19_MARK, VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), - RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, +static const unsigned int vin4_data18_b_pins[] = { + RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data18_b_mux[] = { + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const unsigned int vin4_data18_b_pins[] = { +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; -static const unsigned int vin4_data18_b_mux[] = { +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, VI4_DATA10_MARK, VI4_DATA11_MARK, VI4_DATA12_MARK, VI4_DATA13_MARK, VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, VI4_DATA18_MARK, VI4_DATA19_MARK, VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), - RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - }, -}; - -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, -}; - static const unsigned int vin4_sync_pins[] = { /* VSYNC_N, HSYNC_N */ RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), @@ -4373,30 +4303,26 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_pins = { - .data16 = { - RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), - RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), - RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - }, +static const unsigned int vin5_data_pins[] = { + RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), }; -static const union vin_data16 vin5_data_mux = { - .data16 = { - VI5_DATA0_MARK, VI5_DATA1_MARK, - VI5_DATA2_MARK, VI5_DATA3_MARK, - VI5_DATA4_MARK, VI5_DATA5_MARK, - VI5_DATA6_MARK, VI5_DATA7_MARK, - VI5_DATA8_MARK, VI5_DATA9_MARK, - VI5_DATA10_MARK, VI5_DATA11_MARK, - VI5_DATA12_MARK, VI5_DATA13_MARK, - VI5_DATA14_MARK, VI5_DATA15_MARK, - }, +static const unsigned int vin5_data_mux[] = { + VI5_DATA0_MARK, VI5_DATA1_MARK, + VI5_DATA2_MARK, VI5_DATA3_MARK, + VI5_DATA4_MARK, VI5_DATA5_MARK, + VI5_DATA6_MARK, VI5_DATA7_MARK, + VI5_DATA8_MARK, VI5_DATA9_MARK, + VI5_DATA10_MARK, VI5_DATA11_MARK, + VI5_DATA12_MARK, VI5_DATA13_MARK, + VI5_DATA14_MARK, VI5_DATA15_MARK, }; static const unsigned int vin5_sync_pins[] = { @@ -4433,9 +4359,9 @@ static const unsigned int vin5_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[324]; + struct sh_pfc_pin_group common[326]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 - struct sh_pfc_pin_group automotive[30]; + struct sh_pfc_pin_group automotive[31]; #endif } pinmux_groups = { .common = { @@ -4639,11 +4565,11 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(sata0_devslp_a), SH_PFC_PIN_GROUP(sata0_devslp_b), SH_PFC_PIN_GROUP(scif0_data), @@ -4675,28 +4601,28 @@ static const struct { SH_PFC_PIN_GROUP(scif5_clk_b), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_data8), + BUS_DATA_PIN_GROUP(sdhi2_data, 1), + BUS_DATA_PIN_GROUP(sdhi2_data, 4), + BUS_DATA_PIN_GROUP(sdhi2_data, 8), SH_PFC_PIN_GROUP(sdhi2_ctrl), SH_PFC_PIN_GROUP(sdhi2_cd_a), SH_PFC_PIN_GROUP(sdhi2_wp_a), SH_PFC_PIN_GROUP(sdhi2_cd_b), SH_PFC_PIN_GROUP(sdhi2_wp_b), SH_PFC_PIN_GROUP(sdhi2_ds), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4737,28 +4663,30 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb1), SH_PFC_PIN_GROUP(usb30), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8), - VIN_DATA_PIN_GROUP(vin5_data, 10), - VIN_DATA_PIN_GROUP(vin5_data, 12), - VIN_DATA_PIN_GROUP(vin5_data, 16), + BUS_DATA_PIN_GROUP(vin5_data, 8), + BUS_DATA_PIN_GROUP(vin5_data, 10), + BUS_DATA_PIN_GROUP(vin5_data, 12), + BUS_DATA_PIN_GROUP(vin5_data, 16), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8), SH_PFC_PIN_GROUP(vin5_sync), SH_PFC_PIN_GROUP(vin5_field), SH_PFC_PIN_GROUP(vin5_clkenb), @@ -4796,6 +4724,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; @@ -4991,6 +4920,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77965 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77965 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -5309,6 +5244,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -5320,6 +5256,7 @@ static const char * const vin5_groups[] = { "vin5_data10", "vin5_data12", "vin5_data16", + "vin5_high8", "vin5_sync", "vin5_field", "vin5_clkenb", @@ -5329,7 +5266,7 @@ static const char * const vin5_groups[] = { static const struct { struct sh_pfc_function common[53]; #ifdef CONFIG_PINCTRL_PFC_R8A77965 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -5393,6 +5330,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77965 */ }; @@ -5400,23 +5338,11 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_16 RESERVED */ GP_0_15_FN, GPSR0_15, GP_0_14_FN, GPSR0_14, GP_0_13_FN, GPSR0_13, @@ -5468,24 +5394,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP2_31_15 RESERVED */ GP_2_14_FN, GPSR2_14, GP_2_13_FN, GPSR2_13, GP_2_12_FN, GPSR2_12, @@ -5502,23 +5415,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_16 RESERVED */ GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, GP_3_13_FN, GPSR3_13, @@ -5536,21 +5437,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_18 RESERVED */ GP_4_17_FN, GPSR4_17, GP_4_16_FN, GPSR4_16, GP_4_15_FN, GPSR4_15, @@ -5638,35 +5529,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, GPSR6_1, GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32, + GROUP(-28, 1, 1, 1, 1), + GROUP( + /* GP7_31_4 RESERVED */ GP_7_3_FN, GPSR7_3, GP_7_2_FN, GPSR7_2, GP_7_1_FN, GPSR7_1, @@ -5747,12 +5613,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP6_7_4 IP6_3_0 )) }, - { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( + { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32, + GROUP(4, 4, 4, 4, -4, 4, 4, 4), + GROUP( IP7_31_28 IP7_27_24 IP7_23_20 IP7_19_16 - /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* IP7_15_12 RESERVED */ IP7_11_8 IP7_7_4 IP7_3_0 )) @@ -5857,13 +5725,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP17_7_4 IP17_3_0 )) }, - { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP( - /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32, + GROUP(-24, 4, 4), + GROUP( + /* IP18_31_8 RESERVED */ IP18_7_4 IP18_3_0 )) }, @@ -5873,8 +5738,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2, - 1, 1, 1, 2, 2, 1, 2, 3), + GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2, + 1, 1, 1, 2, 2, 1, 2, -3), GROUP( MOD_SEL0_31_30_29 MOD_SEL0_28_27 @@ -5886,7 +5751,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_19 MOD_SEL0_18_17 MOD_SEL0_16 - 0, 0, /* RESERVED 15 */ + /* RESERVED 15 */ MOD_SEL0_14_13 MOD_SEL0_12 MOD_SEL0_11 @@ -5895,12 +5760,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_7_6 MOD_SEL0_5 MOD_SEL0_4_3 - /* RESERVED 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0 )) + /* RESERVED 2, 1, 0 */ )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1, - 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1), + 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1), GROUP( MOD_SEL1_31_30 MOD_SEL1_29_28_27 @@ -5917,7 +5781,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_11 MOD_SEL1_10 MOD_SEL1_9 - 0, 0, 0, 0, /* RESERVED 8, 7 */ + /* RESERVED 8, 7 */ MOD_SEL1_6 MOD_SEL1_5 MOD_SEL1_4 @@ -5928,7 +5792,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32, GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, - 1, 4, 4, 4, 3, 1), + -16, 1), GROUP( MOD_SEL2_31 MOD_SEL2_30 @@ -5942,19 +5806,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL2_19 MOD_SEL2_18 MOD_SEL2_17 - /* RESERVED 16 */ - 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 11, 10, 9, 8 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 7, 6, 5, 4 */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 3, 2, 1 */ - 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 16-1 */ MOD_SEL2_0 )) }, { }, @@ -6219,7 +6071,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -6476,57 +6328,16 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - -static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77965_pfc_ops = { .pin_to_pocctrl = r8a77965_pin_to_pocctrl, - .get_bias = r8a77965_pinmux_get_bias, - .set_bias = r8a77965_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774B1 const struct sh_pfc_soc_info r8a774b1_pinmux_info = { .name = "r8a774b1_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -6551,7 +6362,7 @@ const struct sh_pfc_soc_info r8a774b1_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77965 const struct sh_pfc_soc_info r8a77965_pinmux_info = { .name = "r8a77965_pfc", - .ops = &r8a77965_pinmux_ops, + .ops = &r8a77965_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 8cf133a2ba..04f0345233 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -21,12 +21,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_6(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -161,7 +172,7 @@ #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -222,7 +233,6 @@ #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -281,8 +291,7 @@ FM(IP8_11_8) IP8_11_8 \ FM(IP8_15_12) IP8_15_12 \ FM(IP8_19_16) IP8_19_16 \ FM(IP8_23_20) IP8_23_20 \ -FM(IP8_27_24) IP8_27_24 \ -FM(IP8_31_28) IP8_31_28 +FM(IP8_27_24) IP8_27_24 /* MOD_SEL0 */ /* 0 */ /* 1 */ #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1) @@ -720,8 +729,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB0 ------------------------------------------------------------------- */ @@ -1084,30 +1102,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 6), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1375,22 +1377,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1400,36 +1386,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1621,25 +1585,21 @@ static const unsigned int tmu_tclk2_b_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data12 vin0_data_pins = { - .data12 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - }, -}; -static const union vin_data12 vin0_data_mux = { - .data12 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), +}; +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, }; static const unsigned int vin0_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1671,25 +1631,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -1765,9 +1721,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -1804,13 +1760,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -1835,16 +1791,16 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tmu_tclk1_b), SH_PFC_PIN_GROUP(tmu_tclk2_a), SH_PFC_PIN_GROUP(tmu_tclk2_b), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2129,17 +2085,11 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_22 RESERVED */ GP_0_21_FN, GPSR0_21, GP_0_20_FN, GPSR0_20, GP_0_19_FN, GPSR0_19, @@ -2197,22 +2147,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP2_31_17 RESERVED */ GP_2_16_FN, GPSR2_16, GP_2_15_FN, GPSR2_15, GP_2_14_FN, GPSR2_14, @@ -2231,22 +2170,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_17 RESERVED */ GP_3_16_FN, GPSR3_16, GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, @@ -2265,33 +2193,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-26, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_6 RESERVED */ GP_4_5_FN, GPSR4_5, GP_4_4_FN, GPSR4_4, GP_4_3_FN, GPSR4_3, @@ -2299,24 +2204,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, GPSR4_1, GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP5_31_15 RESERVED */ GP_5_14_FN, GPSR5_14, GP_5_13_FN, GPSR5_13, GP_5_12_FN, GPSR5_12, @@ -2418,8 +2310,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP7_7_4 IP7_3_0 )) }, - { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( - IP8_31_28 + { PINMUX_CFG_REG_VAR("IPSR8", 0xe6060220, 32, + GROUP(-4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + /* IP8_31_28 RESERVED */ IP8_27_24 IP8_23_20 IP8_19_16 @@ -2434,19 +2328,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1), + GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), GROUP( - /* RESERVED 31, 30, 29, 28 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 27, 26, 25, 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 23, 22, 21, 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 19, 18, 17, 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 31-12 */ MOD_SEL0_11 MOD_SEL0_10 MOD_SEL0_9 @@ -2478,8 +2362,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -2498,13 +2381,155 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return -EINVAL; } -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ + [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ + [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ + [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ + [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ + [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ + [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ + [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ + [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ + [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ + [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ + [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ + [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ + [22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ + [23] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [24] = PIN_EXTALR, /* EXTALR */ + [25] = PIN_FSCLKST_N, /* FSCLKST# */ + [26] = RCAR_GP_PIN(1, 0), /* IRQ0 */ + [27] = PIN_TRST_N, /* TRST# */ + [28] = PIN_TCK, /* TCK */ + [29] = PIN_TMS, /* TMS */ + [30] = PIN_TDI, /* TDI */ + [31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ + [ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ + [ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ + [ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ + [ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ + [ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ + [ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ + [ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ + [ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ + [ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ + [10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ + [11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ + [12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ + [13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ + [14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ + [15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ + [16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ + [17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ + [18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ + [19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ + [20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ + [21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ + [22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ + [23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ + [24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ + [25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ + [26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ + [27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ + [28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ + [29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ + [30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ + [31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ + [ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */ + [ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */ + [ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */ + [ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */ + [ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */ + [ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */ + [ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */ + [ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */ + [ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */ + [10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */ + [11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */ + [12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */ + [13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */ + [14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */ + [15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */ + [16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */ + [17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */ + [18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */ + [19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */ + [20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */ + [21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */ + [22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */ + [23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */ + [24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */ + [25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */ + [26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */ + [27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ + [28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ + [29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ + [30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ + [31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ + [ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ + [ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ + [ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ + [ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ + [ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ + [10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ + [11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ + [12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ + [13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ + [14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ + [15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ + [16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + +static const struct sh_pfc_soc_operations r8a77970_pfc_ops = { .pin_to_pocctrl = r8a77970_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77970_pinmux_info = { .name = "r8a77970_pfc", - .ops = &pinmux_ops, + .ops = &r8a77970_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2517,6 +2542,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 7cd4ef9830..19bd46c9e4 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -21,12 +21,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_25(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) /* * F_() : just information @@ -88,7 +99,7 @@ #define GPSR1_0 F_(IRQ0, IP2_27_24) /* GPSR2 */ -#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) +#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) #define GPSR2_26 F_(SDA3, IP10_7_4) @@ -253,11 +264,11 @@ #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -269,9 +280,6 @@ #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -331,9 +339,9 @@ FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \ FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \ FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \ FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \ -FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \ -FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \ -FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 +FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 \ +FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 \ +FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 /* MOD_SEL0 */ /* 0 */ /* 1 */ #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1) @@ -832,8 +840,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB -------------------------------------------------------------------- */ @@ -1347,30 +1364,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_D0 */ - RCAR_GP_PIN(3, 8), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_D[0:3] */ - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_D[0:7] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1669,22 +1670,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2), - RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { @@ -1694,36 +1679,14 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { - /* MOSI_IO0, MISO_IO1, IO2, IO3 */ - RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), - RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), -}; -static const unsigned int qspi1_data4_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, - QSPI1_IO2_MARK, QSPI1_IO3_MARK -}; /* - RPC -------------------------------------------------------------------- */ -static const unsigned int rpc_clk1_pins[] = { +static const unsigned int rpc_clk_pins[] = { /* Octal-SPI flash: C/SCLK */ - RCAR_GP_PIN(5, 0), -}; -static const unsigned int rpc_clk1_mux[] = { - QSPI0_SPCLK_MARK, -}; -static const unsigned int rpc_clk2_pins[] = { /* HyperFlash: CK, CK# */ RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6), }; -static const unsigned int rpc_clk2_mux[] = { +static const unsigned int rpc_clk_mux[] = { QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; static const unsigned int rpc_ctrl_pins[] = { @@ -1945,37 +1908,33 @@ static const unsigned int tpu_to3_mux[] = { }; /* - VIN0 ------------------------------------------------------------------- */ -static const union vin_data vin0_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), - RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), - }, +static const unsigned int vin0_data_pins[] = { + RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), + RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), + RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28), }; -static const union vin_data vin0_data_mux = { - .data24 = { - VI0_DATA0_MARK, VI0_DATA1_MARK, - VI0_DATA2_MARK, VI0_DATA3_MARK, - VI0_DATA4_MARK, VI0_DATA5_MARK, - VI0_DATA6_MARK, VI0_DATA7_MARK, - VI0_DATA8_MARK, VI0_DATA9_MARK, - VI0_DATA10_MARK, VI0_DATA11_MARK, - VI0_DATA12_MARK, VI0_DATA13_MARK, - VI0_DATA14_MARK, VI0_DATA15_MARK, - VI0_DATA16_MARK, VI0_DATA17_MARK, - VI0_DATA18_MARK, VI0_DATA19_MARK, - VI0_DATA20_MARK, VI0_DATA21_MARK, - VI0_DATA22_MARK, VI0_DATA23_MARK, - }, +static const unsigned int vin0_data_mux[] = { + VI0_DATA0_MARK, VI0_DATA1_MARK, + VI0_DATA2_MARK, VI0_DATA3_MARK, + VI0_DATA4_MARK, VI0_DATA5_MARK, + VI0_DATA6_MARK, VI0_DATA7_MARK, + VI0_DATA8_MARK, VI0_DATA9_MARK, + VI0_DATA10_MARK, VI0_DATA11_MARK, + VI0_DATA12_MARK, VI0_DATA13_MARK, + VI0_DATA14_MARK, VI0_DATA15_MARK, + VI0_DATA16_MARK, VI0_DATA17_MARK, + VI0_DATA18_MARK, VI0_DATA19_MARK, + VI0_DATA20_MARK, VI0_DATA21_MARK, + VI0_DATA22_MARK, VI0_DATA23_MARK, }; static const unsigned int vin0_data18_pins[] = { RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), @@ -2029,25 +1988,21 @@ static const unsigned int vin0_clk_mux[] = { }; /* - VIN1 ------------------------------------------------------------------- */ -static const union vin_data12 vin1_data_pins = { - .data12 = { - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), - RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), - RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), - RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), - RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), - RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), - }, +static const unsigned int vin1_data_pins[] = { + RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), + RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), + RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), + RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), }; -static const union vin_data12 vin1_data_mux = { - .data12 = { - VI1_DATA0_MARK, VI1_DATA1_MARK, - VI1_DATA2_MARK, VI1_DATA3_MARK, - VI1_DATA4_MARK, VI1_DATA5_MARK, - VI1_DATA6_MARK, VI1_DATA7_MARK, - VI1_DATA8_MARK, VI1_DATA9_MARK, - VI1_DATA10_MARK, VI1_DATA11_MARK, - }, +static const unsigned int vin1_data_mux[] = { + VI1_DATA0_MARK, VI1_DATA1_MARK, + VI1_DATA2_MARK, VI1_DATA3_MARK, + VI1_DATA4_MARK, VI1_DATA5_MARK, + VI1_DATA6_MARK, VI1_DATA7_MARK, + VI1_DATA8_MARK, VI1_DATA9_MARK, + VI1_DATA10_MARK, VI1_DATA11_MARK, }; static const unsigned int vin1_sync_pins[] = { /* VI1_VSYNC#, VI1_HSYNC# */ @@ -2138,9 +2093,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq3), SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2180,13 +2135,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4_a), SH_PFC_PIN_GROUP(pwm4_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), - SH_PFC_PIN_GROUP(rpc_clk1), - SH_PFC_PIN_GROUP(rpc_clk2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), SH_PFC_PIN_GROUP(rpc_ctrl), SH_PFC_PIN_GROUP(rpc_data), SH_PFC_PIN_GROUP(rpc_reset), @@ -2215,20 +2170,20 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(tpu_to1), SH_PFC_PIN_GROUP(tpu_to2), SH_PFC_PIN_GROUP(tpu_to3), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 16), + BUS_DATA_PIN_GROUP(vin0_data, 8), + BUS_DATA_PIN_GROUP(vin0_data, 10), + BUS_DATA_PIN_GROUP(vin0_data, 12), + BUS_DATA_PIN_GROUP(vin0_data, 16), SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 20), - VIN_DATA_PIN_GROUP(vin0_data, 24), + BUS_DATA_PIN_GROUP(vin0_data, 20), + BUS_DATA_PIN_GROUP(vin0_data, 24), SH_PFC_PIN_GROUP(vin0_sync), SH_PFC_PIN_GROUP(vin0_field), SH_PFC_PIN_GROUP(vin0_clkenb), SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 12), + BUS_DATA_PIN_GROUP(vin1_data, 8), + BUS_DATA_PIN_GROUP(vin1_data, 10), + BUS_DATA_PIN_GROUP(vin1_data, 12), SH_PFC_PIN_GROUP(vin1_sync), SH_PFC_PIN_GROUP(vin1_field), SH_PFC_PIN_GROUP(vin1_clkenb), @@ -2551,17 +2506,11 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_22 RESERVED */ GP_0_21_FN, GPSR0_21, GP_0_20_FN, GPSR0_20, GP_0_19_FN, GPSR0_19, @@ -2653,22 +2602,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_17 RESERVED */ GP_3_16_FN, GPSR3_16, GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, @@ -2687,14 +2625,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1), + GROUP( + /* GP4_31_25 RESERVED */ GP_4_24_FN, GPSR4_24, GP_4_23_FN, GPSR4_23, GP_4_22_FN, GPSR4_22, @@ -2721,24 +2657,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, GPSR4_1, GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, + GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1), + GROUP( + /* GP5_31_15 RESERVED */ GP_5_14_FN, GPSR5_14, GP_5_13_FN, GPSR5_13, GP_5_12_FN, GPSR5_12, @@ -2860,10 +2783,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP9_7_4 IP9_3_0 )) }, - { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( - IP10_31_28 - IP10_27_24 - IP10_23_20 + { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32, + GROUP(-12, 4, 4, 4, 4, 4), + GROUP( + /* IP10_31_20 RESERVED */ IP10_19_16 IP10_15_12 IP10_11_8 @@ -2876,19 +2799,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1), + GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1), GROUP( - /* RESERVED 31, 30, 29, 28 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 27, 26, 25, 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 23, 22, 21, 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 19, 18, 17, 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /* RESERVED 31-12 */ MOD_SEL0_11 MOD_SEL0_10 MOD_SEL0_9 @@ -2897,7 +2810,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_6 MOD_SEL0_5 MOD_SEL0_4 - 0, 0, + /* RESERVED 3 */ MOD_SEL0_2 MOD_SEL0_1 MOD_SEL0_0 )) @@ -2922,8 +2835,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -2947,13 +2859,189 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return -EINVAL; } -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ + [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ + [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ + [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ + [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ + [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ + [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ + [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ + [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ + [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ + [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ + [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ + [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ + [25] = SH_PFC_PIN_NONE, + [26] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = PIN_EXTALR, /* EXTALR */ + [31] = PIN_FSCLKST_N, /* FSCLKST# */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = PIN_FSCLKST, /* FSCLKST */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */ + [ 3] = PIN_DCUTRST_N, /* DCUTRST# */ + [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */ + [ 5] = PIN_DCUTMS, /* DCUTMS */ + [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */ + [ 7] = SH_PFC_PIN_NONE, + [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ + [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ + [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ + [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ + [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ + [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ + [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ + [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ + [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ + [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ + [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ + [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ + [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ + [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ + [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ + [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ + [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ + [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ + [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ + [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ + [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ + [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ + [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ + [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ + [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ + [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ + [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ + [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ + [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ + [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ + [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ + [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ + [10] = RCAR_GP_PIN(4, 0), /* SCL0 */ + [11] = RCAR_GP_PIN(4, 1), /* SDA0 */ + [12] = RCAR_GP_PIN(4, 2), /* SCL1 */ + [13] = RCAR_GP_PIN(4, 3), /* SDA1 */ + [14] = RCAR_GP_PIN(4, 4), /* SCL2 */ + [15] = RCAR_GP_PIN(4, 5), /* SDA2 */ + [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */ + [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */ + [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */ + [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */ + [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */ + [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */ + [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */ + [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */ + [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */ + [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */ + [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */ + [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */ + [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */ + [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */ + [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */ + [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */ + [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */ + [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */ + [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */ + [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */ + [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */ + [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */ + [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */ + [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */ + [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */ + [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */ + [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */ + [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */ + [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */ + [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */ + [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */ + [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */ + [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */ + [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */ + [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */ + [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */ + [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */ + [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */ + [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ + [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ + [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ + [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ + [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */ + [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ + [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ + [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ + [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ + [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ + [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ + [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ + [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ + [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ + [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ + [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ + [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ + [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ + [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ + [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ + [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ + [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */ + [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */ + [15] = RCAR_GP_PIN(2, 25), /* SCL3 */ + [16] = RCAR_GP_PIN(2, 26), /* SDA3 */ + [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */ + [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */ + [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */ + [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */ + [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */ + [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */ + [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */ + [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */ + [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */ + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + +static const struct sh_pfc_soc_operations r8a77980_pfc_ops = { .pin_to_pocctrl = r8a77980_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77980_pinmux_info = { .name = "r8a77980_pfc", - .ops = &pinmux_ops, + .ops = &r8a77980_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2966,6 +3054,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index 78b46de041..c6c3d0988b 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -26,12 +26,12 @@ PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \ - PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \ PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ @@ -57,10 +57,10 @@ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS) + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP) /* * F_() : just information @@ -2343,6 +2343,16 @@ static const unsigned int intc_ex_irq5_mux[] = { IRQ5_MARK, }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), +}; +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + /* - MSIOF0 ----------------------------------------------------------------- */ static const unsigned int msiof0_clk_pins[] = { /* SCK */ @@ -2821,23 +2831,6 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { - /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */ - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - /* QSPI0_IO2, QSPI0_IO3 */ - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), -}; -static const unsigned int qspi0_data4_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, - QSPI0_IO2_MARK, QSPI0_IO3_MARK, -}; /* - QSPI1 ------------------------------------------------------------------ */ static const unsigned int qspi1_ctrl_pins[] = { /* QSPI1_SPCLK, QSPI1_SSL */ @@ -2846,23 +2839,51 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + +/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk_pins[] = { + /* Octal-SPI flash: C/SCLK */ + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6), }; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, +static const unsigned int rpc_clk_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, }; -static const unsigned int qspi1_data4_pins[] = { - /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */ +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - /* QSPI1_IO2, QSPI1_IO3 */ RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK, }; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { @@ -3142,22 +3163,13 @@ static const unsigned int scif_clk_b_mux[] = { }; /* - SDHI0 ------------------------------------------------------------------ */ -static const unsigned int sdhi0_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), -}; - -static const unsigned int sdhi0_data1_mux[] = { - SD0_DAT0_MARK, -}; - -static const unsigned int sdhi0_data4_pins[] = { +static const unsigned int sdhi0_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), }; -static const unsigned int sdhi0_data4_mux[] = { +static const unsigned int sdhi0_data_mux[] = { SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, }; @@ -3190,22 +3202,13 @@ static const unsigned int sdhi0_wp_mux[] = { }; /* - SDHI1 ------------------------------------------------------------------ */ -static const unsigned int sdhi1_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 8), -}; - -static const unsigned int sdhi1_data1_mux[] = { - SD1_DAT0_MARK, -}; - -static const unsigned int sdhi1_data4_pins[] = { +static const unsigned int sdhi1_data_pins[] = { /* D[0:3] */ RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), }; -static const unsigned int sdhi1_data4_mux[] = { +static const unsigned int sdhi1_data_mux[] = { SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, }; @@ -3238,27 +3241,7 @@ static const unsigned int sdhi1_wp_mux[] = { }; /* - SDHI3 ------------------------------------------------------------------ */ -static const unsigned int sdhi3_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(4, 2), -}; - -static const unsigned int sdhi3_data1_mux[] = { - SD3_DAT0_MARK, -}; - -static const unsigned int sdhi3_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), - RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), -}; - -static const unsigned int sdhi3_data4_mux[] = { - SD3_DAT0_MARK, SD3_DAT1_MARK, - SD3_DAT2_MARK, SD3_DAT3_MARK, -}; - -static const unsigned int sdhi3_data8_pins[] = { +static const unsigned int sdhi3_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), @@ -3266,7 +3249,7 @@ static const unsigned int sdhi3_data8_pins[] = { RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), }; -static const unsigned int sdhi3_data8_mux[] = { +static const unsigned int sdhi3_data_mux[] = { SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, SD3_DAT4_MARK, SD3_DAT5_MARK, @@ -3608,38 +3591,34 @@ static const unsigned int vin4_data18_a_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_a_pins = { - .data24 = { - RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), - RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), - RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), - RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, +static const unsigned int vin4_data_a_pins[] = { + RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), + RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), + RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const union vin_data vin4_data_a_mux = { - .data24 = { - VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, - VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, - VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, - VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_a_mux[] = { + VI4_DATA0_A_MARK, VI4_DATA1_A_MARK, + VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, + VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, + VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_data18_b_pins[] = { @@ -3666,38 +3645,34 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_b_pins = { - .data24 = { - RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), - RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), - RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), - RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), - RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), - RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), - }, +static const unsigned int vin4_data_b_pins[] = { + RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11), + RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22), + RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), + RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10), + RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), + RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1), }; -static const union vin_data vin4_data_b_mux = { - .data24 = { - VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, - VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, - VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, - VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_b_mux[] = { + VI4_DATA0_B_MARK, VI4_DATA1_B_MARK, + VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, + VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, + VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { @@ -3734,30 +3709,26 @@ static const unsigned int vin4_clk_mux[] = { }; /* - VIN5 ------------------------------------------------------------------- */ -static const union vin_data16 vin5_data_a_pins = { - .data16 = { - RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), - RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), - RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), - RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), - RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), - RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), - RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - }, +static const unsigned int vin5_data_a_pins[] = { + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11), + RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), }; -static const union vin_data16 vin5_data_a_mux = { - .data16 = { - VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, - VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, - VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, - VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, - VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, - VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, - VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, - VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, - }, +static const unsigned int vin5_data_a_mux[] = { + VI5_DATA0_A_MARK, VI5_DATA1_A_MARK, + VI5_DATA2_A_MARK, VI5_DATA3_A_MARK, + VI5_DATA4_A_MARK, VI5_DATA5_A_MARK, + VI5_DATA6_A_MARK, VI5_DATA7_A_MARK, + VI5_DATA8_A_MARK, VI5_DATA9_A_MARK, + VI5_DATA10_A_MARK, VI5_DATA11_A_MARK, + VI5_DATA12_A_MARK, VI5_DATA13_A_MARK, + VI5_DATA14_A_MARK, VI5_DATA15_A_MARK, }; static const unsigned int vin5_data8_b_pins[] = { @@ -3816,9 +3787,9 @@ static const unsigned int vin5_clk_b_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[253]; + struct sh_pfc_pin_group common[261]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_pin_group automotive[21]; + struct sh_pfc_pin_group automotive[22]; #endif } pinmux_groups = { .common = { @@ -3965,11 +3936,17 @@ static const struct { SH_PFC_PIN_GROUP(pwm6_a), SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_ctrl_a), @@ -4000,19 +3977,19 @@ static const struct { SH_PFC_PIN_GROUP(scif5_data_c), SH_PFC_PIN_GROUP(scif_clk_a), SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), + BUS_DATA_PIN_GROUP(sdhi0_data, 1), + BUS_DATA_PIN_GROUP(sdhi0_data, 4), SH_PFC_PIN_GROUP(sdhi0_ctrl), SH_PFC_PIN_GROUP(sdhi0_cd), SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), + BUS_DATA_PIN_GROUP(sdhi1_data, 1), + BUS_DATA_PIN_GROUP(sdhi1_data, 4), SH_PFC_PIN_GROUP(sdhi1_ctrl), SH_PFC_PIN_GROUP(sdhi1_cd), SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_data8), + BUS_DATA_PIN_GROUP(sdhi3_data, 1), + BUS_DATA_PIN_GROUP(sdhi3_data, 4), + BUS_DATA_PIN_GROUP(sdhi3_data, 8), SH_PFC_PIN_GROUP(sdhi3_ctrl), SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), @@ -4047,29 +4024,31 @@ static const struct { SH_PFC_PIN_GROUP(usb0_id), SH_PFC_PIN_GROUP(usb30), SH_PFC_PIN_GROUP(usb30_id), - VIN_DATA_PIN_GROUP(vin4_data, 8, _a), - VIN_DATA_PIN_GROUP(vin4_data, 10, _a), - VIN_DATA_PIN_GROUP(vin4_data, 12, _a), - VIN_DATA_PIN_GROUP(vin4_data, 16, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _a), + BUS_DATA_PIN_GROUP(vin4_data, 10, _a), + BUS_DATA_PIN_GROUP(vin4_data, 12, _a), + BUS_DATA_PIN_GROUP(vin4_data, 16, _a), SH_PFC_PIN_GROUP(vin4_data18_a), - VIN_DATA_PIN_GROUP(vin4_data, 20, _a), - VIN_DATA_PIN_GROUP(vin4_data, 24, _a), - VIN_DATA_PIN_GROUP(vin4_data, 8, _b), - VIN_DATA_PIN_GROUP(vin4_data, 10, _b), - VIN_DATA_PIN_GROUP(vin4_data, 12, _b), - VIN_DATA_PIN_GROUP(vin4_data, 16, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _a), + BUS_DATA_PIN_GROUP(vin4_data, 24, _a), + BUS_DATA_PIN_GROUP(vin4_data, 8, _b), + BUS_DATA_PIN_GROUP(vin4_data, 10, _b), + BUS_DATA_PIN_GROUP(vin4_data, 12, _b), + BUS_DATA_PIN_GROUP(vin4_data, 16, _b), SH_PFC_PIN_GROUP(vin4_data18_b), - VIN_DATA_PIN_GROUP(vin4_data, 20, _b), - VIN_DATA_PIN_GROUP(vin4_data, 24, _b), + BUS_DATA_PIN_GROUP(vin4_data, 20, _b), + BUS_DATA_PIN_GROUP(vin4_data, 24, _b), + SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), SH_PFC_PIN_GROUP(vin4_clk), - VIN_DATA_PIN_GROUP(vin5_data, 8, _a), - VIN_DATA_PIN_GROUP(vin5_data, 10, _a), - VIN_DATA_PIN_GROUP(vin5_data, 12, _a), - VIN_DATA_PIN_GROUP(vin5_data, 16, _a), + BUS_DATA_PIN_GROUP(vin5_data, 8, _a), + BUS_DATA_PIN_GROUP(vin5_data, 10, _a), + BUS_DATA_PIN_GROUP(vin5_data, 12, _a), + BUS_DATA_PIN_GROUP(vin5_data, 16, _a), SH_PFC_PIN_GROUP(vin5_data8_b), + SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8), SH_PFC_PIN_GROUP(vin5_sync_a), SH_PFC_PIN_GROUP(vin5_field_a), SH_PFC_PIN_GROUP(vin5_clkenb_a), @@ -4099,6 +4078,7 @@ static const struct { SH_PFC_PIN_GROUP(drif3_ctrl_b), SH_PFC_PIN_GROUP(drif3_data0_b), SH_PFC_PIN_GROUP(drif3_data1_b), + SH_PFC_PIN_GROUP(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -4289,6 +4269,12 @@ static const char * const intc_ex_groups[] = { "intc_ex_irq5", }; +#ifdef CONFIG_PINCTRL_PFC_R8A77990 +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; +#endif /* CONFIG_PINCTRL_PFC_R8A77990 */ + static const char * const msiof0_groups[] = { "msiof0_clk", "msiof0_sync", @@ -4385,6 +4371,15 @@ static const char * const qspi1_groups[] = { "qspi1_data4", }; +static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -4519,6 +4514,7 @@ static const char * const vin4_groups[] = { "vin4_data18_b", "vin4_data20_b", "vin4_data24_b", + "vin4_g8", "vin4_sync", "vin4_field", "vin4_clkenb", @@ -4531,6 +4527,7 @@ static const char * const vin5_groups[] = { "vin5_data12_a", "vin5_data16_a", "vin5_data8_b", + "vin5_high8", "vin5_sync_a", "vin5_field_a", "vin5_clkenb_a", @@ -4539,9 +4536,9 @@ static const char * const vin5_groups[] = { }; static const struct { - struct sh_pfc_function common[49]; + struct sh_pfc_function common[50]; #ifdef CONFIG_PINCTRL_PFC_R8A77990 - struct sh_pfc_function automotive[4]; + struct sh_pfc_function automotive[5]; #endif } pinmux_functions = { .common = { @@ -4578,6 +4575,7 @@ static const struct { SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(qspi0), SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -4601,6 +4599,7 @@ static const struct { SH_PFC_FUNCTION(drif1), SH_PFC_FUNCTION(drif2), SH_PFC_FUNCTION(drif3), + SH_PFC_FUNCTION(mlb_3pin), } #endif /* CONFIG_PINCTRL_PFC_R8A77990 */ }; @@ -4608,21 +4607,11 @@ static const struct { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_18 RESERVED */ GP_0_17_FN, GPSR0_17, GP_0_16_FN, GPSR0_16, GP_0_15_FN, GPSR0_15, @@ -4642,16 +4631,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_0_1_FN, GPSR0_1, GP_0_0_FN, GPSR0_0, )) }, - { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32, + GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP1_31_23 RESERVED */ GP_1_22_FN, GPSR1_22, GP_1_21_FN, GPSR1_21, GP_1_20_FN, GPSR1_20, @@ -4710,23 +4694,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_16 RESERVED */ GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, GP_3_13_FN, GPSR3_13, @@ -4744,28 +4716,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_3_1_FN, GPSR3_1, GP_3_0_FN, GPSR3_0, )) }, - { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32, + GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP4_31_11 RESERVED */ GP_4_10_FN, GPSR4_10, GP_4_9_FN, GPSR4_9, GP_4_8_FN, GPSR4_8, @@ -4778,19 +4732,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, GPSR4_1, GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, + GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_20 RESERVED */ GP_5_19_FN, GPSR5_19, GP_5_18_FN, GPSR5_18, GP_5_17_FN, GPSR5_17, @@ -4812,21 +4758,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_FN, GPSR5_1, GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32, + GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP6_31_18 RESERVED */ GP_6_17_FN, GPSR6_17, GP_6_16_FN, GPSR6_16, GP_6_15_FN, GPSR6_15, @@ -5017,11 +4953,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, + GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2), GROUP( /* RESERVED 31 */ - 0, 0, MOD_SEL0_30_29 MOD_SEL0_28 MOD_SEL0_27_26 @@ -5046,15 +4981,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_1_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, - 1, 2, 2, 2, 1, 1, 2, 1, 4), + GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1, + 1, 2, 2, 2, 1, 1, 2, 1, -4), GROUP( MOD_SEL1_31 MOD_SEL1_30 MOD_SEL1_29 MOD_SEL1_28 /* RESERVED 27 */ - 0, 0, MOD_SEL1_26 MOD_SEL1_25 MOD_SEL1_24_23_22 @@ -5070,12 +5004,44 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_7 MOD_SEL1_6_5 MOD_SEL1_4 - /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) + /* RESERVED 3, 2, 1, 0 */ )) }, { }, }; +static const struct pinmux_drive_reg pinmux_drive_regs[] = { + { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) { + { RCAR_GP_PIN(3, 0), 18, 2 }, /* SD0_CLK */ + { RCAR_GP_PIN(3, 1), 15, 2 }, /* SD0_CMD */ + { RCAR_GP_PIN(3, 2), 12, 2 }, /* SD0_DAT0 */ + { RCAR_GP_PIN(3, 3), 9, 2 }, /* SD0_DAT1 */ + { RCAR_GP_PIN(3, 4), 6, 2 }, /* SD0_DAT2 */ + { RCAR_GP_PIN(3, 5), 3, 2 }, /* SD0_DAT3 */ + { RCAR_GP_PIN(3, 6), 0, 2 }, /* SD1_CLK */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) { + { RCAR_GP_PIN(3, 7), 29, 2 }, /* SD1_CMD */ + { RCAR_GP_PIN(3, 8), 26, 2 }, /* SD1_DAT0 */ + { RCAR_GP_PIN(3, 9), 23, 2 }, /* SD1_DAT1 */ + { RCAR_GP_PIN(3, 10), 20, 2 }, /* SD1_DAT2 */ + { RCAR_GP_PIN(3, 11), 17, 2 }, /* SD1_DAT3 */ + { RCAR_GP_PIN(4, 0), 14, 2 }, /* SD3_CLK */ + { RCAR_GP_PIN(4, 1), 11, 2 }, /* SD3_CMD */ + { RCAR_GP_PIN(4, 2), 8, 2 }, /* SD3_DAT0 */ + { RCAR_GP_PIN(4, 3), 5, 2 }, /* SD3_DAT1 */ + { RCAR_GP_PIN(4, 4), 2, 2 }, /* SD3_DAT2 */ + } }, + { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) { + { RCAR_GP_PIN(4, 5), 29, 2 }, /* SD3_DAT3 */ + { RCAR_GP_PIN(4, 6), 26, 2 }, /* SD3_DAT4 */ + { RCAR_GP_PIN(4, 7), 23, 2 }, /* SD3_DAT5 */ + { RCAR_GP_PIN(4, 8), 20, 2 }, /* SD3_DAT6 */ + { RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */ + { RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */ + } }, + { }, +}; + enum ioctrl_regs { POCCTRL0, TDSELCTRL, @@ -5087,8 +5053,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -5169,8 +5134,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(1, 0), /* A0 */ [28] = SH_PFC_PIN_NONE, [29] = SH_PFC_PIN_NONE, - [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ - [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ + [30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */ + [31] = RCAR_GP_PIN(2, 24), /* RD/WR# */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ @@ -5305,63 +5270,22 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = SH_PFC_PIN_NONE, [28] = SH_PFC_PIN_NONE, [29] = SH_PFC_PIN_NONE, - [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ - [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ + [30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */ + [31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */ } }, { /* sentinel */ }, }; -static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - -static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = { +static const struct sh_pfc_soc_operations r8a77990_pfc_ops = { .pin_to_pocctrl = r8a77990_pin_to_pocctrl, - .get_bias = r8a77990_pinmux_get_bias, - .set_bias = r8a77990_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A774C0 const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .name = "r8a774c0_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5374,6 +5298,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, @@ -5385,7 +5310,7 @@ const struct sh_pfc_soc_info r8a774c0_pinmux_info = { #ifdef CONFIG_PINCTRL_PFC_R8A77990 const struct sh_pfc_soc_info r8a77990_pinmux_info = { .name = "r8a77990_pfc", - .ops = &r8a77990_pinmux_ops, + .ops = &r8a77990_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -5400,6 +5325,7 @@ const struct sh_pfc_soc_info r8a77990_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .drive_regs = pinmux_drive_regs, .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c index 4ff1b76588..06caf16c99 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -19,14 +19,24 @@ #include "sh_pfc.h" -#define CPU_ALL_GP(fn, sfx) \ - PORT_GP_9(0, fn, sfx), \ - PORT_GP_32(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_21(5, fn, sfx), \ - PORT_GP_14(6, fn, sfx) +#define CPU_ALL_GP(fn, sfx) \ + PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) /* * F_() : just information @@ -933,8 +943,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AUDIO CLOCK ------------------------------------------------------------- */ @@ -1240,31 +1259,23 @@ static const unsigned int i2c3_b_mux[] = { SCL3_B_MARK, SDA3_B_MARK, }; -/* - MMC ------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* D0 */ - RCAR_GP_PIN(3, 2), +/* - MLB+ ------------------------------------------------------------------- */ +static const unsigned int mlb_3pin_pins[] = { + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), }; -static const unsigned int mmc_data1_mux[] = { - MMC_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* D[0:3] */ - RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), - RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_D0_MARK, MMC_D1_MARK, - MMC_D2_MARK, MMC_D3_MARK, +static const unsigned int mlb_3pin_mux[] = { + MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, }; -static const unsigned int mmc_data8_pins[] = { + +/* - MMC ------------------------------------------------------------------- */ +static const unsigned int mmc_data_pins[] = { /* D[0:7] */ RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -1673,6 +1684,68 @@ static const unsigned int pwm3_c_mux[] = { PWM3_C_MARK, }; +/* - QSPI0 ------------------------------------------------------------------ */ +static const unsigned int qspi0_ctrl_pins[] = { + /* QSPI0_SPCLK, QSPI0_SSL */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), +}; +static const unsigned int qspi0_ctrl_mux[] = { + QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, +}; +/* - QSPI1 ------------------------------------------------------------------ */ +static const unsigned int qspi1_ctrl_pins[] = { + /* QSPI1_SPCLK, QSPI1_SSL */ + RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11), +}; +static const unsigned int qspi1_ctrl_mux[] = { + QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, +}; + +/* - RPC -------------------------------------------------------------------- */ +static const unsigned int rpc_clk_pins[] = { + /* Octal-SPI flash: C/SCLK */ + /* HyperFlash: CK, CK# */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6), +}; +static const unsigned int rpc_clk_mux[] = { + QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, +}; +static const unsigned int rpc_ctrl_pins[] = { + /* Octal-SPI flash: S#/CS, DQS */ + /* HyperFlash: CS#, RDS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11), +}; +static const unsigned int rpc_ctrl_mux[] = { + QSPI0_SSL_MARK, QSPI1_SSL_MARK, +}; +static const unsigned int rpc_data_pins[] = { + /* DQ[0:7] */ + RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), + RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), + RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8), + RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10), +}; +static const unsigned int rpc_data_mux[] = { + QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, + QSPI0_IO2_MARK, QSPI0_IO3_MARK, + QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, + QSPI1_IO2_MARK, QSPI1_IO3_MARK, +}; +static const unsigned int rpc_reset_pins[] = { + /* RPC_RESET# */ + RCAR_GP_PIN(6, 12), +}; +static const unsigned int rpc_reset_mux[] = { + RPC_RESET_N_MARK, +}; +static const unsigned int rpc_int_pins[] = { + /* RPC_INT# */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int rpc_int_mux[] = { + RPC_INT_N_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_a_pins[] = { /* RX, TX */ @@ -1933,37 +2006,33 @@ static const unsigned int vin4_data18_mux[] = { VI4_DATA20_MARK, VI4_DATA21_MARK, VI4_DATA22_MARK, VI4_DATA23_MARK, }; -static const union vin_data vin4_data_pins = { - .data24 = { - RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), - RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), - RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), - RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), - RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), - RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), - RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), - RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), - RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), - RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), - RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), - RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), - }, +static const unsigned int vin4_data_pins[] = { + RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), + RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), + RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), + RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), + RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), + RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), + RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), + RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), + RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), + RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), + RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), }; -static const union vin_data vin4_data_mux = { - .data24 = { - VI4_DATA0_MARK, VI4_DATA1_MARK, - VI4_DATA2_MARK, VI4_DATA3_MARK, - VI4_DATA4_MARK, VI4_DATA5_MARK, - VI4_DATA6_MARK, VI4_DATA7_MARK, - VI4_DATA8_MARK, VI4_DATA9_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA16_MARK, VI4_DATA17_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, - }, +static const unsigned int vin4_data_mux[] = { + VI4_DATA0_MARK, VI4_DATA1_MARK, + VI4_DATA2_MARK, VI4_DATA3_MARK, + VI4_DATA4_MARK, VI4_DATA5_MARK, + VI4_DATA6_MARK, VI4_DATA7_MARK, + VI4_DATA8_MARK, VI4_DATA9_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA16_MARK, VI4_DATA17_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const unsigned int vin4_sync_pins[] = { /* HSYNC#, VSYNC# */ @@ -2032,9 +2101,10 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(i2c2_b), SH_PFC_PIN_GROUP(i2c3_a), SH_PFC_PIN_GROUP(i2c3_b), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mlb_3pin), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(msiof0_clk), SH_PFC_PIN_GROUP(msiof0_sync), @@ -2079,6 +2149,18 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm3_a), SH_PFC_PIN_GROUP(pwm3_b), SH_PFC_PIN_GROUP(pwm3_c), + SH_PFC_PIN_GROUP(qspi0_ctrl), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), + SH_PFC_PIN_GROUP(qspi1_ctrl), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), + SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), + BUS_DATA_PIN_GROUP(rpc_clk, 1), + BUS_DATA_PIN_GROUP(rpc_clk, 2), + SH_PFC_PIN_GROUP(rpc_ctrl), + SH_PFC_PIN_GROUP(rpc_data), + SH_PFC_PIN_GROUP(rpc_reset), + SH_PFC_PIN_GROUP(rpc_int), SH_PFC_PIN_GROUP(scif0_data_a), SH_PFC_PIN_GROUP(scif0_clk_a), SH_PFC_PIN_GROUP(scif0_data_b), @@ -2111,13 +2193,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi4_ctrl_b), SH_PFC_PIN_GROUP(ssi4_data_b), SH_PFC_PIN_GROUP(usb0), - VIN_DATA_PIN_GROUP(vin4_data, 8), - VIN_DATA_PIN_GROUP(vin4_data, 10), - VIN_DATA_PIN_GROUP(vin4_data, 12), - VIN_DATA_PIN_GROUP(vin4_data, 16), + BUS_DATA_PIN_GROUP(vin4_data, 8), + BUS_DATA_PIN_GROUP(vin4_data, 10), + BUS_DATA_PIN_GROUP(vin4_data, 12), + BUS_DATA_PIN_GROUP(vin4_data, 16), SH_PFC_PIN_GROUP(vin4_data18), - VIN_DATA_PIN_GROUP(vin4_data, 20), - VIN_DATA_PIN_GROUP(vin4_data, 24), + BUS_DATA_PIN_GROUP(vin4_data, 20), + BUS_DATA_PIN_GROUP(vin4_data, 24), SH_PFC_PIN_GROUP(vin4_sync), SH_PFC_PIN_GROUP(vin4_field), SH_PFC_PIN_GROUP(vin4_clkenb), @@ -2193,6 +2275,10 @@ static const char * const i2c3_groups[] = { "i2c3_b", }; +static const char * const mlb_3pin_groups[] = { + "mlb_3pin", +}; + static const char * const mmc_groups[] = { "mmc_data1", "mmc_data4", @@ -2200,6 +2286,49 @@ static const char * const mmc_groups[] = { "mmc_ctrl", }; +static const char * const msiof0_groups[] = { + "msiof0_clk", + "msiof0_sync", + "msiof0_ss1", + "msiof0_ss2", + "msiof0_txd", + "msiof0_rxd", +}; + +static const char * const msiof1_groups[] = { + "msiof1_clk", + "msiof1_sync", + "msiof1_ss1", + "msiof1_ss2", + "msiof1_txd", + "msiof1_rxd", +}; + +static const char * const msiof2_groups[] = { + "msiof2_clk", + "msiof2_sync_a", + "msiof2_sync_b", + "msiof2_ss1", + "msiof2_ss2", + "msiof2_txd", + "msiof2_rxd", +}; + +static const char * const msiof3_groups[] = { + "msiof3_clk_a", + "msiof3_sync_a", + "msiof3_ss1_a", + "msiof3_ss2_a", + "msiof3_txd_a", + "msiof3_rxd_a", + "msiof3_clk_b", + "msiof3_sync_b", + "msiof3_ss1_b", + "msiof3_ss2_b", + "msiof3_txd_b", + "msiof3_rxd_b", +}; + static const char * const pwm0_groups[] = { "pwm0_a", "pwm0_b", @@ -2224,6 +2353,27 @@ static const char * const pwm3_groups[] = { "pwm3_c", }; +static const char * const qspi0_groups[] = { + "qspi0_ctrl", + "qspi0_data2", + "qspi0_data4", +}; + +static const char * const qspi1_groups[] = { + "qspi1_ctrl", + "qspi1_data2", + "qspi1_data4", +}; + +static const char * const rpc_groups[] = { + "rpc_clk1", + "rpc_clk2", + "rpc_ctrl", + "rpc_data", + "rpc_reset", + "rpc_int", +}; + static const char * const scif0_groups[] = { "scif0_data_a", "scif0_clk_a", @@ -2297,49 +2447,6 @@ static const char * const vin4_groups[] = { "vin4_clk", }; -static const char * const msiof0_groups[] = { - "msiof0_clk", - "msiof0_sync", - "msiof0_ss1", - "msiof0_ss2", - "msiof0_txd", - "msiof0_rxd", -}; - -static const char * const msiof1_groups[] = { - "msiof1_clk", - "msiof1_sync", - "msiof1_ss1", - "msiof1_ss2", - "msiof1_txd", - "msiof1_rxd", -}; - -static const char * const msiof2_groups[] = { - "msiof2_clk", - "msiof2_sync_a", - "msiof2_sync_b", - "msiof2_ss1", - "msiof2_ss2", - "msiof2_txd", - "msiof2_rxd", -}; - -static const char * const msiof3_groups[] = { - "msiof3_clk_a", - "msiof3_sync_a", - "msiof3_ss1_a", - "msiof3_ss2_a", - "msiof3_txd_a", - "msiof3_rxd_a", - "msiof3_clk_b", - "msiof3_sync_b", - "msiof3_ss1_b", - "msiof3_ss2_b", - "msiof3_txd_b", - "msiof3_rxd_b", -}; - static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb0), @@ -2353,6 +2460,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(i2c1), SH_PFC_FUNCTION(i2c2), SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(mlb_3pin), SH_PFC_FUNCTION(mmc), SH_PFC_FUNCTION(msiof0), SH_PFC_FUNCTION(msiof1), @@ -2362,6 +2470,9 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(pwm1), SH_PFC_FUNCTION(pwm2), SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(qspi0), + SH_PFC_FUNCTION(qspi1), + SH_PFC_FUNCTION(rpc), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -2377,30 +2488,10 @@ static const struct sh_pfc_function pinmux_functions[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) FN_##y #define FM(x) FN_##x - { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, + GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP0_31_9 RESERVED */ GP_0_8_FN, GPSR0_8, GP_0_7_FN, GPSR0_7, GP_0_6_FN, GPSR0_6, @@ -2479,29 +2570,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, + GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_10 RESERVED */ GP_3_9_FN, GPSR3_9, GP_3_8_FN, GPSR3_8, GP_3_7_FN, GPSR3_7, @@ -2547,18 +2619,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, GPSR4_1, GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_21 RESERVED */ GP_5_20_FN, GPSR5_20, GP_5_19_FN, GPSR5_19, GP_5_18_FN, GPSR5_18, @@ -2581,25 +2646,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_FN, GPSR5_1, GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32, + GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1), + GROUP( + /* GP6_31_14 RESERVED */ GP_6_13_FN, GPSR6_13, GP_6_12_FN, GPSR6_12, GP_6_11_FN, GPSR6_11, @@ -2750,13 +2801,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP12_7_4 IP12_3_0 )) }, - { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP( - /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32, + GROUP(-24, 4, 4), + GROUP( + /* IP13_31_8 RESERVED */ IP13_7_4 IP13_3_0 )) }, @@ -2766,11 +2814,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, - GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1, - 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1), + GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1, + 1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1), GROUP( /* RESERVED 31 */ - 0, 0, MOD_SEL0_30 MOD_SEL0_29 MOD_SEL0_28 @@ -2782,7 +2829,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_20_19 MOD_SEL0_18_17 /* RESERVED 16 */ - 0, 0, MOD_SEL0_15 MOD_SEL0_14 MOD_SEL0_13 @@ -2790,7 +2836,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_11 MOD_SEL0_10 /* RESERVED 9, 8, 7, 6 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, MOD_SEL0_5 MOD_SEL0_4 MOD_SEL0_3 @@ -2799,7 +2844,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL0_0 )) }, { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, - GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4), + GROUP(1, 1, 1, 1, 1, 1, -26), GROUP( MOD_SEL1_31 MOD_SEL1_30 @@ -2807,25 +2852,12 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { MOD_SEL1_28 MOD_SEL1_27 MOD_SEL1_26 - /* RESERVED 25, 24 */ - 0, 0, 0, 0, - /* RESERVED 23, 22, 21, 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 19, 18, 17, 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 15, 14, 13, 12 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 11, 10, 9, 8 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 7, 6, 5, 4 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 3, 2, 1, 0 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 )) + /* RESERVED 25-0 */ )) }, { }, }; -static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; @@ -2837,6 +2869,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po return bit; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */ + [ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */ + [ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */ + [ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */ + [ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */ + [ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */ + [ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */ + [ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */ + [ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */ + [ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */ + [10] = PIN_MLB_REF, /* MLB_REF */ + [11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */ + [12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */ + [13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */ + [14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */ + [15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */ + [16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */ + [17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */ + [18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */ + [19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */ + [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ + [22] = PIN_FSCLKST_N, /* FSCLKST# */ + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = PIN_TDI, /* TDI */ + [29] = PIN_TMS, /* TMS */ + [30] = PIN_TCK, /* TCK */ + [31] = PIN_TRST_N, /* TRST# */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */ + [ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */ + [ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */ + [ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */ + [ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */ + [ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */ + [ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */ + [ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */ + [ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */ + [ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */ + [10] = RCAR_GP_PIN(1, 31), /* QPOLB */ + [11] = RCAR_GP_PIN(1, 30), /* QPOLA */ + [12] = RCAR_GP_PIN(1, 29), /* DU_CDE */ + [13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */ + [14] = RCAR_GP_PIN(1, 27), /* DU_DISP */ + [15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */ + [16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */ + [17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */ + [18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */ + [19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */ + [20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */ + [21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */ + [22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */ + [23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */ + [24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */ + [25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */ + [26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */ + [27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */ + [28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */ + [29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */ + [30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */ + [31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */ + [ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */ + [ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */ + [ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */ + [ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */ + [ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */ + [ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */ + [ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */ + [ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */ + [ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */ + [10] = RCAR_GP_PIN(2, 31), /* NFCE# */ + [11] = RCAR_GP_PIN(2, 30), /* NFCLE */ + [12] = RCAR_GP_PIN(2, 29), /* NFALE */ + [13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */ + [14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */ + [15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */ + [16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */ + [17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */ + [18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */ + [19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */ + [20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */ + [21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */ + [22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */ + [23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */ + [24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */ + [25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */ + [26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */ + [27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */ + [28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */ + [29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */ + [30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */ + [31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */ + [ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */ + [ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */ + [ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */ + [ 4] = RCAR_GP_PIN(4, 27), /* TX2 */ + [ 5] = RCAR_GP_PIN(4, 26), /* RX2 */ + [ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */ + [ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */ + [ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */ + [ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */ + [10] = RCAR_GP_PIN(4, 21), /* TX0_A */ + [11] = RCAR_GP_PIN(4, 20), /* RX0_A */ + [12] = RCAR_GP_PIN(4, 19), /* SCK0_A */ + [13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */ + [14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */ + [15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */ + [16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */ + [17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */ + [18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */ + [19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */ + [20] = RCAR_GP_PIN(4, 11), /* SDA1 */ + [21] = RCAR_GP_PIN(4, 10), /* SCL1 */ + [22] = RCAR_GP_PIN(4, 9), /* SDA0 */ + [23] = RCAR_GP_PIN(4, 8), /* SCL0 */ + [24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */ + [25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */ + [26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */ + [27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */ + [28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */ + [29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */ + [30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */ + [31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */ + [ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */ + [ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */ + [ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */ + [ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */ + [ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */ + [ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */ + [10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */ + [11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */ + [12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */ + [13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */ + [14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */ + [15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */ + [16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */ + [17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */ + [18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */ + [19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */ + [20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */ + [21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */ + [22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */ + [23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */ + [24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */ + [25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */ + [26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */ + [27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */ + [28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */ + [29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */ + [30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */ + [31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */ + } }, + { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) { + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */ + [30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */ + [31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */ + } }, + { /* sentinel */ } +}; + enum ioctrl_regs { TDSELCTRL, }; @@ -2846,13 +3086,88 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = { +static const struct pinmux_bias_reg * +r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, + unsigned int *puen_bit, unsigned int *pud_bit) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); + if (!reg) + return reg; + + *puen_bit = bit; + + /* NFWE# and NFRE# use different bit positions in PUD2 */ + switch (pin) { + case RCAR_GP_PIN(3, 0): /* NFRE# */ + *pud_bit = 7; + break; + + case RCAR_GP_PIN(3, 1): /* NFWE# */ + *pud_bit = 8; + break; + + default: + *pud_bit = bit; + break; + } + + return reg; +} + +static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc, + unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int puen_bit, pud_bit; + + reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit)) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; +} + +static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + unsigned int puen_bit, pud_bit; + u32 enable, updown; + + reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); + if (!reg) + return; + + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) { + enable |= BIT(puen_bit); + + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(pud_bit); + + sh_pfc_write(pfc, reg->pud, updown); + } + sh_pfc_write(pfc, reg->puen, enable); +} + +static const struct sh_pfc_soc_operations r8a77995_pfc_ops = { .pin_to_pocctrl = r8a77995_pin_to_pocctrl, + .get_bias = r8a77995_pinmux_get_bias, + .set_bias = r8a77995_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77995_pinmux_info = { .name = "r8a77995_pfc", - .ops = &r8a77995_pinmux_ops, + .ops = &r8a77995_pfc_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2865,6 +3180,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c index d99b6e2e07..544d796444 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779a0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c @@ -392,7 +392,6 @@ #define IP3SR1_19_16 FM(GP1_28) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3SR1_23_20 FM(GP1_29) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP3SR1_27_24 FM(GP1_30) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP3SR1_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0SR2_3_0 FM(IPC_CLKIN) FM(IPC_CLKEN_IN) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -423,11 +422,8 @@ #define IP2SR2_31_28 FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(EX_WAIT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR3 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP0SR3_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_7_4 FM(CANFD0_TX) FM(FXR_TXDA_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_11_8 FM(CANFD0_RX) FM(RXDA_EXTFXR_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_15_12 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP0SR3_19_16 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_23_20 FM(CANFD2_TX) FM(TPU0TO2) FM(PWM0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_27_24 FM(CANFD2_RX) FM(TPU0TO3) FM(PWM1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP0SR3_31_28 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -438,8 +434,6 @@ #define IP1SR3_15_12 FM(CANFD5_TX) F_(0, 0) F_(0, 0) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_19_16 FM(CANFD5_RX) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR3_23_20 FM(CANFD6_TX) F_(0, 0) F_(0, 0) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP1SR3_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0SR4_3_0 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -460,14 +454,10 @@ #define IP1SR4_27_24 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR4_31_28 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR4 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP2SR4_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR4_7_4 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR4_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR4_15_12 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR4_19_16 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR4_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR4_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR4_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP0SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ #define IP0SR5_3_0 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -488,14 +478,10 @@ #define IP1SR5_27_24 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP1SR5_31_28 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IP2SR5 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ -#define IP2SR5_3_0 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR5_7_4 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR5_11_8 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR5_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP2SR5_19_16 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR5_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR5_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP2SR5_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define PINMUX_GPSR \ \ @@ -540,7 +526,7 @@ FM(IP0SR1_15_12) IP0SR1_15_12 FM(IP1SR1_15_12) IP1SR1_15_12 FM(IP2SR1_15_12) IP2 FM(IP0SR1_19_16) IP0SR1_19_16 FM(IP1SR1_19_16) IP1SR1_19_16 FM(IP2SR1_19_16) IP2SR1_19_16 FM(IP3SR1_19_16) IP3SR1_19_16 \ FM(IP0SR1_23_20) IP0SR1_23_20 FM(IP1SR1_23_20) IP1SR1_23_20 FM(IP2SR1_23_20) IP2SR1_23_20 FM(IP3SR1_23_20) IP3SR1_23_20 \ FM(IP0SR1_27_24) IP0SR1_27_24 FM(IP1SR1_27_24) IP1SR1_27_24 FM(IP2SR1_27_24) IP2SR1_27_24 FM(IP3SR1_27_24) IP3SR1_27_24 \ -FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 FM(IP3SR1_31_28) IP3SR1_31_28 \ +FM(IP0SR1_31_28) IP0SR1_31_28 FM(IP1SR1_31_28) IP1SR1_31_28 FM(IP2SR1_31_28) IP2SR1_31_28 \ \ FM(IP0SR2_3_0) IP0SR2_3_0 FM(IP1SR2_3_0) IP1SR2_3_0 FM(IP2SR2_3_0) IP2SR2_3_0 \ FM(IP0SR2_7_4) IP0SR2_7_4 FM(IP1SR2_7_4) IP1SR2_7_4 FM(IP2SR2_7_4) IP2SR2_7_4 \ @@ -551,51 +537,51 @@ FM(IP0SR2_23_20) IP0SR2_23_20 FM(IP1SR2_23_20) IP1SR2_23_20 FM(IP2SR2_23_20) IP2 FM(IP0SR2_27_24) IP0SR2_27_24 FM(IP1SR2_27_24) IP1SR2_27_24 FM(IP2SR2_27_24) IP2SR2_27_24 \ FM(IP0SR2_31_28) IP0SR2_31_28 FM(IP1SR2_31_28) IP1SR2_31_28 FM(IP2SR2_31_28) IP2SR2_31_28 \ \ -FM(IP0SR3_3_0) IP0SR3_3_0 FM(IP1SR3_3_0) IP1SR3_3_0 \ + FM(IP1SR3_3_0) IP1SR3_3_0 \ FM(IP0SR3_7_4) IP0SR3_7_4 FM(IP1SR3_7_4) IP1SR3_7_4 \ FM(IP0SR3_11_8) IP0SR3_11_8 FM(IP1SR3_11_8) IP1SR3_11_8 \ -FM(IP0SR3_15_12) IP0SR3_15_12 FM(IP1SR3_15_12) IP1SR3_15_12 \ -FM(IP0SR3_19_16) IP0SR3_19_16 FM(IP1SR3_19_16) IP1SR3_19_16 \ + FM(IP1SR3_15_12) IP1SR3_15_12 \ + FM(IP1SR3_19_16) IP1SR3_19_16 \ FM(IP0SR3_23_20) IP0SR3_23_20 FM(IP1SR3_23_20) IP1SR3_23_20 \ -FM(IP0SR3_27_24) IP0SR3_27_24 FM(IP1SR3_27_24) IP1SR3_27_24 \ -FM(IP0SR3_31_28) IP0SR3_31_28 FM(IP1SR3_31_28) IP1SR3_31_28 \ +FM(IP0SR3_27_24) IP0SR3_27_24 \ +FM(IP0SR3_31_28) IP0SR3_31_28 \ \ -FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 FM(IP2SR4_3_0) IP2SR4_3_0 \ +FM(IP0SR4_3_0) IP0SR4_3_0 FM(IP1SR4_3_0) IP1SR4_3_0 \ FM(IP0SR4_7_4) IP0SR4_7_4 FM(IP1SR4_7_4) IP1SR4_7_4 FM(IP2SR4_7_4) IP2SR4_7_4 \ FM(IP0SR4_11_8) IP0SR4_11_8 FM(IP1SR4_11_8) IP1SR4_11_8 FM(IP2SR4_11_8) IP2SR4_11_8 \ FM(IP0SR4_15_12) IP0SR4_15_12 FM(IP1SR4_15_12) IP1SR4_15_12 FM(IP2SR4_15_12) IP2SR4_15_12 \ FM(IP0SR4_19_16) IP0SR4_19_16 FM(IP1SR4_19_16) IP1SR4_19_16 FM(IP2SR4_19_16) IP2SR4_19_16 \ -FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 FM(IP2SR4_23_20) IP2SR4_23_20 \ -FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 FM(IP2SR4_27_24) IP2SR4_27_24 \ -FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 FM(IP2SR4_31_28) IP2SR4_31_28 \ +FM(IP0SR4_23_20) IP0SR4_23_20 FM(IP1SR4_23_20) IP1SR4_23_20 \ +FM(IP0SR4_27_24) IP0SR4_27_24 FM(IP1SR4_27_24) IP1SR4_27_24 \ +FM(IP0SR4_31_28) IP0SR4_31_28 FM(IP1SR4_31_28) IP1SR4_31_28 \ \ -FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 FM(IP2SR5_3_0) IP2SR5_3_0 \ +FM(IP0SR5_3_0) IP0SR5_3_0 FM(IP1SR5_3_0) IP1SR5_3_0 \ FM(IP0SR5_7_4) IP0SR5_7_4 FM(IP1SR5_7_4) IP1SR5_7_4 FM(IP2SR5_7_4) IP2SR5_7_4 \ FM(IP0SR5_11_8) IP0SR5_11_8 FM(IP1SR5_11_8) IP1SR5_11_8 FM(IP2SR5_11_8) IP2SR5_11_8 \ FM(IP0SR5_15_12) IP0SR5_15_12 FM(IP1SR5_15_12) IP1SR5_15_12 FM(IP2SR5_15_12) IP2SR5_15_12 \ FM(IP0SR5_19_16) IP0SR5_19_16 FM(IP1SR5_19_16) IP1SR5_19_16 FM(IP2SR5_19_16) IP2SR5_19_16 \ -FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 FM(IP2SR5_23_20) IP2SR5_23_20 \ -FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 FM(IP2SR5_27_24) IP2SR5_27_24 \ -FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 FM(IP2SR5_31_28) IP2SR5_31_28 +FM(IP0SR5_23_20) IP0SR5_23_20 FM(IP1SR5_23_20) IP1SR5_23_20 \ +FM(IP0SR5_27_24) IP0SR5_27_24 FM(IP1SR5_27_24) IP1SR5_27_24 \ +FM(IP0SR5_31_28) IP0SR5_31_28 FM(IP1SR5_31_28) IP1SR5_31_28 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ -#define MOD_SEL2_14_15 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) -#define MOD_SEL2_12_13 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) -#define MOD_SEL2_10_11 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) -#define MOD_SEL2_8_9 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) -#define MOD_SEL2_6_7 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) -#define MOD_SEL2_4_5 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) -#define MOD_SEL2_2_3 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) +#define MOD_SEL2_15_14 FM(SEL_I2C6_0) F_(0, 0) F_(0, 0) FM(SEL_I2C6_3) +#define MOD_SEL2_13_12 FM(SEL_I2C5_0) F_(0, 0) F_(0, 0) FM(SEL_I2C5_3) +#define MOD_SEL2_11_10 FM(SEL_I2C4_0) F_(0, 0) F_(0, 0) FM(SEL_I2C4_3) +#define MOD_SEL2_9_8 FM(SEL_I2C3_0) F_(0, 0) F_(0, 0) FM(SEL_I2C3_3) +#define MOD_SEL2_7_6 FM(SEL_I2C2_0) F_(0, 0) F_(0, 0) FM(SEL_I2C2_3) +#define MOD_SEL2_5_4 FM(SEL_I2C1_0) F_(0, 0) F_(0, 0) FM(SEL_I2C1_3) +#define MOD_SEL2_3_2 FM(SEL_I2C0_0) F_(0, 0) F_(0, 0) FM(SEL_I2C0_3) #define PINMUX_MOD_SELS \ \ -MOD_SEL2_14_15 \ -MOD_SEL2_12_13 \ -MOD_SEL2_10_11 \ -MOD_SEL2_8_9 \ -MOD_SEL2_6_7 \ -MOD_SEL2_4_5 \ -MOD_SEL2_2_3 +MOD_SEL2_15_14 \ +MOD_SEL2_13_12 \ +MOD_SEL2_11_10 \ +MOD_SEL2_9_8 \ +MOD_SEL2_7_6 \ +MOD_SEL2_5_4 \ +MOD_SEL2_3_2 #define PINMUX_PHYS \ FM(SCL0) FM(SDA0) FM(SCL1) FM(SDA1) FM(SCL2) FM(SDA2) FM(SCL3) FM(SDA3) \ @@ -632,7 +618,36 @@ enum { }; static const u16 pinmux_data[] = { +/* Using GP_2_[2-15] requires disabling I2C in MOD_SEL2 */ +#define GP_2_2_FN GP_2_2_FN, FN_SEL_I2C0_0 +#define GP_2_3_FN GP_2_3_FN, FN_SEL_I2C0_0 +#define GP_2_4_FN GP_2_4_FN, FN_SEL_I2C1_0 +#define GP_2_5_FN GP_2_5_FN, FN_SEL_I2C1_0 +#define GP_2_6_FN GP_2_6_FN, FN_SEL_I2C2_0 +#define GP_2_7_FN GP_2_7_FN, FN_SEL_I2C2_0 +#define GP_2_8_FN GP_2_8_FN, FN_SEL_I2C3_0 +#define GP_2_9_FN GP_2_9_FN, FN_SEL_I2C3_0 +#define GP_2_10_FN GP_2_10_FN, FN_SEL_I2C4_0 +#define GP_2_11_FN GP_2_11_FN, FN_SEL_I2C4_0 +#define GP_2_12_FN GP_2_12_FN, FN_SEL_I2C5_0 +#define GP_2_13_FN GP_2_13_FN, FN_SEL_I2C5_0 +#define GP_2_14_FN GP_2_14_FN, FN_SEL_I2C6_0 +#define GP_2_15_FN GP_2_15_FN, FN_SEL_I2C6_0 PINMUX_DATA_GP_ALL(), +#undef GP_2_2_FN +#undef GP_2_3_FN +#undef GP_2_4_FN +#undef GP_2_5_FN +#undef GP_2_6_FN +#undef GP_2_7_FN +#undef GP_2_8_FN +#undef GP_2_9_FN +#undef GP_2_10_FN +#undef GP_2_11_FN +#undef GP_2_12_FN +#undef GP_2_13_FN +#undef GP_2_14_FN +#undef GP_2_15_FN PINMUX_SINGLE(MMC_D7), PINMUX_SINGLE(MMC_D6), @@ -2012,30 +2027,14 @@ static const unsigned int intc_ex_irq5_mux[] = { }; /* - MMC -------------------------------------------------------------------- */ -static const unsigned int mmc_data1_pins[] = { - /* MMC_SD_D0 */ - RCAR_GP_PIN(0, 19), -}; -static const unsigned int mmc_data1_mux[] = { - MMC_SD_D0_MARK, -}; -static const unsigned int mmc_data4_pins[] = { - /* MMC_SD_D[0:3] */ - RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), - RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), -}; -static const unsigned int mmc_data4_mux[] = { - MMC_SD_D0_MARK, MMC_SD_D1_MARK, - MMC_SD_D2_MARK, MMC_SD_D3_MARK, -}; -static const unsigned int mmc_data8_pins[] = { +static const unsigned int mmc_data_pins[] = { /* MMC_SD_D[0:3], MMC_D[4:7] */ RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27), }; -static const unsigned int mmc_data8_mux[] = { +static const unsigned int mmc_data_mux[] = { MMC_SD_D0_MARK, MMC_SD_D1_MARK, MMC_SD_D2_MARK, MMC_SD_D3_MARK, MMC_D4_MARK, MMC_D5_MARK, @@ -2387,19 +2386,12 @@ static const unsigned int qspi0_ctrl_pins[] = { static const unsigned int qspi0_ctrl_mux[] = { QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, }; -static const unsigned int qspi0_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), -}; -static const unsigned int qspi0_data2_mux[] = { - QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, -}; -static const unsigned int qspi0_data4_pins[] = { +static const unsigned int qspi0_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), }; -static const unsigned int qspi0_data4_mux[] = { +static const unsigned int qspi0_data_mux[] = { QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_IO2_MARK, QSPI0_IO3_MARK }; @@ -2412,19 +2404,12 @@ static const unsigned int qspi1_ctrl_pins[] = { static const unsigned int qspi1_ctrl_mux[] = { QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, }; -static const unsigned int qspi1_data2_pins[] = { - /* MOSI_IO0, MISO_IO1 */ - RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), -}; -static const unsigned int qspi1_data2_mux[] = { - QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, -}; -static const unsigned int qspi1_data4_pins[] = { +static const unsigned int qspi1_data_pins[] = { /* MOSI_IO0, MISO_IO1, IO2, IO3 */ RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), }; -static const unsigned int qspi1_data4_mux[] = { +static const unsigned int qspi1_data_mux[] = { QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_IO2_MARK, QSPI1_IO3_MARK }; @@ -2718,9 +2703,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(intc_ex_irq4), SH_PFC_PIN_GROUP(intc_ex_irq5), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), + BUS_DATA_PIN_GROUP(mmc_data, 1), + BUS_DATA_PIN_GROUP(mmc_data, 4), + BUS_DATA_PIN_GROUP(mmc_data, 8), SH_PFC_PIN_GROUP(mmc_ctrl), SH_PFC_PIN_GROUP(mmc_cd), SH_PFC_PIN_GROUP(mmc_wp), @@ -2770,11 +2755,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(qspi0_ctrl), - SH_PFC_PIN_GROUP(qspi0_data2), - SH_PFC_PIN_GROUP(qspi0_data4), + BUS_DATA_PIN_GROUP(qspi0_data, 2), + BUS_DATA_PIN_GROUP(qspi0_data, 4), SH_PFC_PIN_GROUP(qspi1_ctrl), - SH_PFC_PIN_GROUP(qspi1_data2), - SH_PFC_PIN_GROUP(qspi1_data4), + BUS_DATA_PIN_GROUP(qspi1_data, 2), + BUS_DATA_PIN_GROUP(qspi1_data, 4), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), @@ -3256,14 +3241,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_1_1_FN, GPSR1_1, GP_1_0_FN, GPSR1_0, )) }, - { PINMUX_CFG_REG("GPSR2", 0xe6050840, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR2", 0xe6050840, 32, + GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP2_31_25 RESERVED */ GP_2_24_FN, GPSR2_24, GP_2_23_FN, GPSR2_23, GP_2_22_FN, GPSR2_22, @@ -3290,22 +3272,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_2_1_FN, GPSR2_1, GP_2_0_FN, GPSR2_0, )) }, - { PINMUX_CFG_REG("GPSR3", 0xe6058840, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR3", 0xe6058840, 32, + GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1), + GROUP( + /* GP3_31_17 RESERVED */ GP_3_16_FN, GPSR3_16, GP_3_15_FN, GPSR3_15, GP_3_14_FN, GPSR3_14, @@ -3358,18 +3329,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_4_1_FN, GPSR4_1, GP_4_0_FN, GPSR4_0, )) }, - { PINMUX_CFG_REG("GPSR5", 0xe6060840, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060840, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP5_31_21 RESERVED */ GP_5_20_FN, GPSR5_20, GP_5_19_FN, GPSR5_19, GP_5_18_FN, GPSR5_18, @@ -3392,18 +3356,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_5_1_FN, GPSR5_1, GP_5_0_FN, GPSR5_0, )) }, - { PINMUX_CFG_REG("GPSR6", 0xe6068040, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR6", 0xe6068040, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP6_31_21 RESERVED */ GP_6_20_FN, GPSR6_20, GP_6_19_FN, GPSR6_19, GP_6_18_FN, GPSR6_18, @@ -3426,18 +3383,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_6_1_FN, GPSR6_1, GP_6_0_FN, GPSR6_0, )) }, - { PINMUX_CFG_REG("GPSR7", 0xe6068840, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR7", 0xe6068840, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP7_31_21 RESERVED */ GP_7_20_FN, GPSR7_20, GP_7_19_FN, GPSR7_19, GP_7_18_FN, GPSR7_18, @@ -3460,18 +3410,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_7_1_FN, GPSR7_1, GP_7_0_FN, GPSR7_0, )) }, - { PINMUX_CFG_REG("GPSR8", 0xe6069040, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR8", 0xe6069040, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP8_31_21 RESERVED */ GP_8_20_FN, GPSR8_20, GP_8_19_FN, GPSR8_19, GP_8_18_FN, GPSR8_18, @@ -3494,18 +3437,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { GP_8_1_FN, GPSR8_1, GP_8_0_FN, GPSR8_0, )) }, - { PINMUX_CFG_REG("GPSR9", 0xe6069840, 32, 1, GROUP( - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, - 0, 0, + { PINMUX_CFG_REG_VAR("GPSR9", 0xe6069840, 32, + GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), + GROUP( + /* GP9_31_21 RESERVED */ GP_9_20_FN, GPSR9_20, GP_9_19_FN, GPSR9_19, GP_9_18_FN, GPSR9_18, @@ -3563,8 +3499,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2SR1_7_4 IP2SR1_3_0)) }, - { PINMUX_CFG_REG("IP3SR1", 0xe605006c, 32, 4, GROUP( - IP3SR1_31_28 + { PINMUX_CFG_REG_VAR("IP3SR1", 0xe605006c, 32, + GROUP(-4, 4, 4, 4, 4, 4, 4, 4), + GROUP( + /* IP3SR1_31_28 RESERVED */ IP3SR1_27_24 IP3SR1_23_20 IP3SR1_19_16 @@ -3603,19 +3541,21 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP2SR2_7_4 IP2SR2_3_0)) }, - { PINMUX_CFG_REG("IP0SR3", 0xe6058860, 32, 4, GROUP( + { PINMUX_CFG_REG_VAR("IP0SR3", 0xe6058860, 32, + GROUP(4, 4, 4, -8, 4, 4, -4), + GROUP( IP0SR3_31_28 IP0SR3_27_24 IP0SR3_23_20 - IP0SR3_19_16 - IP0SR3_15_12 + /* IP0SR3_19_12 RESERVED */ IP0SR3_11_8 IP0SR3_7_4 - IP0SR3_3_0)) + /* IP0SR3_3_0 RESERVED */ )) }, - { PINMUX_CFG_REG("IP1SR3", 0xe6058864, 32, 4, GROUP( - IP1SR3_31_28 - IP1SR3_27_24 + { PINMUX_CFG_REG_VAR("IP1SR3", 0xe6058864, 32, + GROUP(-8, 4, 4, 4, 4, 4, 4), + GROUP( + /* IP1SR3_31_24 RESERVED */ IP1SR3_23_20 IP1SR3_19_16 IP1SR3_15_12 @@ -3643,15 +3583,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1SR4_7_4 IP1SR4_3_0)) }, - { PINMUX_CFG_REG("IP2SR4", 0xe6060068, 32, 4, GROUP( - IP2SR4_31_28 - IP2SR4_27_24 - IP2SR4_23_20 + { PINMUX_CFG_REG_VAR("IP2SR4", 0xe6060068, 32, + GROUP(-12, 4, 4, 4, 4, -4), + GROUP( + /* IP2SR4_31_20 RESERVED */ IP2SR4_19_16 IP2SR4_15_12 IP2SR4_11_8 IP2SR4_7_4 - IP2SR4_3_0)) + /* IP2SR4_3_0 RESERVED */ )) }, { PINMUX_CFG_REG("IP0SR5", 0xe6060860, 32, 4, GROUP( IP0SR5_31_28 @@ -3673,15 +3613,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { IP1SR5_7_4 IP1SR5_3_0)) }, - { PINMUX_CFG_REG("IP2SR5", 0xe6060868, 32, 4, GROUP( - IP2SR5_31_28 - IP2SR5_27_24 - IP2SR5_23_20 + { PINMUX_CFG_REG_VAR("IP2SR5", 0xe6060868, 32, + GROUP(-12, 4, 4, 4, 4, -4), + GROUP( + /* IP2SR5_31_20 RESERVED */ IP2SR5_19_16 IP2SR5_15_12 IP2SR5_11_8 IP2SR5_7_4 - IP2SR5_3_0)) + /* IP2SR5_3_0 RESERVED */ )) }, #undef F_ #undef FM @@ -3689,25 +3629,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { #define F_(x, y) x, #define FM(x) FN_##x, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6050900, 32, - GROUP(4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 1, 1), + GROUP(-16, 2, 2, 2, 2, 2, 2, 2, -2), GROUP( - /* RESERVED 31, 30, 29, 28 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 27, 26, 25, 24 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 23, 22, 21, 20 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /* RESERVED 19, 18, 17, 16 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - MOD_SEL2_14_15 - MOD_SEL2_12_13 - MOD_SEL2_10_11 - MOD_SEL2_8_9 - MOD_SEL2_6_7 - MOD_SEL2_4_5 - MOD_SEL2_2_3 - 0, 0, - 0, 0, )) + /* RESERVED 31-16 */ + MOD_SEL2_15_14 + MOD_SEL2_13_12 + MOD_SEL2_11_10 + MOD_SEL2_9_8 + MOD_SEL2_7_6 + MOD_SEL2_5_4 + MOD_SEL2_3_2 + /* RESERVED 1-0 */ )) }, { }, }; @@ -3838,7 +3770,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */ { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */ { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */ - { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX*/ + { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */ { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */ } }, { PINMUX_DRIVE_REG("DRV2CTRL3", 0xe6058888) { @@ -4044,8 +3976,7 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a779a0_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, - u32 *pocctrl) +static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) { int bit = pin & 0x1f; @@ -4308,7 +4239,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */ [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */ [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */ - [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC*/ + [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */ [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */ [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */ [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */ @@ -4432,56 +4363,15 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { { /* sentinel */ }, }; -static unsigned int r8a779a0_pinmux_get_bias(struct sh_pfc *pfc, - unsigned int pin) -{ - const struct pinmux_bias_reg *reg; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return PIN_CONFIG_BIAS_DISABLE; - - if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) - return PIN_CONFIG_BIAS_DISABLE; - else if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) - return PIN_CONFIG_BIAS_PULL_UP; - else - return PIN_CONFIG_BIAS_PULL_DOWN; -} - -static void r8a779a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, - unsigned int bias) -{ - const struct pinmux_bias_reg *reg; - u32 enable, updown; - unsigned int bit; - - reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit); - if (!reg) - return; - - enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); - if (bias != PIN_CONFIG_BIAS_DISABLE) - enable |= BIT(bit); - - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); - if (bias == PIN_CONFIG_BIAS_PULL_UP) - updown |= BIT(bit); - - sh_pfc_write(pfc, reg->pud, updown); - sh_pfc_write(pfc, reg->puen, enable); -} - -static const struct sh_pfc_soc_operations pinmux_ops = { +static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = { .pin_to_pocctrl = r8a779a0_pin_to_pocctrl, - .get_bias = r8a779a0_pinmux_get_bias, - .set_bias = r8a779a0_pinmux_set_bias, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a779a0_pinmux_info = { .name = "r8a779a0_pfc", - .ops = &pinmux_ops, + .ops = &r8a779a0_pfc_ops, .unlock_reg = 0x1ff, /* PMMRn mask */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c index 490d34e56b..8f7f9a74b4 100644 --- a/drivers/pinctrl/renesas/pfc.c +++ b/drivers/pinctrl/renesas/pfc.c @@ -31,7 +31,8 @@ enum sh_pfc_model { SH_PFC_R8A7793, SH_PFC_R8A7794, SH_PFC_R8A7795, - SH_PFC_R8A7796, + SH_PFC_R8A77960, + SH_PFC_R8A77961, SH_PFC_R8A774A1, SH_PFC_R8A774B1, SH_PFC_R8A774C0, @@ -171,7 +172,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, *maskp = (1 << crp->var_field_width[in_pos]) - 1; *posp = crp->reg_width; for (k = 0; k <= in_pos; k++) - *posp -= crp->var_field_width[k]; + *posp -= abs(crp->var_field_width[k]); } } @@ -219,14 +220,17 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, if (!r_width) break; - for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { + for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) { u32 ncomb; u32 n; - if (f_width) + if (f_width) { curr_width = f_width; - else - curr_width = config_reg->var_field_width[m]; + } else { + curr_width = abs(config_reg->var_field_width[m]); + if (config_reg->var_field_width[m] < 0) + continue; + } ncomb = 1 << curr_width; for (n = 0; n < ncomb; n++) { @@ -238,7 +242,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, } } pos += ncomb; - m++; } k++; } @@ -350,16 +353,16 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) } const struct pinmux_bias_reg * -sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, - unsigned int *bit) +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, + unsigned int *bit) { unsigned int i, j; - for (i = 0; pfc->info->bias_regs[i].puen; i++) { - for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) { - if (pfc->info->bias_regs[i].pins[j] == pin) { + for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) { + for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) { + if (info->bias_regs[i].pins[j] == pin) { *bit = j; - return &pfc->info->bias_regs[i]; + return &info->bias_regs[i]; } } } @@ -369,6 +372,64 @@ sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, return NULL; } +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) +{ + const struct pinmux_bias_reg *reg; + unsigned int bit; + + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); + if (!reg) + return PIN_CONFIG_BIAS_DISABLE; + + if (reg->puen) { + if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit))) + return PIN_CONFIG_BIAS_DISABLE; + else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit))) + return PIN_CONFIG_BIAS_PULL_UP; + else + return PIN_CONFIG_BIAS_PULL_DOWN; + } else { + if (sh_pfc_read(pfc, reg->pud) & BIT(bit)) + return PIN_CONFIG_BIAS_PULL_DOWN; + else + return PIN_CONFIG_BIAS_DISABLE; + } +} + +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias) +{ + const struct pinmux_bias_reg *reg; + u32 enable, updown; + unsigned int bit; + + reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); + if (!reg) + return; + + if (reg->puen) { + enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); + if (bias != PIN_CONFIG_BIAS_DISABLE) { + enable |= BIT(bit); + + if (reg->pud) { + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_UP) + updown |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, updown); + } + } + sh_pfc_write(pfc, reg->puen, enable); + } else { + enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); + if (bias == PIN_CONFIG_BIAS_PULL_DOWN) + enable |= BIT(bit); + + sh_pfc_write(pfc, reg->pud, enable); + } +} + static int sh_pfc_init_ranges(struct sh_pfc *pfc) { struct sh_pfc_pin_range *range; @@ -775,7 +836,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin, if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) return -ENOTSUPP; - bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr); + bit = pfc->info->ops->pin_to_pocctrl(_pin, &addr); if (bit < 0) { printf("invalid pin %#x", _pin); return bit; @@ -912,13 +973,17 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev) if (model == SH_PFC_R8A7794) priv->pfc.info = &r8a7794_pinmux_info; #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 if (model == SH_PFC_R8A7795) - priv->pfc.info = &r8a7795_pinmux_info; + priv->pfc.info = &r8a77951_pinmux_info; +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A77960 + if (model == SH_PFC_R8A77960) + priv->pfc.info = &r8a77960_pinmux_info; #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7796 - if (model == SH_PFC_R8A7796) - priv->pfc.info = &r8a7796_pinmux_info; +#ifdef CONFIG_PINCTRL_PFC_R8A77961 + if (model == SH_PFC_R8A77961) + priv->pfc.info = &r8a77961_pinmux_info; #endif #ifdef CONFIG_PINCTRL_PFC_R8A774A1 if (model == SH_PFC_R8A774A1) @@ -999,16 +1064,22 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = { .data = SH_PFC_R8A7794, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7795 +#ifdef CONFIG_PINCTRL_PFC_R8A77951 { .compatible = "renesas,pfc-r8a7795", .data = SH_PFC_R8A7795, }, #endif -#ifdef CONFIG_PINCTRL_PFC_R8A7796 +#ifdef CONFIG_PINCTRL_PFC_R8A77960 { .compatible = "renesas,pfc-r8a7796", - .data = SH_PFC_R8A7796, + .data = SH_PFC_R8A77960, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A77961 + { + .compatible = "renesas,pfc-r8a77961", + .data = SH_PFC_R8A77961, }, #endif #ifdef CONFIG_PINCTRL_PFC_R8A774A1 diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index c94757b9a2..59d447ead5 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -46,15 +46,34 @@ struct sh_pfc_pin { u16 enum_id; }; -#define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ - { \ - .name = #alias, \ - .pins = n##_pins, \ - .mux = n##_mux, \ - .nr_pins = ARRAY_SIZE(n##_pins) + \ - BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ - } -#define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) +#define SH_PFC_PIN_GROUP_ALIAS(alias, _name) { \ + .name = #alias, \ + .pins = _name##_pins, \ + .mux = _name##_mux, \ + .nr_pins = ARRAY_SIZE(_name##_pins) + \ + BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \ +} +#define SH_PFC_PIN_GROUP(name) SH_PFC_PIN_GROUP_ALIAS(name, name) + +/* + * Define a pin group referring to a subset of an array of pins. + */ +#define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) { \ + .name = #_name, \ + .pins = data##_pins + first, \ + .mux = data##_mux + first, \ + .nr_pins = n + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) + \ + BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)), \ +} + +/* + * Define a pin group for the data pins of a resizable bus. + * An optional 'suffix' argument is accepted, to be used when the same group + * can appear on a different set of pins. + */ +#define BUS_DATA_PIN_GROUP(base, n, ...) \ + SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n) struct sh_pfc_pin_group { const char *name; @@ -63,49 +82,11 @@ struct sh_pfc_pin_group { unsigned int nr_pins; }; -/* - * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. - * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups - * in this case. It accepts an optional 'version' argument used when the - * same group can appear on a different set of pins. - */ -#define VIN_DATA_PIN_GROUP(n, s, ...) \ - { \ - .name = #n#s#__VA_ARGS__, \ - .pins = n##__VA_ARGS__##_pins.data##s, \ - .mux = n##__VA_ARGS__##_mux.data##s, \ - .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ - } - -union vin_data12 { - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data16 { - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; -}; - -union vin_data { - unsigned int data24[24]; - unsigned int data20[20]; - unsigned int data16[16]; - unsigned int data12[12]; - unsigned int data10[10]; - unsigned int data8[8]; - unsigned int data4[4]; -}; - -#define SH_PFC_FUNCTION(n) \ - { \ - .name = #n, \ - .groups = n##_groups, \ - .nr_groups = ARRAY_SIZE(n##_groups), \ - } +#define SH_PFC_FUNCTION(n) { \ + .name = #n, \ + .groups = n##_groups, \ + .nr_groups = ARRAY_SIZE(n##_groups), \ +} struct sh_pfc_function { const char *name; @@ -128,7 +109,7 @@ struct pinmux_cfg_reg { #define SET_NR_ENUM_IDS(n) #endif const u16 *enum_ids; - const u8 *var_field_width; + const s8 *var_field_width; }; #define GROUP(...) __VA_ARGS__ @@ -148,9 +129,8 @@ struct pinmux_cfg_reg { .reg = r, .reg_width = r_width, \ .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ - (r_width / f_width) * (1 << f_width)), \ - .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ - { ids } + (r_width / f_width) << f_width), \ + .enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids } /* * Describe a config register consisting of several fields of different widths @@ -159,14 +139,15 @@ struct pinmux_cfg_reg { * - r_width: Width of the register (in bits) * - f_widths: List of widths of the register fields (in bits), from left * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. - * - ids: For each register field (from left to right, i.e. MSB to LSB), - * 2^f_widths[i] enum IDs must be specified, one for each possible - * combination of the register field bit values, all wrapped using - * the GROUP() macro. + * Reserved fields are indicated by negating the field width. + * - ids: For each non-reserved register field (from left to right, i.e. MSB + * to LSB), 2^f_widths[i] enum IDs must be specified, one for each + * possible combination of the register field bit values, all wrapped + * using the GROUP() macro. */ #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ .reg = r, .reg_width = r_width, \ - .var_field_width = (const u8 []) { f_widths, 0 }, \ + .var_field_width = (const s8 []) { f_widths, 0 }, \ SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ .enum_ids = (const u16 []) { ids } @@ -178,16 +159,16 @@ struct pinmux_drive_reg_field { struct pinmux_drive_reg { u32 reg; - const struct pinmux_drive_reg_field fields[8]; + const struct pinmux_drive_reg_field fields[10]; }; #define PINMUX_DRIVE_REG(name, r) \ .reg = r, \ .fields = -struct pinmux_bias_reg { +struct pinmux_bias_reg { /* At least one of puen/pud must exist */ u32 puen; /* Pull-enable or pull-up control register */ - u32 pud; /* Pull-up/down control register (optional) */ + u32 pud; /* Pull-up/down or pull-down control register */ const u16 pins[32]; }; @@ -228,8 +209,9 @@ struct pinmux_irq { * Describe the mapping from GPIOs to a single IRQ * - ids...: List of GPIOs that are mapped to the same IRQ */ -#define PINMUX_IRQ(ids...) \ - { .gpios = (const short []) { ids, -1 } } +#define PINMUX_IRQ(ids...) { \ + .gpios = (const short []) { ids, -1 } \ +} struct pinmux_range { u16 begin; @@ -264,7 +246,8 @@ struct sh_pfc_soc_operations { unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, unsigned int bias); - int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); + int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl); + int (*pin_to_portcr)(unsigned int pin); }; struct sh_pfc_soc_info { @@ -291,35 +274,56 @@ struct sh_pfc_soc_info { const u16 *pinmux_data; unsigned int pinmux_data_size; - const struct pinmux_irq *gpio_irq; - unsigned int gpio_irq_size; - u32 unlock_reg; /* can be literal address or mask */ }; u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); -const struct pinmux_bias_reg * -sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, - unsigned int *bit); +extern const struct sh_pfc_soc_info emev2_pinmux_info; +extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; +extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7742_pinmux_info; +extern const struct sh_pfc_soc_info r8a7743_pinmux_info; +extern const struct sh_pfc_soc_info r8a7744_pinmux_info; +extern const struct sh_pfc_soc_info r8a7745_pinmux_info; +extern const struct sh_pfc_soc_info r8a77470_pinmux_info; extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; +extern const struct sh_pfc_soc_info r8a7778_pinmux_info; +extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a7795_pinmux_info; -extern const struct sh_pfc_soc_info r8a7796_pinmux_info; +extern const struct sh_pfc_soc_info r8a77950_pinmux_info; +extern const struct sh_pfc_soc_info r8a77951_pinmux_info; +extern const struct sh_pfc_soc_info r8a77960_pinmux_info; +extern const struct sh_pfc_soc_info r8a77961_pinmux_info; extern const struct sh_pfc_soc_info r8a77965_pinmux_info; extern const struct sh_pfc_soc_info r8a77970_pinmux_info; extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; +extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; +extern const struct sh_pfc_soc_info r8a779g0_pinmux_info; +extern const struct sh_pfc_soc_info sh7203_pinmux_info; +extern const struct sh_pfc_soc_info sh7264_pinmux_info; +extern const struct sh_pfc_soc_info sh7269_pinmux_info; +extern const struct sh_pfc_soc_info sh73a0_pinmux_info; +extern const struct sh_pfc_soc_info sh7720_pinmux_info; +extern const struct sh_pfc_soc_info sh7722_pinmux_info; +extern const struct sh_pfc_soc_info sh7723_pinmux_info; +extern const struct sh_pfc_soc_info sh7724_pinmux_info; +extern const struct sh_pfc_soc_info sh7734_pinmux_info; +extern const struct sh_pfc_soc_info sh7757_pinmux_info; +extern const struct sh_pfc_soc_info sh7785_pinmux_info; +extern const struct sh_pfc_soc_info sh7786_pinmux_info; +extern const struct sh_pfc_soc_info shx3_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists @@ -444,9 +448,13 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) -#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_7(bank, fn, sfx, cfg) \ PORT_GP_CFG_6(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 6, fn, sfx, cfg) +#define PORT_GP_7(bank, fn, sfx) PORT_GP_CFG_7(bank, fn, sfx, 0) + +#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ + PORT_GP_CFG_7(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) @@ -470,9 +478,13 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) -#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_13(bank, fn, sfx, cfg) \ PORT_GP_CFG_12(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 12, fn, sfx, cfg) +#define PORT_GP_13(bank, fn, sfx) PORT_GP_CFG_13(bank, fn, sfx, 0) + +#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ + PORT_GP_CFG_13(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) @@ -496,9 +508,13 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) -#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ +#define PORT_GP_CFG_19(bank, fn, sfx, cfg) \ PORT_GP_CFG_18(bank, fn, sfx, cfg), \ - PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ + PORT_GP_CFG_1(bank, 18, fn, sfx, cfg) +#define PORT_GP_19(bank, fn, sfx) PORT_GP_CFG_19(bank, fn, sfx, 0) + +#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ + PORT_GP_CFG_19(bank, fn, sfx, cfg), \ PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) @@ -585,13 +601,12 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ - { \ - .pin = (bank * 32) + _pin, \ - .name = __stringify(_name), \ - .enum_id = _name##_DATA, \ - .configs = cfg, \ - } +#define _GP_GPIO(bank, _pin, _name, sfx, cfg) { \ + .pin = (bank * 32) + _pin, \ + .name = __stringify(_name), \ + .enum_id = _name##_DATA, \ + .configs = cfg, \ +} #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ @@ -649,13 +664,12 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; } /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ -#define SH_PFC_PIN_CFG(_pin, cfgs) \ - { \ - .pin = _pin, \ - .name = __stringify(PORT##_pin), \ - .enum_id = PORT##_pin##_DATA, \ - .configs = cfgs, \ - } +#define SH_PFC_PIN_CFG(_pin, cfgs) { \ + .pin = _pin, \ + .name = __stringify(PORT##_pin), \ + .enum_id = PORT##_pin##_DATA, \ + .configs = cfgs, \ +} /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, * PORT_name_OUT, PORT_name_IN marks @@ -704,40 +718,44 @@ extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ -#define _NOGP_PINMUX(_pin, _name, cfg) \ - { \ - .pin = PIN_##_pin, \ - .name = "PIN_" _name, \ - .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ - } +#define _NOGP_PINMUX(_pin, _name, cfg) { \ + .pin = PIN_##_pin, \ + .name = "PIN_" _name, \ + .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ +} #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) /* * PORTnCR helper macro for SH-Mobile/R-Mobile */ -#define PORTCR(nr, reg) \ - { \ - PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ - GROUP(2, 2, 1, 3), \ - GROUP( \ - /* PULMD[1:0], handled by .set_bias() */ \ - 0, 0, 0, 0, \ - /* IE and OE */ \ - 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ - /* SEC, not supported */ \ - 0, 0, \ - /* PTMD[2:0] */ \ - PORT##nr##_FN0, PORT##nr##_FN1, \ - PORT##nr##_FN2, PORT##nr##_FN3, \ - PORT##nr##_FN4, PORT##nr##_FN5, \ - PORT##nr##_FN6, PORT##nr##_FN7 \ - )) \ - } +#define PORTCR(nr, reg) { \ + PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \ + GROUP( \ + /* PULMD[1:0], handled by .set_bias() */ \ + /* IE and OE */ \ + 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ + /* SEC, not supported */ \ + /* PTMD[2:0] */ \ + PORT##nr##_FN0, PORT##nr##_FN1, \ + PORT##nr##_FN2, PORT##nr##_FN3, \ + PORT##nr##_FN4, PORT##nr##_FN5, \ + PORT##nr##_FN6, PORT##nr##_FN7 \ + )) \ +} /* * GPIO number helper macro for R-Car */ #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) -#include <linux/bug.h> +/* + * Bias helpers + */ +const struct pinmux_bias_reg * +rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin, + unsigned int *bit); +unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin); +void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, + unsigned int bias); + #endif /* __SH_PFC_H */ diff --git a/drivers/power/Makefile b/drivers/power/Makefile index f805027784..ba64b2c593 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -4,10 +4,7 @@ # Tom Rix <Tom.Rix at windriver.com> obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += acpi_pmc/ -obj-y += battery/ obj-$(CONFIG_$(SPL_TPL_)POWER_DOMAIN) += domain/ -obj-y += fuel_gauge/ -obj-y += mfd/ obj-y += pmic/ obj-y += regulator/ @@ -18,7 +15,6 @@ obj-$(CONFIG_AXP305_POWER) += axp305.o obj-$(CONFIG_AXP809_POWER) += axp809.o obj-$(CONFIG_AXP818_POWER) += axp818.o obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o -obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o obj-$(CONFIG_SY8106A_POWER) += sy8106a.o obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o obj-$(CONFIG_TWL4030_POWER) += twl4030.o diff --git a/drivers/power/battery/Makefile b/drivers/power/battery/Makefile deleted file mode 100644 index 370923a6ed..0000000000 --- a/drivers/power/battery/Makefile +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> - -obj-$(CONFIG_POWER_BATTERY_TRATS) += bat_trats.o -obj-$(CONFIG_POWER_BATTERY_TRATS2) += bat_trats2.o diff --git a/drivers/power/battery/bat_trats.c b/drivers/power/battery/bat_trats.c deleted file mode 100644 index 54b2bf91e5..0000000000 --- a/drivers/power/battery/bat_trats.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <console.h> -#include <log.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max8997_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - struct battery *battery = p_bat->bat; - int k; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -1; - - for (k = 0; bat->chrg->chrg_bat_present(p_bat->chrg) && - bat->chrg->chrg_type(p_bat->muic) && - battery->state_of_chrg < 100; k++) { - udelay(2000000); - if (!(k % 5)) - puts("."); - bat->fg->fg_battery_update(p_bat->fg, bat); - - if (k == 200) { - debug(" %d [V]", battery->voltage_uV); - puts("\n"); - k = 0; - } - - if (ctrlc()) { - printf("\nCharging disabled on request.\n"); - goto exit; - } - } - exit: - bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_DISABLE, 0); - - return 0; -} - -static int power_battery_init_trats(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats; - return 0; -} diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c deleted file mode 100644 index 1172970d1e..0000000000 --- a/drivers/power/battery/bat_trats2.c +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/battery.h> -#include <power/max77693_pmic.h> -#include <errno.h> - -static struct battery battery_trats; - -static int power_battery_charge(struct pmic *bat) -{ - struct power_battery *p_bat = bat->pbat; - - if (bat->chrg->chrg_state(p_bat->chrg, PMIC_CHARGER_ENABLE, 450)) - return -EINVAL; - - return 0; -} - -static int power_battery_init_trats2(struct pmic *bat_, - struct pmic *fg_, - struct pmic *chrg_, - struct pmic *muic_) -{ - bat_->pbat->fg = fg_; - bat_->pbat->chrg = chrg_; - bat_->pbat->muic = muic_; - - bat_->fg = fg_->fg; - bat_->chrg = chrg_->chrg; - bat_->chrg->chrg_type = muic_->chrg->chrg_type; - return 0; -} - -static struct power_battery power_bat_trats2 = { - .bat = &battery_trats, - .battery_init = power_battery_init_trats2, - .battery_charge = power_battery_charge, -}; - -int power_bat_init(unsigned char bus) -{ - static const char name[] = "BAT_TRATS2"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board BAT init\n"); - - p->interface = PMIC_NONE; - p->name = name; - p->bus = bus; - - p->pbat = &power_bat_trats2; - return 0; -} diff --git a/drivers/power/ftpmu010.c b/drivers/power/ftpmu010.c deleted file mode 100644 index 9a48b36554..0000000000 --- a/drivers/power/ftpmu010.c +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * Copyright (C) 2010 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <faraday/ftpmu010.h> - -/* OSCC: OSC Control Register */ -void ftpmu010_32768osc_enable(void) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int oscc; - - /* enable the 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); - writel(oscc, &pmu->OSCC); - - /* wait until ready */ - while (!(readl(&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) - ; - - /* select 32768Hz oscillator */ - oscc = readl(&pmu->OSCC); - oscc |= FTPMU010_OSCC_OSCL_RTCLSEL; - writel(oscc, &pmu->OSCC); -} - -/* MFPSR: Multi-Function Port Setting Register */ -void ftpmu010_mfpsr_select_dev(unsigned int dev) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int mfpsr; - - mfpsr = readl(&pmu->MFPSR); - mfpsr |= dev; - writel(mfpsr, &pmu->MFPSR); -} - -void ftpmu010_mfpsr_diselect_dev(unsigned int dev) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int mfpsr; - - mfpsr = readl(&pmu->MFPSR); - mfpsr &= ~dev; - writel(mfpsr, &pmu->MFPSR); -} - -/* PDLLCR0: PLL/DLL Control Register 0 */ -void ftpmu010_dlldis_disable(void) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int pdllcr0; - - pdllcr0 = readl(&pmu->PDLLCR0); - pdllcr0 |= FTPMU010_PDLLCR0_DLLDIS; - writel(pdllcr0, &pmu->PDLLCR0); -} - -void ftpmu010_sdram_clk_disable(unsigned int cr0) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int pdllcr0; - - pdllcr0 = readl(&pmu->PDLLCR0); - pdllcr0 |= FTPMU010_PDLLCR0_HCLKOUTDIS(cr0); - writel(pdllcr0, &pmu->PDLLCR0); -} - -/* SDRAMHTC: SDRAM Signal Hold Time Control */ -void ftpmu010_sdramhtc_set(unsigned int val) -{ - static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_FTPMU010_BASE; - unsigned int sdramhtc; - - sdramhtc = readl(&pmu->SDRAMHTC); - sdramhtc |= val; - writel(sdramhtc, &pmu->SDRAMHTC); -} diff --git a/drivers/power/fuel_gauge/Makefile b/drivers/power/fuel_gauge/Makefile deleted file mode 100644 index ca2df94758..0000000000 --- a/drivers/power/fuel_gauge/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2012 Samsung Electronics -# Lukasz Majewski <l.majewski@samsung.com> - -obj-$(CONFIG_POWER_FG_MAX17042) += fg_max17042.o diff --git a/drivers/power/fuel_gauge/fg_max17042.c b/drivers/power/fuel_gauge/fg_max17042.c deleted file mode 100644 index a395d587a8..0000000000 --- a/drivers/power/fuel_gauge/fg_max17042.c +++ /dev/null @@ -1,287 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <linux/delay.h> -#include <power/pmic.h> -#include <power/max17042_fg.h> -#include <i2c.h> -#include <power/max8997_pmic.h> -#include <power/power_chrg.h> -#include <power/battery.h> -#include <power/fg_battery_cell_params.h> -#include <errno.h> - -static int fg_write_regs(struct pmic *p, u8 addr, u16 *data, int num) -{ - int ret = 0; - int i; - - for (i = 0; i < num; i++, addr++) { - ret = pmic_reg_write(p, addr, *(data + i)); - if (ret) - return ret; - } - - return 0; -} - -static int fg_read_regs(struct pmic *p, u8 addr, u16 *data, int num) -{ - unsigned int dat; - int ret = 0; - int i; - - for (i = 0; i < num; i++, addr++) { - ret = pmic_reg_read(p, addr, &dat); - if (ret) - return ret; - - *(data + i) = (u16)dat; - } - - return 0; -} - -static int fg_write_and_verify(struct pmic *p, u8 addr, u16 data) -{ - unsigned int val = data; - int ret = 0; - - ret |= pmic_reg_write(p, addr, val); - ret |= pmic_reg_read(p, addr, &val); - - if (ret) - return ret; - - if (((u16) val) == data) - return 0; - - return -1; -} - -static void por_fuelgauge_init(struct pmic *p) -{ - u16 r_data0[16], r_data1[16], r_data2[16]; - u32 rewrite_count = 5; - u32 check_count; - u32 lock_count; - u32 i = 0; - u32 val; - s32 ret = 0; - char *status_msg; - - /* Delay 500 ms */ - mdelay(500); - /* Initilize Configuration */ - pmic_reg_write(p, MAX17042_CONFIG, 0x2310); - -rewrite_model: - check_count = 5; - lock_count = 5; - - if (!rewrite_count--) { - status_msg = "init failed!"; - goto error; - } - - /* Unlock Model Access */ - pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_UNLOCK1); - pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_UNLOCK2); - - /* Write/Read/Verify the Custom Model */ - ret = fg_write_regs(p, MAX17042_MODEL1, cell_character0, - ARRAY_SIZE(cell_character0)); - if (ret) - goto rewrite_model; - - ret = fg_write_regs(p, MAX17042_MODEL2, cell_character1, - ARRAY_SIZE(cell_character1)); - if (ret) - goto rewrite_model; - - ret = fg_write_regs(p, MAX17042_MODEL3, cell_character2, - ARRAY_SIZE(cell_character2)); - if (ret) - goto rewrite_model; - -check_model: - if (!check_count--) { - if (rewrite_count) - goto rewrite_model; - else - status_msg = "check failed!"; - - goto error; - } - - ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - if (ret) - goto check_model; - - ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - if (ret) - goto check_model; - - ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); - if (ret) - goto check_model; - - for (i = 0; i < 16; i++) { - if ((cell_character0[i] != r_data0[i]) - || (cell_character1[i] != r_data1[i]) - || (cell_character2[i] != r_data2[i])) - goto rewrite_model; - } - -lock_model: - if (!lock_count--) { - if (rewrite_count) - goto rewrite_model; - else - status_msg = "lock failed!"; - - goto error; - } - - /* Lock model access */ - pmic_reg_write(p, MAX17042_MLOCKReg1, MODEL_LOCK1); - pmic_reg_write(p, MAX17042_MLOCKReg2, MODEL_LOCK2); - - /* Verify the model access is locked */ - ret = fg_read_regs(p, MAX17042_MODEL1, r_data0, ARRAY_SIZE(r_data0)); - if (ret) - goto lock_model; - - ret = fg_read_regs(p, MAX17042_MODEL2, r_data1, ARRAY_SIZE(r_data1)); - if (ret) - goto lock_model; - - ret = fg_read_regs(p, MAX17042_MODEL3, r_data2, ARRAY_SIZE(r_data2)); - if (ret) - goto lock_model; - - for (i = 0; i < ARRAY_SIZE(r_data0); i++) { - /* Check if model locked */ - if (r_data0[i] || r_data1[i] || r_data2[i]) - goto lock_model; - } - - /* Write Custom Parameters */ - fg_write_and_verify(p, MAX17042_RCOMP0, RCOMP0); - fg_write_and_verify(p, MAX17042_TEMPCO, TempCo); - - /* Delay at least 350mS */ - mdelay(350); - - /* Initialization Complete */ - pmic_reg_read(p, MAX17042_STATUS, &val); - /* Write and Verify Status with POR bit Cleared */ - fg_write_and_verify(p, MAX17042_STATUS, val & ~MAX17042_POR); - - /* Delay at least 350 ms */ - mdelay(350); - - status_msg = "OK!"; -error: - debug("%s: model init status: %s\n", p->name, status_msg); - return; -} - -static int power_update_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max17042 fuel gauge\n"); - return -ENODEV; - } - - ret |= pmic_reg_read(p, MAX17042_VFSOC, &val); - pb->bat->state_of_chrg = (val >> 8); - - pmic_reg_read(p, MAX17042_VCELL, &val); - debug("vfsoc: 0x%x\n", val); - pb->bat->voltage_uV = ((val & 0xFFUL) >> 3) + ((val & 0xFF00) >> 3); - pb->bat->voltage_uV = (pb->bat->voltage_uV * 625); - - pmic_reg_read(p, 0x05, &val); - pb->bat->capacity = val >> 2; - - return ret; -} - -static int power_check_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max17042 fuel gauge\n"); - return -ENODEV; - } - - ret |= pmic_reg_read(p, MAX17042_STATUS, &val); - debug("fg status: 0x%x\n", val); - - if (val & MAX17042_POR) - por_fuelgauge_init(p); - - ret |= pmic_reg_read(p, MAX17042_VERSION, &val); - pb->bat->version = val; - - power_update_battery(p, bat); - debug("fg ver: 0x%x\n", pb->bat->version); - printf("BAT: state_of_charge(SOC):%d%%\n", - pb->bat->state_of_chrg); - - printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", - pb->bat->voltage_uV / 1000000, - pb->bat->voltage_uV % 1000000, - pb->bat->capacity); - - if (pb->bat->voltage_uV > 3850000) - pb->bat->state = EXT_SOURCE; - else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) - pb->bat->state = CHARGE; - else - pb->bat->state = NORMAL; - - return ret; -} - -static struct power_fg power_fg_ops = { - .fg_battery_check = power_check_battery, - .fg_battery_update = power_update_battery, -}; - -int power_fg_init(unsigned char bus) -{ - static const char name[] = "MAX17042_FG"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Fuel Gauge init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = FG_NUM_OF_REGS; - p->hw.i2c.addr = MAX17042_I2C_ADDR; - p->hw.i2c.tx_num = 2; - p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; - p->bus = bus; - - p->fg = &power_fg_ops; - return 0; -} diff --git a/drivers/power/mfd/Makefile b/drivers/power/mfd/Makefile deleted file mode 100644 index a8eb7f81e7..0000000000 --- a/drivers/power/mfd/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (C) 2013 Samsung Electronics -# Piotr Wilczek <p.wilczek@samsung.com> - -obj-$(CONFIG_POWER_PMIC_MAX77693) += pmic_max77693.o -obj-$(CONFIG_POWER_MUIC_MAX77693) += muic_max77693.o -obj-$(CONFIG_POWER_FG_MAX77693) += fg_max77693.o diff --git a/drivers/power/mfd/fg_max77693.c b/drivers/power/mfd/fg_max77693.c deleted file mode 100644 index 983a6d4a2b..0000000000 --- a/drivers/power/mfd/fg_max77693.c +++ /dev/null @@ -1,137 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_fg.h> -#include <i2c.h> -#include <power/power_chrg.h> -#include <power/battery.h> -#include <power/fg_battery_cell_params.h> -#include <errno.h> - -static int max77693_get_vcell(u32 *vcell) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VCELL, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *vcell = (u32)(value >> 3); - *vcell = *vcell * 625; - - return 0; -} - -static int max77693_get_soc(u32 *soc) -{ - u16 value; - u8 ret; - - ret = i2c_read(MAX77693_FUEL_I2C_ADDR, MAX77693_VFSOC, 1, - (u8 *)&value, 2); - if (ret) - return ret; - - *soc = (u32)(value >> 8); - - return 0; -} - -static int power_update_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - int ret; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = max77693_get_soc(&pb->bat->state_of_chrg); - if (ret) - return ret; - - max77693_get_vcell(&pb->bat->voltage_uV); - - return 0; -} - -static int power_check_battery(struct pmic *p, struct pmic *bat) -{ - struct power_battery *pb = bat->pbat; - unsigned int val; - int ret = 0; - - if (pmic_probe(p)) { - puts("Can't find max77693 fuel gauge\n"); - return -ENODEV; - } - - ret = pmic_reg_read(p, MAX77693_STATUS, &val); - if (ret) - return ret; - debug("fg status: 0x%x\n", val); - - ret = pmic_reg_read(p, MAX77693_VERSION, &pb->bat->version); - if (ret) - return ret; - - ret = power_update_battery(p, bat); - if (ret) - return ret; - debug("fg ver: 0x%x\n", pb->bat->version); - printf("BAT: state_of_charge(SOC):%d%%\n", - pb->bat->state_of_chrg); - - printf(" voltage: %d.%6.6d [V] (expected to be %d [mAh])\n", - pb->bat->voltage_uV / 1000000, - pb->bat->voltage_uV % 1000000, - pb->bat->capacity); - - if (pb->bat->voltage_uV > 3850000) - pb->bat->state = EXT_SOURCE; - else if (pb->bat->voltage_uV < 3600000 || pb->bat->state_of_chrg < 5) - pb->bat->state = CHARGE; - else - pb->bat->state = NORMAL; - - return 0; -} - -static struct power_fg power_fg_ops = { - .fg_battery_check = power_check_battery, - .fg_battery_update = power_update_battery, -}; - -int power_fg_init(unsigned char bus) -{ - static const char name[] = "MAX77693_FG"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Fuel Gauge init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = FG_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_FUEL_I2C_ADDR; - p->hw.i2c.tx_num = 2; - p->sensor_byte_order = PMIC_SENSOR_BYTE_ORDER_BIG; - p->bus = bus; - - p->fg = &power_fg_ops; - - return 0; -} diff --git a/drivers/power/mfd/muic_max77693.c b/drivers/power/mfd/muic_max77693.c deleted file mode 100644 index 36ee44b9a2..0000000000 --- a/drivers/power/mfd/muic_max77693.c +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/power_chrg.h> -#include <power/max77693_muic.h> -#include <i2c.h> -#include <errno.h> - -static int power_chrg_get_type(struct pmic *p) -{ - unsigned int val; - unsigned int charge_type, charger; - - /* if probe failed, return cable none */ - if (pmic_probe(p)) - return CHARGER_NO; - - pmic_reg_read(p, MAX77693_MUIC_STATUS2, &val); - - charge_type = val & MAX77693_MUIC_CHG_MASK; - - switch (charge_type) { - case MAX77693_MUIC_CHG_NO: - charger = CHARGER_NO; - break; - case MAX77693_MUIC_CHG_USB: - case MAX77693_MUIC_CHG_USB_D: - charger = CHARGER_USB; - break; - case MAX77693_MUIC_CHG_TA: - case MAX77693_MUIC_CHG_TA_1A: - charger = CHARGER_TA; - break; - case MAX77693_MUIC_CHG_TA_500: - charger = CHARGER_TA_500; - break; - default: - charger = CHARGER_UNKNOWN; - break; - } - - return charger; -} - -static struct power_chrg power_chrg_muic_ops = { - .chrg_type = power_chrg_get_type, -}; - -int power_muic_init(unsigned int bus) -{ - static const char name[] = "MAX77693_MUIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Micro USB Interface Controller init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = MUIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_MUIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_muic_ops; - - return 0; -} diff --git a/drivers/power/mfd/pmic_max77693.c b/drivers/power/mfd/pmic_max77693.c deleted file mode 100644 index e32a9722a4..0000000000 --- a/drivers/power/mfd/pmic_max77693.c +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Samsung Electronics - * Piotr Wilczek <p.wilczek@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/max77693_pmic.h> -#include <i2c.h> -#include <errno.h> - -static int max77693_charger_state(struct pmic *p, int state, int current) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - /* unlock write capability */ - val = MAX77693_CHG_UNLOCK; - pmic_reg_write(p, MAX77693_CHG_CNFG_06, val); - - if (state == PMIC_CHARGER_DISABLE) { - puts("Disable the charger.\n"); - pmic_reg_read(p, MAX77693_CHG_CNFG_00, &val); - val &= ~0x01; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - return -ENOTSUPP; - } - - if (current < CHARGER_MIN_CURRENT || current > CHARGER_MAX_CURRENT) { - printf("%s: Wrong charge current: %d [mA]\n", - __func__, current); - return -EINVAL; - } - - /* set charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= ~MAX77693_CHG_CC; - val |= current * 10 / 333; /* 0.1A/3 steps */ - pmic_reg_write(p, MAX77693_CHG_CNFG_02, val); - - /* enable charging */ - val = MAX77693_CHG_MODE_ON; - pmic_reg_write(p, MAX77693_CHG_CNFG_00, val); - - /* check charging current */ - pmic_reg_read(p, MAX77693_CHG_CNFG_02, &val); - val &= 0x3f; - printf("Enable the charger @ %d [mA]\n", val * 333 / 10); - - return 0; -} - -static int max77693_charger_bat_present(struct pmic *p) -{ - unsigned int val; - - if (pmic_probe(p)) - return -ENODEV; - - pmic_reg_read(p, MAX77693_CHG_INT_OK, &val); - - return !(val & MAX77693_CHG_DETBAT); -} - -static struct power_chrg power_chrg_pmic_ops = { - .chrg_bat_present = max77693_charger_bat_present, - .chrg_state = max77693_charger_state, -}; - -int pmic_init_max77693(unsigned char bus) -{ - static const char name[] = "MAX77693_PMIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board PMIC init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = PMIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX77693_PMIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_pmic_ops; - - return 0; -} diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index c3180c5820..0b3b3d62d0 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y) obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o -obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o obj-$(CONFIG_POWER_PFUZE3000) += pmic_pfuze3000.o diff --git a/drivers/power/pmic/muic_max8997.c b/drivers/power/pmic/muic_max8997.c deleted file mode 100644 index 969ce90239..0000000000 --- a/drivers/power/pmic/muic_max8997.c +++ /dev/null @@ -1,74 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2012 Samsung Electronics - * Lukasz Majewski <l.majewski@samsung.com> - */ - -#include <common.h> -#include <log.h> -#include <power/pmic.h> -#include <power/power_chrg.h> -#include <power/max8997_muic.h> -#include <i2c.h> -#include <errno.h> - -static int power_chrg_get_type(struct pmic *p) -{ - unsigned int val; - unsigned char charge_type, charger; - - if (pmic_probe(p)) - return CHARGER_NO; - - pmic_reg_read(p, MAX8997_MUIC_STATUS2, &val); - charge_type = val & MAX8997_MUIC_CHG_MASK; - - switch (charge_type) { - case MAX8997_MUIC_CHG_NO: - charger = CHARGER_NO; - break; - case MAX8997_MUIC_CHG_USB: - case MAX8997_MUIC_CHG_USB_D: - charger = CHARGER_USB; - break; - case MAX8997_MUIC_CHG_TA: - case MAX8997_MUIC_CHG_TA_1A: - charger = CHARGER_TA; - break; - case MAX8997_MUIC_CHG_TA_500: - charger = CHARGER_TA_500; - break; - default: - charger = CHARGER_UNKNOWN; - break; - } - - return charger; -} - -static struct power_chrg power_chrg_muic_ops = { - .chrg_type = power_chrg_get_type, -}; - -int power_muic_init(unsigned int bus) -{ - static const char name[] = "MAX8997_MUIC"; - struct pmic *p = pmic_alloc(); - - if (!p) { - printf("%s: POWER allocation error!\n", __func__); - return -ENOMEM; - } - - debug("Board Micro USB Interface Controller init\n"); - - p->name = name; - p->interface = PMIC_I2C; - p->number_of_regs = MUIC_NUM_OF_REGS; - p->hw.i2c.addr = MAX8997_MUIC_I2C_ADDR; - p->hw.i2c.tx_num = 1; - p->bus = bus; - - p->chrg = &power_chrg_muic_ops; - return 0; -} diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index a186edc08d..2427abfb7a 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -86,6 +86,7 @@ static int pca9450_bind(struct udevice *dev) static int pca9450_probe(struct udevice *dev) { struct pca9450_priv *priv = dev_get_priv(dev); + unsigned int reset_ctrl; int ret = 0; if (CONFIG_IS_ENABLED(DM_GPIO) && CONFIG_IS_ENABLED(DM_REGULATOR_PCA9450)) { @@ -95,10 +96,18 @@ static int pca9450_probe(struct udevice *dev) if (IS_ERR(priv->sd_vsel_gpio)) { ret = PTR_ERR(priv->sd_vsel_gpio); dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + if (ret) + return ret; } } - return ret; + if (ofnode_read_bool(dev_ofnode(dev), "nxp,wdog_b-warm-reset")) + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_WARM; + else + reset_ctrl = PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12; + + return pmic_clrsetbits(dev, PCA9450_RESET_CTRL, + PCA9450_PMIC_RESET_WDOG_B_CFG_MASK, reset_ctrl); } static struct dm_pmic_ops pca9450_ops = { diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index acfd130bbc..447551e15a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -6,49 +6,35 @@ obj-$(CONFIG_$(SPL_TPL_)DM_RTC) += rtc-uclass.o -obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_ARMADA38X) += armada38x.o obj-$(CONFIG_RTC_DAVINCI) += davinci.o -obj-$(CONFIG_RTC_DS1302) += ds1302.o -obj-$(CONFIG_RTC_DS1306) += ds1306.o obj-$(CONFIG_RTC_DS1307) += ds1307.o obj-$(CONFIG_RTC_DS1338) += ds1307.o -obj-$(CONFIG_RTC_DS1339) += ds1307.o obj-$(CONFIG_RTC_DS1337) += ds1337.o obj-$(CONFIG_RTC_DS1374) += ds1374.o -obj-$(CONFIG_RTC_DS1388) += ds1337.o obj-$(CONFIG_RTC_DS3231) += ds3231.o obj-$(CONFIG_RTC_DS3232) += ds3232.o obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o -obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o obj-$(CONFIG_RTC_HT1380) += ht1380.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o -obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o obj-$(CONFIG_RTC_M41T62) += m41t62.o -obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o -obj-$(CONFIG_RTC_MCP79411) += ds1307.o obj-$(CONFIG_MCFRTC) += mcfrtc.o -obj-$(CONFIG_RTC_MK48T59) += mk48t59.o obj-$(CONFIG_RTC_MV) += mvrtc.o -obj-$(CONFIG_RTC_MX27) += mx27rtc.o obj-$(CONFIG_RTC_MXS) += mxsrtc.o obj-$(CONFIG_RTC_PCF8563) += pcf8563.o obj-$(CONFIG_RTC_PCF2127) += pcf2127.o obj-$(CONFIG_RTC_PL031) += pl031.o obj-$(CONFIG_RTC_PT7C4338) += pt7c4338.o -obj-$(CONFIG_RTC_RS5C372A) += rs5c372.o obj-$(CONFIG_RTC_RV3028) += rv3028.o obj-$(CONFIG_RTC_RV3029) += rv3029.o obj-$(CONFIG_RTC_RV8803) += rv8803.o obj-$(CONFIG_RTC_RX8025) += rx8025.o obj-$(CONFIG_RTC_RX8010SJ) += rx8010sj.o -obj-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o obj-$(CONFIG_RTC_S35392A) += s35392a.o obj-$(CONFIG_RTC_STM32) += stm32_rtc.o obj-$(CONFIG_SANDBOX) += sandbox_rtc.o -obj-$(CONFIG_RTC_X1205) += x1205.o obj-$(CONFIG_RTC_ABX80X) += abx80x.o obj-$(CONFIG_RTC_ZYNQMP) += zynqmp_rtc.o diff --git a/drivers/rtc/at91sam9_rtt.c b/drivers/rtc/at91sam9_rtt.c deleted file mode 100644 index 6f92660ef1..0000000000 --- a/drivers/rtc/at91sam9_rtt.c +++ /dev/null @@ -1,78 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - */ - -/* - * Date & Time support for the internal Real-time Timer - * of AT91SAM9260 and compatibles. - * Compatible with the LinuX rtc driver workaround: - * The RTT cannot be written to, but only reset. - * The actual time is the sum of RTT and one of - * the four GPBR registers. - * - * The at91sam9260 has 4 GPBR (0-3). - * For their typical use see at91_gpbr.h ! - * - * make sure u-boot and kernel use the same GPBR ! - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/hardware.h> -#include <asm/arch/at91_rtt.h> -#include <asm/arch/at91_gpbr.h> - -int rtc_get (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - ulong tim2; - ulong off; - - do { - tim = readl(&rtt->vr); - tim2 = readl(&rtt->vr); - } while (tim!=tim2); - off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* off==0 means time is invalid, but we ignore that */ - rtc_to_tm(tim+off, tmp); - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - ulong tim; - - tim = rtc_mktime(tmp); - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; - return 0; -} - -void rtc_reset (void) -{ - at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; - at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - - /* clear alarm, set prescaler to 32768, clear counter */ - writel(32768+AT91_RTT_RTTRST, &rtt->mr); - writel(~0, &rtt->ar); - writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); - /* wait for counter clear to happen, takes less than a 1/32768th second */ - while (readl(&rtt->vr) != 0) - ; -} diff --git a/drivers/rtc/ds1302.c b/drivers/rtc/ds1302.c deleted file mode 100644 index 189607c3e0..0000000000 --- a/drivers/rtc/ds1302.c +++ /dev/null @@ -1,329 +0,0 @@ -/* - * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip - * - * Rex G. Feany <rfeany@zumanetworks.com> - * - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <linux/delay.h> - -/* GPP Pins */ -#define DATA 0x200 -#define SCLK 0x400 -#define RST 0x800 - -/* Happy Fun Defines(tm) */ -#define RESET rtc_go_low(RST), rtc_go_low(SCLK) -#define N_RESET rtc_go_high(RST), rtc_go_low(SCLK) - -#define CLOCK_HIGH rtc_go_high(SCLK) -#define CLOCK_LOW rtc_go_low(SCLK) - -#define DATA_HIGH rtc_go_high(DATA) -#define DATA_LOW rtc_go_low(DATA) -#define DATA_READ (GTREGREAD(GPP_VALUE) & DATA) - -#undef RTC_DEBUG - -#ifdef RTC_DEBUG -# define DPRINTF(x,args...) printf("ds1302: " x , ##args) -static inline void DUMP(const char *ptr, int num) -{ - while (num--) printf("%x ", *ptr++); - printf("]\n"); -} -#else -# define DPRINTF(x,args...) -# define DUMP(ptr, num) -#endif - -/* time data format for DS1302 */ -struct ds1302_st -{ - unsigned char CH:1; /* clock halt 1=stop 0=start */ - unsigned char sec10:3; - unsigned char sec:4; - - unsigned char zero0:1; - unsigned char min10:3; - unsigned char min:4; - - unsigned char fmt:1; /* 1=12 hour 0=24 hour */ - unsigned char zero1:1; - unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */ - unsigned char hr:4; - - unsigned char zero2:2; - unsigned char date10:2; - unsigned char date:4; - - unsigned char zero3:3; - unsigned char month10:1; - unsigned char month:4; - - unsigned char zero4:5; - unsigned char day:3; /* day of week */ - - unsigned char year10:4; - unsigned char year:4; - - unsigned char WP:1; /* write protect 1=protect 0=unprot */ - unsigned char zero5:7; -}; - -static int ds1302_initted=0; - -/* Pin control */ -static inline void -rtc_go_high(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) | mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_low(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_VALUE) & ~mask; - - GT_REG_WRITE(GPP_VALUE, f); -} - -static inline void -rtc_go_input(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) & ~mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -static inline void -rtc_go_output(unsigned int mask) -{ - unsigned int f = GTREGREAD(GPP_IO_CONTROL) | mask; - - GT_REG_WRITE(GPP_IO_CONTROL, f); -} - -/* Access data in RTC */ - -static void -write_byte(unsigned char b) -{ - int i; - unsigned char mask=1; - - for(i=0;i<8;i++) { - CLOCK_LOW; /* Lower clock */ - (b&mask)?DATA_HIGH:DATA_LOW; /* set data */ - udelay(1); - CLOCK_HIGH; /* latch data with rising clock */ - udelay(1); - mask=mask<<1; - } -} - -static unsigned char -read_byte(void) -{ - int i; - unsigned char mask=1; - unsigned char b=0; - - for(i=0;i<8;i++) { - CLOCK_LOW; - udelay(1); - if (DATA_READ) b|=mask; /* if this bit is high, set in b */ - CLOCK_HIGH; /* clock out next bit */ - udelay(1); - mask=mask<<1; - } - return b; -} - -static void -read_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; -#ifdef RTC_DEBUG - char *foo = buf; -#endif - - DPRINTF("READ 0x%x bytes @ 0x%x [ ", count, addr); - - addr|=1; /* READ */ - N_RESET; - udelay(4); - write_byte(addr); - rtc_go_input(DATA); /* Put gpp pin into input mode */ - udelay(1); - for(i=0;i<count;i++) *(buf++)=read_byte(); - RESET; - rtc_go_output(DATA);/* Reset gpp for output */ - udelay(4); - - DUMP(foo, count); -} - -static void -write_ser_drv(unsigned char addr, unsigned char *buf, int count) -{ - int i; - - DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr); - DUMP(buf, count); - - addr&=~1; /* WRITE */ - N_RESET; - udelay(4); - write_byte(addr); - for(i=0;i<count;i++) write_byte(*(buf++)); - RESET; - udelay(4); - -} - -void -rtc_init(void) -{ - struct ds1302_st bbclk; - unsigned char b; - int mod; - - DPRINTF("init\n"); - - rtc_go_output(DATA|SCLK|RST); - - /* disable write protect */ - b = 0; - write_ser_drv(0x8e,&b,1); - - /* enable trickle */ - b = 0xa5; /* 1010.0101 */ - write_ser_drv(0x90,&b,1); - - /* read burst */ - read_ser_drv(0xbe, (unsigned char *)&bbclk, 8); - - /* Sanity checks */ - mod = 0; - if (bbclk.CH) { - printf("ds1302: Clock was halted, starting clock\n"); - bbclk.CH=0; - mod=1; - } - - if (bbclk.fmt) { - printf("ds1302: Clock was in 12 hour mode, fixing\n"); - bbclk.fmt=0; - mod=1; - } - - if (bbclk.year>9) { - printf("ds1302: Year was corrupted, fixing\n"); - bbclk.year10=100/10; /* 2000 - why not? ;) */ - bbclk.year=0; - mod=1; - } - - /* Write out the changes if needed */ - if (mod) { - /* enable write protect */ - bbclk.WP = 1; - write_ser_drv(0xbe,(unsigned char *)&bbclk,8); - } else { - /* Else just turn write protect on */ - b = 0x80; - write_ser_drv(0x8e,&b,1); - } - DPRINTF("init done\n"); - - ds1302_initted=1; -} - -void -rtc_reset(void) -{ - if(!ds1302_initted) rtc_init(); - /* TODO */ -} - -int -rtc_get(struct rtc_time *tmp) -{ - int rel = 0; - struct ds1302_st bbclk; - - if(!ds1302_initted) rtc_init(); - - read_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* read burst */ - - if (bbclk.CH) { - printf("ds1302: rtc_get: Clock was halted, clock probably " - "corrupt\n"); - rel = -1; - } - - tmp->tm_sec=10*bbclk.sec10+bbclk.sec; - tmp->tm_min=10*bbclk.min10+bbclk.min; - tmp->tm_hour=10*bbclk.hr10+bbclk.hr; - tmp->tm_wday=bbclk.day; - tmp->tm_mday=10*bbclk.date10+bbclk.date; - tmp->tm_mon=10*bbclk.month10+bbclk.month; - tmp->tm_year=10*bbclk.year10+bbclk.year + 1900; - - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - DPRINTF("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec ); - - return rel; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct ds1302_st bbclk; - unsigned char b=0; - - if(!ds1302_initted) rtc_init(); - - DPRINTF("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - memset(&bbclk,0,sizeof(bbclk)); - bbclk.CH=0; /* dont halt */ - bbclk.WP=1; /* write protect when we're done */ - - bbclk.sec10=tmp->tm_sec/10; - bbclk.sec=tmp->tm_sec%10; - - bbclk.min10=tmp->tm_min/10; - bbclk.min=tmp->tm_min%10; - - bbclk.hr10=tmp->tm_hour/10; - bbclk.hr=tmp->tm_hour%10; - - bbclk.day=tmp->tm_wday; - - bbclk.date10=tmp->tm_mday/10; - bbclk.date=tmp->tm_mday%10; - - bbclk.month10=tmp->tm_mon/10; - bbclk.month=tmp->tm_mon%10; - - tmp->tm_year -= 1900; - bbclk.year10=tmp->tm_year/10; - bbclk.year=tmp->tm_year%10; - - write_ser_drv(0x8e,&b,1); /* disable write protect */ - write_ser_drv(0xbe,(unsigned char *)&bbclk, 8); /* write burst */ - - return 0; -} diff --git a/drivers/rtc/ds1306.c b/drivers/rtc/ds1306.c deleted file mode 100644 index 36d615812b..0000000000 --- a/drivers/rtc/ds1306.c +++ /dev/null @@ -1,438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 SIXNET, dge@sixnetio.com. - * - * (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> - * Stephan Linz <linz@li-pro.net> - */ - -/* - * Date & Time support for DS1306 RTC using SPI: - * - * - SXNI855T: it uses its own soft SPI here in this file - * - all other: use the external spi_xfer() function - * (see include/spi.h) - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <spi.h> -#include <linux/delay.h> - -#define RTC_SECONDS 0x00 -#define RTC_MINUTES 0x01 -#define RTC_HOURS 0x02 -#define RTC_DAY_OF_WEEK 0x03 -#define RTC_DATE_OF_MONTH 0x04 -#define RTC_MONTH 0x05 -#define RTC_YEAR 0x06 - -#define RTC_SECONDS_ALARM0 0x07 -#define RTC_MINUTES_ALARM0 0x08 -#define RTC_HOURS_ALARM0 0x09 -#define RTC_DAY_OF_WEEK_ALARM0 0x0a - -#define RTC_SECONDS_ALARM1 0x0b -#define RTC_MINUTES_ALARM1 0x0c -#define RTC_HOURS_ALARM1 0x0d -#define RTC_DAY_OF_WEEK_ALARM1 0x0e - -#define RTC_CONTROL 0x0f -#define RTC_STATUS 0x10 -#define RTC_TRICKLE_CHARGER 0x11 - -#define RTC_USER_RAM_BASE 0x20 - -/* ************************************************************************* */ -#ifdef CONFIG_SXNI855T /* !!! SHOULD BE CHANGED TO NEW CODE !!! */ - -static void soft_spi_send (unsigned char n); -static unsigned char soft_spi_read (void); -static void init_spi (void); - -/*----------------------------------------------------------------------- - * Definitions - */ - -#define PB_SPISCK 0x00000002 /* PB 30 */ -#define PB_SPIMOSI 0x00000004 /* PB 29 */ -#define PB_SPIMISO 0x00000008 /* PB 28 */ -#define PB_SPI_CE 0x00010000 /* PB 15 */ - -/* ------------------------------------------------------------------------- */ - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char spi_byte; /* Data Byte */ - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Shift out the address (0) of the time in the Clock Chip */ - soft_spi_send (0); - - /* Put the clock readings into the rtc_time structure */ - tmp->tm_sec = bcd2bin (soft_spi_read ()); /* Read seconds */ - tmp->tm_min = bcd2bin (soft_spi_read ()); /* Read minutes */ - - /* Hours are trickier */ - spi_byte = soft_spi_read (); /* Read Hours into temporary value */ - if (spi_byte & 0x40) { - /* 12 hour mode bit is set (time is in 1-12 format) */ - if (spi_byte & 0x20) { - /* since PM we add 11 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) + 11; - } else { - /* since AM we subtract 1 to get 0-23 for hours */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x1F)) - 1; - } - } else { - /* Otherwise, 0-23 hour format */ - tmp->tm_hour = (bcd2bin (spi_byte & 0x3F)); - } - - soft_spi_read (); /* Read and discard Day of week */ - tmp->tm_mday = bcd2bin (soft_spi_read ()); /* Read Day of the Month */ - tmp->tm_mon = bcd2bin (soft_spi_read ()); /* Read Month */ - - /* Read Year and convert to this century */ - tmp->tm_year = bcd2bin (soft_spi_read ()) + 2000; - - /* Now we can disable the DS1306 RTC */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - rtc_calc_weekday(tmp); /* Determine the day of week */ - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time in DS1306 RTC and in MPC8xx RTC */ -int rtc_set (struct rtc_time *tmp) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - init_spi (); /* set port B for software SPI */ - - /* Now we can enable the DS1306 RTC */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First disable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x00); /* send control register contents */ - - /* Now disable the DS1306 to terminate the write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; - udelay(10); - - /* Now enable the DS1306 to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; - udelay(10); - - /* Next, send the address of the clock time write registers */ - soft_spi_send (0x80); /* send address of the first time register */ - - /* Use Burst Mode to send all of the time data to the clock */ - bin2bcd (tmp->tm_sec); - soft_spi_send (bin2bcd (tmp->tm_sec)); /* Send Seconds */ - soft_spi_send (bin2bcd (tmp->tm_min)); /* Send Minutes */ - soft_spi_send (bin2bcd (tmp->tm_hour)); /* Send Hour */ - soft_spi_send (bin2bcd (tmp->tm_wday)); /* Send Day of the Week */ - soft_spi_send (bin2bcd (tmp->tm_mday)); /* Send Day of Month */ - soft_spi_send (bin2bcd (tmp->tm_mon)); /* Send Month */ - soft_spi_send (bin2bcd (tmp->tm_year - 2000)); /* Send Year */ - - /* Now we can disable the Clock chip to terminate the burst write */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Now we can enable the Clock chip to initiate a new write */ - immap->im_cpm.cp_pbdat |= PB_SPI_CE; /* Enable DS1306 Chip */ - udelay(10); - - /* First we Enable write protect in the clock chip control register */ - soft_spi_send (0x8F); /* send address of the control register */ - soft_spi_send (0x40); /* send out Control Register contents */ - - /* Now disable the DS1306 */ - immap->im_cpm.cp_pbdat &= ~PB_SPI_CE; /* Disable DS1306 Chip */ - udelay(10); - - /* Set standard MPC8xx clock to the same time so Linux will - * see the time even if it doesn't have a DS1306 clock driver. - * This helps with experimenting with standard kernels. - */ - { - ulong tim; - - tim = rtc_mktime(tmp); - - immap->im_sitk.sitk_rtck = KAPWR_KEY; - immap->im_sit.sit_rtc = tim; - } - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* Initialize Port B for software SPI */ -static void init_spi (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - /* Force output pins to begin at logic 0 */ - immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK); - - /* Set these 3 signals as outputs */ - immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK); - - immap->im_cpm.cp_pbdir &= ~PB_SPIMISO; /* Make MISO pin an input */ - udelay(10); -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */ -static void soft_spi_send (unsigned char n) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to send, start with most significant bit */ - bitpos = 0x80; - - /* Send 8 bits to software SPI */ - for (i = 0; i < 8; i++) { /* Loop for 8 bits */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - - if (n & bitpos) - immap->im_cpm.cp_pbdat |= PB_SPIMOSI; /* Set MOSI to 1 */ - else - immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI; /* Set MOSI to 0 */ - udelay(10); - - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - - bitpos >>= 1; /* Shift for next bit position */ - } -} - -/* ------------------------------------------------------------------------- */ - -/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */ -static unsigned char soft_spi_read (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - - unsigned char spi_byte = 0; /* Return value, assume success */ - unsigned char bitpos; /* bit position to receive */ - unsigned char i; /* Loop Control */ - - /* bit position to receive, start with most significant bit */ - bitpos = 0x80; - - /* Read 8 bits here */ - for (i = 0; i < 8; i++) { /* Do 8 bits in loop */ - immap->im_cpm.cp_pbdat |= PB_SPISCK; /* Raise SCK */ - udelay(10); - if (immap->im_cpm.cp_pbdat & PB_SPIMISO) /* Get a bit of data */ - spi_byte |= bitpos; /* Set data accordingly */ - immap->im_cpm.cp_pbdat &= ~PB_SPISCK; /* Lower SCK */ - udelay(10); - bitpos >>= 1; /* Shift for next bit position */ - } - - return spi_byte; /* Return the byte read */ -} - -/* ------------------------------------------------------------------------- */ - -void rtc_reset (void) -{ - return; /* nothing to do */ -} - -#else /* not CONFIG_SXNI855T */ -/* ************************************************************************* */ - -static unsigned char rtc_read (unsigned char reg); -static void rtc_write (unsigned char reg, unsigned char val); - -static struct spi_slave *slave; - -/* read clock time from DS1306 and return it in *tmp */ -int rtc_get (struct rtc_time *tmp) -{ - unsigned char sec, min, hour, mday, wday, mon, year; - - /* - * Assuming Vcc = 2.0V (lowest speed) - * - * REVISIT: If we add an rtc_init() function we can do this - * step just once. - */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DATE_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - spi_release_bus(slave); - - debug ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - debug ("Alarms[0]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM0), - rtc_read (RTC_HOURS_ALARM0), - rtc_read (RTC_MINUTES_ALARM0), rtc_read (RTC_SECONDS_ALARM0)); - debug ("Alarms[1]: wday: %02x hour: %02x min: %02x sec: %02x\n", - rtc_read (RTC_DAY_OF_WEEK_ALARM1), - rtc_read (RTC_HOURS_ALARM1), - rtc_read (RTC_MINUTES_ALARM1), rtc_read (RTC_SECONDS_ALARM1)); - - tmp->tm_sec = bcd2bin (sec & 0x7F); /* convert Seconds */ - tmp->tm_min = bcd2bin (min & 0x7F); /* convert Minutes */ - - /* convert Hours */ - tmp->tm_hour = (hour & 0x40) - ? ((hour & 0x20) /* 12 hour mode */ - ? bcd2bin (hour & 0x1F) + 11 /* PM */ - : bcd2bin (hour & 0x1F) - 1 /* AM */ - ) - : bcd2bin (hour & 0x3F); /* 24 hour mode */ - - tmp->tm_mday = bcd2bin (mday & 0x3F); /* convert Day of the Month */ - tmp->tm_mon = bcd2bin (mon & 0x1F); /* convert Month */ - tmp->tm_year = bcd2bin (year) + 2000; /* convert Year */ - tmp->tm_wday = bcd2bin (wday & 0x07) - 1; /* convert Day of the Week */ - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - debug ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -/* ------------------------------------------------------------------------- */ - -/* set clock time from *tmp in DS1306 RTC */ -int rtc_set (struct rtc_time *tmp) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - debug ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (RTC_SECONDS, bin2bcd (tmp->tm_sec)); - rtc_write (RTC_MINUTES, bin2bcd (tmp->tm_min)); - rtc_write (RTC_HOURS, bin2bcd (tmp->tm_hour)); - rtc_write (RTC_DAY_OF_WEEK, bin2bcd (tmp->tm_wday + 1)); - rtc_write (RTC_DATE_OF_MONTH, bin2bcd (tmp->tm_mday)); - rtc_write (RTC_MONTH, bin2bcd (tmp->tm_mon)); - rtc_write (RTC_YEAR, bin2bcd (tmp->tm_year - 2000)); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -/* reset the DS1306 */ -void rtc_reset (void) -{ - /* Assuming Vcc = 2.0V (lowest speed) */ - if (!slave) { - slave = spi_setup_slave(0, CONFIG_SYS_SPI_RTC_DEVID, 600000, - SPI_MODE_3 | SPI_CS_HIGH); - if (!slave) - return; - } - - if (spi_claim_bus(slave)) - return; - - /* clear the control register */ - rtc_write (RTC_CONTROL, 0x00); /* 1st step: reset WP */ - rtc_write (RTC_CONTROL, 0x00); /* 2nd step: reset 1Hz, AIE1, AIE0 */ - - /* reset all alarms */ - rtc_write (RTC_SECONDS_ALARM0, 0x00); - rtc_write (RTC_SECONDS_ALARM1, 0x00); - rtc_write (RTC_MINUTES_ALARM0, 0x00); - rtc_write (RTC_MINUTES_ALARM1, 0x00); - rtc_write (RTC_HOURS_ALARM0, 0x00); - rtc_write (RTC_HOURS_ALARM1, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM0, 0x00); - rtc_write (RTC_DAY_OF_WEEK_ALARM1, 0x00); - - spi_release_bus(slave); -} - -/* ------------------------------------------------------------------------- */ - -static unsigned char rtc_read (unsigned char reg) -{ - int ret; - - ret = spi_w8r8(slave, reg); - return ret < 0 ? 0 : ret; -} - -/* ------------------------------------------------------------------------- */ - -static void rtc_write (unsigned char reg, unsigned char val) -{ - unsigned char dout[2]; /* SPI Output Data Bytes */ - unsigned char din[2]; /* SPI Input Data Bytes */ - - dout[0] = 0x80 | reg; - dout[1] = val; - - spi_xfer (slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END); -} - -#endif /* end of code exclusion (see #ifdef CONFIG_SXNI855T above) */ diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c deleted file mode 100644 index e384922f47..0000000000 --- a/drivers/rtc/ftrtc010.c +++ /dev/null @@ -1,122 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday FTRTC010 Real Time Clock - * - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -#include <config.h> -#include <common.h> -#include <log.h> -#include <rtc.h> -#include <asm/io.h> - -struct ftrtc010 { - unsigned int sec; /* 0x00 */ - unsigned int min; /* 0x04 */ - unsigned int hour; /* 0x08 */ - unsigned int day; /* 0x0c */ - unsigned int alarm_sec; /* 0x10 */ - unsigned int alarm_min; /* 0x14 */ - unsigned int alarm_hour; /* 0x18 */ - unsigned int record; /* 0x1c */ - unsigned int cr; /* 0x20 */ - unsigned int wsec; /* 0x24 */ - unsigned int wmin; /* 0x28 */ - unsigned int whour; /* 0x2c */ - unsigned int wday; /* 0x30 */ - unsigned int intr; /* 0x34 */ - unsigned int div; /* 0x38 */ - unsigned int rev; /* 0x3c */ -}; - -/* - * RTC Control Register - */ -#define FTRTC010_CR_ENABLE (1 << 0) -#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ -#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ -#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ -#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ - -static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; - -static void ftrtc010_enable(void) -{ - writel(FTRTC010_CR_ENABLE, &rtc->cr); -} - -/* - * return current time in seconds - */ -static unsigned long ftrtc010_time(void) -{ - unsigned long day; - unsigned long hour; - unsigned long minute; - unsigned long second; - unsigned long second2; - - do { - second = readl(&rtc->sec); - day = readl(&rtc->day); - hour = readl(&rtc->hour); - minute = readl(&rtc->min); - second2 = readl(&rtc->sec); - } while (second != second2); - - return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; -} - -/* - * Get the current time from the RTC - */ - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - - debug("%s(): record register: %x\n", - __func__, readl(&rtc->record)); - -#ifdef CFG_FTRTC010_PCLK - now = (ftrtc010_time() + readl(&rtc->record)) / RTC_DIV_COUNT; -#else /* CFG_FTRTC010_EXTCLK */ - now = ftrtc010_time() + readl(&rtc->record); -#endif - - rtc_to_tm(now, tmp); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set(struct rtc_time *tmp) -{ - unsigned long new; - unsigned long now; - - debug("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - __func__, - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - new = rtc_mktime(tmp); - - now = ftrtc010_time(); - - debug("%s(): write %lx to record register\n", __func__, new - now); - - writel(new - now, &rtc->record); - - return 0; -} - -void rtc_reset(void) -{ - debug("%s()\n", __func__); - ftrtc010_enable(); -} diff --git a/drivers/rtc/imxdi.c b/drivers/rtc/imxdi.c deleted file mode 100644 index e3a1393266..0000000000 --- a/drivers/rtc/imxdi.c +++ /dev/null @@ -1,223 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009-2012 ADVANSEE - * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> - * - * Based on the Linux rtc-imxdi.c driver, which is: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - * Copyright 2010 Orex Computed Radiography - */ - -/* - * Date & Time support for Freescale i.MX DryIce RTC - */ - -#include <common.h> -#include <command.h> -#include <linux/compat.h> -#include <rtc.h> -#include <linux/delay.h> - -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -/* DryIce Register Definitions */ - -struct imxdi_regs { - u32 dtcmr; /* Time Counter MSB Reg */ - u32 dtclr; /* Time Counter LSB Reg */ - u32 dcamr; /* Clock Alarm MSB Reg */ - u32 dcalr; /* Clock Alarm LSB Reg */ - u32 dcr; /* Control Reg */ - u32 dsr; /* Status Reg */ - u32 dier; /* Interrupt Enable Reg */ -}; - -#define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */ - -#define DCR_TCE (1 << 3) /* Time Counter Enable */ - -#define DSR_WBF (1 << 10) /* Write Busy Flag */ -#define DSR_WNF (1 << 9) /* Write Next Flag */ -#define DSR_WCF (1 << 8) /* Write Complete Flag */ -#define DSR_WEF (1 << 7) /* Write Error Flag */ -#define DSR_CAF (1 << 4) /* Clock Alarm Flag */ -#define DSR_NVF (1 << 1) /* Non-Valid Flag */ -#define DSR_SVF (1 << 0) /* Security Violation Flag */ - -#define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */ -#define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */ -#define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */ -#define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */ - -/* Driver Private Data */ - -struct imxdi_data { - struct imxdi_regs __iomem *regs; - int init_done; -}; - -static struct imxdi_data data; - -/* - * This function attempts to clear the dryice write-error flag. - * - * A dryice write error is similar to a bus fault and should not occur in - * normal operation. Clearing the flag requires another write, so the root - * cause of the problem may need to be fixed before the flag can be cleared. - */ -static void clear_write_error(void) -{ - int cnt; - - puts("### Warning: RTC - Register write error!\n"); - - /* clear the write error flag */ - __raw_writel(DSR_WEF, &data.regs->dsr); - - /* wait for it to take effect */ - for (cnt = 0; cnt < 1000; cnt++) { - if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) - return; - udelay(10); - } - puts("### Error: RTC - Cannot clear write-error flag!\n"); -} - -/* - * Write a dryice register and wait until it completes. - * - * Use interrupt flags to determine when the write has completed. - */ -#define DI_WRITE_WAIT(val, reg) \ -( \ - /* do the register write */ \ - __raw_writel((val), &data.regs->reg), \ - \ - di_write_wait((val), #reg) \ -) -static int di_write_wait(u32 val, const char *reg) -{ - int cnt; - int ret = 0; - int rc = 0; - - /* wait for the write to finish */ - for (cnt = 0; cnt < 100; cnt++) { - if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { - ret = 1; - break; - } - udelay(10); - } - if (ret == 0) - printf("### Warning: RTC - Write-wait timeout " - "val = 0x%.8x reg = %s\n", val, reg); - - /* check for write error */ - if (__raw_readl(&data.regs->dsr) & DSR_WEF) { - clear_write_error(); - rc = -1; - } - - return rc; -} - -/* - * Initialize dryice hardware - */ -static int di_init(void) -{ - int rc = 0; - - data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE; - - /* mask all interrupts */ - __raw_writel(0, &data.regs->dier); - - /* put dryice into valid state */ - if (__raw_readl(&data.regs->dsr) & DSR_NVF) { - rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr); - if (rc) - goto err; - } - - /* initialize alarm */ - rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr); - if (rc) - goto err; - rc = DI_WRITE_WAIT(0, dcalr); - if (rc) - goto err; - - /* clear alarm flag */ - if (__raw_readl(&data.regs->dsr) & DSR_CAF) { - rc = DI_WRITE_WAIT(DSR_CAF, dsr); - if (rc) - goto err; - } - - /* the timer won't count if it has never been written to */ - if (__raw_readl(&data.regs->dtcmr) == 0) { - rc = DI_WRITE_WAIT(0, dtcmr); - if (rc) - goto err; - } - - /* start keeping time */ - if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { - rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); - if (rc) - goto err; - } - - data.init_done = 1; - return 0; - -err: - return rc; -} - -int rtc_get(struct rtc_time *tmp) -{ - unsigned long now; - int rc = 0; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = __raw_readl(&data.regs->dtcmr); - rtc_to_tm(now, tmp); - -err: - return rc; -} - -int rtc_set(struct rtc_time *tmp) -{ - unsigned long now; - int rc; - - if (!data.init_done) { - rc = di_init(); - if (rc) - goto err; - } - - now = rtc_mktime(tmp); - /* zero the fractional part first */ - rc = DI_WRITE_WAIT(0, dtclr); - if (rc == 0) - rc = DI_WRITE_WAIT(now, dtcmr); - -err: - return rc; -} - -void rtc_reset(void) -{ - di_init(); -} diff --git a/drivers/rtc/max6900.c b/drivers/rtc/max6900.c deleted file mode 100644 index e03a87f94d..0000000000 --- a/drivers/rtc/max6900.c +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * Date & Time support for MAXIM MAX6900 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> -#include <linux/delay.h> - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x50 -#endif - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read (uchar reg) -{ - return (i2c_reg_read (CFG_SYS_I2C_RTC_ADDR, reg)); -} - -static void rtc_write (uchar reg, uchar val) -{ - i2c_reg_write (CFG_SYS_I2C_RTC_ADDR, reg, val); - udelay(2500); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, mday, wday, mon, cent, year; - int retry = 1; - - do { - sec = rtc_read (0x80); - min = rtc_read (0x82); - hour = rtc_read (0x84); - mday = rtc_read (0x86); - mon = rtc_read (0x88); - wday = rtc_read (0x8a); - year = rtc_read (0x8c); - cent = rtc_read (0x92); - /* - * Check for seconds rollover - */ - if ((sec != 59) || (rtc_read(0x80) == sec)){ - retry = 0; - } - } while (retry); - - debug ( "Get RTC year: %02x mon: %02x cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, cent, mday, wday, - hour, min, sec ); - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year) + bcd2bin(cent) * 100; - tmp->tm_wday = bcd2bin (wday & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - rtc_write (0x9E, 0x00); - rtc_write (0x80, 0); /* Clear seconds to ensure no rollover */ - rtc_write (0x92, bin2bcd(tmp->tm_year / 100)); - rtc_write (0x8c, bin2bcd(tmp->tm_year % 100)); - rtc_write (0x8a, bin2bcd(tmp->tm_wday)); - rtc_write (0x88, bin2bcd(tmp->tm_mon)); - rtc_write (0x86, bin2bcd(tmp->tm_mday)); - rtc_write (0x84, bin2bcd(tmp->tm_hour)); - rtc_write (0x82, bin2bcd(tmp->tm_min )); - rtc_write (0x80, bin2bcd(tmp->tm_sec )); - - return 0; -} - -void rtc_reset (void) -{ -} diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c deleted file mode 100644 index 8c90a70407..0000000000 --- a/drivers/rtc/mk48t59.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - -#undef RTC_DEBUG - -#include <common.h> -#include <command.h> -#include <config.h> -#include <rtc.h> -#include <mk48t59.h> - -#if defined(CONFIG_BAB7xx) - -static uchar rtc_read (short reg) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - return in8(RTC_PORT_DATA); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC_PORT_ADDR0, reg & 0xFF); - out8(RTC_PORT_ADDR1, (reg>>8) & 0xFF); - out8(RTC_PORT_DATA, val); -} - -#elif defined(CONFIG_EVAL5200) - -static uchar rtc_read (short reg) -{ - return in8(RTC(reg)); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC(reg),val); -} - -#else -# error Board specific rtc access functions should be supplied -#endif - -/* ------------------------------------------------------------------------- */ - -void *nvram_read(void *dest, const short src, size_t count) -{ - uchar *d = (uchar *) dest; - short s = src; - - while (count--) - *d++ = rtc_read(s++); - - return dest; -} - -void nvram_write(short dest, const void *src, size_t count) -{ - short d = dest; - uchar *s = (uchar *) src; - - while (count--) - rtc_write(d++, *s++); -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - uchar sec, min, hour, mday, wday, mon, year; - - /* Simple: freeze the clock, read it and allow updates again */ - save_ctrl_a = rtc_read(RTC_CONTROLA); - - /* Set the register to read the value. */ - save_ctrl_a |= RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - - sec = rtc_read (RTC_SECONDS); - min = rtc_read (RTC_MINUTES); - hour = rtc_read (RTC_HOURS); - mday = rtc_read (RTC_DAY_OF_MONTH); - wday = rtc_read (RTC_DAY_OF_WEEK); - mon = rtc_read (RTC_MONTH); - year = rtc_read (RTC_YEAR); - - /* re-enable update */ - save_ctrl_a &= ~RTC_CA_READ; - rtc_write(RTC_CONTROLA, save_ctrl_a); - -#ifdef RTC_DEBUG - printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, - hour, min, sec ); -#endif - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (mday & 0x3F); - tmp->tm_mon = bcd2bin (mon & 0x1F); - tmp->tm_year = bcd2bin (year); - tmp->tm_wday = bcd2bin (wday & 0x07); - if(tmp->tm_year<70) - tmp->tm_year+=2000; - else - tmp->tm_year+=1900; - tmp->tm_yday = 0; - tmp->tm_isdst= 0; -#ifdef RTC_DEBUG - printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar save_ctrl_a; - -#ifdef RTC_DEBUG - printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - save_ctrl_a = rtc_read(RTC_CONTROLA); - - save_ctrl_a |= RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* disables the RTC to update the regs */ - - rtc_write (RTC_YEAR, bin2bcd(tmp->tm_year % 100)); - rtc_write (RTC_MONTH, bin2bcd(tmp->tm_mon)); - - rtc_write (RTC_DAY_OF_WEEK, bin2bcd(tmp->tm_wday)); - rtc_write (RTC_DAY_OF_MONTH, bin2bcd(tmp->tm_mday)); - rtc_write (RTC_HOURS, bin2bcd(tmp->tm_hour)); - rtc_write (RTC_MINUTES, bin2bcd(tmp->tm_min )); - rtc_write (RTC_SECONDS, bin2bcd(tmp->tm_sec )); - - save_ctrl_a &= ~RTC_CA_WRITE; - rtc_write(RTC_CONTROLA, save_ctrl_a); /* enables the RTC to update the regs */ - - return 0; -} - -void rtc_reset (void) -{ - uchar control_b; - - /* - * Start oscillator here. - */ - control_b = rtc_read(RTC_CONTROLB); - - control_b &= ~RTC_CB_STOP; - rtc_write(RTC_CONTROLB, control_b); -} - -void rtc_set_watchdog(short multi, short res) -{ - uchar wd_value; - - wd_value = RTC_WDS | ((multi & 0x1F) << 2) | (res & 0x3); - rtc_write(RTC_WATCHDOG, wd_value); -} diff --git a/drivers/rtc/mx27rtc.c b/drivers/rtc/mx27rtc.c deleted file mode 100644 index 563e8a4a36..0000000000 --- a/drivers/rtc/mx27rtc.c +++ /dev/null @@ -1,64 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Freescale i.MX27 RTC Driver - * - * Copyright (C) 2012 Philippe Reynes <tremyfr@yahoo.fr> - */ - -#include <common.h> -#include <rtc.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> - -#define HOUR_SHIFT 8 -#define HOUR_MASK 0x1f -#define MIN_SHIFT 0 -#define MIN_MASK 0x3f - -int rtc_get(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - day = readl(&rtc_regs->dayr); - hour = readl(&rtc_regs->hourmin); - sec = readl(&rtc_regs->seconds); - - min = (hour >> MIN_SHIFT) & MIN_MASK; - hour = (hour >> HOUR_SHIFT) & HOUR_MASK; - - sec += min * 60 + hour * 3600 + day * 24 * 3600; - - rtc_to_tm(sec, time); - - return 0; -} - -int rtc_set(struct rtc_time *time) -{ - struct rtc_regs *rtc_regs = (struct rtc_regs *)IMX_RTC_BASE; - uint32_t day, hour, min, sec; - - sec = rtc_mktime(time); - - day = sec / (24 * 3600); - sec = sec % (24 * 3600); - hour = sec / 3600; - sec = sec % 3600; - min = sec / 60; - sec = sec % 60; - - hour = (hour & HOUR_MASK) << HOUR_SHIFT; - hour |= (min & MIN_MASK) << MIN_SHIFT; - - writel(day, &rtc_regs->dayr); - writel(hour, &rtc_regs->hourmin); - writel(sec, &rtc_regs->seconds); - - return 0; -} - -void rtc_reset(void) -{ - /* nothing to do */ -} diff --git a/drivers/rtc/rs5c372.c b/drivers/rtc/rs5c372.c deleted file mode 100644 index 6b1c23ca5d..0000000000 --- a/drivers/rtc/rs5c372.c +++ /dev/null @@ -1,256 +0,0 @@ -/* - * rs5c372.c - * - * Device driver for Ricoh's Real Time Controller RS5C372A. - * - * Copyright (C) 2004 Gary Jennejohn garyj@denx.de - * - * Based in part in ds1307.c - - * (C) Copyright 2001, 2002, 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * Keith Outwater, keith_outwater@mvis.com` - * Steven Scholz, steven.scholz@imc-berlin.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <i2c.h> - -/* - * Reads are always done starting with register 15, which requires some - * jumping-through-hoops to access the data correctly. - * - * Writes are always done starting with register 0. - */ - -#define DEBUG 0 - -#if DEBUG -static unsigned int rtc_debug = DEBUG; -#else -#define rtc_debug 0 /* gcc will remove all the debug code for us */ -#endif - -#ifndef CFG_SYS_I2C_RTC_ADDR -#define CFG_SYS_I2C_RTC_ADDR 0x32 -#endif - -#define RS5C372_RAM_SIZE 0x10 -#define RATE_32000HZ 0x80 /* Rate Select 32.000KHz */ -#define RATE_32768HZ 0x00 /* Rate Select 32.768KHz */ - -#define STATUS_XPT 0x10 /* data invalid because voltage was 0 */ - -#define USE_24HOUR_MODE 0x20 -#define TWELVE_HOUR_MODE(n) ((((n) >> 5) & 1) == 0) -#define HOURS_AP(n) (((n) >> 5) & 1) -#define HOURS_12(n) bcd2bin((n) & 0x1F) -#define HOURS_24(n) bcd2bin((n) & 0x3F) - - -static int setup_done = 0; - -static int -rs5c372_readram(unsigned char *buf, int len) -{ - int ret; - - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, len); - if (ret != 0) { - printf("%s: failed to read\n", __FUNCTION__); - return ret; - } - - if (buf[0] & STATUS_XPT) - printf("### Warning: RTC lost power\n"); - - return ret; -} - -static void -rs5c372_enable(void) -{ - unsigned char buf[RS5C372_RAM_SIZE + 1]; - int ret; - - /* note that this returns reg. 15 in buf[1] */ - ret = rs5c372_readram(&buf[1], RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - - buf[0] = 0; - /* we want to start writing at register 0 so we have to copy the */ - /* register contents up one slot */ - for (ret = 2; ret < 9; ret++) - buf[ret - 1] = buf[ret]; - /* registers 0 to 6 (time values) are not touched */ - buf[8] = RATE_32768HZ; /* reg. 7 */ - buf[9] = 0; /* reg. 8 */ - buf[10] = 0; /* reg. 9 */ - buf[11] = 0; /* reg. 10 */ - buf[12] = 0; /* reg. 11 */ - buf[13] = 0; /* reg. 12 */ - buf[14] = 0; /* reg. 13 */ - buf[15] = 0; /* reg. 14 */ - buf[16] = USE_24HOUR_MODE; /* reg. 15 */ - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, RS5C372_RAM_SIZE+1); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return; - } - setup_done = 1; - - return; -} - -static void -rs5c372_convert_to_time(struct rtc_time *dt, unsigned char *buf) -{ - /* buf[0] is register 15 */ - dt->tm_sec = bcd2bin(buf[1]); - dt->tm_min = bcd2bin(buf[2]); - - if (TWELVE_HOUR_MODE(buf[0])) { - dt->tm_hour = HOURS_12(buf[3]); - if (HOURS_AP(buf[3])) /* PM */ - dt->tm_hour += 12; - } else /* 24-hour-mode */ - dt->tm_hour = HOURS_24(buf[3]); - - dt->tm_mday = bcd2bin(buf[5]); - dt->tm_mon = bcd2bin(buf[6]); - dt->tm_year = bcd2bin(buf[7]); - if (dt->tm_year >= 70) - dt->tm_year += 1900; - else - dt->tm_year += 2000; - /* 0 is Sunday */ - dt->tm_wday = bcd2bin(buf[4] & 0x07); - dt->tm_yday = 0; - dt->tm_isdst= 0; - - if(rtc_debug > 2) { - printf("rs5c372_convert_to_time: year = %d\n", dt->tm_year); - printf("rs5c372_convert_to_time: mon = %d\n", dt->tm_mon); - printf("rs5c372_convert_to_time: mday = %d\n", dt->tm_mday); - printf("rs5c372_convert_to_time: hour = %d\n", dt->tm_hour); - printf("rs5c372_convert_to_time: min = %d\n", dt->tm_min); - printf("rs5c372_convert_to_time: sec = %d\n", dt->tm_sec); - } -} - -/* - * Get the current time from the RTC - */ -int -rtc_get (struct rtc_time *tmp) -{ - unsigned char buf[RS5C372_RAM_SIZE]; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - memset(buf, 0, sizeof(buf)); - - /* note that this returns reg. 15 in buf[0] */ - ret = rs5c372_readram(buf, RS5C372_RAM_SIZE); - if (ret != 0) { - printf("%s: failed\n", __FUNCTION__); - return -1; - } - - rs5c372_convert_to_time(tmp, buf); - - return 0; -} - -/* - * Set the RTC - */ -int rtc_set (struct rtc_time *tmp) -{ - unsigned char buf[8], reg15; - int ret; - - if (!setup_done) - rs5c372_enable(); - - if (!setup_done) - return -1; - - if(rtc_debug > 2) { - printf("rtc_set: tm_year = %d\n", tmp->tm_year); - printf("rtc_set: tm_mon = %d\n", tmp->tm_mon); - printf("rtc_set: tm_mday = %d\n", tmp->tm_mday); - printf("rtc_set: tm_hour = %d\n", tmp->tm_hour); - printf("rtc_set: tm_min = %d\n", tmp->tm_min); - printf("rtc_set: tm_sec = %d\n", tmp->tm_sec); - } - - memset(buf, 0, sizeof(buf)); - - /* only read register 15 */ - ret = i2c_read(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 1); - - if (ret == 0) { - /* need to save register 15 */ - reg15 = buf[0]; - buf[0] = 0; /* register address on RS5C372 */ - buf[1] = bin2bcd(tmp->tm_sec); - buf[2] = bin2bcd(tmp->tm_min); - /* need to handle 12 hour mode */ - if (TWELVE_HOUR_MODE(reg15)) { - if (tmp->tm_hour >= 12) { /* PM */ - /* 12 PM is a special case */ - if (tmp->tm_hour == 12) - buf[3] = bin2bcd(tmp->tm_hour); - else - buf[3] = bin2bcd(tmp->tm_hour - 12); - buf[3] |= 0x20; - } - } else { - buf[3] = bin2bcd(tmp->tm_hour); - } - - buf[4] = bin2bcd(tmp->tm_wday); - buf[5] = bin2bcd(tmp->tm_mday); - buf[6] = bin2bcd(tmp->tm_mon); - if (tmp->tm_year < 1970 || tmp->tm_year > 2069) - printf("WARNING: year should be between 1970 and 2069!\n"); - buf[7] = bin2bcd(tmp->tm_year % 100); - - ret = i2c_write(CFG_SYS_I2C_RTC_ADDR, 0, 0, buf, 8); - if (ret != 0) { - printf("rs5c372_set_datetime(), i2c_master_send() returned %d\n",ret); - return -1; - } - } else { - return -1; - } - - return 0; -} - -/* - * Reset the RTC. - */ -void -rtc_reset (void) -{ - if (!setup_done) - rs5c372_enable(); -} diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c deleted file mode 100644 index 96ea3cf878..0000000000 --- a/drivers/rtc/s3c24x0_rtc.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - */ - -/* - * Date & Time support for the built-in Samsung S3C24X0 RTC - */ - -#include <common.h> -#include <command.h> - -#include <asm/arch/s3c24x0_cpu.h> - -#include <rtc.h> -#include <asm/io.h> -#include <linux/compiler.h> - -typedef enum { - RTC_ENABLE, - RTC_DISABLE -} RTC_ACCESS; - - -static inline void SetRTC_Access(RTC_ACCESS a) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - switch (a) { - case RTC_ENABLE: - writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); - break; - - case RTC_DISABLE: - writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); - break; - } -} - -/* ------------------------------------------------------------------------- */ - -int rtc_get(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - __maybe_unused uchar a_sec, a_min, a_hour, a_date, - a_mon, a_year, a_armed; - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* read RTC registers */ - do { - sec = readb(&rtc->bcdsec); - min = readb(&rtc->bcdmin); - hour = readb(&rtc->bcdhour); - mday = readb(&rtc->bcddate); - wday = readb(&rtc->bcdday); - mon = readb(&rtc->bcdmon); - year = readb(&rtc->bcdyear); - } while (sec != readb(&rtc->bcdsec)); - - /* read ALARM registers */ - a_sec = readb(&rtc->almsec); - a_min = readb(&rtc->almmin); - a_hour = readb(&rtc->almhour); - a_date = readb(&rtc->almdate); - a_mon = readb(&rtc->almmon); - a_year = readb(&rtc->almyear); - a_armed = readb(&rtc->rtcalm); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - -#ifdef RTC_DEBUG - printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, mon, mday, wday, hour, min, sec); - printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: " - "%02x min: %02x sec: %02x\n", - a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec); -#endif - - tmp->tm_sec = bcd2bin(sec & 0x7F); - tmp->tm_min = bcd2bin(min & 0x7F); - tmp->tm_hour = bcd2bin(hour & 0x3F); - tmp->tm_mday = bcd2bin(mday & 0x3F); - tmp->tm_mon = bcd2bin(mon & 0x1F); - tmp->tm_year = bcd2bin(year); - tmp->tm_wday = bcd2bin(wday & 0x07); - if (tmp->tm_year < 70) - tmp->tm_year += 2000; - else - tmp->tm_year += 1900; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; -#ifdef RTC_DEBUG - printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - - return 0; -} - -int rtc_set(struct rtc_time *tmp) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - uchar sec, min, hour, mday, wday, mon, year; - -#ifdef RTC_DEBUG - printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); -#endif - year = bin2bcd(tmp->tm_year % 100); - mon = bin2bcd(tmp->tm_mon); - wday = bin2bcd(tmp->tm_wday); - mday = bin2bcd(tmp->tm_mday); - hour = bin2bcd(tmp->tm_hour); - min = bin2bcd(tmp->tm_min); - sec = bin2bcd(tmp->tm_sec); - - /* enable access to RTC registers */ - SetRTC_Access(RTC_ENABLE); - - /* write RTC registers */ - writeb(sec, &rtc->bcdsec); - writeb(min, &rtc->bcdmin); - writeb(hour, &rtc->bcdhour); - writeb(mday, &rtc->bcddate); - writeb(wday, &rtc->bcdday); - writeb(mon, &rtc->bcdmon); - writeb(year, &rtc->bcdyear); - - /* disable access to RTC registers */ - SetRTC_Access(RTC_DISABLE); - - return 0; -} - -void rtc_reset(void) -{ - struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc(); - - writeb((readb(&rtc->rtccon) & ~0x06) | 0x08, &rtc->rtccon); - writeb(readb(&rtc->rtccon) & ~(0x08 | 0x01), &rtc->rtccon); -} diff --git a/drivers/rtc/x1205.c b/drivers/rtc/x1205.c deleted file mode 100644 index 4a8d1c5903..0000000000 --- a/drivers/rtc/x1205.c +++ /dev/null @@ -1,161 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * based on a the Linux rtc-x1207.c driver which is: - * Copyright 2004 Karen Spearel - * Copyright 2005 Alessandro Zummo - * - * Information and datasheet: - * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html - */ - -/* - * Date & Time support for Xicor/Intersil X1205 RTC - */ - -/* #define DEBUG */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <rtc.h> -#include <i2c.h> - -#define CCR_SEC 0 -#define CCR_MIN 1 -#define CCR_HOUR 2 -#define CCR_MDAY 3 -#define CCR_MONTH 4 -#define CCR_YEAR 5 -#define CCR_WDAY 6 -#define CCR_Y2K 7 - -#define X1205_REG_SR 0x3F /* status register */ -#define X1205_REG_Y2K 0x37 -#define X1205_REG_DW 0x36 -#define X1205_REG_YR 0x35 -#define X1205_REG_MO 0x34 -#define X1205_REG_DT 0x33 -#define X1205_REG_HR 0x32 -#define X1205_REG_MN 0x31 -#define X1205_REG_SC 0x30 -#define X1205_REG_DTR 0x13 -#define X1205_REG_ATR 0x12 -#define X1205_REG_INT 0x11 -#define X1205_REG_0 0x10 -#define X1205_REG_Y2K1 0x0F -#define X1205_REG_DWA1 0x0E -#define X1205_REG_YRA1 0x0D -#define X1205_REG_MOA1 0x0C -#define X1205_REG_DTA1 0x0B -#define X1205_REG_HRA1 0x0A -#define X1205_REG_MNA1 0x09 -#define X1205_REG_SCA1 0x08 -#define X1205_REG_Y2K0 0x07 -#define X1205_REG_DWA0 0x06 -#define X1205_REG_YRA0 0x05 -#define X1205_REG_MOA0 0x04 -#define X1205_REG_DTA0 0x03 -#define X1205_REG_HRA0 0x02 -#define X1205_REG_MNA0 0x01 -#define X1205_REG_SCA0 0x00 - -#define X1205_CCR_BASE 0x30 /* Base address of CCR */ -#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ - -#define X1205_SR_RTCF 0x01 /* Clock failure */ -#define X1205_SR_WEL 0x02 /* Write Enable Latch */ -#define X1205_SR_RWEL 0x04 /* Register Write Enable */ - -#define X1205_DTR_DTR0 0x01 -#define X1205_DTR_DTR1 0x02 -#define X1205_DTR_DTR2 0x04 - -#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ - -static void rtc_write(int reg, u8 val) -{ - i2c_write(CFG_SYS_I2C_RTC_ADDR, reg, 2, &val, 1); -} - -/* - * In the routines that deal directly with the x1205 hardware, we use - * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch - * Epoch is initialized as 2000. Time is set to UTC. - */ -int rtc_get(struct rtc_time *tm) -{ - u8 buf[8]; - - i2c_read(CFG_SYS_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); - - debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " - "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", - __FUNCTION__, - buf[0], buf[1], buf[2], buf[3], - buf[4], buf[5], buf[6], buf[7]); - - tm->tm_sec = bcd2bin(buf[CCR_SEC]); - tm->tm_min = bcd2bin(buf[CCR_MIN]); - tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ - tm->tm_mday = bcd2bin(buf[CCR_MDAY]); - tm->tm_mon = bcd2bin(buf[CCR_MONTH]); /* mon is 0-11 */ - tm->tm_year = bcd2bin(buf[CCR_YEAR]) - + (bcd2bin(buf[CCR_Y2K]) * 100); - tm->tm_wday = buf[CCR_WDAY]; - - debug("%s: tm is secs=%d, mins=%d, hours=%d, " - "mday=%d, mon=%d, year=%d, wday=%d\n", - __FUNCTION__, - tm->tm_sec, tm->tm_min, tm->tm_hour, - tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); - - return 0; -} - -int rtc_set(struct rtc_time *tm) -{ - int i; - u8 buf[8]; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, - tm->tm_hour, tm->tm_min, tm->tm_sec); - - buf[CCR_SEC] = bin2bcd(tm->tm_sec); - buf[CCR_MIN] = bin2bcd(tm->tm_min); - - /* set hour and 24hr bit */ - buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL; - - buf[CCR_MDAY] = bin2bcd(tm->tm_mday); - - /* month, 1 - 12 */ - buf[CCR_MONTH] = bin2bcd(tm->tm_mon); - - /* year, since the rtc epoch*/ - buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100); - buf[CCR_WDAY] = tm->tm_wday & 0x07; - buf[CCR_Y2K] = bin2bcd(tm->tm_year / 100); - - /* this sequence is required to unlock the chip */ - rtc_write(X1205_REG_SR, X1205_SR_WEL); - rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); - - /* write register's data */ - for (i = 0; i < 8; i++) - rtc_write(X1205_CCR_BASE + i, buf[i]); - - rtc_write(X1205_REG_SR, 0); - - return 0; -} - -void rtc_reset(void) -{ - /* - * Nothing to do - */ -} diff --git a/drivers/serial/serial_bcm283x_mu.c b/drivers/serial/serial_bcm283x_mu.c index 12cbcb9858..7585f790d2 100644 --- a/drivers/serial/serial_bcm283x_mu.c +++ b/drivers/serial/serial_bcm283x_mu.c @@ -197,7 +197,7 @@ U_BOOT_DRIVER(serial_bcm283x_mu) = { .plat_auto = sizeof(struct bcm283x_mu_serial_plat), .probe = bcm283x_mu_serial_probe, .ops = &bcm283x_mu_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) +#if !CONFIG_IS_ENABLED(OF_CONTROL) || IS_ENABLED(CONFIG_OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif .priv_auto = sizeof(struct bcm283x_mu_priv), diff --git a/drivers/serial/serial_bcm283x_pl011.c b/drivers/serial/serial_bcm283x_pl011.c index 7d172cdac0..09a9868a38 100644 --- a/drivers/serial/serial_bcm283x_pl011.c +++ b/drivers/serial/serial_bcm283x_pl011.c @@ -94,7 +94,7 @@ U_BOOT_DRIVER(bcm283x_pl011_uart) = { .probe = bcm283x_pl011_serial_probe, .plat_auto = sizeof(struct pl01x_serial_plat), .ops = &bcm283x_pl011_serial_ops, -#if !CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_BOARD) +#if !CONFIG_IS_ENABLED(OF_CONTROL) || IS_ENABLED(CONFIG_OF_BOARD) .flags = DM_FLAG_PRE_RELOC, #endif .priv_auto = sizeof(struct pl01x_priv), diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 8bcbbf2bbf..cc85a50272 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -13,6 +13,7 @@ #include <dm/platform_data/serial_mxc.h> #include <serial.h> #include <linux/compiler.h> +#include <linux/delay.h> /* UART Control Register Bit Fields.*/ #define URXD_CHARRDY (1<<15) @@ -144,8 +145,22 @@ struct mxc_uart { u32 ts; }; +static void _mxc_serial_flush(struct mxc_uart *base) +{ + unsigned int timeout = 4000; + + if (!(readl(&base->cr1) & UCR1_UARTEN) || + !(readl(&base->cr2) & UCR2_TXEN)) + return; + + while (!(readl(&base->sr2) & USR2_TXDC) && --timeout) + udelay(1); +} + static void _mxc_serial_init(struct mxc_uart *base, int use_dte) { + _mxc_serial_flush(base); + writel(0, &base->cr1); writel(0, &base->cr2); @@ -169,6 +184,8 @@ static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk, { u32 tmp; + _mxc_serial_flush(base); + tmp = RFDIV << UFCR_RFDIV_SHF; if (use_dte) tmp |= UFCR_DCEDTE; @@ -223,11 +240,11 @@ static void mxc_serial_putc(const char c) if (c == '\n') serial_putc('\r'); - writel(c, &mxc_base->txd); - /* wait for transmitter to be ready */ - while (!(readl(&mxc_base->ts) & UTS_TXEMPTY)) + while (readl(&mxc_base->ts) & UTS_TXFULL) schedule(); + + writel(c, &mxc_base->txd); } /* Test whether a character is in the RX buffer */ @@ -252,10 +269,17 @@ static int mxc_serial_init(void) return 0; } +static int mxc_serial_stop(void) +{ + _mxc_serial_flush(mxc_base); + + return 0; +} + static struct serial_device mxc_serial_drv = { .name = "mxc_serial", .start = mxc_serial_init, - .stop = NULL, + .stop = mxc_serial_stop, .setbrg = mxc_serial_setbrg, .putc = mxc_serial_putc, .puts = default_serial_puts, @@ -311,7 +335,7 @@ static int mxc_serial_putc(struct udevice *dev, const char ch) struct mxc_serial_plat *plat = dev_get_plat(dev); struct mxc_uart *const uart = plat->reg; - if (!(readl(&uart->ts) & UTS_TXEMPTY)) + if (readl(&uart->ts) & UTS_TXFULL) return -EAGAIN; writel(ch, &uart->txd); diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index e6ab6f1b9b..660aaab663 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -13,7 +13,6 @@ struct uart_port { }; #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ # define PORT_PTCR 0xA405011EUL @@ -149,7 +148,6 @@ struct uart_port { #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCIF_ORER 0x0200 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) @@ -197,7 +195,6 @@ struct uart_port { (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) #if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) @@ -278,8 +275,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ SCI_OUT(sci_size, sci_offset, value);\ } -#if defined(CONFIG_SH73A0) || \ - defined(CONFIG_R8A7740) +#if defined(CONFIG_R8A7740) #if defined(CONFIG_CPU_SH7721) || \ defined(CONFIG_SH73A0) #define SCIF_FNS(name, scif_offset, scif_size) \ @@ -323,8 +319,7 @@ static inline void sci_##name##_out(struct uart_port *port,\ CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) #endif -#if defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) +#if defined(CONFIG_CPU_SH7721) SCIF_FNS(SCSMR, 0x00, 16) SCIF_FNS(SCBRR, 0x04, 8) @@ -477,7 +472,6 @@ static inline int sci_rxd_in(struct uart_port *port) #if defined(CONFIG_CPU_SH7780) #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) #elif defined(CONFIG_CPU_SH7721) || \ - defined(CONFIG_SH73A0) || \ defined(CONFIG_R8A7740) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 4b1818313a..9bb9b7d3b8 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -108,7 +108,7 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (CONFIG_IS_ENABLED(DEBUG_UART_ZYNQ)) { + if (IS_ENABLED(CONFIG_DEBUG_UART_ZYNQ)) { if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) return -EAGAIN; } else { diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index e0d5e6b9e6..434c6038f3 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -216,7 +216,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev) void cadence_qspi_apb_enable_linear_mode(bool enable) { - if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) { + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) { if (enable) /* ahb read mode */ xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI, diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 328dfb0a38..c7f10c5013 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -215,7 +215,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->tchsh_ns = plat->tchsh_ns; priv->tslch_ns = plat->tslch_ns; - if (CONFIG_IS_ENABLED(ZYNQMP_FIRMWARE)) + if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI, ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS, ZYNQMP_PM_REQUEST_ACK_NO, NULL); @@ -249,7 +249,7 @@ static int cadence_spi_probe(struct udevice *bus) priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz); - if (CONFIG_IS_ENABLED(ARCH_VERSAL)) { + if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { /* Versal platform uses spi calibration to set read delay */ if (priv->read_delay >= 0) priv->read_delay = -1; diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index 0ed3bbf356..40c876764a 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -20,6 +20,6 @@ obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o -obj-$(CONFIG_SYSRESET_$(SPL_TPL_)AT91) += sysreset_at91.o +obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/sysreset/sysreset_mpc83xx.c b/drivers/sysreset/sysreset_mpc83xx.c index 81fccf9576..c9a0326659 100644 --- a/drivers/sysreset/sysreset_mpc83xx.c +++ b/drivers/sysreset/sysreset_mpc83xx.c @@ -120,7 +120,7 @@ static int print_83xx_arb_event(bool force, char *buf, int size) "Master ID", mstr_id, master[mstr_id], "Transfer Size", tsize_val, tsize_bytes, "Transfer Type", ttype, transfer[ttype]); - } else if (CONFIG_IS_ENABLED(DISPLAY_AER_BRIEF)) { + } else if (IS_ENABLED(CONFIG_DISPLAY_AER_BRIEF)) { res = snprintf(buf, size, "Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", gd->arch.arbiter_event_attributes, @@ -185,7 +185,7 @@ static int mpc83xx_sysreset_get_status(struct udevice *dev, char *buf, int size) * arbiter driver */ if (CONFIG_IS_ENABLED(DISPLAY_AER_FULL) || - CONFIG_IS_ENABLED(DISPLAY_AER_BRIEF)) { + IS_ENABLED(CONFIG_DISPLAY_AER_BRIEF)) { /* * If there was a bus monitor reset event, we force the arbiter * event to be printed diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6d6665005c..f32bd16227 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -252,6 +252,14 @@ config STM32_TIMER Select this to enable support for the timer found on STM32 devices. +config TEGRA_TIMER + bool "Tegra timer support" + depends on TIMER + select TIMER_EARLY + help + Select this to enable support for the timer found on + Tegra devices. + config X86_TSC_TIMER bool "x86 Time-Stamp Counter (TSC) timer support" depends on TIMER && X86 diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 6470fd5426..3c92113fc6 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c new file mode 100644 index 0000000000..a867c649c3 --- /dev/null +++ b/drivers/timer/tegra-timer.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/tegra.h> + +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) + +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) + +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ + +/* + * On pre-DM stage timer should be left configured by + * previous bootloader for correct 1MHz clock. + * In the case of reset default value is set to 1/13 of + * CLK_M which should be decent enough to safely + * get to DM stage. + */ +u64 notrace timer_early_get_count(void) +{ + /* At this stage raw timer is used */ + return readl(TEGRA_TIMER_USEC_CNTR); +} + +unsigned long notrace timer_early_get_rate(void) +{ + return TEGRA_TIMER_RATE; +} + +ulong timer_get_boot_us(void) +{ + return timer_early_get_count(); +} + +/* + * At moment of calling get_count, timer driver is already + * probed and is configured to have precise 1MHz clock. + * Tegra timer has a step of 1 microsecond which removes + * need of using adjusments involving uc_priv->clock_rate. + */ +static notrace u64 tegra_timer_get_count(struct udevice *dev) +{ + u32 val = timer_early_get_count(); + return timer_conv_64(val); +} + +static int tegra_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 usec_config, value; + + /* Timer rate has to be set unconditionally */ + uc_priv->clock_rate = TEGRA_TIMER_RATE; + + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (clock_get_rate(CLOCK_ID_CLK_M)) { + case 12000000: + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ + break; + case 13000000: + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ + break; + case 19200000: + usec_config = 0x045f; /* (95+1)/(4+1) */ + break; + case 26000000: + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ + break; + default: + return -EINVAL; + } + + /* Enable clock to timer hardware */ + value = readl_relaxed(TEGRA_OSC_CLK_ENB_L_SET); + writel_relaxed(value | TEGRA_OSC_SET_CLK_ENB_TMR, + TEGRA_OSC_CLK_ENB_L_SET); + + writel_relaxed(usec_config, TEGRA_TIMER_USEC_CFG); + + return 0; +} + +static const struct timer_ops tegra_timer_ops = { + .get_count = tegra_timer_get_count, +}; + +static const struct udevice_id tegra_timer_ids[] = { + { .compatible = "nvidia,tegra20-timer" }, + { .compatible = "nvidia,tegra30-timer" }, + { .compatible = "nvidia,tegra114-timer" }, + { .compatible = "nvidia,tegra124-timer" }, + { .compatible = "nvidia,tegra210-timer" }, + { } +}; + +U_BOOT_DRIVER(tegra_timer) = { + .name = "tegra_timer", + .id = UCLASS_TIMER, + .of_match = tegra_timer_ids, + .probe = tegra_timer_probe, + .ops = &tegra_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index bb71979213..f4b871ac23 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -136,7 +136,7 @@ u64 timer_conv_64(u32 count) return ((u64)gd->timebase_h << 32) | gd->timebase_l; } -int notrace dm_timer_init(void) +int dm_timer_init(void) { struct udevice *dev = NULL; __maybe_unused ofnode node; diff --git a/drivers/tpm/tpm-uclass.c b/drivers/tpm/tpm-uclass.c index 5ff0cd3958..b2286f7e7e 100644 --- a/drivers/tpm/tpm-uclass.c +++ b/drivers/tpm/tpm-uclass.c @@ -156,7 +156,7 @@ static int tpm_uclass_post_probe(struct udevice *dev) const char *drv = TPM_RNG_DRV_NAME; struct udevice *child; - if (CONFIG_IS_ENABLED(TPM_RNG)) { + if (IS_ENABLED(CONFIG_TPM_RNG)) { ret = device_find_first_child_by_uclass(dev, UCLASS_RNG, &child); diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c index 90418ddc1d..c62e42de73 100644 --- a/drivers/usb/dwc3/dwc3-meson-g12a.c +++ b/drivers/usb/dwc3/dwc3-meson-g12a.c @@ -455,6 +455,22 @@ static int dwc3_meson_g12a_remove(struct udevice *dev) return dm_scan_fdt_dev(dev); } +static int dwc3_meson_g12a_child_pre_probe(struct udevice *dev) +{ + if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb")) + return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL); + + return 0; +} + +static int dwc3_meson_g12a_child_post_remove(struct udevice *dev) +{ + if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb")) + return dwc3_meson_g12a_force_mode(dev->parent, USB_DR_MODE_HOST); + + return 0; +} + static const struct udevice_id dwc3_meson_g12a_ids[] = { { .compatible = "amlogic,meson-g12a-usb-ctrl" }, { } @@ -466,6 +482,8 @@ U_BOOT_DRIVER(dwc3_generic_wrapper) = { .of_match = dwc3_meson_g12a_ids, .probe = dwc3_meson_g12a_probe, .remove = dwc3_meson_g12a_remove, + .child_pre_probe = dwc3_meson_g12a_child_pre_probe, + .child_post_remove = dwc3_meson_g12a_child_post_remove, .plat_auto = sizeof(struct dwc3_meson_g12a), }; diff --git a/drivers/usb/dwc3/dwc3-meson-gxl.c b/drivers/usb/dwc3/dwc3-meson-gxl.c index 6c6d463203..d56f2747b6 100644 --- a/drivers/usb/dwc3/dwc3-meson-gxl.c +++ b/drivers/usb/dwc3/dwc3-meson-gxl.c @@ -408,6 +408,22 @@ static int dwc3_meson_gxl_remove(struct udevice *dev) return dm_scan_fdt_dev(dev); } +static int dwc3_meson_gxl_child_pre_probe(struct udevice *dev) +{ + if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb")) + return dwc3_meson_gxl_force_mode(dev->parent, USB_DR_MODE_PERIPHERAL); + + return 0; +} + +static int dwc3_meson_gxl_child_post_remove(struct udevice *dev) +{ + if (ofnode_device_is_compatible(dev_ofnode(dev), "amlogic,meson-g12a-usb")) + return dwc3_meson_gxl_force_mode(dev->parent, USB_DR_MODE_HOST); + + return 0; +} + static const struct udevice_id dwc3_meson_gxl_ids[] = { { .compatible = "amlogic,meson-axg-usb-ctrl" }, { .compatible = "amlogic,meson-gxl-usb-ctrl" }, @@ -421,6 +437,8 @@ U_BOOT_DRIVER(dwc3_generic_wrapper) = { .of_match = dwc3_meson_gxl_ids, .probe = dwc3_meson_gxl_probe, .remove = dwc3_meson_gxl_remove, + .child_pre_probe = dwc3_meson_gxl_child_pre_probe, + .child_post_remove = dwc3_meson_gxl_child_post_remove, .plat_auto = sizeof(struct dwc3_meson_gxl), }; diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 9c04403da3..6cfe0f3a04 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -19,7 +19,6 @@ obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o obj-$(CONFIG_USB_GADGET_DWC2_OTG) += dwc2_udc_otg.o obj-$(CONFIG_USB_GADGET_DWC2_OTG_PHY) += dwc2_udc_otg_phy.o -obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o obj-$(CONFIG_USB_GADGET_MAX3420) += max3420_udc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o diff --git a/drivers/usb/gadget/fotg210.c b/drivers/usb/gadget/fotg210.c deleted file mode 100644 index af43433d88..0000000000 --- a/drivers/usb/gadget/fotg210.c +++ /dev/null @@ -1,964 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday USB 2.0 OTG Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#include <common.h> -#include <command.h> -#include <config.h> -#include <cpu_func.h> -#include <log.h> -#include <net.h> -#include <malloc.h> -#include <asm/io.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <linux/types.h> -#include <linux/usb/ch9.h> -#include <linux/usb/gadget.h> - -#include <usb/fotg210.h> - -#define CFG_NUM_ENDPOINTS 4 -#define CFG_EP0_MAX_PACKET_SIZE 64 -#define CFG_EPX_MAX_PACKET_SIZE 512 - -#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */ - -struct fotg210_chip; - -struct fotg210_ep { - struct usb_ep ep; - - uint maxpacket; - uint id; - uint stopped; - - struct list_head queue; - struct fotg210_chip *chip; - const struct usb_endpoint_descriptor *desc; -}; - -struct fotg210_request { - struct usb_request req; - struct list_head queue; - struct fotg210_ep *ep; -}; - -struct fotg210_chip { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct fotg210_regs *regs; - uint8_t irq; - uint16_t addr; - int pullup; - enum usb_device_state state; - struct fotg210_ep ep[1 + CFG_NUM_ENDPOINTS]; -}; - -static struct usb_endpoint_descriptor ep0_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_IN, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static inline int fifo_to_ep(struct fotg210_chip *chip, int id, int in) -{ - return (id < 0) ? 0 : ((id & 0x03) + 1); -} - -static inline int ep_to_fifo(struct fotg210_chip *chip, int id) -{ - return (id <= 0) ? -1 : ((id - 1) & 0x03); -} - -static inline int ep_reset(struct fotg210_chip *chip, uint8_t ep_addr) -{ - int ep = ep_addr & USB_ENDPOINT_NUMBER_MASK; - struct fotg210_regs *regs = chip->regs; - - if (ep_addr & USB_DIR_IN) { - /* reset endpoint */ - setbits_le32(®s->iep[ep - 1], IEP_RESET); - mdelay(1); - clrbits_le32(®s->iep[ep - 1], IEP_RESET); - /* clear endpoint stall */ - clrbits_le32(®s->iep[ep - 1], IEP_STALL); - } else { - /* reset endpoint */ - setbits_le32(®s->oep[ep - 1], OEP_RESET); - mdelay(1); - clrbits_le32(®s->oep[ep - 1], OEP_RESET); - /* clear endpoint stall */ - clrbits_le32(®s->oep[ep - 1], OEP_STALL); - } - - return 0; -} - -static int fotg210_reset(struct fotg210_chip *chip) -{ - struct fotg210_regs *regs = chip->regs; - uint32_t i; - - chip->state = USB_STATE_POWERED; - - /* chip enable */ - writel(DEVCTRL_EN, ®s->dev_ctrl); - - /* device address reset */ - chip->addr = 0; - writel(0, ®s->dev_addr); - - /* set idle counter to 7ms */ - writel(7, ®s->idle); - - /* disable all interrupts */ - writel(IMR_MASK, ®s->imr); - writel(GIMR_MASK, ®s->gimr); - writel(GIMR0_MASK, ®s->gimr0); - writel(GIMR1_MASK, ®s->gimr1); - writel(GIMR2_MASK, ®s->gimr2); - - /* clear interrupts */ - writel(ISR_MASK, ®s->isr); - writel(0, ®s->gisr); - writel(0, ®s->gisr0); - writel(0, ®s->gisr1); - writel(0, ®s->gisr2); - - /* chip reset */ - setbits_le32(®s->dev_ctrl, DEVCTRL_RESET); - mdelay(10); - if (readl(®s->dev_ctrl) & DEVCTRL_RESET) { - printf("fotg210: chip reset failed\n"); - return -1; - } - - /* CX FIFO reset */ - setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR); - mdelay(10); - if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) { - printf("fotg210: ep0 fifo reset failed\n"); - return -1; - } - - /* create static ep-fifo map (EP1 <-> FIFO0, EP2 <-> FIFO1 ...) */ - writel(EPMAP14_DEFAULT, ®s->epmap14); - writel(EPMAP58_DEFAULT, ®s->epmap58); - writel(FIFOMAP_DEFAULT, ®s->fifomap); - writel(0, ®s->fifocfg); - for (i = 0; i < 8; ++i) { - writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]); - writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]); - } - - /* FIFO reset */ - for (i = 0; i < 4; ++i) { - writel(FIFOCSR_RESET, ®s->fifocsr[i]); - mdelay(10); - if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) { - printf("fotg210: fifo%d reset failed\n", i); - return -1; - } - } - - /* enable only device interrupt and triggered at level-high */ - writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr); - writel(ISR_MASK, ®s->isr); - /* disable EP0 IN/OUT interrupt */ - writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0); - /* disable EPX IN+SPK+OUT interrupts */ - writel(GIMR1_MASK, ®s->gimr1); - /* disable wakeup+idle+dma+zlp interrupts */ - writel(GIMR2_WAKEUP | GIMR2_IDLE | GIMR2_DMAERR | GIMR2_DMAFIN - | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2); - /* enable all group interrupt */ - writel(0, ®s->gimr); - - /* suspend delay = 3 ms */ - writel(3, ®s->idle); - - /* turn-on device interrupts */ - setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN); - - return 0; -} - -static inline int fotg210_cxwait(struct fotg210_chip *chip, uint32_t mask) -{ - struct fotg210_regs *regs = chip->regs; - int ret = -1; - ulong ts; - - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - if ((readl(®s->cxfifo) & mask) != mask) - continue; - ret = 0; - break; - } - - if (ret) - printf("fotg210: cx/ep0 timeout\n"); - - return ret; -} - -static int fotg210_dma(struct fotg210_ep *ep, struct fotg210_request *req) -{ - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - uint32_t tmp, ts; - uint8_t *buf = req->req.buf + req->req.actual; - uint32_t len = req->req.length - req->req.actual; - int fifo = ep_to_fifo(chip, ep->id); - int ret = -EBUSY; - - /* 1. init dma buffer */ - if (len > ep->maxpacket) - len = ep->maxpacket; - - /* 2. wait for dma ready (hardware) */ - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - if (!(readl(®s->dma_ctrl) & DMACTRL_START)) { - ret = 0; - break; - } - } - if (ret) { - printf("fotg210: dma busy\n"); - req->req.status = ret; - return ret; - } - - /* 3. DMA target setup */ - if (ep->desc->bEndpointAddress & USB_DIR_IN) - flush_dcache_range((ulong)buf, (ulong)buf + len); - else - invalidate_dcache_range((ulong)buf, (ulong)buf + len); - - writel(virt_to_phys(buf), ®s->dma_addr); - - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - if (ep->id == 0) { - /* Wait until cx/ep0 fifo empty */ - fotg210_cxwait(chip, CXFIFO_CXFIFOE); - udelay(1); - writel(DMAFIFO_CX, ®s->dma_fifo); - } else { - /* Wait until epx fifo empty */ - fotg210_cxwait(chip, CXFIFO_FIFOE(fifo)); - writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); - } - writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl); - } else { - uint32_t blen; - - if (ep->id == 0) { - writel(DMAFIFO_CX, ®s->dma_fifo); - do { - blen = CXFIFO_BYTES(readl(®s->cxfifo)); - } while (blen < len); - } else { - writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo); - blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo])); - } - len = (len < blen) ? len : blen; - writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl); - } - - /* 4. DMA start */ - setbits_le32(®s->dma_ctrl, DMACTRL_START); - - /* 5. DMA wait */ - ret = -EBUSY; - for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { - tmp = readl(®s->gisr2); - /* DMA complete */ - if (tmp & GISR2_DMAFIN) { - ret = 0; - break; - } - /* DMA error */ - if (tmp & GISR2_DMAERR) { - printf("fotg210: dma error\n"); - break; - } - /* resume, suspend, reset */ - if (tmp & (GISR2_RESUME | GISR2_SUSPEND | GISR2_RESET)) { - printf("fotg210: dma reset by host\n"); - break; - } - } - - /* 7. DMA target reset */ - if (ret) - writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl); - - writel(0, ®s->gisr2); - writel(0, ®s->dma_fifo); - - req->req.status = ret; - if (!ret) - req->req.actual += len; - else - printf("fotg210: ep%d dma error(code=%d)\n", ep->id, ret); - - return len; -} - -/* - * result of setup packet - */ -#define CX_IDLE 0 -#define CX_FINISH 1 -#define CX_STALL 2 - -static void fotg210_setup(struct fotg210_chip *chip) -{ - int id, ret = CX_IDLE; - uint32_t tmp[2]; - struct usb_ctrlrequest *req = (struct usb_ctrlrequest *)tmp; - struct fotg210_regs *regs = chip->regs; - - /* - * If this is the first Cx 8 byte command, - * we can now query USB mode (high/full speed; USB 2.0/USB 1.0) - */ - if (chip->state == USB_STATE_POWERED) { - chip->state = USB_STATE_DEFAULT; - if (readl(®s->otgcsr) & OTGCSR_DEV_B) { - /* Mini-B */ - if (readl(®s->dev_ctrl) & DEVCTRL_HS) { - puts("fotg210: HS\n"); - chip->gadget.speed = USB_SPEED_HIGH; - /* SOF mask timer = 1100 ticks */ - writel(SOFMTR_TMR(1100), ®s->sof_mtr); - } else { - puts("fotg210: FS\n"); - chip->gadget.speed = USB_SPEED_FULL; - /* SOF mask timer = 10000 ticks */ - writel(SOFMTR_TMR(10000), ®s->sof_mtr); - } - } else { - printf("fotg210: mini-A?\n"); - } - } - - /* switch data port to ep0 */ - writel(DMAFIFO_CX, ®s->dma_fifo); - /* fetch 8 bytes setup packet */ - tmp[0] = readl(®s->ep0_data); - tmp[1] = readl(®s->ep0_data); - /* release data port */ - writel(0, ®s->dma_fifo); - - if (req->bRequestType & USB_DIR_IN) - ep0_desc.bEndpointAddress = USB_DIR_IN; - else - ep0_desc.bEndpointAddress = USB_DIR_OUT; - - ret = CX_IDLE; - - if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { - switch (req->bRequest) { - case USB_REQ_SET_CONFIGURATION: - debug("fotg210: set_cfg(%d)\n", req->wValue & 0x00FF); - if (!(req->wValue & 0x00FF)) { - chip->state = USB_STATE_ADDRESS; - writel(chip->addr, ®s->dev_addr); - } else { - chip->state = USB_STATE_CONFIGURED; - writel(chip->addr | DEVADDR_CONF, - ®s->dev_addr); - } - ret = CX_IDLE; - break; - - case USB_REQ_SET_ADDRESS: - debug("fotg210: set_addr(0x%04X)\n", req->wValue); - chip->state = USB_STATE_ADDRESS; - chip->addr = req->wValue & DEVADDR_ADDR_MASK; - ret = CX_FINISH; - writel(chip->addr, ®s->dev_addr); - break; - - case USB_REQ_CLEAR_FEATURE: - debug("fotg210: clr_feature(%d, %d)\n", - req->bRequestType & 0x03, req->wValue); - switch (req->wValue) { - case 0: /* [Endpoint] halt */ - ep_reset(chip, req->wIndex); - ret = CX_FINISH; - break; - case 1: /* [Device] remote wake-up */ - case 2: /* [Device] test mode */ - default: - ret = CX_STALL; - break; - } - break; - - case USB_REQ_SET_FEATURE: - debug("fotg210: set_feature(%d, %d)\n", - req->wValue, req->wIndex & 0xf); - switch (req->wValue) { - case 0: /* Endpoint Halt */ - id = req->wIndex & 0xf; - setbits_le32(®s->iep[id - 1], IEP_STALL); - setbits_le32(®s->oep[id - 1], OEP_STALL); - ret = CX_FINISH; - break; - case 1: /* Remote Wakeup */ - case 2: /* Test Mode */ - default: - ret = CX_STALL; - break; - } - break; - - case USB_REQ_GET_STATUS: - debug("fotg210: get_status\n"); - ret = CX_STALL; - break; - - case USB_REQ_SET_DESCRIPTOR: - debug("fotg210: set_descriptor\n"); - ret = CX_STALL; - break; - - case USB_REQ_SYNCH_FRAME: - debug("fotg210: sync frame\n"); - ret = CX_STALL; - break; - } - } /* if ((req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) */ - - if (ret == CX_IDLE && chip->driver->setup) { - if (chip->driver->setup(&chip->gadget, req) < 0) - ret = CX_STALL; - else - ret = CX_FINISH; - } - - switch (ret) { - case CX_FINISH: - setbits_le32(®s->cxfifo, CXFIFO_CXFIN); - break; - - case CX_STALL: - setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN); - printf("fotg210: cx_stall!\n"); - break; - - case CX_IDLE: - debug("fotg210: cx_idle?\n"); - default: - break; - } -} - -/* - * fifo - FIFO id - * zlp - zero length packet - */ -static void fotg210_recv(struct fotg210_chip *chip, int ep_id) -{ - struct fotg210_regs *regs = chip->regs; - struct fotg210_ep *ep = chip->ep + ep_id; - struct fotg210_request *req; - int len; - - if (ep->stopped || (ep->desc->bEndpointAddress & USB_DIR_IN)) { - printf("fotg210: ep%d recv, invalid!\n", ep->id); - return; - } - - if (list_empty(&ep->queue)) { - printf("fotg210: ep%d recv, drop!\n", ep->id); - return; - } - - req = list_first_entry(&ep->queue, struct fotg210_request, queue); - len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket || req->req.length <= req->req.actual) { - list_del_init(&req->queue); - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - } - - if (ep->id > 0 && list_empty(&ep->queue)) { - setbits_le32(®s->gimr1, - GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); - } -} - -/* - * USB Gadget Layer - */ -static int fotg210_ep_enable( - struct usb_ep *_ep, const struct usb_endpoint_descriptor *desc) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int id = ep_to_fifo(chip, ep->id); - int in = (desc->bEndpointAddress & USB_DIR_IN) ? 1 : 0; - - if (!_ep || !desc - || desc->bDescriptorType != USB_DT_ENDPOINT - || le16_to_cpu(desc->wMaxPacketSize) == 0) { - printf("fotg210: bad ep or descriptor\n"); - return -EINVAL; - } - - ep->desc = desc; - ep->stopped = 0; - - if (in) - setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN)); - - switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { - case USB_ENDPOINT_XFER_CONTROL: - return -EINVAL; - - case USB_ENDPOINT_XFER_ISOC: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_ISOC)); - break; - - case USB_ENDPOINT_XFER_BULK: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_BULK)); - break; - - case USB_ENDPOINT_XFER_INT: - setbits_le32(®s->fifocfg, - FIFOCFG(id, FIFOCFG_EN | FIFOCFG_INTR)); - break; - } - - return 0; -} - -static int fotg210_ep_disable(struct usb_ep *_ep) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int id = ep_to_fifo(chip, ep->id); - - ep->desc = NULL; - ep->stopped = 1; - - clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK)); - clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK)); - - return 0; -} - -static struct usb_request *fotg210_ep_alloc_request( - struct usb_ep *_ep, gfp_t gfp_flags) -{ - struct fotg210_request *req = malloc(sizeof(*req)); - - if (req) { - memset(req, 0, sizeof(*req)); - INIT_LIST_HEAD(&req->queue); - } - return &req->req; -} - -static void fotg210_ep_free_request( - struct usb_ep *_ep, struct usb_request *_req) -{ - struct fotg210_request *req; - - req = container_of(_req, struct fotg210_request, req); - free(req); -} - -static int fotg210_ep_queue( - struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - struct fotg210_request *req; - - req = container_of(_req, struct fotg210_request, req); - if (!_req || !_req->complete || !_req->buf - || !list_empty(&req->queue)) { - printf("fotg210: invalid request to ep%d\n", ep->id); - return -EINVAL; - } - - if (!chip || chip->state == USB_STATE_SUSPENDED) { - printf("fotg210: request while chip suspended\n"); - return -EINVAL; - } - - req->req.actual = 0; - req->req.status = -EINPROGRESS; - - if (req->req.length == 0) { - req->req.status = 0; - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - return 0; - } - - if (ep->id == 0) { - do { - int len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket) - break; - if (ep->desc->bEndpointAddress & USB_DIR_IN) - udelay(100); - } while (req->req.length > req->req.actual); - } else { - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - do { - int len = fotg210_dma(ep, req); - if (len < ep->ep.maxpacket) - break; - } while (req->req.length > req->req.actual); - } else { - list_add_tail(&req->queue, &ep->queue); - clrbits_le32(®s->gimr1, - GIMR1_FIFO_RX(ep_to_fifo(chip, ep->id))); - } - } - - if (ep->id == 0 || (ep->desc->bEndpointAddress & USB_DIR_IN)) { - if (req->req.complete) - req->req.complete(&ep->ep, &req->req); - } - - return 0; -} - -static int fotg210_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_request *req; - - /* make sure it's actually queued on this endpoint */ - list_for_each_entry(req, &ep->queue, queue) { - if (&req->req == _req) - break; - } - if (&req->req != _req) - return -EINVAL; - - /* remove the request */ - list_del_init(&req->queue); - - /* update status & invoke complete callback */ - if (req->req.status == -EINPROGRESS) { - req->req.status = -ECONNRESET; - if (req->req.complete) - req->req.complete(_ep, &req->req); - } - - return 0; -} - -static int fotg210_ep_halt(struct usb_ep *_ep, int halt) -{ - struct fotg210_ep *ep = container_of(_ep, struct fotg210_ep, ep); - struct fotg210_chip *chip = ep->chip; - struct fotg210_regs *regs = chip->regs; - int ret = -1; - - debug("fotg210: ep%d halt=%d\n", ep->id, halt); - - /* Endpoint STALL */ - if (ep->id > 0 && ep->id <= CFG_NUM_ENDPOINTS) { - if (halt) { - /* wait until all ep fifo empty */ - fotg210_cxwait(chip, 0xf00); - /* stall */ - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - setbits_le32(®s->iep[ep->id - 1], - IEP_STALL); - } else { - setbits_le32(®s->oep[ep->id - 1], - OEP_STALL); - } - } else { - if (ep->desc->bEndpointAddress & USB_DIR_IN) { - clrbits_le32(®s->iep[ep->id - 1], - IEP_STALL); - } else { - clrbits_le32(®s->oep[ep->id - 1], - OEP_STALL); - } - } - ret = 0; - } - - return ret; -} - -/* - * activate/deactivate link with host. - */ -static void pullup(struct fotg210_chip *chip, int is_on) -{ - struct fotg210_regs *regs = chip->regs; - - if (is_on) { - if (!chip->pullup) { - chip->state = USB_STATE_POWERED; - chip->pullup = 1; - /* enable the chip */ - setbits_le32(®s->dev_ctrl, DEVCTRL_EN); - /* clear unplug bit (BIT0) */ - clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); - } - } else { - chip->state = USB_STATE_NOTATTACHED; - chip->pullup = 0; - chip->addr = 0; - writel(chip->addr, ®s->dev_addr); - /* set unplug bit (BIT0) */ - setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG); - /* disable the chip */ - clrbits_le32(®s->dev_ctrl, DEVCTRL_EN); - } -} - -static int fotg210_pullup(struct usb_gadget *_gadget, int is_on) -{ - struct fotg210_chip *chip; - - chip = container_of(_gadget, struct fotg210_chip, gadget); - - debug("fotg210: pullup=%d\n", is_on); - - pullup(chip, is_on); - - return 0; -} - -static int fotg210_get_frame(struct usb_gadget *_gadget) -{ - struct fotg210_chip *chip; - struct fotg210_regs *regs; - - chip = container_of(_gadget, struct fotg210_chip, gadget); - regs = chip->regs; - - return SOFFNR_FNR(readl(®s->sof_fnr)); -} - -static struct usb_gadget_ops fotg210_gadget_ops = { - .get_frame = fotg210_get_frame, - .pullup = fotg210_pullup, -}; - -static struct usb_ep_ops fotg210_ep_ops = { - .enable = fotg210_ep_enable, - .disable = fotg210_ep_disable, - .queue = fotg210_ep_queue, - .dequeue = fotg210_ep_dequeue, - .set_halt = fotg210_ep_halt, - .alloc_request = fotg210_ep_alloc_request, - .free_request = fotg210_ep_free_request, -}; - -static struct fotg210_chip controller = { - .regs = (void __iomem *)CONFIG_FOTG210_BASE, - .gadget = { - .name = "fotg210_udc", - .ops = &fotg210_gadget_ops, - .ep0 = &controller.ep[0].ep, - .speed = USB_SPEED_UNKNOWN, - .is_dualspeed = 1, - .is_otg = 0, - .is_a_peripheral = 0, - .b_hnp_enable = 0, - .a_hnp_support = 0, - .a_alt_hnp_support = 0, - }, - .ep[0] = { - .id = 0, - .ep = { - .name = "ep0", - .ops = &fotg210_ep_ops, - }, - .desc = &ep0_desc, - .chip = &controller, - .maxpacket = CFG_EP0_MAX_PACKET_SIZE, - }, - .ep[1] = { - .id = 1, - .ep = { - .name = "ep1", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[2] = { - .id = 2, - .ep = { - .name = "ep2", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[3] = { - .id = 3, - .ep = { - .name = "ep3", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, - .ep[4] = { - .id = 4, - .ep = { - .name = "ep4", - .ops = &fotg210_ep_ops, - }, - .chip = &controller, - .maxpacket = CFG_EPX_MAX_PACKET_SIZE, - }, -}; - -int usb_gadget_handle_interrupts(int index) -{ - struct fotg210_chip *chip = &controller; - struct fotg210_regs *regs = chip->regs; - uint32_t id, st, isr, gisr; - - isr = readl(®s->isr) & (~readl(®s->imr)); - gisr = readl(®s->gisr) & (~readl(®s->gimr)); - if (!(isr & ISR_DEV) || !gisr) - return 0; - - writel(ISR_DEV, ®s->isr); - - /* CX interrupts */ - if (gisr & GISR_GRP0) { - st = readl(®s->gisr0); - /* - * Write 1 and then 0 works for both W1C & RW. - * - * HW v1.11.0+: It's a W1C register (write 1 clear) - * HW v1.10.0-: It's a R/W register (write 0 clear) - */ - writel(st & GISR0_CXABORT, ®s->gisr0); - writel(0, ®s->gisr0); - - if (st & GISR0_CXERR) - printf("fotg210: cmd error\n"); - - if (st & GISR0_CXABORT) - printf("fotg210: cmd abort\n"); - - if (st & GISR0_CXSETUP) /* setup */ - fotg210_setup(chip); - else if (st & GISR0_CXEND) /* command finish */ - setbits_le32(®s->cxfifo, CXFIFO_CXFIN); - } - - /* FIFO interrupts */ - if (gisr & GISR_GRP1) { - st = readl(®s->gisr1); - for (id = 0; id < 4; ++id) { - if (st & GISR1_RX_FIFO(id)) - fotg210_recv(chip, fifo_to_ep(chip, id, 0)); - } - } - - /* Device Status Interrupts */ - if (gisr & GISR_GRP2) { - st = readl(®s->gisr2); - /* - * Write 1 and then 0 works for both W1C & RW. - * - * HW v1.11.0+: It's a W1C register (write 1 clear) - * HW v1.10.0-: It's a R/W register (write 0 clear) - */ - writel(st, ®s->gisr2); - writel(0, ®s->gisr2); - - if (st & GISR2_RESET) - printf("fotg210: reset by host\n"); - else if (st & GISR2_SUSPEND) - printf("fotg210: suspend/removed\n"); - else if (st & GISR2_RESUME) - printf("fotg210: resume\n"); - - /* Errors */ - if (st & GISR2_ISOCERR) - printf("fotg210: iso error\n"); - if (st & GISR2_ISOCABT) - printf("fotg210: iso abort\n"); - if (st & GISR2_DMAERR) - printf("fotg210: dma error\n"); - } - - return 0; -} - -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - int i, ret = 0; - struct fotg210_chip *chip = &controller; - - if (!driver || !driver->bind || !driver->setup) { - puts("fotg210: bad parameter.\n"); - return -EINVAL; - } - - INIT_LIST_HEAD(&chip->gadget.ep_list); - for (i = 0; i < CFG_NUM_ENDPOINTS + 1; ++i) { - struct fotg210_ep *ep = chip->ep + i; - - ep->ep.maxpacket = ep->maxpacket; - INIT_LIST_HEAD(&ep->queue); - - if (ep->id == 0) { - ep->stopped = 0; - } else { - ep->stopped = 1; - list_add_tail(&ep->ep.ep_list, &chip->gadget.ep_list); - } - } - - if (fotg210_reset(chip)) { - puts("fotg210: reset failed.\n"); - return -EINVAL; - } - - ret = driver->bind(&chip->gadget); - if (ret) { - debug("fotg210: driver->bind() returned %d\n", ret); - return ret; - } - chip->driver = driver; - - return ret; -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - struct fotg210_chip *chip = &controller; - - driver->unbind(&chip->gadget); - chip->driver = NULL; - - pullup(chip, 0); - - return 0; -} diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index abc6dc7f89..98156c312d 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -117,12 +117,6 @@ #define gadget_is_ci(g) 0 #endif -#ifdef CONFIG_USB_GADGET_FOTG210 -#define gadget_is_fotg210(g) (!strcmp("fotg210_udc", (g)->name)) -#else -#define gadget_is_fotg210(g) 0 -#endif - #ifdef CONFIG_USB_DWC3_GADGET #define gadget_is_dwc3(g) (!strcmp("dwc3-gadget", (g)->name)) #else @@ -202,8 +196,6 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x20; else if (gadget_is_ci(gadget)) return 0x21; - else if (gadget_is_fotg210(gadget)) - return 0x22; else if (gadget_is_dwc3(gadget)) return 0x23; else if (gadget_is_cdns3(gadget)) diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index ddc3663206..8dad36f936 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -17,7 +17,6 @@ obj-$(CONFIG_USB_OHCI_NEW) += ohci-hcd.o obj-$(CONFIG_USB_ATMEL) += ohci-at91.o obj-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o -obj-$(CONFIG_USB_SL811HS) += sl811-hcd.o obj-$(CONFIG_USB_OHCI_LPC32XX) += ohci-lpc32xx.o obj-$(CONFIG_USB_OHCI_PCI) += ohci-pci.o obj-$(CONFIG_USB_OHCI_GENERIC) += ohci-generic.o @@ -25,10 +24,8 @@ obj-$(CONFIG_USB_OHCI_NPCM) += ohci-npcm.o # echi obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o -obj-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o obj-$(CONFIG_USB_EHCI_ATMEL) += ehci-atmel.o obj-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o -obj-$(CONFIG_USB_EHCI_FARADAY) += ehci-faraday.o obj-$(CONFIG_USB_EHCI_GENERIC) += ehci-generic.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o @@ -41,9 +38,7 @@ obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o -obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o -obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci diff --git a/drivers/usb/host/ehci-armada100.c b/drivers/usb/host/ehci-armada100.c deleted file mode 100644 index 2ce9f27b86..0000000000 --- a/drivers/usb/host/ehci-armada100.c +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * This driver is based on Kirkwood echi driver - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <usb.h> -#include "ehci.h" -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> - -/* - * EHCI host controller init - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - if (utmi_init() < 0) - return -1; - - *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - return 0; -} - -/* - * EHCI host controller stop - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-faraday.c b/drivers/usb/host/ehci-faraday.c deleted file mode 100644 index 85a3526960..0000000000 --- a/drivers/usb/host/ehci-faraday.c +++ /dev/null @@ -1,144 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Faraday USB 2.0 EHCI Controller - * - * (C) Copyright 2010 Faraday Technology - * Dante Su <dantesu@faraday-tech.com> - */ - -#include <common.h> -#include <log.h> -#include <asm/io.h> -#include <usb.h> -#include <linux/delay.h> -#include <usb/fusbh200.h> -#include <usb/fotg210.h> - -#include "ehci.h" - -#ifndef CFG_USB_EHCI_BASE_LIST -#define CFG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE } -#endif - -union ehci_faraday_regs { - struct fusbh200_regs usb; - struct fotg210_regs otg; -}; - -static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs) -{ - return !readl(®s->usb.easstr); -} - -void faraday_ehci_set_usbmode(struct ehci_ctrl *ctrl) -{ - /* nothing needs to be done */ -} - -int faraday_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) -{ - int spd, ret = PORTSC_PSPD_HS; - union ehci_faraday_regs *regs; - - ret = (void __iomem *)((ulong)ctrl->hcor - 0x10); - if (ehci_is_fotg2xx(regs)) - spd = OTGCSR_SPD(readl(®s->otg.otgcsr)); - else - spd = BMCSR_SPD(readl(®s->usb.bmcsr)); - - switch (spd) { - case 0: /* full speed */ - ret = PORTSC_PSPD_FS; - break; - case 1: /* low speed */ - ret = PORTSC_PSPD_LS; - break; - case 2: /* high speed */ - ret = PORTSC_PSPD_HS; - break; - default: - printf("ehci-faraday: invalid device speed\n"); - break; - } - - return ret; -} - -uint32_t *faraday_ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) -{ - /* Faraday EHCI has one and only one portsc register */ - if (port) { - /* Printing the message would cause a scan failure! */ - debug("The request port(%d) is not configured\n", port); - return NULL; - } - - /* Faraday EHCI PORTSC register offset is 0x20 from hcor */ - return (uint32_t *)((uint8_t *)ctrl->hcor + 0x20); -} - -static const struct ehci_ops faraday_ehci_ops = { - .set_usb_mode = faraday_ehci_set_usbmode, - .get_port_speed = faraday_ehci_get_port_speed, - .get_portsc_register = faraday_ehci_get_portsc_register, -}; - -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor) -{ - struct ehci_hccr *hccr; - struct ehci_hcor *hcor; - union ehci_faraday_regs *regs; - uint32_t base_list[] = CFG_USB_EHCI_BASE_LIST; - - if (index < 0 || index >= ARRAY_SIZE(base_list)) - return -1; - ehci_set_controller_priv(index, NULL, &faraday_ehci_ops); - regs = (void __iomem *)base_list[index]; - hccr = (struct ehci_hccr *)®s->usb.hccr; - hcor = (struct ehci_hcor *)®s->usb.hcor; - - if (ehci_is_fotg2xx(regs)) { - /* A-device bus reset */ - /* ... Power off A-device */ - setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drop vbus and bus traffic */ - clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* ... Power on A-device */ - clrbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSDROP); - /* ... Drive vbus and bus traffic */ - setbits_le32(®s->otg.otgcsr, OTGCSR_A_BUSREQ); - mdelay(1); - /* Disable OTG & DEV interrupts, triggered at level-high */ - writel(IMR_IRQLH | IMR_OTG | IMR_DEV, ®s->otg.imr); - /* Clear all interrupt status */ - writel(ISR_HOST | ISR_OTG | ISR_DEV, ®s->otg.isr); - } else { - /* Interrupt=level-high */ - setbits_le32(®s->usb.bmcsr, BMCSR_IRQLH); - /* VBUS on */ - clrbits_le32(®s->usb.bmcsr, BMCSR_VBUS_OFF); - /* Disable all interrupts */ - writel(0x00, ®s->usb.bmier); - writel(0x1f, ®s->usb.bmisr); - } - - *ret_hccr = hccr; - *ret_hcor = hcor; - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 9139d61dd0..9839aa1749 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -705,12 +705,10 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, dev->act_len = length - QT_TOKEN_GET_TOTALBYTES(qhtoken); } else { dev->act_len = 0; -#ifndef CONFIG_USB_EHCI_FARADAY debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n", dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts), ehci_readl(&ctrl->hcor->or_portsc[0]), ehci_readl(&ctrl->hcor->or_portsc[1])); -#endif } free(qtd); @@ -1190,9 +1188,6 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) if (rc) return rc; #endif -#ifdef CONFIG_USB_EHCI_FARADAY - tweaks |= EHCI_TWEAK_NO_INIT_CF; -#endif rc = ehci_common_init(ctrl, tweaks); if (rc) return rc; diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 0a12db614f..91633f013a 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -360,7 +360,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index > 3) return -EINVAL; - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (usb_fused((ulong)ehci)) { printf("SoC fuse indicates USB@0x%lx is unavailable.\n", (ulong)ehci); @@ -641,7 +641,7 @@ static int ehci_usb_probe(struct udevice *dev) struct ehci_hcor *hcor; int ret; - if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (IS_ENABLED(CONFIG_IMX_MODULE_FUSE)) { if (usb_fused((ulong)ehci)) { printf("SoC fuse indicates USB@0x%lx is unavailable.\n", (ulong)ehci); diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c deleted file mode 100644 index 60525f2286..0000000000 --- a/drivers/usb/host/ehci-rmobile.c +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * EHCI HCD (Host Controller Driver) for USB. - * - * Copyright (C) 2013,2014 Renesas Electronics Corporation - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/ehci-rmobile.h> -#include <linux/delay.h> -#include "ehci.h" - -#if defined(CONFIG_R8A7740) -static u32 usb_base_address[] = { - 0xC6700000 -}; -#elif defined(CONFIG_R8A7790) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0A0000, /* USB1 */ - 0xEE0C0000, /* USB2 */ -}; -#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) -static u32 usb_base_address[] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0C0000, /* USB1 */ -}; -#else -#error rmobile EHCI USB driver not supported on this platform -#endif - -int ehci_hcd_stop(int index) -{ - int i; - u32 base; - struct ahbcom_pci_bridge *ahbcom_pci; - - base = usb_base_address[index]; - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - writel(0, &ahbcom_pci->ahb_bus_ctr); - - /* reset ehci */ - setbits_le32(base + EHCI_USBCMD, CMD_RESET); - for (i = 100; i > 0; i--) { - if (!(readl(base + EHCI_USBCMD) & CMD_RESET)) - break; - udelay(100); - } - - if (!i) - printf("error : ehci(%d) reset failed.\n", index); - - if (index == (ARRAY_SIZE(usb_base_address) - 1)) - setbits_le32(SMSTPCR7, SMSTPCR703); - - return 0; -} - -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - u32 base; - u32 phys_base; - struct rmobile_ehci_reg *rehci; - struct ahbcom_pci_bridge *ahbcom_pci; - struct ahbconf_pci_bridge *ahbconf_pci; - struct ahb_pciconf *ahb_pciconf_ohci; - struct ahb_pciconf *ahb_pciconf_ehci; - uint32_t cap_base; - - base = usb_base_address[index]; - phys_base = base; - if (index == 0) - clrbits_le32(SMSTPCR7, SMSTPCR703); - - rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET); - ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET); - ahbconf_pci = - (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET); - ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET); - ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET); - - /* Clock & Reset & Direct Power Down */ - clrsetbits_le32(&ahbcom_pci->usbctr, - (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB); - clrbits_le32(&ahbcom_pci->usbctr, PLL_RST); - - /* AHB-PCI Bridge Communication Registers */ - writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr); - writel((CFG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win1_ctr); - writel(0xf0000000 | PCIAHB_WIN_PREFETCH, - &ahbcom_pci->pciahb_win2_ctr); - writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr); - - setbits_le32(&ahbcom_pci->pci_arbiter_ctr, - PCIBP_MODE | PCIREQ1 | PCIREQ0); - - /* PCI Configuration Registers for AHBPCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI, - &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead); - writel(CFG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead); - writel(0xf0000000, &ahbconf_pci->win2_basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahbconf_pci->cmnd_sts); - - /* PCI Configuration Registers for EHCI */ - writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr); - writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead); - writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ohci->cmnd_sts); - writel(SERREN | PERREN | MASTEREN | MEMEN, - &ahb_pciconf_ehci->cmnd_sts); - - /* Enable PCI interrupt */ - setbits_le32(&ahbcom_pci->pci_int_enable, - USBH_PMEEN | USBH_INTBEN | USBH_INTAEN); - - *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion); - cap_base = ehci_readl(&(*hccr)->cr_capbase); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base)); - - return 0; -} diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index 11d776747c..76562bd749 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c @@ -127,42 +127,70 @@ struct fdt_usb { static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, - { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } }; static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, + { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }, + { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, - { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } + { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } }; static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, + { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 }, - { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 }, { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, - { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 } + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }, + { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 } }; /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */ static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */ { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 }, - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, - { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 }, { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 }, - { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 } + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 }, + { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, + { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0, 0 }, + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 } }; /* UTMIP Idle Wait Delay */ diff --git a/drivers/usb/host/ehci-vct.c b/drivers/usb/host/ehci-vct.c deleted file mode 100644 index 7167f82b48..0000000000 --- a/drivers/usb/host/ehci-vct.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering - */ - -#include <common.h> -#include <usb.h> - -#include "ehci.h" - -int vct_ehci_hcd_init(u32 *hccr, u32 *hcor); - -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - int ret; - u32 vct_hccr; - u32 vct_hcor; - - /* - * Init VCT specific stuff - */ - ret = vct_ehci_hcd_init(&vct_hccr, &vct_hcor); - if (ret) - return ret; - - *hccr = (struct ehci_hccr *)vct_hccr; - *hcor = (struct ehci_hcor *)vct_hcor; - - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c deleted file mode 100644 index 7c823f241a..0000000000 --- a/drivers/usb/host/sl811-hcd.c +++ /dev/null @@ -1,714 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * This code is based on linux driver for sl811hs chip, source at - * drivers/usb/host/sl811.c: - * - * SL811 Host Controller Interface driver for USB. - * - * Copyright (c) 2003/06, Courage Co., Ltd. - * - * Based on: - * 1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap, - * Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber, - * Adam Richter, Gregory P. Smith; - * 2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com> - * 3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn> - */ - -#include <common.h> -#include <mpc8xx.h> -#include <usb.h> -#include <linux/delay.h> -#include "sl811.h" - -#include "../../../board/kup/common/kup.h" - -#ifdef __PPC__ -# define EIEIO __asm__ volatile ("eieio") -#else -# define EIEIO /* nothing */ -#endif - -#define SL811_ADR (0x50000000) -#define SL811_DAT (0x50000001) - -#ifdef SL811_DEBUG -static int debug = 9; -#endif - -static int root_hub_devnum = 0; -static struct usb_port_status rh_status = { 0 };/* root hub port status */ - -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd); - -static void sl811_write (__u8 index, __u8 data) -{ - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - *(volatile unsigned char *) (SL811_DAT) = data; - EIEIO; -} - -static __u8 sl811_read (__u8 index) -{ - __u8 data; - - *(volatile unsigned char *) (SL811_ADR) = index; - EIEIO; - data = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - return (data); -} - -/* - * Read consecutive bytes of data from the SL811H/SL11H buffer - */ -static void inline sl811_read_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *buf++ = *(volatile unsigned char *) (SL811_DAT); - EIEIO; - } -} - -/* - * Write consecutive bytes of data to the SL811H/SL11H buffer - */ -static void inline sl811_write_buf(__u8 offset, __u8 *buf, __u8 size) -{ - *(volatile unsigned char *) (SL811_ADR) = offset; - EIEIO; - while (size--) { - *(volatile unsigned char *) (SL811_DAT) = *buf++; - EIEIO; - } -} - -int usb_init_kup4x (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - int i; - unsigned char tmp; - - memctl = &immap->im_memctl; - memctl->memc_or7 = 0xFFFF8726; - memctl->memc_br7 = 0x50000401; /* start at 0x50000000 */ - /* BP 14 low = USB ON */ - immap->im_cpm.cp_pbdat &= ~(BP_USB_VCC); - /* PB 14 nomal port */ - immap->im_cpm.cp_pbpar &= ~(BP_USB_VCC); - /* output */ - immap->im_cpm.cp_pbdir |= (BP_USB_VCC); - - puts ("USB: "); - - for (i = 0x10; i < 0xff; i++) { - sl811_write(i, i); - tmp = (sl811_read(i)); - if (tmp != i) { - printf ("SL811 compare error index=0x%02x read=0x%02x\n", i, tmp); - return (-1); - } - } - printf ("SL811 ready\n"); - return (0); -} - -/* - * This function resets SL811HS controller and detects the speed of - * the connecting device - * - * Return: 0 = no device attached; 1 = USB device attached - */ -static int sl811_hc_reset(void) -{ - int status ; - - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - - mdelay(20); - - /* Disable hardware SOF generation, clear all irq status. */ - sl811_write(SL811_CTRL1, 0); - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_INTRSTS); - - if (status & SL811_INTR_NOTPRESENT) { - /* Device is not present */ - PDEBUG(0, "Device not present\n"); - rh_status.wPortStatus &= ~(USB_PORT_STAT_CONNECTION | USB_PORT_STAT_ENABLE); - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, SL811_INTR_INSRMV); - return 0; - } - - /* Send SOF to address 0, endpoint 0. */ - sl811_write(SL811_LEN_B, 0); - sl811_write(SL811_PIDEP_B, PIDEP(USB_PID_SOF, 0)); - sl811_write(SL811_DEV_B, 0x00); - sl811_write(SL811_SOFLOW, SL811_12M_LOW); - - if (status & SL811_INTR_SPEED_FULL) { - /* full speed device connect directly to root hub */ - PDEBUG (0, "Full speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION; - rh_status.wPortStatus &= ~USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } else { - /* slow speed device connect directly to root-hub */ - PDEBUG(0, "Low speed Device attached\n"); - - sl811_write(SL811_CTRL1, SL811_CTRL1_RESET); - mdelay(20); - sl811_write(SL811_CTRL2, SL811_CTL2_HOST | SL811_CTL2_DSWAP | SL811_12M_HI); - sl811_write(SL811_CTRL1, SL811_CTRL1_SPEED_LOW | SL811_CTRL1_SOF); - - /* start the SOF or EOP */ - sl811_write(SL811_CTRL_B, SL811_USB_CTRL_ARM); - rh_status.wPortStatus |= USB_PORT_STAT_CONNECTION | USB_PORT_STAT_LOW_SPEED; - mdelay(2); - sl811_write(SL811_INTRSTS, 0xff); - } - - rh_status.wPortChange |= USB_PORT_STAT_C_CONNECTION; - sl811_write(SL811_INTR, /*SL811_INTR_INSRMV*/SL811_INTR_DONE_A); - - return 1; -} - -int usb_lowlevel_init(int index, enum usb_init_type init, void **controller) -{ - root_hub_devnum = 0; - sl811_hc_reset(); - return 0; -} - -int usb_lowlevel_stop(int index) -{ - sl811_hc_reset(); - return 0; -} - -static int calc_needed_buswidth(int bytes, int need_preamble) -{ - return !need_preamble ? bytes * 8 + 256 : 8 * 8 * bytes + 2048; -} - -static int sl811_send_packet(struct usb_device *dev, unsigned long pipe, __u8 *buffer, int len) -{ - __u8 ctrl = SL811_USB_CTRL_ARM | SL811_USB_CTRL_ENABLE; - __u16 status = 0; - int err = 0, time_start = get_timer(0); - int need_preamble = !(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - (dev->speed == USB_SPEED_LOW); - - if (len > 239) - return -1; - - if (usb_pipeout(pipe)) - ctrl |= SL811_USB_CTRL_DIR_OUT; - if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) - ctrl |= SL811_USB_CTRL_TOGGLE_1; - if (need_preamble) - ctrl |= SL811_USB_CTRL_PREAMBLE; - - sl811_write(SL811_INTRSTS, 0xff); - - while (err < 3) { - sl811_write(SL811_ADDR_A, 0x10); - sl811_write(SL811_LEN_A, len); - if (usb_pipeout(pipe) && len) - sl811_write_buf(0x10, buffer, len); - - if (!(rh_status.wPortStatus & USB_PORT_STAT_LOW_SPEED) && - sl811_read(SL811_SOFCNTDIV)*64 < calc_needed_buswidth(len, need_preamble)) - ctrl |= SL811_USB_CTRL_SOF; - else - ctrl &= ~SL811_USB_CTRL_SOF; - - sl811_write(SL811_CTRL_A, ctrl); - while (!(sl811_read(SL811_INTRSTS) & SL811_INTR_DONE_A)) { - if (5*CONFIG_SYS_HZ < get_timer(time_start)) { - printf("USB transmit timed out\n"); - return -USB_ST_CRC_ERR; - } - } - - sl811_write(SL811_INTRSTS, 0xff); - status = sl811_read(SL811_STS_A); - - if (status & SL811_USB_STS_ACK) { - int remainder = sl811_read(SL811_CNT_A); - if (remainder) { - PDEBUG(0, "usb transfer remainder = %d\n", remainder); - len -= remainder; - } - if (usb_pipein(pipe) && len) - sl811_read_buf(0x10, buffer, len); - return len; - } - - if ((status & SL811_USB_STS_NAK) == SL811_USB_STS_NAK) - continue; - - PDEBUG(0, "usb transfer error %#x\n", (int)status); - err++; - } - - err = 0; - - if (status & SL811_USB_STS_ERROR) - err |= USB_ST_BUF_ERR; - if (status & SL811_USB_STS_TIMEOUT) - err |= USB_ST_CRC_ERR; - if (status & SL811_USB_STS_STALL) - err |= USB_ST_STALLED; - - return -err; -} - -int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len) -{ - int dir_out = usb_pipeout(pipe); - int ep = usb_pipeendpoint(pipe); - int max = usb_maxpacket(dev, pipe); - int done = 0; - - PDEBUG(7, "dev = %ld pipe = %ld buf = %p size = %d dir_out = %d\n", - usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out); - - dev->status = 0; - - sl811_write(SL811_DEV_A, usb_pipedevice(pipe)); - sl811_write(SL811_PIDEP_A, PIDEP(!dir_out ? USB_PID_IN : USB_PID_OUT, ep)); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - dev->status = -res; - return res; - } - - if (!dir_out && res < max) /* short packet */ - break; - - done += res; - usb_dotoggle(dev, ep, dir_out); - } - - dev->act_len = done; - - return 0; -} - -int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len,struct devrequest *setup) -{ - int done = 0; - int devnum = usb_pipedevice(pipe); - int ep = usb_pipeendpoint(pipe); - - dev->status = 0; - - if (devnum == root_hub_devnum) - return sl811_rh_submit_urb(dev, pipe, buffer, len, setup); - - PDEBUG(7, "dev = %d pipe = %ld buf = %p size = %d rt = %#x req = %#x bus = %i\n", - devnum, ep, buffer, len, (int)setup->requesttype, - (int)setup->request, sl811_read(SL811_SOFCNTDIV)*64); - - sl811_write(SL811_DEV_A, devnum); - sl811_write(SL811_PIDEP_A, PIDEP(USB_PID_SETUP, ep)); - /* setup phase */ - usb_settoggle(dev, ep, 1, 0); - if (sl811_send_packet(dev, usb_sndctrlpipe(dev, ep), - (__u8*)setup, sizeof(*setup)) == sizeof(*setup)) { - int dir_in = usb_pipein(pipe); - int max = usb_maxpacket(dev, pipe); - - /* data phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, usb_pipeout(pipe), 1); - while (done < len) { - int res = sl811_send_packet(dev, pipe, (__u8*)buffer+done, - max > len - done ? len - done : max); - if (res < 0) { - PDEBUG(0, "status data failed!\n"); - dev->status = -res; - return 0; - } - done += res; - usb_dotoggle(dev, ep, usb_pipeout(pipe)); - if (dir_in && res < max) /* short packet */ - break; - } - - /* status phase */ - sl811_write(SL811_PIDEP_A, - PIDEP(!dir_in ? USB_PID_IN : USB_PID_OUT, ep)); - usb_settoggle(dev, ep, !usb_pipeout(pipe), 1); - if (sl811_send_packet(dev, - !dir_in ? usb_rcvctrlpipe(dev, ep) : - usb_sndctrlpipe(dev, ep), - 0, 0) < 0) { - PDEBUG(0, "status phase failed!\n"); - dev->status = -1; - } - } else { - PDEBUG(0, "setup phase failed!\n"); - dev->status = -1; - } - - dev->act_len = done; - - return done; -} - -int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, - int len, int interval, bool nonblock) -{ - PDEBUG(0, "dev = %p pipe = %#lx buf = %p size = %d int = %d\n", dev, pipe, - buffer, len, interval); - return -1; -} - -/* - * SL811 Virtual Root Hub - */ - -/* Device descriptor */ -static __u8 sl811_rh_dev_des[] = -{ - 0x12, /* __u8 bLength; */ - 0x01, /* __u8 bDescriptorType; Device */ - 0x10, /* __u16 bcdUSB; v1.1 */ - 0x01, - 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ - 0x00, /* __u8 bDeviceSubClass; */ - 0x00, /* __u8 bDeviceProtocol; */ - 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */ - 0x00, /* __u16 idVendor; */ - 0x00, - 0x00, /* __u16 idProduct; */ - 0x00, - 0x00, /* __u16 bcdDevice; */ - 0x00, - 0x00, /* __u8 iManufacturer; */ - 0x02, /* __u8 iProduct; */ - 0x01, /* __u8 iSerialNumber; */ - 0x01 /* __u8 bNumConfigurations; */ -}; - -/* Configuration descriptor */ -static __u8 sl811_rh_config_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x02, /* __u8 bDescriptorType; Configuration */ - 0x19, /* __u16 wTotalLength; */ - 0x00, - 0x01, /* __u8 bNumInterfaces; */ - 0x01, /* __u8 bConfigurationValue; */ - 0x00, /* __u8 iConfiguration; */ - 0x40, /* __u8 bmAttributes; - Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, - 4..0: resvd */ - 0x00, /* __u8 MaxPower; */ - - /* interface */ - 0x09, /* __u8 if_bLength; */ - 0x04, /* __u8 if_bDescriptorType; Interface */ - 0x00, /* __u8 if_bInterfaceNumber; */ - 0x00, /* __u8 if_bAlternateSetting; */ - 0x01, /* __u8 if_bNumEndpoints; */ - 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ - 0x00, /* __u8 if_bInterfaceSubClass; */ - 0x00, /* __u8 if_bInterfaceProtocol; */ - 0x00, /* __u8 if_iInterface; */ - - /* endpoint */ - 0x07, /* __u8 ep_bLength; */ - 0x05, /* __u8 ep_bDescriptorType; Endpoint */ - 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ - 0x03, /* __u8 ep_bmAttributes; Interrupt */ - 0x08, /* __u16 ep_wMaxPacketSize; */ - 0x00, - 0xff /* __u8 ep_bInterval; 255 ms */ -}; - -/* root hub class descriptor*/ -static __u8 sl811_rh_hub_des[] = -{ - 0x09, /* __u8 bLength; */ - 0x29, /* __u8 bDescriptorType; Hub-descriptor */ - 0x01, /* __u8 bNbrPorts; */ - 0x00, /* __u16 wHubCharacteristics; */ - 0x00, - 0x50, /* __u8 bPwrOn2pwrGood; 2ms */ - 0x00, /* __u8 bHubContrCurrent; 0 mA */ - 0xfc, /* __u8 DeviceRemovable; *** 7 Ports max *** */ - 0xff /* __u8 PortPwrCtrlMask; *** 7 ports max *** */ -}; - -/* - * helper routine for returning string descriptors in UTF-16LE - * input can actually be ISO-8859-1; ASCII is its 7-bit subset - */ -static int ascii2utf (char *s, u8 *utf, int utfmax) -{ - int retval; - - for (retval = 0; *s && utfmax > 1; utfmax -= 2, retval += 2) { - *utf++ = *s++; - *utf++ = 0; - } - return retval; -} - -/* - * root_hub_string is used by each host controller's root hub code, - * so that they're identified consistently throughout the system. - */ -static int usb_root_hub_string (int id, int serial, char *type, __u8 *data, int len) -{ - char buf [30]; - - /* assert (len > (2 * (sizeof (buf) + 1))); - assert (strlen (type) <= 8);*/ - - /* language ids */ - if (id == 0) { - *data++ = 4; *data++ = 3; /* 4 bytes data */ - *data++ = 0; *data++ = 0; /* some language id */ - return 4; - - /* serial number */ - } else if (id == 1) { - sprintf (buf, "%#x", serial); - - /* product description */ - } else if (id == 2) { - sprintf (buf, "USB %s Root Hub", type); - - /* id 3 == vendor description */ - - /* unsupported IDs --> "stall" */ - } else - return 0; - - ascii2utf (buf, data + 2, len - 2); - data [0] = 2 + strlen(buf) * 2; - data [1] = 3; - return data [0]; -} - -/* helper macro */ -#define OK(x) len = (x); break - -/* - * This function handles all USB request to the the virtual root hub - */ -static int sl811_rh_submit_urb(struct usb_device *usb_dev, unsigned long pipe, - void *data, int buf_len, struct devrequest *cmd) -{ - __u8 data_buf[16]; - __u8 *bufp = data_buf; - int len = 0; - int status = 0; - __u16 bmRType_bReq; - __u16 wValue = le16_to_cpu (cmd->value); - __u16 wLength = le16_to_cpu (cmd->length); -#ifdef SL811_DEBUG - __u16 wIndex = le16_to_cpu (cmd->index); -#endif - - if (usb_pipeint(pipe)) { - PDEBUG(0, "interrupt transfer unimplemented!\n"); - return 0; - } - - bmRType_bReq = cmd->requesttype | (cmd->request << 8); - - PDEBUG(5, "submit rh urb, req = %d(%x) val = %#x index = %#x len=%d\n", - bmRType_bReq, bmRType_bReq, wValue, wIndex, wLength); - - /* Request Destination: - without flags: Device, - USB_RECIP_INTERFACE: interface, - USB_RECIP_ENDPOINT: endpoint, - USB_TYPE_CLASS means HUB here, - USB_RECIP_OTHER | USB_TYPE_CLASS almost ever means HUB_PORT here - */ - switch (bmRType_bReq) { - case RH_GET_STATUS: - *(__u16 *)bufp = cpu_to_le16(1); - OK(2); - - case RH_GET_STATUS | USB_RECIP_INTERFACE: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_RECIP_ENDPOINT: - *(__u16 *)bufp = cpu_to_le16(0); - OK(2); - - case RH_GET_STATUS | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(0); - OK(4); - - case RH_GET_STATUS | USB_RECIP_OTHER | USB_TYPE_CLASS: - *(__u32 *)bufp = cpu_to_le32(rh_status.wPortChange<<16 | rh_status.wPortStatus); - OK(4); - - case RH_CLEAR_FEATURE | USB_RECIP_ENDPOINT: - switch (wValue) { - case 1: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_TYPE_CLASS: - switch (wValue) { - case C_HUB_LOCAL_POWER: - OK(0); - - case C_HUB_OVER_CURRENT: - OK(0); - } - break; - - case RH_CLEAR_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus &= ~USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus &= ~USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus &= ~USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_C_CONNECTION: - rh_status.wPortChange &= ~USB_PORT_STAT_C_CONNECTION; - OK(0); - - case USB_PORT_FEAT_C_ENABLE: - rh_status.wPortChange &= ~USB_PORT_STAT_C_ENABLE; - OK(0); - - case USB_PORT_FEAT_C_SUSPEND: - rh_status.wPortChange &= ~USB_PORT_STAT_C_SUSPEND; - OK(0); - - case USB_PORT_FEAT_C_OVER_CURRENT: - rh_status.wPortChange &= ~USB_PORT_STAT_C_OVERCURRENT; - OK(0); - - case USB_PORT_FEAT_C_RESET: - rh_status.wPortChange &= ~USB_PORT_STAT_C_RESET; - OK(0); - } - break; - - case RH_SET_FEATURE | USB_RECIP_OTHER | USB_TYPE_CLASS: - switch (wValue) { - case USB_PORT_FEAT_SUSPEND: - rh_status.wPortStatus |= USB_PORT_STAT_SUSPEND; - OK(0); - - case USB_PORT_FEAT_RESET: - rh_status.wPortStatus |= USB_PORT_STAT_RESET; - rh_status.wPortChange = 0; - rh_status.wPortChange |= USB_PORT_STAT_C_RESET; - rh_status.wPortStatus &= ~USB_PORT_STAT_RESET; - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - - case USB_PORT_FEAT_POWER: - rh_status.wPortStatus |= USB_PORT_STAT_POWER; - OK(0); - - case USB_PORT_FEAT_ENABLE: - rh_status.wPortStatus |= USB_PORT_STAT_ENABLE; - OK(0); - } - break; - - case RH_SET_ADDRESS: - root_hub_devnum = wValue; - OK(0); - - case RH_GET_DESCRIPTOR: - switch ((wValue & 0xff00) >> 8) { - case USB_DT_DEVICE: - len = sizeof(sl811_rh_dev_des); - bufp = sl811_rh_dev_des; - OK(len); - - case USB_DT_CONFIG: - len = sizeof(sl811_rh_config_des); - bufp = sl811_rh_config_des; - OK(len); - - case USB_DT_STRING: - len = usb_root_hub_string(wValue & 0xff, (int)(long)0, "SL811HS", data, wLength); - if (len > 0) { - bufp = data; - OK(len); - } - - default: - status = -32; - } - break; - - case RH_GET_DESCRIPTOR | USB_TYPE_CLASS: - len = sizeof(sl811_rh_hub_des); - bufp = sl811_rh_hub_des; - OK(len); - - case RH_GET_CONFIGURATION: - bufp[0] = 0x01; - OK(1); - - case RH_SET_CONFIGURATION: - OK(0); - - default: - PDEBUG(1, "unsupported root hub command\n"); - status = -32; - } - - len = min(len, buf_len); - if (data != bufp) - memcpy(data, bufp, len); - - PDEBUG(5, "len = %d, status = %d\n", len, status); - - usb_dev->status = status; - usb_dev->act_len = len; - - return status == 0 ? len : status; -} diff --git a/drivers/usb/host/sl811.h b/drivers/usb/host/sl811.h deleted file mode 100644 index c1f9f013bd..0000000000 --- a/drivers/usb/host/sl811.h +++ /dev/null @@ -1,104 +0,0 @@ -#ifndef __UBOOT_SL811_H -#define __UBOOT_SL811_H - -#undef SL811_DEBUG - -#ifdef SL811_DEBUG - #define PDEBUG(level, fmt, args...) \ - if (debug >= (level)) printf("[%s:%d] " fmt, \ - __PRETTY_FUNCTION__, __LINE__ , ## args) -#else - #define PDEBUG(level, fmt, args...) do {} while(0) -#endif - -/* Sl811 host control register */ -#define SL811_CTRL_A 0x00 -#define SL811_ADDR_A 0x01 -#define SL811_LEN_A 0x02 -#define SL811_STS_A 0x03 /* read */ -#define SL811_PIDEP_A 0x03 /* write */ -#define SL811_CNT_A 0x04 /* read */ -#define SL811_DEV_A 0x04 /* write */ -#define SL811_CTRL1 0x05 -#define SL811_INTR 0x06 -#define SL811_CTRL_B 0x08 -#define SL811_ADDR_B 0x09 -#define SL811_LEN_B 0x0A -#define SL811_STS_B 0x0B /* read */ -#define SL811_PIDEP_B 0x0B /* write */ -#define SL811_CNT_B 0x0C /* read */ -#define SL811_DEV_B 0x0C /* write */ -#define SL811_INTRSTS 0x0D /* write clears bitwise */ -#define SL811_HWREV 0x0E /* read */ -#define SL811_SOFLOW 0x0E /* write */ -#define SL811_SOFCNTDIV 0x0F /* read */ -#define SL811_CTRL2 0x0F /* write */ - -/* USB control register bits (addr 0x00 and addr 0x08) */ -#define SL811_USB_CTRL_ARM 0x01 -#define SL811_USB_CTRL_ENABLE 0x02 -#define SL811_USB_CTRL_DIR_OUT 0x04 -#define SL811_USB_CTRL_ISO 0x10 -#define SL811_USB_CTRL_SOF 0x20 -#define SL811_USB_CTRL_TOGGLE_1 0x40 -#define SL811_USB_CTRL_PREAMBLE 0x80 - -/* USB status register bits (addr 0x03 and addr 0x0B) */ -#define SL811_USB_STS_ACK 0x01 -#define SL811_USB_STS_ERROR 0x02 -#define SL811_USB_STS_TIMEOUT 0x04 -#define SL811_USB_STS_TOGGLE_1 0x08 -#define SL811_USB_STS_SETUP 0x10 -#define SL811_USB_STS_OVERFLOW 0x20 -#define SL811_USB_STS_NAK 0x40 -#define SL811_USB_STS_STALL 0x80 - -/* Control register 1 bits (addr 0x05) */ -#define SL811_CTRL1_SOF 0x01 -#define SL811_CTRL1_RESET 0x08 -#define SL811_CTRL1_JKSTATE 0x10 -#define SL811_CTRL1_SPEED_LOW 0x20 -#define SL811_CTRL1_SUSPEND 0x40 - -/* Interrut enable (addr 0x06) and interrupt status register bits (addr 0x0D) */ -#define SL811_INTR_DONE_A 0x01 -#define SL811_INTR_DONE_B 0x02 -#define SL811_INTR_SOF 0x10 -#define SL811_INTR_INSRMV 0x20 -#define SL811_INTR_DETECT 0x40 -#define SL811_INTR_NOTPRESENT 0x40 -#define SL811_INTR_SPEED_FULL 0x80 /* only in status reg */ - -/* HW rev and SOF lo register bits (addr 0x0E) */ -#define SL811_HWR_HWREV 0xF0 - -/* SOF counter and control reg 2 (addr 0x0F) */ -#define SL811_CTL2_SOFHI 0x3F -#define SL811_CTL2_DSWAP 0x40 -#define SL811_CTL2_HOST 0x80 - -/* Set up for 1-ms SOF time. */ -#define SL811_12M_LOW 0xE0 -#define SL811_12M_HI 0x2E - -#define SL811_DATA_START 0x10 -#define SL811_DATA_LIMIT 240 - -/* Requests: bRequest << 8 | bmRequestType */ -#define RH_GET_STATUS 0x0080 -#define RH_CLEAR_FEATURE 0x0100 -#define RH_SET_FEATURE 0x0300 -#define RH_SET_ADDRESS 0x0500 -#define RH_GET_DESCRIPTOR 0x0680 -#define RH_SET_DESCRIPTOR 0x0700 -#define RH_GET_CONFIGURATION 0x0880 -#define RH_SET_CONFIGURATION 0x0900 -#define RH_GET_STATE 0x0280 -#define RH_GET_INTERFACE 0x0A80 -#define RH_SET_INTERFACE 0x0B00 -#define RH_SYNC_FRAME 0x0C80 - - -#define PIDEP(pid, ep) (((pid) & 0x0f) << 4 | (ep)) - -#endif /* __UBOOT_SL811_H */ diff --git a/drivers/usb/host/utmi-armada100.c b/drivers/usb/host/utmi-armada100.c deleted file mode 100644 index 5d66e5881f..0000000000 --- a/drivers/usb/host/utmi-armada100.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * eInfochips Ltd. <www.einfochips.com> - * Written-by: Ajay Bhargav <contact@8051projects.net> - * - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - */ - -#include <common.h> -#include <asm/io.h> -#include <usb.h> -#include <asm/arch/cpu.h> -#include <asm/arch/armada100.h> -#include <asm/arch/utmi-armada100.h> -#include <linux/delay.h> - -static int utmi_phy_init(void) -{ - struct armd1usb_phy_reg *phy_regs = - (struct armd1usb_phy_reg *)UTMI_PHY_BASE; - int timeout; - - setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); - udelay(1000); - setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); - - clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); - setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); - - setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); - - /* Calibrate pll */ - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - udelay(200); - setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); - - udelay(200); - setbits_le32(&phy_regs->utmi_tx, RCAL_START); - udelay(400); - clrbits_le32(&phy_regs->utmi_tx, RCAL_START); - - timeout = 10000; - while (--timeout && ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)) - ; - if (!timeout) - return -1; - - return 0; -} - -/* - * Initialize USB host controller's UTMI Physical interface - */ -int utmi_init(void) -{ - struct armd1mpmu_registers *mpmu_regs = - (struct armd1mpmu_registers *)ARMD1_MPMU_BASE; - - struct armd1apmu_registers *apmu_regs = - (struct armd1apmu_registers *)ARMD1_APMU_BASE; - - /* Turn on 26Mhz ref clock for UTMI PLL */ - setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); - - /* USB Clock reset */ - writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc); - writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc); - - /* Initialize UTMI transceiver */ - return utmi_phy_init(); -} diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index 42e7abddbc..482dfdc6be 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -231,7 +231,7 @@ static int omap2430_musb_probe(struct udevice *dev) otg_board_data = &plat->otg_board_data; - if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) { + if (IS_ENABLED(CONFIG_USB_MUSB_HOST)) { struct musb_host_data *host = dev_get_priv(dev); struct usb_bus_priv *priv = dev_get_uclass_priv(dev); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 440b161b84..2a76d19cc8 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -576,6 +576,8 @@ config ATMEL_HLCD help HLCDC supports video output to an attached LCD panel. +source "drivers/video/ti/Kconfig" + source "drivers/video/exynos/Kconfig" config LOGICORE_DP_TX @@ -634,6 +636,8 @@ config VIDEO_SANDBOX_SDL source "drivers/video/stm32/Kconfig" +source "drivers/video/tidss/Kconfig" + config VIDEO_TEGRA20 bool "Enable LCD support on Tegra20" depends on OF_CONTROL diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 40a871d638..cdb7d9a54d 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -26,16 +26,16 @@ obj-${CONFIG_EXYNOS_FB} += exynos/ obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/ obj-${CONFIG_VIDEO_STM32} += stm32/ obj-${CONFIG_VIDEO_TEGRA124} += tegra124/ +obj-${CONFIG_VIDEO_TIDSS} += tidss/ +obj-y += ti/ obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o -obj-$(CONFIG_LG4573) += lg4573.o obj-$(CONFIG_LOGICORE_DP_TX) += logicore_dp_tx.o obj-$(CONFIG_NXP_TDA19988) += tda19988.o obj-$(CONFIG_OSD) += video_osd-uclass.o obj-$(CONFIG_SANDBOX_OSD) += sandbox_osd.o -obj-$(CONFIG_SCF0403_LCD) += scf0403_lcd.o obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o diff --git a/drivers/video/exynos/Makefile b/drivers/video/exynos/Makefile index 0f58954e49..45067f562c 100644 --- a/drivers/video/exynos/Makefile +++ b/drivers/video/exynos/Makefile @@ -7,4 +7,3 @@ obj-$(CONFIG_EXYNOS_DP) += exynos_dp.o exynos_dp_lowlevel.o obj-$(CONFIG_EXYNOS_FB) += exynos_fb.o obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o -obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index 8b01a1be11..7e60385bcf 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -615,7 +615,7 @@ static int ipuv3_video_probe(struct udevice *dev) if (ret < 0) return ret; #endif - if (CONFIG_IS_ENABLED(PANEL)) { + if (IS_ENABLED(CONFIG_PANEL)) { struct udevice *panel_dev; ret = uclass_get_device(UCLASS_PANEL, 0, &panel_dev); diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c deleted file mode 100644 index dd87fc461b..0000000000 --- a/drivers/video/lg4573.c +++ /dev/null @@ -1,331 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * LCD: LG4573, TFT 4.3", 480x800, RGB24 - * LCD initialization via SPI - * - */ -#include <common.h> -#include <backlight.h> -#include <command.h> -#include <display.h> -#include <dm.h> -#include <log.h> -#include <dm/read.h> -#include <dm/uclass-internal.h> -#include <errno.h> -#include <spi.h> -#include <asm/gpio.h> -#include <linux/delay.h> - -#define PWR_ON_DELAY_MSECS 120 - -static int lb043wv_spi_write_u16(struct spi_slave *slave, u16 val) -{ - unsigned short buf16 = htons(val); - int ret = 0; - - ret = spi_xfer(slave, 16, &buf16, NULL, - SPI_XFER_BEGIN | SPI_XFER_END); - if (ret) - debug("%s: Failed to send: %d\n", __func__, ret); - - return ret; -} - -static void lb043wv_spi_write_u16_array(struct spi_slave *slave, u16 *buff, - int size) -{ - int i; - - for (i = 0; i < size; i++) - lb043wv_spi_write_u16(slave, buff[i]); -} - -static void lb043wv_display_mode_settings(struct spi_slave *slave) -{ - static u16 display_mode_settings[] = { - 0x703A, - 0x7270, - 0x70B1, - 0x7208, - 0x723B, - 0x720F, - 0x70B2, - 0x7200, - 0x72C8, - 0x70B3, - 0x7200, - 0x70B4, - 0x7200, - 0x70B5, - 0x7242, - 0x7210, - 0x7210, - 0x7200, - 0x7220, - 0x70B6, - 0x720B, - 0x720F, - 0x723C, - 0x7213, - 0x7213, - 0x72E8, - 0x70B7, - 0x7246, - 0x7206, - 0x720C, - 0x7200, - 0x7200, - }; - - debug("transfer display mode settings\n"); - lb043wv_spi_write_u16_array(slave, display_mode_settings, - ARRAY_SIZE(display_mode_settings)); -} - -static void lb043wv_power_settings(struct spi_slave *slave) -{ - static u16 power_settings[] = { - 0x70C0, - 0x7201, - 0x7211, - 0x70C3, - 0x7207, - 0x7203, - 0x7204, - 0x7204, - 0x7204, - 0x70C4, - 0x7212, - 0x7224, - 0x7218, - 0x7218, - 0x7202, - 0x7249, - 0x70C5, - 0x726F, - 0x70C6, - 0x7241, - 0x7263, - }; - - debug("transfer power settings\n"); - lb043wv_spi_write_u16_array(slave, power_settings, - ARRAY_SIZE(power_settings)); -} - -static void lb043wv_gamma_settings(struct spi_slave *slave) -{ - static u16 gamma_settings[] = { - 0x70D0, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D1, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D2, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D3, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D4, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - 0x70D5, - 0x7203, - 0x7207, - 0x7273, - 0x7235, - 0x7200, - 0x7201, - 0x7220, - 0x7200, - 0x7203, - }; - - debug("transfer gamma settings\n"); - lb043wv_spi_write_u16_array(slave, gamma_settings, - ARRAY_SIZE(gamma_settings)); -} - -static void lb043wv_display_on(struct spi_slave *slave) -{ - static u16 sleep_out = 0x7011; - static u16 display_on = 0x7029; - - lb043wv_spi_write_u16(slave, sleep_out); - mdelay(PWR_ON_DELAY_MSECS); - lb043wv_spi_write_u16(slave, display_on); -} - -static int lg4573_spi_startup(struct spi_slave *slave) -{ - int ret; - - ret = spi_claim_bus(slave); - if (ret) - return ret; - - lb043wv_display_mode_settings(slave); - lb043wv_power_settings(slave); - lb043wv_gamma_settings(slave); - lb043wv_display_on(slave); - - spi_release_bus(slave); - return 0; -} - -static int do_lgset(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - struct spi_slave *slave; - struct udevice *dev; - int ret; - - ret = uclass_get_device_by_driver(UCLASS_DISPLAY, - DM_DRIVER_GET(lg4573_lcd), &dev); - if (ret) { - printf("%s: Could not get lg4573 device\n", __func__); - return ret; - } - slave = dev_get_parent_priv(dev); - if (!slave) { - printf("%s: No slave data\n", __func__); - return -ENODEV; - } - lg4573_spi_startup(slave); - - return 0; -} - -U_BOOT_CMD( - lgset, 2, 1, do_lgset, - "set lgdisplay", - "" -); - -static int lg4573_bind(struct udevice *dev) -{ - return 0; -} - -static int lg4573_probe(struct udevice *dev) -{ - return 0; -} - -static const struct udevice_id lg4573_ids[] = { - { .compatible = "lg,lg4573" }, - { } -}; - -struct lg4573_lcd_priv { - struct display_timing timing; - struct udevice *backlight; - struct gpio_desc enable; - int panel_bpp; - u32 power_on_delay; -}; - -static int lg4573_lcd_read_timing(struct udevice *dev, - struct display_timing *timing) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - - memcpy(timing, &priv->timing, sizeof(struct display_timing)); - - return 0; -} - -static int lg4573_lcd_enable(struct udevice *dev, int bpp, - const struct display_timing *edid) -{ - struct spi_slave *slave = dev_get_parent_priv(dev); - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret = 0; - - dm_gpio_set_value(&priv->enable, 1); - ret = backlight_enable(priv->backlight); - - mdelay(priv->power_on_delay); - lg4573_spi_startup(slave); - - return ret; -}; - -static const struct dm_display_ops lg4573_lcd_ops = { - .read_timing = lg4573_lcd_read_timing, - .enable = lg4573_lcd_enable, -}; - -static int lg4573_of_to_plat(struct udevice *dev) -{ - struct lg4573_lcd_priv *priv = dev_get_priv(dev); - int ret; - - ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, - "backlight", &priv->backlight); - if (ret) { - debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); - } - ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, - GPIOD_IS_OUT); - if (ret) { - debug("%s: Warning: cannot get enable GPIO: ret=%d\n", - __func__, ret); - if (ret != -ENOENT) - return log_ret(ret); - } - - priv->power_on_delay = dev_read_u32_default(dev, "power-on-delay", 10); - - return 0; -} - -U_BOOT_DRIVER(lg4573_lcd) = { - .name = "lg4573", - .id = UCLASS_DISPLAY, - .ops = &lg4573_lcd_ops, - .of_to_plat = lg4573_of_to_plat, - .of_match = lg4573_ids, - .bind = lg4573_bind, - .probe = lg4573_probe, - .priv_auto = sizeof(struct lg4573_lcd_priv), -}; diff --git a/drivers/video/scf0403_lcd.c b/drivers/video/scf0403_lcd.c deleted file mode 100644 index 54f0f88b4c..0000000000 --- a/drivers/video/scf0403_lcd.c +++ /dev/null @@ -1,297 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * scf0403.c -- support for DataImage SCF0403 LCD - * - * Copyright (c) 2013 Adapted from Linux driver: - * Copyright (c) 2012 Anders Electronics plc. All Rights Reserved. - * Copyright (c) 2012 CompuLab, Ltd - * Dmitry Lifshitz <lifshitz@compulab.co.il> - * Ilya Ledvich <ilya@compulab.co.il> - * Inspired by Alberto Panizzo <maramaopercheseimorto@gmail.com> & - * Marek Vasut work in l4f00242t03.c - * - * U-Boot port: Nikita Kiryanov <nikita@compulab.co.il> - */ - -#include <common.h> -#include <malloc.h> -#include <asm/gpio.h> -#include <spi.h> -#include <linux/delay.h> - -struct scf0403_cmd { - u16 cmd; - u16 *params; - int count; -}; - -struct scf0403_initseq_entry { - struct scf0403_cmd cmd; - int delay_ms; -}; - -struct scf0403_priv { - struct spi_slave *spi; - unsigned int reset_gpio; - u32 rddid; - struct scf0403_initseq_entry *init_seq; - int seq_size; -}; - -struct scf0403_priv priv; - -#define SCF0403852GGU04_ID 0x000080 - -/* SCF0403526GGU20 model commands parameters */ -static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06}; -static u16 spiinttype_params_sn20[] = {0x60}; -static u16 bc_params_sn20[] = { - 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B, - 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01, - 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40, -}; -static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67}; -static u16 be_params_sn20[] = { - 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22, -}; -static u16 vcom_params_sn20[] = {0x74}; -static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00}; -static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00}; -static u16 lvglvolt_params_sn20[] = {0x08}; -static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20}; -static u16 dispfunc_params_sn20[] = {0xa0}; -static u16 dvddvolt_params_sn20[] = {0x74}; -static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00}; -static u16 panelres_params_sn20[] = {0x82}; -static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13}; -static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28}; -static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20}; -static u16 memaccess_params_sn20[] = {0x00}; -static u16 pixfmt_params_sn20[] = {0x66}; -static u16 pgamma_params_sn20[] = { - 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04, - 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10, -}; -static u16 ngamma_params_sn20[] = { - 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03, - 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00, -}; -static u16 tearing_params_sn20[] = {0x00}; - -/* SCF0403852GGU04 model commands parameters */ -static u16 memaccess_params_sn04[] = {0x08}; -static u16 pixfmt_params_sn04[] = {0x66}; -static u16 modectl_params_sn04[] = {0x01}; -static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04}; -static u16 vcom_params_sn04[] = {0x00, 0x6A}; -static u16 pgamma_params_sn04[] = { - 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c, - 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f, -}; -static u16 ngamma_params_sn04[] = { - 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05, - 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00, -}; -static u16 dispinv_params_sn04[] = {0x02}; - -/* Common commands */ -static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0}; -static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0}; - -/* SCF0403852GGU04 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn04[] = { - {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0}, - {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0}, - {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0}, - {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0}, - {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0}, - {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20}, - {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0}, - {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100}, -}; - -/* SCF0403526GGU20 init sequence */ -static struct scf0403_initseq_entry scf0403_initseq_sn20[] = { - {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0}, - {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0}, - {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0}, - {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0}, - {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0}, - {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0}, - {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0}, - {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0}, - {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0}, - {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0}, - {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0}, - {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0}, - {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0}, - {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0}, - {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0}, - {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0}, - {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0}, - {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0}, - {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0}, - {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0}, - {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0}, - {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0}, -}; - -static void scf0403_gpio_reset(unsigned int gpio) -{ - if (!gpio_is_valid(gpio)) - return; - - gpio_set_value(gpio, 1); - mdelay(100); - gpio_set_value(gpio, 0); - mdelay(40); - gpio_set_value(gpio, 1); - mdelay(100); -} - -static int scf0403_spi_read_rddid(struct spi_slave *spi, u32 *rddid) -{ - int error = 0; - u8 ids_buf = 0x00; - u16 dummy_buf = 0x00; - u16 cmd = 0x04; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - /* Here 9 bits required to transmit a command */ - error = spi_xfer(spi, 9, &cmd, NULL, SPI_XFER_ONCE); - if (error) - return error; - - /* - * Here 8 + 1 bits required to arrange extra clock cycle - * before the first data bit. - * According to the datasheet - first parameter is the dummy data. - */ - error = spi_xfer(spi, 9, NULL, &dummy_buf, SPI_XFER_ONCE); - if (error) - return error; - - error = spi_set_wordlen(spi, 8); - if (error) - return error; - - /* Read rest of the data */ - error = spi_xfer(spi, 8, NULL, &ids_buf, SPI_XFER_ONCE); - if (error) - return error; - - *rddid = ids_buf; - - return 0; -} - -static int scf0403_spi_transfer(struct spi_slave *spi, struct scf0403_cmd *cmd) -{ - int i, error; - u32 command = cmd->cmd; - u32 msg; - - error = spi_set_wordlen(spi, 9); - if (error) - return error; - - error = spi_xfer(spi, 9, &command, NULL, SPI_XFER_ONCE); - if (error) - return error; - - for (i = 0; i < cmd->count; i++) { - msg = (cmd->params[i] | 0x100); - error = spi_xfer(spi, 9, &msg, NULL, SPI_XFER_ONCE); - if (error) - return error; - } - - return 0; -} - -static void scf0403_lcd_init(struct scf0403_priv *priv) -{ - int i; - - /* reset LCD */ - scf0403_gpio_reset(priv->reset_gpio); - - for (i = 0; i < priv->seq_size; i++) { - if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) - puts("SPI transfer failed\n"); - - mdelay(priv->init_seq[i].delay_ms); - } -} - -static int scf0403_request_reset_gpio(unsigned gpio) -{ - int err = gpio_request(gpio, "lcd reset"); - - if (err) - return err; - - err = gpio_direction_output(gpio, 0); - if (err) - gpio_free(gpio); - - return err; -} - -int scf0403_init(int reset_gpio) -{ - int error; - - if (gpio_is_valid(reset_gpio)) { - error = scf0403_request_reset_gpio(reset_gpio); - if (error) { - printf("Failed requesting reset GPIO%d: %d\n", - reset_gpio, error); - return error; - } - } - - priv.reset_gpio = reset_gpio; - priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); - error = spi_claim_bus(priv.spi); - if (error) - goto bus_claim_fail; - - /* reset LCD */ - scf0403_gpio_reset(reset_gpio); - - error = scf0403_spi_read_rddid(priv.spi, &priv.rddid); - if (error) { - puts("IDs read failed\n"); - goto readid_fail; - } - - if (priv.rddid == SCF0403852GGU04_ID) { - priv.init_seq = scf0403_initseq_sn04; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn04); - } else { - priv.init_seq = scf0403_initseq_sn20; - priv.seq_size = ARRAY_SIZE(scf0403_initseq_sn20); - } - - scf0403_lcd_init(&priv); - - /* Start operation */ - scf0403_spi_transfer(priv.spi, &scf0403_cmd_dison); - mdelay(100); - scf0403_spi_transfer(priv.spi, &scf0403_cmd_slpout); - spi_release_bus(priv.spi); - - return 0; - -readid_fail: - spi_release_bus(priv.spi); -bus_claim_fail: - if (gpio_is_valid(priv.reset_gpio)) - gpio_free(priv.reset_gpio); - - return error; -} diff --git a/drivers/video/simple_panel.c b/drivers/video/simple_panel.c index c8f7022ea6..91c91ee75d 100644 --- a/drivers/video/simple_panel.c +++ b/drivers/video/simple_panel.c @@ -63,12 +63,15 @@ static int simple_panel_of_to_plat(struct udevice *dev) return ret; } } + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, - "backlight", &priv->backlight); + "backlight", &priv->backlight); if (ret) { debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); - return log_ret(ret); + if (ret != -ENOENT) + return log_ret(ret); } + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, GPIOD_IS_OUT); if (ret) { diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig new file mode 100644 index 0000000000..3081e9e8c0 --- /dev/null +++ b/drivers/video/ti/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> +# +config AM335X_LCD + bool "Enable AM335x video support" + help + Supports video output to an attached LCD panel. diff --git a/drivers/video/ti/Makefile b/drivers/video/ti/Makefile new file mode 100644 index 0000000000..1f551c84f3 --- /dev/null +++ b/drivers/video/ti/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> +# + +obj-$(CONFIG_AM335X_LCD) += tilcdc.o tilcdc-panel.o diff --git a/drivers/video/ti/tilcdc-panel.c b/drivers/video/ti/tilcdc-panel.c new file mode 100644 index 0000000000..df95086a51 --- /dev/null +++ b/drivers/video/ti/tilcdc-panel.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * OMAP panel support + * + * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> + */ + +#include <common.h> +#include <backlight.h> +#include <clk.h> +#include <display.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <log.h> +#include <panel.h> +#include <asm/gpio.h> +#include <linux/err.h> +#include "tilcdc.h" + +struct tilcdc_panel_priv { + struct tilcdc_panel_info info; + struct display_timing timing; + struct udevice *backlight; + struct gpio_desc enable; +}; + +static int tilcdc_panel_enable_backlight(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_set_value(&priv->enable, 1); + + if (priv->backlight) + return backlight_enable(priv->backlight); + + return 0; +} + +static int tilcdc_panel_set_backlight(struct udevice *dev, int percent) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_set_value(&priv->enable, 1); + + if (priv->backlight) + return backlight_set_brightness(priv->backlight, percent); + + return 0; +} + +int tilcdc_panel_get_display_info(struct udevice *dev, + struct tilcdc_panel_info *info) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + memcpy(info, &priv->info, sizeof(*info)); + return 0; +} + +static int tilcdc_panel_get_display_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(*timing)); + return 0; +} + +static int tilcdc_panel_remove(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + + if (dm_gpio_is_valid(&priv->enable)) + dm_gpio_free(dev, &priv->enable); + + return 0; +} + +static int tilcdc_panel_probe(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + int err; + + err = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (err) + dev_warn(dev, "failed to get backlight\n"); + + err = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (err) { + dev_warn(dev, "failed to get enable GPIO\n"); + if (err != -ENOENT) + return err; + } + + return 0; +} + +static int tilcdc_panel_of_to_plat(struct udevice *dev) +{ + struct tilcdc_panel_priv *priv = dev_get_priv(dev); + ofnode node; + int err; + + err = ofnode_decode_display_timing(dev_ofnode(dev), 0, &priv->timing); + if (err) { + dev_err(dev, "failed to get display timing\n"); + return err; + } + + node = dev_read_subnode(dev, "panel-info"); + if (!ofnode_valid(node)) { + dev_err(dev, "missing 'panel-info' node\n"); + return -ENXIO; + } + + err |= ofnode_read_u32(node, "ac-bias", &priv->info.ac_bias); + err |= ofnode_read_u32(node, "ac-bias-intrpt", + &priv->info.ac_bias_intrpt); + err |= ofnode_read_u32(node, "dma-burst-sz", &priv->info.dma_burst_sz); + err |= ofnode_read_u32(node, "bpp", &priv->info.bpp); + err |= ofnode_read_u32(node, "fdd", &priv->info.fdd); + err |= ofnode_read_u32(node, "sync-edge", &priv->info.sync_edge); + err |= ofnode_read_u32(node, "sync-ctrl", &priv->info.sync_ctrl); + err |= ofnode_read_u32(node, "raster-order", &priv->info.raster_order); + err |= ofnode_read_u32(node, "fifo-th", &priv->info.fifo_th); + if (err) { + dev_err(dev, "failed to get panel info\n"); + return err; + } + + /* optional */ + priv->info.tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode"); + priv->info.invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk"); + + dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n", + priv->timing.hactive.typ, priv->timing.vactive.typ, + priv->info.bpp, priv->timing.pixelclock.typ); + dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n", + priv->timing.hback_porch.typ, priv->timing.hfront_porch.typ, + priv->timing.hsync_len.typ); + dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n", + priv->timing.vback_porch.typ, priv->timing.vfront_porch.typ, + priv->timing.vsync_len.typ); + + return 0; +} + +static const struct panel_ops tilcdc_panel_ops = { + .enable_backlight = tilcdc_panel_enable_backlight, + .set_backlight = tilcdc_panel_set_backlight, + .get_display_timing = tilcdc_panel_get_display_timing, +}; + +static const struct udevice_id tilcdc_panel_ids[] = { + {.compatible = "ti,tilcdc,panel"}, + {} +}; + +U_BOOT_DRIVER(tilcdc_panel) = { + .name = "tilcdc_panel", + .id = UCLASS_PANEL, + .of_match = tilcdc_panel_ids, + .ops = &tilcdc_panel_ops, + .of_to_plat = tilcdc_panel_of_to_plat, + .probe = tilcdc_panel_probe, + .remove = tilcdc_panel_remove, + .priv_auto = sizeof(struct tilcdc_panel_priv), +}; diff --git a/drivers/video/ti/tilcdc-panel.h b/drivers/video/ti/tilcdc-panel.h new file mode 100644 index 0000000000..6bcfbf8a8b --- /dev/null +++ b/drivers/video/ti/tilcdc-panel.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> + */ + +#ifndef _TILCDC_PANEL_H +#define _TILCDC_PANEL_H + +#include "tilcdc.h" + +int tilcdc_panel_get_display_info(struct udevice *dev, + struct tilcdc_panel_info *info); + +#endif /* _TILCDC_PANEL_H */ diff --git a/drivers/video/ti/tilcdc.c b/drivers/video/ti/tilcdc.c new file mode 100644 index 0000000000..88043fc18c --- /dev/null +++ b/drivers/video/ti/tilcdc.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <log.h> +#include <panel.h> +#include <video.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <asm/utils.h> +#include "tilcdc.h" +#include "tilcdc-panel.h" + +#define LCDC_FMAX 200000000 + +/* LCD Control Register */ +#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8) +#define LCDC_CTRL_RASTER_MODE BIT(0) +#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8) +/* LCD Clock Enable Register */ +#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0) +#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1) +#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2) +/* LCD DMA Control Register */ +#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4) +#define LCDC_DMA_CTRL_BURST_1 0x0 +#define LCDC_DMA_CTRL_BURST_2 0x1 +#define LCDC_DMA_CTRL_BURST_4 0x2 +#define LCDC_DMA_CTRL_BURST_8 0x3 +#define LCDC_DMA_CTRL_BURST_16 0x4 +#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8) +/* LCD Timing_0 Register */ +#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7) +#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4) +#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24) +/* LCD Timing_1 Register */ +#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0)) +#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10) +#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16) +#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24) +/* LCD Timing_2 Register */ +#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8) +#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4) +#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8) +#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16) +#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20) +#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21) +#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22) +#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23) +#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24) +#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25) +#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16) +#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21) +/* LCD Raster Ctrl Register */ +#define LCDC_RASTER_CTRL_ENABLE BIT(0) +#define LCDC_RASTER_CTRL_TFT_MODE BIT(7) +#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8) +#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12) +#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20) +#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23) +#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25) +#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26) + +enum { + LCDC_MAX_WIDTH = 2048, + LCDC_MAX_HEIGHT = 2048, + LCDC_MAX_LOG2_BPP = VIDEO_BPP32, +}; + +struct tilcdc_regs { + u32 pid; + u32 ctrl; + u32 gap0; + u32 lidd_ctrl; + u32 lidd_cs0_conf; + u32 lidd_cs0_addr; + u32 lidd_cs0_data; + u32 lidd_cs1_conf; + u32 lidd_cs1_addr; + u32 lidd_cs1_data; + u32 raster_ctrl; + u32 raster_timing0; + u32 raster_timing1; + u32 raster_timing2; + u32 raster_subpanel; + u32 raster_subpanel2; + u32 lcddma_ctrl; + u32 lcddma_fb0_base; + u32 lcddma_fb0_ceiling; + u32 lcddma_fb1_base; + u32 lcddma_fb1_ceiling; + u32 sysconfig; + u32 irqstatus_raw; + u32 irqstatus; + u32 irqenable_set; + u32 irqenable_clear; + u32 gap1; + u32 clkc_enable; + u32 clkc_reset; +}; + +struct tilcdc_priv { + struct tilcdc_regs *regs; + struct clk gclk; + struct clk dpll_m2_clk; +}; + +DECLARE_GLOBAL_DATA_PTR; + +static ulong tilcdc_set_pixel_clk_rate(struct udevice *dev, ulong rate) +{ + struct tilcdc_priv *priv = dev_get_priv(dev); + struct tilcdc_regs *regs = priv->regs; + ulong mult_rate, mult_round_rate, best_err, err; + u32 v; + int div, i; + + best_err = rate; + div = 0; + for (i = 2; i <= 255; i++) { + mult_rate = rate * i; + mult_round_rate = clk_round_rate(&priv->gclk, mult_rate); + if (IS_ERR_VALUE(mult_round_rate)) + return mult_round_rate; + + err = mult_rate - mult_round_rate; + if (err < best_err) { + best_err = err; + div = i; + if (err == 0) + break; + } + } + + if (div == 0) { + dev_err(dev, "failed to find a divisor\n"); + return -EFAULT; + } + + mult_rate = clk_set_rate(&priv->gclk, rate * div); + v = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK; + v |= LCDC_CTRL_CLK_DIVISOR(div); + writel(v, ®s->ctrl); + rate = mult_rate / div; + dev_dbg(dev, "rate=%ld, div=%d, err=%ld\n", rate, div, err); + return rate; +} + +static int tilcdc_remove(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct tilcdc_priv *priv = dev_get_priv(dev); + + uc_plat->base -= 0x20; + uc_plat->size += 0x20; + clk_release_all(&priv->gclk, 1); + clk_release_all(&priv->dpll_m2_clk, 1); + return 0; +} + +static int tilcdc_probe(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tilcdc_priv *priv = dev_get_priv(dev); + struct tilcdc_regs *regs = priv->regs; + struct udevice *panel, *clk_dev; + struct tilcdc_panel_info info; + struct display_timing timing; + ulong rate; + u32 reg; + int err; + + /* Before relocation we don't need to do anything */ + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + err = uclass_get_device(UCLASS_PANEL, 0, &panel); + if (err) { + dev_err(dev, "failed to get panel\n"); + return err; + } + + err = panel_get_display_timing(panel, &timing); + if (err) { + dev_err(dev, "failed to get display timing\n"); + return err; + } + + if (timing.pixelclock.typ > (LCDC_FMAX / 2)) { + dev_err(dev, "invalid display clock-frequency: %d Hz\n", + timing.pixelclock.typ); + return -EINVAL; + } + + if (timing.hactive.typ > LCDC_MAX_WIDTH) + timing.hactive.typ = LCDC_MAX_WIDTH; + + if (timing.vactive.typ > LCDC_MAX_HEIGHT) + timing.vactive.typ = LCDC_MAX_HEIGHT; + + err = tilcdc_panel_get_display_info(panel, &info); + if (err) { + dev_err(dev, "failed to get panel info\n"); + return err; + } + + switch (info.bpp) { + case 16: + case 24: + case 32: + break; + default: + dev_err(dev, "invalid seting, bpp: %d\n", info.bpp); + return -EINVAL; + } + + switch (info.dma_burst_sz) { + case 1: + case 2: + case 4: + case 8: + case 16: + break; + default: + dev_err(dev, "invalid setting, dma-burst-sz: %d\n", + info.dma_burst_sz); + return -EINVAL; + } + + err = uclass_get_device_by_name(UCLASS_CLK, "lcd_gclk@534", &clk_dev); + if (err) { + dev_err(dev, "failed to get lcd_gclk device\n"); + return err; + } + + err = clk_request(clk_dev, &priv->gclk); + if (err) { + dev_err(dev, "failed to get %s clock\n", clk_dev->name); + return err; + } + + rate = tilcdc_set_pixel_clk_rate(dev, timing.pixelclock.typ); + if (IS_ERR_VALUE(rate)) { + dev_err(dev, "failed to set pixel clock rate\n"); + return rate; + } + + err = uclass_get_device_by_name(UCLASS_CLK, "dpll_disp_m2_ck@4a4", + &clk_dev); + if (err) { + dev_err(dev, "failed to get dpll_disp_m2 clock device\n"); + return err; + } + + err = clk_request(clk_dev, &priv->dpll_m2_clk); + if (err) { + dev_err(dev, "failed to get %s clock\n", clk_dev->name); + return err; + } + + err = clk_set_parent(&priv->gclk, &priv->dpll_m2_clk); + if (err) { + dev_err(dev, "failed to set %s clock as %s's parent\n", + priv->dpll_m2_clk.dev->name, priv->gclk.dev->name); + return err; + } + + /* palette default entry */ + memset((void *)uc_plat->base, 0, 0x20); + *(unsigned int *)uc_plat->base = 0x4000; + /* point fb behind palette */ + uc_plat->base += 0x20; + uc_plat->size -= 0x20; + + writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN | + LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable); + writel(0, ®s->raster_ctrl); + + reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK; + reg |= LCDC_CTRL_RASTER_MODE; + writel(reg, ®s->ctrl); + + reg = (timing.hactive.typ * timing.vactive.typ * info.bpp) >> 3; + reg += uc_plat->base; + writel(uc_plat->base, ®s->lcddma_fb0_base); + writel(reg, ®s->lcddma_fb0_ceiling); + writel(uc_plat->base, ®s->lcddma_fb1_base); + writel(reg, ®s->lcddma_fb1_ceiling); + + reg = LCDC_DMA_CTRL_FIFO_TH(info.fifo_th); + switch (info.dma_burst_sz) { + case 1: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1); + break; + case 2: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2); + break; + case 4: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4); + break; + case 8: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8); + break; + case 16: + reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16); + break; + } + + writel(reg, ®s->lcddma_ctrl); + + writel(LCDC_RASTER_TIMING_0_HORLSB(timing.hactive.typ) | + LCDC_RASTER_TIMING_0_HORMSB(timing.hactive.typ) | + LCDC_RASTER_TIMING_0_HFPLSB(timing.hfront_porch.typ) | + LCDC_RASTER_TIMING_0_HBPLSB(timing.hback_porch.typ) | + LCDC_RASTER_TIMING_0_HSWLSB(timing.hsync_len.typ), + ®s->raster_timing0); + + writel(LCDC_RASTER_TIMING_1_VBP(timing.vback_porch.typ) | + LCDC_RASTER_TIMING_1_VFP(timing.vfront_porch.typ) | + LCDC_RASTER_TIMING_1_VSW(timing.vsync_len.typ) | + LCDC_RASTER_TIMING_1_VERLSB(timing.vactive.typ), + ®s->raster_timing1); + + reg = LCDC_RASTER_TIMING_2_ACB(info.ac_bias) | + LCDC_RASTER_TIMING_2_ACBI(info.ac_bias_intrpt) | + LCDC_RASTER_TIMING_2_HSWMSB(timing.hsync_len.typ) | + LCDC_RASTER_TIMING_2_VERMSB(timing.vactive.typ) | + LCDC_RASTER_TIMING_2_HBPMSB(timing.hback_porch.typ) | + LCDC_RASTER_TIMING_2_HFPMSB(timing.hfront_porch.typ); + + if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) + reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT; + + if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) + reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT; + + if (info.invert_pxl_clk) + reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT; + + if (info.sync_edge) + reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL; + + if (info.sync_ctrl) + reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL; + + writel(reg, ®s->raster_timing2); + + reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE | + LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(info.fdd); + + if (info.tft_alt_mode) + reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE; + + if (info.bpp == 24) + reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE; + else if (info.bpp == 32) + reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE | + LCDC_RASTER_CTRL_TFT_24BPP_UNPACK; + + if (info.raster_order) + reg |= LCDC_RASTER_CTRL_DATA_ORDER; + + writel(reg, ®s->raster_ctrl); + + uc_priv->xsize = timing.hactive.typ; + uc_priv->ysize = timing.vactive.typ; + uc_priv->bpix = log_2_n_round_up(info.bpp); + + err = panel_enable_backlight(panel); + if (err) { + dev_err(dev, "failed to enable panel backlight\n"); + return err; + } + + return 0; +} + +static int tilcdc_of_to_plat(struct udevice *dev) +{ + struct tilcdc_priv *priv = dev_get_priv(dev); + + priv->regs = (struct tilcdc_regs *)dev_read_addr(dev); + if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) { + dev_err(dev, "failed to get base address\n"); + return -EINVAL; + } + + dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs); + return 0; +} + +static int tilcdc_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + uc_plat->size = ((LCDC_MAX_WIDTH * LCDC_MAX_HEIGHT * + (1 << LCDC_MAX_LOG2_BPP)) >> 3) + 0x20; + + dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size); + return 0; +} + +static const struct udevice_id tilcdc_ids[] = { + {.compatible = "ti,am33xx-tilcdc"}, + {} +}; + +U_BOOT_DRIVER(tilcdc) = { + .name = "tilcdc", + .id = UCLASS_VIDEO, + .of_match = tilcdc_ids, + .bind = tilcdc_bind, + .of_to_plat = tilcdc_of_to_plat, + .probe = tilcdc_probe, + .remove = tilcdc_remove, + .priv_auto = sizeof(struct tilcdc_priv) +}; diff --git a/drivers/video/ti/tilcdc.h b/drivers/video/ti/tilcdc.h new file mode 100644 index 0000000000..2645921df6 --- /dev/null +++ b/drivers/video/ti/tilcdc.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> + */ + +#ifndef _TILCDC_H +#define _TILCDC_H + +/** + * tilcdc_panel_info: Panel parameters + * + * @ac_bias: AC Bias Pin Frequency + * @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt + * @dma_burst_sz: DMA burst size + * @bpp: Bits per pixel + * @fdd: FIFO DMA Request Delay + * @tft_alt_mode: TFT Alternative Signal Mapping (Only for active) + * @invert_pxl_clk: Invert pixel clock + * @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling + * @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore + * @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most + * @fifo_th: DMA FIFO threshold + */ +struct tilcdc_panel_info { + u32 ac_bias; + u32 ac_bias_intrpt; + u32 dma_burst_sz; + u32 bpp; + u32 fdd; + bool tft_alt_mode; + bool invert_pxl_clk; + u32 sync_edge; + u32 sync_ctrl; + u32 raster_order; + u32 fifo_th; +}; + +#endif /* _TILCDC_H */ diff --git a/drivers/video/tidss/Kconfig b/drivers/video/tidss/Kconfig new file mode 100644 index 0000000000..2a5e56ea4e --- /dev/null +++ b/drivers/video/tidss/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Nikhil M Jain, n-jain1@ti.com +# +# based on the linux tidss driver, which is +# +# (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ +# Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + +menuconfig VIDEO_TIDSS + bool "Enable TIDSS video support" + depends on VIDEO + help + TIDSS supports video output options LVDS and + DPI . This option enables these supports which can be used on + devices which have OLDI or HDMI display connected. + diff --git a/drivers/video/tidss/Makefile b/drivers/video/tidss/Makefile new file mode 100644 index 0000000000..f4f8c6c470 --- /dev/null +++ b/drivers/video/tidss/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ +# Nikhil M Jain, n-jain1@ti.com +# +# based on the linux tidss driver, which is +# +# (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ +# Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + + +obj-${CONFIG_VIDEO_TIDSS} = tidss_drv.o diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c new file mode 100644 index 0000000000..078e3e82e3 --- /dev/null +++ b/drivers/video/tidss/tidss_drv.c @@ -0,0 +1,943 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#include <common.h> +#include <dm.h> +#include <clk.h> +#include <log.h> +#include <video.h> +#include <errno.h> +#include <panel.h> +#include <reset.h> +#include <malloc.h> +#include <fdtdec.h> +#include <syscon.h> +#include <regmap.h> +#include <cpu_func.h> +#include <media_bus_format.h> + +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/utils.h> +#include <asm/bitops.h> + +#include <dm/devres.h> +#include <dm/of_access.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> + +#include <linux/bug.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/iopoll.h> + +#include "tidss_drv.h" +#include "tidss_regs.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Panel parameters */ +enum { + LCD_MAX_WIDTH = 1920, + LCD_MAX_HEIGHT = 1200, + LCD_MAX_LOG2_BPP = VIDEO_BPP32, +}; + +static const u16 *dss_common_regmap; + +static const u16 tidss_am62x_common_regs[DSS_COMMON_REG_TABLE_LEN] = { + [DSS_REVISION_OFF] = 0x4, + [DSS_SYSCONFIG_OFF] = 0x8, + [DSS_SYSSTATUS_OFF] = 0x20, + [DSS_IRQ_EOI_OFF] = 0x24, + [DSS_IRQSTATUS_RAW_OFF] = 0x28, + [DSS_IRQSTATUS_OFF] = 0x2c, + [DSS_IRQENABLE_SET_OFF] = 0x30, + [DSS_IRQENABLE_CLR_OFF] = 0x40, + [DSS_VID_IRQENABLE_OFF] = 0x44, + [DSS_VID_IRQSTATUS_OFF] = 0x58, + [DSS_VP_IRQENABLE_OFF] = 0x70, + [DSS_VP_IRQSTATUS_OFF] = 0x7c, + + [WB_IRQENABLE_OFF] = 0x88, + [WB_IRQSTATUS_OFF] = 0x8c, + + [DSS_GLOBAL_MFLAG_ATTRIBUTE_OFF] = 0x90, + [DSS_GLOBAL_OUTPUT_ENABLE_OFF] = 0x94, + [DSS_GLOBAL_BUFFER_OFF] = 0x98, + [DSS_CBA_CFG_OFF] = 0x9c, + [DSS_DBG_CONTROL_OFF] = 0xa0, + [DSS_DBG_STATUS_OFF] = 0xa4, + [DSS_CLKGATING_DISABLE_OFF] = 0xa8, + [DSS_SECURE_DISABLE_OFF] = 0xac, +}; + +/* TIDSS AM62x Features */ +const struct dss_features dss_am625_feats = { + .max_pclk_khz = { + [DSS_VP_DPI] = 165000, + [DSS_VP_OLDI] = 165000, + }, + + .subrev = DSS_AM625, + + .common = "common", + .common_regs = tidss_am62x_common_regs, + + .num_vps = 2, + .vp_name = { "vp1", "vp2" }, + .ovr_name = { "ovr1", "ovr2" }, + .vpclk_name = { "vp1", "vp2" }, + .vp_bus_type = { DSS_VP_OLDI, DSS_VP_DPI }, + + .vp_feat = { .color = { + .has_ctm = true, + .gamma_size = 256, + .gamma_type = TIDSS_GAMMA_8BIT, + }, + }, + + .num_planes = 2, + /* note: vid is plane_id 0 and vidl1 is plane_id 1 */ + .vid_name = { "vidl1", "vid1" }, + .vid_lite = { true, false }, + .vid_order = { 1, 0 }, +}; + +/* Wrapper functions to write and read TI_DSS registers */ +static void dss_write(struct tidss_drv_priv *priv, u16 reg, u32 val) +{ + writel(val, priv->base_common + reg); +} + +static u32 dss_read(struct tidss_drv_priv *priv, u16 reg) +{ + return readl(priv->base_common + reg); +} + +static void dss_vid_write(struct tidss_drv_priv *priv, u32 hw_plane, u16 reg, u32 val) +{ + void __iomem *base = priv->base_vid[hw_plane]; + + writel(val, base + reg); +} + +static u32 dss_vid_read(struct tidss_drv_priv *priv, u32 hw_plane, u16 reg) +{ + void __iomem *base = priv->base_vid[hw_plane]; + + return readl(base + reg); +} + +static void dss_ovr_write(struct tidss_drv_priv *priv, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = priv->base_ovr[hw_videoport]; + + writel(val, base + reg); +} + +static u32 dss_ovr_read(struct tidss_drv_priv *priv, u32 hw_videoport, u16 reg) +{ + void __iomem *base = priv->base_ovr[hw_videoport]; + + return readl(base + reg); +} + +static void dss_vp_write(struct tidss_drv_priv *priv, u32 hw_videoport, + u16 reg, u32 val) +{ + void __iomem *base = priv->base_vp[hw_videoport]; + + writel(val, base + reg); +} + +static u32 dss_vp_read(struct tidss_drv_priv *priv, u32 hw_videoport, u16 reg) +{ + void __iomem *base = priv->base_vp[hw_videoport]; + + return readl(base + reg); +} + +/* generate mask on a register */ +static u32 FLD_MASK(u32 start, u32 end) +{ + return ((1 << (start - end + 1)) - 1) << end; +} + +/* set the given val in specified range */ +static u32 FLD_VAL(u32 val, u32 start, u32 end) +{ + return (val << end) & FLD_MASK(start, end); +} + +/* return the value in the specified range */ +static u32 FLD_GET(u32 val, u32 start, u32 end) +{ + return (val & FLD_MASK(start, end)) >> end; +} + +/* modify the value of the specified range */ +static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) +{ + return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); +} + +/* read and modify common register region of DSS*/ +__maybe_unused +static u32 REG_GET(struct tidss_drv_priv *priv, u32 idx, u32 start, u32 end) +{ + return FLD_GET(dss_read(priv, idx), start, end); +} + +static void REG_FLD_MOD(struct tidss_drv_priv *priv, u32 idx, u32 val, + u32 start, u32 end) +{ + dss_write(priv, idx, FLD_MOD(dss_read(priv, idx), val, + start, end)); +} + +/* read and modify planes vid1 and vid2 register of DSS*/ +static u32 VID_REG_GET(struct tidss_drv_priv *priv, u32 hw_plane, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_vid_read(priv, hw_plane, idx), start, end); +} + +static void VID_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 hw_plane, u32 idx, + u32 val, u32 start, u32 end) +{ + dss_vid_write(priv, hw_plane, idx, + FLD_MOD(dss_vid_read(priv, hw_plane, idx), + val, start, end)); +} + +/* read and modify port vid1 and vid2 registers of DSS*/ +__maybe_unused +static u32 VP_REG_GET(struct tidss_drv_priv *priv, u32 vp, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_vp_read(priv, vp, idx), start, end); +} + +static void VP_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 vp, u32 idx, u32 val, + u32 start, u32 end) +{ + dss_vp_write(priv, vp, idx, FLD_MOD(dss_vp_read(priv, vp, idx), + val, start, end)); +} + +/* read and modify overlay ovr1 and ovr2 registers of DSS*/ +__maybe_unused +static u32 OVR_REG_GET(struct tidss_drv_priv *priv, u32 ovr, u32 idx, + u32 start, u32 end) +{ + return FLD_GET(dss_ovr_read(priv, ovr, idx), start, end); +} + +static void OVR_REG_FLD_MOD(struct tidss_drv_priv *priv, u32 ovr, u32 idx, + u32 val, u32 start, u32 end) +{ + dss_ovr_write(priv, ovr, idx, FLD_MOD(dss_ovr_read(priv, ovr, idx), + val, start, end)); +} + +static void dss_oldi_tx_power(struct tidss_drv_priv *priv, bool power) +{ + u32 val; + + if (WARN_ON(!priv->oldi_io_ctrl)) + return; + + if (priv->feat->subrev == DSS_AM625) { + if (power) { + switch (priv->oldi_mode) { + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* Power down OLDI TX 1 */ + val = OLDI1_PWRDN_TX; + break; + case OLDI_DUAL_LINK: + /* No Power down */ + val = 0; + break; + default: + /* Power down both the OLDI TXes */ + val = OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + break; + } + } else { + val = OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX; + } + regmap_update_bits(priv->oldi_io_ctrl, OLDI_PD_CTRL, + OLDI_BANDGAP_PWR | OLDI0_PWRDN_TX | OLDI1_PWRDN_TX, val); + } +} + +static void dss_set_num_datalines(struct tidss_drv_priv *priv, + u32 hw_videoport) +{ + int v; + u32 num_lines = priv->bus_format->data_width; + + switch (num_lines) { + case 12: + v = 0; break; + case 16: + v = 1; break; + case 18: + v = 2; break; + case 24: + v = 3; break; + case 30: + v = 4; break; + case 36: + v = 5; break; + default: + WARN_ON(1); + v = 3; + } + + VP_REG_FLD_MOD(priv, hw_videoport, DSS_VP_CONTROL, v, 10, 8); +} + +static void dss_enable_oldi(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + u32 oldi_cfg = 0; + u32 oldi_reset_bit = BIT(5 + hw_videoport); + int count = 0; + + /* + * For the moment MASTERSLAVE, and SRC bits of DSS_VP_DSS_OLDI_CFG are + * set statically to 0. + */ + + if (priv->bus_format->data_width == 24) + oldi_cfg |= BIT(8); /* MSB */ + else if (priv->bus_format->data_width != 18) + dev_warn(priv->dev, "%s: %d port width not supported\n", + __func__, priv->bus_format->data_width); + + oldi_cfg |= BIT(7); /* DEPOL */ + + oldi_cfg = FLD_MOD(oldi_cfg, priv->bus_format->oldi_mode_reg_val, 3, 1); + + oldi_cfg |= BIT(12); /* SOFTRST */ + + oldi_cfg |= BIT(0); /* ENABLE */ + + switch (priv->oldi_mode) { + case OLDI_MODE_OFF: + oldi_cfg &= ~BIT(0); /* DISABLE */ + break; + + case OLDI_SINGLE_LINK_SINGLE_MODE: + /* All configuration is done for this mode. */ + break; + + case OLDI_SINGLE_LINK_DUPLICATE_MODE: + oldi_cfg |= BIT(5); /* DUPLICATE MODE */ + break; + + case OLDI_DUAL_LINK: + oldi_cfg |= BIT(11); /* DUALMODESYNC */ + oldi_cfg |= BIT(3); /* data-mapping field also indicates dual-link mode */ + break; + + default: + dev_warn(priv->dev, "%s: Incorrect oldi mode. Returning.\n", + __func__); + return; + } + + dss_vp_write(priv, hw_videoport, DSS_VP_DSS_OLDI_CFG, oldi_cfg); + + while (!(oldi_reset_bit & dss_read(priv, DSS_SYSSTATUS)) && + count < 10000) + count++; + + if (!(oldi_reset_bit & dss_read(priv, DSS_SYSSTATUS))) + dev_warn(priv->dev, "%s: timeout waiting OLDI reset done\n", + __func__); +} + +static const struct dss_color_lut dss_vp_gamma_default_lut[] = { + { .red = 0, .green = 0, .blue = 0, }, + { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, +}; + +static void dss_vp_write_gamma_table(struct tidss_drv_priv *priv, + u32 hw_videoport) +{ + u32 *table = priv->vp_data[hw_videoport].gamma_table; + u32 hwlen = priv->feat->vp_feat.color.gamma_size; + unsigned int i; + + dev_dbg(priv->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); + + for (i = 0; i < hwlen; ++i) { + u32 v = table[i]; + + v |= i << 24; + + dss_vp_write(priv, hw_videoport, DSS_VP_GAMMA_TABLE, v); + } +} + +static void dss_vp_set_gamma(struct tidss_drv_priv *priv, + u32 hw_videoport, const struct dss_color_lut *lut, + unsigned int length) +{ + u32 *table = priv->vp_data[hw_videoport].gamma_table; + u32 hwlen = priv->feat->vp_feat.color.gamma_size; + u32 hwbits; + unsigned int i; + + dev_dbg(priv->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", + __func__, hw_videoport, length, hwlen); + + if (priv->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) + hwbits = 10; + else + hwbits = 8; + + lut = dss_vp_gamma_default_lut; + length = ARRAY_SIZE(dss_vp_gamma_default_lut); + + for (i = 0; i < length - 1; ++i) { + unsigned int first = i * (hwlen - 1) / (length - 1); + unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); + unsigned int w = last - first; + u16 r, g, b; + unsigned int j; + + if (w == 0) + continue; + + for (j = 0; j <= w; j++) { + r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; + g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; + b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; + + r >>= 16 - hwbits; + g >>= 16 - hwbits; + b >>= 16 - hwbits; + + table[first + j] = (r << (hwbits * 2)) | + (g << hwbits) | b; + } + } + + dss_vp_write_gamma_table(priv, hw_videoport); +} + +void dss_vp_enable(struct tidss_drv_priv *priv, u32 hw_videoport, struct display_timing *timing) +{ + bool align, onoff, rf, ieo, ipc, ihs, ivs; + u32 hsw, hfp, hbp, vsw, vfp, vbp; + + dss_set_num_datalines(priv, hw_videoport); + + /* panel parameters to set clocks for video port*/ + hfp = timing->hfront_porch.typ; + hsw = timing->hsync_len.typ; + hbp = timing->hback_porch.typ; + vfp = timing->vfront_porch.typ; + vsw = timing->vsync_len.typ; + vbp = timing->vback_porch.typ; + + dss_vp_write(priv, hw_videoport, DSS_VP_TIMING_H, + FLD_VAL(hsw - 1, 7, 0) | + FLD_VAL(hfp - 1, 19, 8) | FLD_VAL(hbp - 1, 31, 20)); + + dss_vp_write(priv, hw_videoport, DSS_VP_TIMING_V, + FLD_VAL(vsw - 1, 7, 0) | + FLD_VAL(vfp, 19, 8) | FLD_VAL(vbp, 31, 20)); + + ivs = !!(timing->flags & (1 << 3)); + + ihs = !!(timing->flags & (1 << 1)); + + ieo = 0; + + ipc = 0; + + /* always use the 'rf' setting */ + onoff = true; + + rf = true; + + /* always use aligned syncs */ + align = true; + + /* always use DE_HIGH for OLDI */ + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI) + ieo = false; + + dss_vp_write(priv, hw_videoport, DSS_VP_POL_FREQ, + FLD_VAL(align, 18, 18) | + FLD_VAL(onoff, 17, 17) | + FLD_VAL(rf, 16, 16) | + FLD_VAL(ieo, 15, 15) | + FLD_VAL(ipc, 14, 14) | + FLD_VAL(ihs, 13, 13) | + FLD_VAL(ivs, 12, 12)); + + dss_vp_write(priv, hw_videoport, DSS_VP_SIZE_SCREEN, + FLD_VAL(timing->hactive.typ - 1, 11, 0) | + FLD_VAL(timing->vactive.typ - 1, 27, 16)); + + VP_REG_FLD_MOD(priv, hw_videoport, DSS_VP_CONTROL, 1, 0, 0); +} + +enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; + +static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) +{ + u16 c12; + + c12 = c8 << 4; + + switch (mode) { + case C8_TO_C12_REPLICATE: + /* Copy c8 4 MSB to 4 LSB for full scale c12 */ + c12 |= c8 >> 4; + break; + case C8_TO_C12_MAX: + c12 |= 0xF; + break; + default: + case C8_TO_C12_MIN: + break; + } + + return c12; +} + +static u64 argb8888_to_argb12121212(u32 argb8888, enum c8_to_c12_mode m) +{ + u8 a, r, g, b; + u64 v; + + a = (argb8888 >> 24) & 0xff; + r = (argb8888 >> 16) & 0xff; + g = (argb8888 >> 8) & 0xff; + b = (argb8888 >> 0) & 0xff; + + v = ((u64)c8_to_c12(a, m) << 36) | ((u64)c8_to_c12(r, m) << 24) | + ((u64)c8_to_c12(g, m) << 12) | (u64)c8_to_c12(b, m); + + return v; +} + +static void dss_vp_set_default_color(struct tidss_drv_priv *priv, + u32 hw_videoport, u32 default_color) +{ + u64 v; + + v = argb8888_to_argb12121212(default_color, C8_TO_C12_REPLICATE); + dss_ovr_write(priv, hw_videoport, + DSS_OVR_DEFAULT_COLOR, v & 0xffffffff); + dss_ovr_write(priv, hw_videoport, + DSS_OVR_DEFAULT_COLOR2, (v >> 32) & 0xffff); +} + +int dss_vp_enable_clk(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + int ret = clk_prepare_enable(&priv->vp_clk[hw_videoport]); + + if (ret) + dev_dbg(priv->dev, "%s: enabling clk failed: %d\n", __func__, + ret); + + return ret; +} + +void dss_vp_prepare(struct tidss_drv_priv *priv, u32 hw_videoport) +{ + dss_vp_set_gamma(priv, hw_videoport, NULL, 0); + dss_vp_set_default_color(priv, 0, 0); + + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI) { + dss_oldi_tx_power(priv, true); + dss_enable_oldi(priv, hw_videoport); + } +} + +static +unsigned int dss_pclk_diff(unsigned long rate, unsigned long real_rate) +{ + int r = rate / 100, rr = real_rate / 100; + + return (unsigned int)(abs(((rr - r) * 100) / r)); +} + +int dss_vp_set_clk_rate(struct tidss_drv_priv *priv, u32 hw_videoport, + unsigned long rate) +{ + int r; + unsigned long new_rate; + + /* + * For AM625 OLDI video ports, the requested pixel clock needs to take into account the + * serial clock required for the serialization of DPI signals into LVDS signals. The + * incoming pixel clock on the OLDI video port gets divided by 7 whenever OLDI enable bit + * gets set. + */ + if (priv->feat->vp_bus_type[hw_videoport] == DSS_VP_OLDI && + priv->feat->subrev == DSS_AM625) + rate *= 7; + + r = clk_set_rate(&priv->vp_clk[hw_videoport], rate); + + new_rate = clk_get_rate(&priv->vp_clk[hw_videoport]); + + if (dss_pclk_diff(rate, new_rate) > 5) + dev_warn(priv->dev, + "vp%d: Clock rate %lu differs over 5%% from requested %lu\n", + hw_videoport, new_rate, rate); + + dev_dbg(priv->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", + hw_videoport, clk_get_rate(&priv->vp_clk[hw_videoport]), rate); + return 0; +} + +static void dss_ovr_set_plane(struct tidss_drv_priv *priv, + u32 hw_plane, u32 hw_ovr, + u32 x, u32 y, u32 layer) +{ + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + 0x1, 4, 1); + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + x, 17, 6); + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + y, 30, 19); +} + +void dss_ovr_enable_layer(struct tidss_drv_priv *priv, + u32 hw_ovr, u32 layer, bool enable) +{ + OVR_REG_FLD_MOD(priv, hw_ovr, DSS_OVR_ATTRIBUTES(layer), + !!enable, 0, 0); +} + +static void dss_vid_csc_enable(struct tidss_drv_priv *priv, u32 hw_plane, + bool enable) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, !!enable, 9, 9); +} + +int dss_plane_setup(struct tidss_drv_priv *priv, u32 hw_plane, u32 hw_videoport) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, + priv->pixel_format, 6, 1); + + dss_vid_write(priv, hw_plane, DSS_VID_PICTURE_SIZE, + ((LCD_MAX_WIDTH - 1) | ((LCD_MAX_HEIGHT - 1) << 16))); + + dss_vid_csc_enable(priv, hw_plane, false); + + dss_vid_write(priv, hw_plane, DSS_VID_GLOBAL_ALPHA, 0xFF); + + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, 1, 28, 28); + return 0; +} + +int dss_plane_enable(struct tidss_drv_priv *priv, u32 hw_plane, bool enable) +{ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, !!enable, 0, 0); + + return 0; +} + +static u32 dss_vid_get_fifo_size(struct tidss_drv_priv *priv, u32 hw_plane) +{ + return VID_REG_GET(priv, hw_plane, DSS_VID_BUF_SIZE_STATUS, 15, 0); +} + +static void dss_vid_set_mflag_threshold(struct tidss_drv_priv *priv, + u32 hw_plane, u32 low, u32 high) +{ + dss_vid_write(priv, hw_plane, DSS_VID_MFLAG_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static +void dss_vid_set_buf_threshold(struct tidss_drv_priv *priv, + u32 hw_plane, u32 low, u32 high) +{ + dss_vid_write(priv, hw_plane, DSS_VID_BUF_THRESHOLD, + FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); +} + +static void dss_plane_init(struct tidss_drv_priv *priv) +{ + unsigned int hw_plane; + u32 cba_lo_pri = 1; + u32 cba_hi_pri = 0; + + REG_FLD_MOD(priv, DSS_CBA_CFG, cba_lo_pri, 2, 0); + REG_FLD_MOD(priv, DSS_CBA_CFG, cba_hi_pri, 5, 3); + + /* MFLAG_CTRL = ENABLED */ + REG_FLD_MOD(priv, DSS_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + /* MFLAG_START = MFLAGNORMALSTARTMODE */ + REG_FLD_MOD(priv, DSS_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + + for (hw_plane = 0; hw_plane < priv->feat->num_planes; hw_plane++) { + u32 size = dss_vid_get_fifo_size(priv, hw_plane); + u32 thr_low, thr_high; + u32 mflag_low, mflag_high; + u32 preload; + + thr_high = size - 1; + thr_low = size / 2; + + mflag_high = size * 2 / 3; + mflag_low = size / 3; + + preload = thr_low; + + dev_dbg(priv->dev, + "%s: bufsize %u, buf_threshold %u/%u, mflag threshold %u/%u preload %u\n", + priv->feat->vid_name[hw_plane], + size, + thr_high, thr_low, + mflag_high, mflag_low, + preload); + + dss_vid_set_buf_threshold(priv, hw_plane, + thr_low, thr_high); + dss_vid_set_mflag_threshold(priv, hw_plane, + mflag_low, mflag_high); + + dss_vid_write(priv, hw_plane, DSS_VID_PRELOAD, preload); + + /* Prefech up to PRELOAD value */ + VID_REG_FLD_MOD(priv, hw_plane, DSS_VID_ATTRIBUTES, 0, + 19, 19); + } +} + +static void dss_vp_init(struct tidss_drv_priv *priv) +{ + unsigned int i; + + /* Enable the gamma Shadow bit-field for all VPs*/ + for (i = 0; i < priv->feat->num_vps; i++) + VP_REG_FLD_MOD(priv, i, DSS_VP_CONFIG, 1, 2, 2); +} + +static int dss_init_am65x_oldi_io_ctrl(struct udevice *dev, + struct tidss_drv_priv *priv) +{ + struct udevice *syscon; + struct regmap *regmap; + int ret = 0; + + ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, "ti,am65x-oldi-io-ctrl", + &syscon); + if (ret) { + debug("unable to find ti,am65x-oldi-io-ctrl syscon device (%d)\n", ret); + return ret; + } + + /* get grf-reg base address */ + regmap = syscon_get_regmap(syscon); + if (!regmap) { + debug("unable to find rockchip grf regmap\n"); + return -ENODEV; + } + priv->oldi_io_ctrl = regmap; + return 0; +} + +static int tidss_drv_probe(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct tidss_drv_priv *priv = dev_get_priv(dev); + struct udevice *panel = NULL; + struct display_timing timings; + unsigned int i; + int ret = 0; + const char *mode; + + priv->dev = dev; + + priv->feat = &dss_am625_feats; + + /* + * set your plane format based on your bmp image + * Supported 24bpp and 32bpp bmpimages + */ + + priv->pixel_format = DSS_FORMAT_XRGB8888; + + dss_common_regmap = priv->feat->common_regs; + + ret = uclass_first_device_err(UCLASS_PANEL, &panel); + if (ret) { + if (ret != -ENODEV) + dev_err(dev, "panel device error %d\n", ret); + return ret; + } + + ret = panel_get_display_timing(panel, &timings); + if (ret) { + ret = ofnode_decode_panel_timing(dev_ofnode(panel), + &timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + } + + mode = ofnode_read_string(dev_ofnode(panel), "data-mapping"); + if (!mode) { + debug("%s: Could not read mode property\n", dev->name); + return -EINVAL; + } + + uc_priv->bpix = VIDEO_BPP32; + + if (!strcmp(mode, "vesa-24")) + priv->bus_format = &dss_bus_formats[7]; + else + priv->bus_format = &dss_bus_formats[8]; + + /* Common address */ + priv->base_common = dev_remap_addr_index(dev, 0); + if (!priv->base_common) + return -EINVAL; + + /* plane address setup and enable */ + for (i = 0; i < priv->feat->num_planes; i++) { + priv->base_vid[i] = dev_remap_addr_index(dev, i + 2); + if (!priv->base_vid[i]) + return -EINVAL; + } + + dss_vid_write(priv, 0, DSS_VID_BA_0, uc_plat->base & 0xffffffff); + dss_vid_write(priv, 0, DSS_VID_BA_EXT_0, (u64)uc_plat->base >> 32); + dss_vid_write(priv, 0, DSS_VID_BA_1, uc_plat->base & 0xffffffff); + dss_vid_write(priv, 0, DSS_VID_BA_EXT_1, (u64)uc_plat->base >> 32); + + ret = dss_plane_setup(priv, 0, 0); + if (ret) { + dss_plane_enable(priv, 0, false); + return ret; + } + + dss_plane_enable(priv, 0, true); + dss_plane_init(priv); + + /* video port address clocks and enable */ + for (i = 0; i < priv->feat->num_vps; i++) { + priv->base_ovr[i] = dev_remap_addr_index(dev, i + 4); + priv->base_vp[i] = dev_remap_addr_index(dev, i + 6); + } + + ret = clk_get_by_name(dev, "vp1", &priv->vp_clk[0]); + if (ret) { + dev_err(dev, "video port %d clock enable error %d\n", i, ret); + return ret; + } + + dss_ovr_set_plane(priv, 1, 0, 0, 0, 0); + dss_ovr_enable_layer(priv, 0, 0, true); + + /* Video Port cloks */ + dss_vp_enable_clk(priv, 0); + + dss_vp_set_clk_rate(priv, 0, timings.pixelclock.typ * 1000); + + priv->oldi_mode = OLDI_MODE_OFF; + uc_priv->xsize = timings.hactive.typ; + uc_priv->ysize = timings.vactive.typ; + if (priv->feat->subrev == DSS_AM65X || priv->feat->subrev == DSS_AM625) { + priv->oldi_mode = OLDI_DUAL_LINK; + if (priv->oldi_mode) { + ret = dss_init_am65x_oldi_io_ctrl(dev, priv); + if (ret) + return ret; + } + } + + dss_vp_prepare(priv, 0); + dss_vp_enable(priv, 0, &timings); + dss_vp_init(priv); + + ret = clk_get_by_name(dev, "fck", &priv->fclk); + if (ret) { + dev_err(dev, "peripheral clock get error %d\n", ret); + return ret; + } + + ret = clk_enable(&priv->fclk); + if (ret) { + dev_err(dev, "peripheral clock enable error %d\n", ret); + return ret; + } + + if (IS_ERR(&priv->fclk)) { + dev_err(dev, "%s: Failed to get fclk: %ld\n", + __func__, PTR_ERR(&priv->fclk)); + return PTR_ERR(&priv->fclk); + } + + dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(&priv->fclk)); + + video_set_flush_dcache(dev, true); + return 0; +} + +static int tidss_drv_remove(struct udevice *dev) +{ + u32 val; + int ret; + struct tidss_drv_priv *priv = dev_get_priv(dev); + + priv->base_common = dev_remap_addr_index(dev, 0); + REG_FLD_MOD(priv, DSS_SYSCONFIG, 1, 1, 1); + /* Wait for reset to complete */ + ret = readl_poll_timeout(priv->base_common + DSS_SYSSTATUS, + val, val & 1, 5000); + if (ret) { + dev_warn(priv->dev, "failed to reset priv\n"); + return ret; + } + return 0; +} + +static int tidss_drv_bind(struct udevice *dev) +{ + struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev); + + uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT * + (1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20; + return 0; +} + +static const struct udevice_id tidss_drv_ids[] = { + { .compatible = "ti,am625-dss" }, + { } +}; + +U_BOOT_DRIVER(tidss_drv) = { + .name = "tidss_drv", + .id = UCLASS_VIDEO, + .of_match = tidss_drv_ids, + .bind = tidss_drv_bind, + .probe = tidss_drv_probe, + .remove = tidss_drv_remove, + .priv_auto = sizeof(struct tidss_drv_priv), + .flags = DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/video/tidss/tidss_drv.h b/drivers/video/tidss/tidss_drv.h new file mode 100644 index 0000000000..e229d975ff --- /dev/null +++ b/drivers/video/tidss/tidss_drv.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * (C) Copyright 2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> + */ + +#ifndef __TIDSS_DRV_H__ +#define __TIDSS_DRV_H__ + +#include <media_bus_format.h> + +#define TIDSS_MAX_PORTS 4 +#define TIDSS_MAX_PLANES 4 + +enum dss_vp_bus_type { + DSS_VP_DPI, /* DPI output */ + DSS_VP_OLDI, /* OLDI (LVDS) output */ + DSS_VP_INTERNAL, /* SoC internal routing */ + DSS_VP_MAX_BUS_TYPE, +}; + +enum dss_oldi_modes { + OLDI_MODE_OFF, /* OLDI turned off / tied off in IP. */ + OLDI_SINGLE_LINK_SINGLE_MODE, /* Single Output over OLDI 0. */ + OLDI_SINGLE_LINK_DUPLICATE_MODE, /* Duplicate Output over OLDI 0 and 1. */ + OLDI_DUAL_LINK, /* Combined Output over OLDI 0 and 1. */ +}; + +struct dss_features_scaling { + u32 in_width_max_5tap_rgb; + u32 in_width_max_3tap_rgb; + u32 in_width_max_5tap_yuv; + u32 in_width_max_3tap_yuv; + u32 upscale_limit; + u32 downscale_limit_5tap; + u32 downscale_limit_3tap; + u32 xinc_max; +}; + +enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; + +/* choose specific DSS based on the board */ +enum dss_subrevision { + DSS_K2G, + DSS_AM65X, + DSS_J721E, + DSS_AM625, +}; + +struct tidss_vp_feat { + struct tidss_vp_color_feat { + u32 gamma_size; + enum tidss_gamma_type gamma_type; + bool has_ctm; + } color; +}; + +struct dss_color_lut { + /* + * Data is U0.16 fixed point format. + */ + __u16 red; + __u16 green; + __u16 blue; + __u16 reserved; +}; + +struct dss_vp_data { + u32 *gamma_table; +}; + +struct dss_features { + int min_pclk_khz; + int max_pclk_khz[DSS_VP_MAX_BUS_TYPE]; + + struct dss_features_scaling scaling; + + enum dss_subrevision subrev; + + const char *common; + const u16 *common_regs; + u32 num_vps; + const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ + const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ + const enum dss_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; + struct tidss_vp_feat vp_feat; + u32 num_planes; + const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ + bool vid_lite[TIDSS_MAX_PLANES]; + u32 vid_order[TIDSS_MAX_PLANES]; +}; + +enum dss_oldi_mode_reg_val { SPWG_18 = 0, JEIDA_24 = 1, SPWG_24 = 2 }; + +struct dss_bus_format { + u32 bus_fmt; + u32 data_width; + bool is_oldi_fmt; + enum dss_oldi_mode_reg_val oldi_mode_reg_val; +}; + +static struct dss_bus_format dss_bus_formats[] = { + { MEDIA_BUS_FMT_RGB444_1X12, 12, false, 0 }, + { MEDIA_BUS_FMT_RGB565_1X16, 16, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X18, 18, false, 0 }, + { MEDIA_BUS_FMT_RGB888_1X24, 24, false, 0 }, + { MEDIA_BUS_FMT_RGB101010_1X30, 30, false, 0 }, + { MEDIA_BUS_FMT_RGB121212_1X36, 36, false, 0 }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, true, SPWG_18 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, true, SPWG_24 }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, true, JEIDA_24 }, +}; + +struct tidss_drv_priv { + struct udevice *dev; + void __iomem *base_common; /* common register region of dss*/ + void __iomem *base_vid[TIDSS_MAX_PLANES]; /* plane register region of dss*/ + void __iomem *base_ovr[TIDSS_MAX_PORTS]; /* overlay register region of dss*/ + void __iomem *base_vp[TIDSS_MAX_PORTS]; /* video port register region of dss*/ + struct regmap *oldi_io_ctrl; + struct clk vp_clk[TIDSS_MAX_PORTS]; + const struct dss_features *feat; + struct clk fclk; + struct dss_vp_data vp_data[TIDSS_MAX_PORTS]; + enum dss_oldi_modes oldi_mode; + struct dss_bus_format *bus_format; + u32 pixel_format; + u32 memory_bandwidth_limit; +}; + +#endif diff --git a/drivers/video/tidss/tidss_regs.h b/drivers/video/tidss/tidss_regs.h new file mode 100644 index 0000000000..440db8d1c7 --- /dev/null +++ b/drivers/video/tidss/tidss_regs.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 Texas Instruments Incorporated - https://www.ti.com/ + * Nikhil M Jain, n-jain1@ti.com + * + * based on the linux tidss driver, which is + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#ifndef __TIDSS_REGS_H +#define __TIDSS_REGS_H + +enum dss_common_regs { + NOT_APPLICABLE_OFF = 0, + DSS_REVISION_OFF, + DSS_SYSCONFIG_OFF, + DSS_SYSSTATUS_OFF, + DSS_IRQ_EOI_OFF, + DSS_IRQSTATUS_RAW_OFF, + DSS_IRQSTATUS_OFF, + DSS_IRQENABLE_SET_OFF, + DSS_IRQENABLE_CLR_OFF, + DSS_VID_IRQENABLE_OFF, + DSS_VID_IRQSTATUS_OFF, + DSS_VP_IRQENABLE_OFF, + DSS_VP_IRQSTATUS_OFF, + WB_IRQENABLE_OFF, + WB_IRQSTATUS_OFF, + DSS_GLOBAL_MFLAG_ATTRIBUTE_OFF, + DSS_GLOBAL_OUTPUT_ENABLE_OFF, + DSS_GLOBAL_BUFFER_OFF, + DSS_CBA_CFG_OFF, + DSS_DBG_CONTROL_OFF, + DSS_DBG_STATUS_OFF, + DSS_CLKGATING_DISABLE_OFF, + DSS_SECURE_DISABLE_OFF, + FBDC_REVISION_1_OFF, + FBDC_REVISION_2_OFF, + FBDC_REVISION_3_OFF, + FBDC_REVISION_4_OFF, + FBDC_REVISION_5_OFF, + FBDC_REVISION_6_OFF, + FBDC_COMMON_CONTROL_OFF, + FBDC_CONSTANT_COLOR_0_OFF, + FBDC_CONSTANT_COLOR_1_OFF, + DSS_CONNECTIONS_OFF, + DSS_MSS_VP1_OFF, + DSS_MSS_VP3_OFF, + DSS_COMMON_REG_TABLE_LEN, +}; + +/* + * dss_common_regmap should be defined as const u16 * and pointing + * to a valid dss common register map for the platform, before the + * macros bellow can be used. + */ + +#define REG(r) (dss_common_regmap[r ## _OFF]) + +#define DSS_REVISION REG(DSS_REVISION) +#define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DSS_IRQ_EOI REG(DSS_IRQ_EOI) +#define DSS_IRQSTATUS_RAW REG(DSS_IRQSTATUS_RAW) +#define DSS_IRQSTATUS REG(DSS_IRQSTATUS) +#define DSS_IRQENABLE_SET REG(DSS_IRQENABLE_SET) +#define DSS_IRQENABLE_CLR REG(DSS_IRQENABLE_CLR) +#define DSS_VID_IRQENABLE(n) (REG(DSS_VID_IRQENABLE) + (n) * 4) +#define DSS_VID_IRQSTATUS(n) (REG(DSS_VID_IRQSTATUS) + (n) * 4) +#define DSS_VP_IRQENABLE(n) (REG(DSS_VP_IRQENABLE) + (n) * 4) +#define DSS_VP_IRQSTATUS(n) (REG(DSS_VP_IRQSTATUS) + (n) * 4) +#define WB_IRQENABLE REG(WB_IRQENABLE) +#define WB_IRQSTATUS REG(WB_IRQSTATUS) + +#define DSS_GLOBAL_MFLAG_ATTRIBUTE REG(DSS_GLOBAL_MFLAG_ATTRIBUTE) +#define DSS_GLOBAL_OUTPUT_ENABLE REG(DSS_GLOBAL_OUTPUT_ENABLE) +#define DSS_GLOBAL_BUFFER REG(DSS_GLOBAL_BUFFER) +#define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DSS_DBG_CONTROL REG(DSS_DBG_CONTROL) +#define DSS_DBG_STATUS REG(DSS_DBG_STATUS) +#define DSS_CLKGATING_DISABLE REG(DSS_CLKGATING_DISABLE) +#define DSS_SECURE_DISABLE REG(DSS_SECURE_DISABLE) + +#define FBDC_REVISION_1 REG(FBDC_REVISION_1) +#define FBDC_REVISION_2 REG(FBDC_REVISION_2) +#define FBDC_REVISION_3 REG(FBDC_REVISION_3) +#define FBDC_REVISION_4 REG(FBDC_REVISION_4) +#define FBDC_REVISION_5 REG(FBDC_REVISION_5) +#define FBDC_REVISION_6 REG(FBDC_REVISION_6) +#define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) +#define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) +#define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) +#define DSS_CONNECTIONS REG(DSS_CONNECTIONS) +#define DSS_MSS_VP1 REG(DSS_MSS_VP1) +#define DSS_MSS_VP3 REG(DSS_MSS_VP3) + +/* VID */ + +#define DSS_VID_ACCUH_0 0x0 +#define DSS_VID_ACCUH_1 0x4 +#define DSS_VID_ACCUH2_0 0x8 +#define DSS_VID_ACCUH2_1 0xc +#define DSS_VID_ACCUV_0 0x10 +#define DSS_VID_ACCUV_1 0x14 +#define DSS_VID_ACCUV2_0 0x18 +#define DSS_VID_ACCUV2_1 0x1c +#define DSS_VID_ATTRIBUTES 0x20 +#define DSS_VID_ATTRIBUTES2 0x24 +#define DSS_VID_BA_0 0x28 +#define DSS_VID_BA_1 0x2c +#define DSS_VID_BA_UV_0 0x30 +#define DSS_VID_BA_UV_1 0x34 +#define DSS_VID_BUF_SIZE_STATUS 0x38 +#define DSS_VID_BUF_THRESHOLD 0x3c +#define DSS_VID_CSC_COEF(n) (0x40 + (n) * 4) + +#define DSS_VID_FIRH 0x5c +#define DSS_VID_FIRH2 0x60 +#define DSS_VID_FIRV 0x64 +#define DSS_VID_FIRV2 0x68 + +#define DSS_VID_FIR_COEFS_H0 0x6c +#define DSS_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) +#define DSS_VID_FIR_COEFS_H0_C 0x90 +#define DSS_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_H12 0xb4 +#define DSS_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) +#define DSS_VID_FIR_COEFS_H12_C 0xf4 +#define DSS_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_V0 0x134 +#define DSS_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) +#define DSS_VID_FIR_COEFS_V0_C 0x158 +#define DSS_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) + +#define DSS_VID_FIR_COEFS_V12 0x17c +#define DSS_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) +#define DSS_VID_FIR_COEFS_V12_C 0x1bc +#define DSS_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) + +#define DSS_VID_GLOBAL_ALPHA 0x1fc +#define DSS_VID_K2G_IRQENABLE 0x200 /* K2G */ +#define DSS_VID_K2G_IRQSTATUS 0x204 /* K2G */ +#define DSS_VID_MFLAG_THRESHOLD 0x208 +#define DSS_VID_PICTURE_SIZE 0x20c +#define DSS_VID_PIXEL_INC 0x210 +#define DSS_VID_K2G_POSITION 0x214 /* K2G */ +#define DSS_VID_PRELOAD 0x218 +#define DSS_VID_ROW_INC 0x21c +#define DSS_VID_SIZE 0x220 +#define DSS_VID_BA_EXT_0 0x22c +#define DSS_VID_BA_EXT_1 0x230 +#define DSS_VID_BA_UV_EXT_0 0x234 +#define DSS_VID_BA_UV_EXT_1 0x238 +#define DSS_VID_CSC_COEF7 0x23c +#define DSS_VID_ROW_INC_UV 0x248 +#define DSS_VID_CLUT 0x260 +#define DSS_VID_SAFETY_ATTRIBUTES 0x2a0 +#define DSS_VID_SAFETY_CAPT_SIGNATURE 0x2a4 +#define DSS_VID_SAFETY_POSITION 0x2a8 +#define DSS_VID_SAFETY_REF_SIGNATURE 0x2ac +#define DSS_VID_SAFETY_SIZE 0x2b0 +#define DSS_VID_SAFETY_LFSR_SEED 0x2b4 +#define DSS_VID_LUMAKEY 0x2b8 +#define DSS_VID_DMA_BUFSIZE 0x2bc /* J721E */ + +/* OVR */ + +#define DSS_OVR_CONFIG 0x0 +#define DSS_OVR_VIRTVP 0x4 /* J721E */ +#define DSS_OVR_DEFAULT_COLOR 0x8 +#define DSS_OVR_DEFAULT_COLOR2 0xc +#define DSS_OVR_TRANS_COLOR_MAX 0x10 +#define DSS_OVR_TRANS_COLOR_MAX2 0x14 +#define DSS_OVR_TRANS_COLOR_MIN 0x18 +#define DSS_OVR_TRANS_COLOR_MIN2 0x1c +#define DSS_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DSS_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +/* VP */ + +#define DSS_VP_CONFIG 0x0 +#define DSS_VP_CONTROL 0x4 +#define DSS_VP_CSC_COEF0 0x8 +#define DSS_VP_CSC_COEF1 0xc +#define DSS_VP_CSC_COEF2 0x10 +#define DSS_VP_DATA_CYCLE_0 0x14 +#define DSS_VP_DATA_CYCLE_1 0x18 +#define DSS_VP_K2G_GAMMA_TABLE 0x20 /* K2G */ +#define DSS_VP_K2G_IRQENABLE 0x3c /* K2G */ +#define DSS_VP_K2G_IRQSTATUS 0x40 /* K2G */ +#define DSS_VP_DATA_CYCLE_2 0x1c +#define DSS_VP_LINE_NUMBER 0x44 +#define DSS_VP_POL_FREQ 0x4c +#define DSS_VP_SIZE_SCREEN 0x50 +#define DSS_VP_TIMING_H 0x54 +#define DSS_VP_TIMING_V 0x58 +#define DSS_VP_CSC_COEF3 0x5c +#define DSS_VP_CSC_COEF4 0x60 +#define DSS_VP_CSC_COEF5 0x64 +#define DSS_VP_CSC_COEF6 0x68 +#define DSS_VP_CSC_COEF7 0x6c +#define DSS_VP_SAFETY_ATTRIBUTES_0 0x70 +#define DSS_VP_SAFETY_ATTRIBUTES_1 0x74 +#define DSS_VP_SAFETY_ATTRIBUTES_2 0x78 +#define DSS_VP_SAFETY_ATTRIBUTES_3 0x7c +#define DSS_VP_SAFETY_CAPT_SIGNATURE_0 0x90 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_1 0x94 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_2 0x98 +#define DSS_VP_SAFETY_CAPT_SIGNATURE_3 0x9c +#define DSS_VP_SAFETY_POSITION_0 0xb0 +#define DSS_VP_SAFETY_POSITION_1 0xb4 +#define DSS_VP_SAFETY_POSITION_2 0xb8 +#define DSS_VP_SAFETY_POSITION_3 0xbc +#define DSS_VP_SAFETY_REF_SIGNATURE_0 0xd0 +#define DSS_VP_SAFETY_REF_SIGNATURE_1 0xd4 +#define DSS_VP_SAFETY_REF_SIGNATURE_2 0xd8 +#define DSS_VP_SAFETY_REF_SIGNATURE_3 0xdc +#define DSS_VP_SAFETY_SIZE_0 0xf0 +#define DSS_VP_SAFETY_SIZE_1 0xf4 +#define DSS_VP_SAFETY_SIZE_2 0xf8 +#define DSS_VP_SAFETY_SIZE_3 0xfc +#define DSS_VP_SAFETY_LFSR_SEED 0x110 +#define DSS_VP_GAMMA_TABLE 0x120 +#define DSS_VP_DSS_OLDI_CFG 0x160 +#define DSS_VP_DSS_OLDI_STATUS 0x164 +#define DSS_VP_DSS_OLDI_LB 0x168 +#define DSS_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ +#define DSS_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ +#define DSS_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ + +/* + * OLDI IO_CTRL register offsets. On AM654 the registers are found + * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from + * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL + * register range. + */ +#define OLDI_DAT0_IO_CTRL 0x00 +#define OLDI_DAT1_IO_CTRL 0x04 +#define OLDI_DAT2_IO_CTRL 0x08 +#define OLDI_DAT3_IO_CTRL 0x0C +#define OLDI_CLK_IO_CTRL 0x10 + +/* Only for AM625 OLDI TX */ +#define OLDI_PD_CTRL 0x100 +#define OLDI_LB_CTRL 0x104 + +#define OLDI_BANDGAP_PWR BIT(8) +#define OLDI_PWRDN_TX BIT(8) +#define OLDI0_PWRDN_TX BIT(0) +#define OLDI1_PWRDN_TX BIT(1) + +/* Supported plane formats */ +#define DSS_FORMAT_ARGB4444 0x0 +#define DSS_FORMAT_ABGR4444 0x1 +#define DSS_FORMAT_RGBA4444 0x2 + +#define DSS_FORMAT_RGB565 0x3 +#define DSS_FORMAT_BGR565 0x4 + +#define DSS_FORMAT_ARGB1555 0x5 +#define DSS_FORMAT_ABGR1555 0x6 + +#define DSS_FORMAT_ARGB8888 0x7 +#define DSS_FORMAT_ABGR8888 0x8 +#define DSS_FORMAT_RGBA8888 0x9 +#define DSS_FORMAT_BGRA8888 0xa + +#define DSS_FORMAT_RGB888 0xb +#define DSS_FORMAT_BGR888 0xc + +#define DSS_FORMAT_ARGB2101010 0xe +#define DSS_FORMAT_ABGR2101010 0xf + +#define DSS_FORMAT_XRGB4444 0x20 +#define DSS_FORMAT_XBGR4444 0x21 +#define DSS_FORMAT_RGBX4444 0x22 + +#define DSS_FORMAT_XRGB1555 0x25 +#define DSS_FORMAT_XBGR1555 0x26 + +#define DSS_FORMAT_XRGB8888 0x27 +#define DSS_FORMAT_XBGR8888 0x28 +#define DSS_FORMAT_RGBX8888 0x29 +#define DSS_FORMAT_BGRX8888 0x2a + +#define DSS_FORMAT_XRGB2101010 0x2e, +#define DSS_FORMAT_XBGR2101010 0x2f, + +#endif /* __TIDSS_DSS_REGS_H */ diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 0ce376ca3f..6aaacff10d 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -196,14 +196,14 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx) { switch (priv->bpix) { case VIDEO_BPP16: - if (CONFIG_IS_ENABLED(VIDEO_BPP16)) { + if (IS_ENABLED(CONFIG_VIDEO_BPP16)) { return ((colours[idx].r >> 3) << 11) | ((colours[idx].g >> 2) << 5) | ((colours[idx].b >> 3) << 0); } break; case VIDEO_BPP32: - if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { + if (IS_ENABLED(CONFIG_VIDEO_BPP32)) { if (priv->format == VIDEO_X2R10G10B10) return (colours[idx].r << 22) | (colours[idx].g << 12) | diff --git a/drivers/virtio/virtio-uclass.c b/drivers/virtio/virtio-uclass.c index 91af412ec1..de9bc90359 100644 --- a/drivers/virtio/virtio-uclass.c +++ b/drivers/virtio/virtio-uclass.c @@ -247,8 +247,8 @@ static int virtio_uclass_post_probe(struct udevice *udev) } device_set_name_alloced(vdev); - if (uc_priv->device == VIRTIO_ID_BLOCK) { - ret = bootdev_setup_for_dev(udev, name); + if (uc_priv->device == VIRTIO_ID_BLOCK && !IS_ENABLED(CONFIG_SANDBOX)) { + ret = bootdev_setup_sibling_blk(vdev, "virtio_bootdev"); if (ret) return log_msg_ret("bootdev", ret); } @@ -275,6 +275,10 @@ static int virtio_uclass_child_pre_probe(struct udevice *vdev) int i; int ret; + /* bootdevs are not virtio devices */ + if (device_get_uclass_id(vdev) == UCLASS_BOOTDEV) + return 0; + /* * Save the real virtio device (eg: virtio-net, virtio-blk) to * the transport (parent) device's uclass priv for future use. diff --git a/drivers/virtio/virtio_blk.c b/drivers/virtio/virtio_blk.c index 30cfc56725..9581058286 100644 --- a/drivers/virtio/virtio_blk.c +++ b/drivers/virtio/virtio_blk.c @@ -4,6 +4,8 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ +#define LOG_CATEGORY UCLASS_VIRTIO + #include <common.h> #include <blk.h> #include <dm.h> @@ -42,6 +44,8 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, sgs[num_out + num_in++] = &data_sg; sgs[num_out + num_in++] = &status_sg; + log_debug("dev=%s, active=%d, priv=%p, priv->vq=%p\n", dev->name, + device_active(dev), priv, priv->vq); ret = virtqueue_add(priv->vq, sgs, num_out, num_in); if (ret) @@ -49,8 +53,10 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, virtqueue_kick(priv->vq); + log_debug("wait..."); while (!virtqueue_get_buf(priv->vq, NULL)) ; + log_debug("done\n"); return status == VIRTIO_BLK_S_OK ? blkcnt : -EIO; } @@ -58,6 +64,7 @@ static ulong virtio_blk_do_req(struct udevice *dev, u64 sector, static ulong virtio_blk_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buffer) { + log_debug("read %s\n", dev->name); return virtio_blk_do_req(dev, start, blkcnt, buffer, VIRTIO_BLK_T_IN); } diff --git a/drivers/xen/events.c b/drivers/xen/events.c index 532216fece..2ebe20dbf2 100644 --- a/drivers/xen/events.c +++ b/drivers/xen/events.c @@ -23,9 +23,9 @@ #include <xen/events.h> #include <xen/hvm.h> -#if CONFIG_IS_ENABLED(XEN_SERIAL) +#if IS_ENABLED(CONFIG_XEN_SERIAL) extern u32 console_evtchn; -#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */ +#endif /* IS_ENABLED(CONFIG_XEN_SERIAL) */ #define NR_EVS 1024 @@ -53,10 +53,10 @@ void unbind_all_ports(void) struct vcpu_info *vcpu_info = &s->vcpu_info[cpu]; for (i = 0; i < NR_EVS; i++) { -#if CONFIG_IS_ENABLED(XEN_SERIAL) +#if IS_ENABLED(CONFIG_XEN_SERIAL) if (i == console_evtchn) continue; -#endif /* CONFIG_IS_ENABLED(XEN_SERIAL) */ +#endif /* IS_ENABLED(CONFIG_XEN_SERIAL) */ if (test_and_clear_bit(i, bound_ports)) { printf("port %d still bound!\n", i); |