diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110.c | 21 | ||||
| -rw-r--r-- | drivers/i2c/designware_i2c.c | 14 | ||||
| -rw-r--r-- | drivers/i2c/designware_i2c.h | 1 | ||||
| -rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 1 |
4 files changed, 6 insertions, 31 deletions
diff --git a/drivers/clk/starfive/clk-jh7110.c b/drivers/clk/starfive/clk-jh7110.c index 5311633c4f..f0b7571097 100644 --- a/drivers/clk/starfive/clk-jh7110.c +++ b/drivers/clk/starfive/clk-jh7110.c @@ -431,51 +431,30 @@ static int jh7110_clk_init(struct udevice *dev) starfive_clk_gate(priv->sys, "u0_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C0_CLK_APB))); - clk_dm(JH7110_I2C0_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u0_dw_i2c_clk_core", "u0_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C1_CLK_APB, starfive_clk_gate(priv->sys, "u1_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C1_CLK_APB))); - clk_dm(JH7110_I2C1_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u1_dw_i2c_clk_core", "u1_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C2_CLK_APB, starfive_clk_gate(priv->sys, "u2_dw_i2c_clk_apb", "apb0", SYS_OFFSET(JH7110_I2C2_CLK_APB))); - clk_dm(JH7110_I2C2_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u2_dw_i2c_clk_core", "u2_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C3_CLK_APB, starfive_clk_gate(priv->sys, "u3_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C3_CLK_APB))); - clk_dm(JH7110_I2C3_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u3_dw_i2c_clk_core", "u3_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C4_CLK_APB, starfive_clk_gate(priv->sys, "u4_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C4_CLK_APB))); - clk_dm(JH7110_I2C4_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u4_dw_i2c_clk_core", "u4_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C5_CLK_APB, starfive_clk_gate(priv->sys, "u5_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C5_CLK_APB))); - clk_dm(JH7110_I2C5_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u5_dw_i2c_clk_core", "u5_dw_i2c_clk_apb", 1, 1)); clk_dm(JH7110_I2C6_CLK_APB, starfive_clk_gate(priv->sys, "u6_dw_i2c_clk_apb", "apb12", SYS_OFFSET(JH7110_I2C6_CLK_APB))); - clk_dm(JH7110_I2C6_CLK_CORE, - starfive_clk_fix_factor(priv->sys, - "u6_dw_i2c_clk_core", "u6_dw_i2c_clk_apb", 1, 1)); /*QSPI*/ clk_dm(JH7110_QSPI_CLK_AHB, diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index c1b3df9600..e57eed0f6c 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -775,14 +775,10 @@ int designware_i2c_of_to_plat(struct udevice *bus) if (ret) return ret; - ret = clk_get_bulk(bus, &priv->clks); - if (ret) - return ret; - - ret = clk_enable_bulk(&priv->clks); + ret = clk_enable(&priv->clk); if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { - clk_release_bulk(&priv->clks); - dev_err(bus, "failed to enable bulk clock\n"); + clk_free(&priv->clk); + dev_err(bus, "failed to enable clock\n"); return ret; } #endif @@ -813,8 +809,8 @@ int designware_i2c_remove(struct udevice *dev) struct dw_i2c *priv = dev_get_priv(dev); #if CONFIG_IS_ENABLED(CLK) - clk_disable_bulk(&priv->clks); - clk_release_bulk(&priv->clks); + clk_disable(&priv->clk); + clk_free(&priv->clk); #endif return reset_release_bulk(&priv->resets); diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h index d5aaef1d79..9b2349a0a2 100644 --- a/drivers/i2c/designware_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -204,7 +204,6 @@ struct dw_i2c { bool has_spk_cnt; #if CONFIG_IS_ENABLED(CLK) struct clk clk; - struct clk_bulk clks; #endif struct dw_i2c_speed_config config; }; diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 35fa347c44..87646ff925 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -366,6 +366,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XTX /* XTX Technology (Shenzhen) Limited */ |