diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/Kconfig | 11 | ||||
| -rw-r--r-- | drivers/clk/Makefile | 1 | ||||
| -rw-r--r-- | drivers/clk/clk-xlnx-clock-wizard.c | 186 | ||||
| -rw-r--r-- | drivers/gpio/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/net/xilinx_axi_emac.c | 193 | ||||
| -rw-r--r-- | drivers/serial/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/serial/serial_zynq.c | 68 | ||||
| -rw-r--r-- | drivers/watchdog/cdns_wdt.c | 41 |
8 files changed, 451 insertions, 55 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 4bc6680121..e07c6dd78a 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -128,6 +128,17 @@ config CLK_ZYNQ This clock driver adds support for clock related settings for Zynq platform. +config CLK_XLNX_CLKWZRD + bool "Xilinx Clocking Wizard" + depends on CLK + help + Support for the Xilinx Clocking Wizard IP core clock generator. + The wizard support for dynamically reconfiguring the clocking + primitives for Multiply, Divide, Phase Shift/Offset, or Duty + Cycle. Limited by U-Boot clk uclass without set_phase API and + set_duty_cycle API, this driver only supports set_rate to modify + the frequency. + config CLK_ZYNQMP bool "Enable clock driver support for ZynqMP" depends on ARCH_ZYNQMP diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f06164bb49..6e9c2d5485 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_VEXPRESS_OSC) += clk_vexpress_osc.o obj-$(CONFIG_CLK_ZYNQ) += clk_zynq.o obj-$(CONFIG_CLK_ZYNQMP) += clk_zynqmp.o +obj-$(CONFIG_CLK_XLNX_CLKWZRD) += clk-xlnx-clock-wizard.o obj-$(CONFIG_ICS8N3QV01) += ics8n3qv01.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o obj-$(CONFIG_SANDBOX) += clk_sandbox.o diff --git a/drivers/clk/clk-xlnx-clock-wizard.c b/drivers/clk/clk-xlnx-clock-wizard.c new file mode 100644 index 0000000000..70ee3af107 --- /dev/null +++ b/drivers/clk/clk-xlnx-clock-wizard.c @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx 'Clocking Wizard' driver + * + * Copyright (c) 2021 Macronix Inc. + * + * Author: Zhengxun Li <zhengxunli@mxic.com.tw> + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <div64.h> +#include <dm/device_compat.h> +#include <linux/iopoll.h> + +#include <linux/bitfield.h> + +#define SRR 0x0 + +#define SR 0x4 +#define SR_LOCKED BIT(0) + +#define CCR(x) (0x200 + ((x) * 4)) + +#define FBOUT_CFG CCR(0) +#define FBOUT_DIV(x) (x) +#define FBOUT_DIV_MASK GENMASK(7, 0) +#define FBOUT_GET_DIV(x) FIELD_GET(FBOUT_DIV_MASK, x) +#define FBOUT_MUL(x) ((x) << 8) +#define FBOUT_MUL_MASK GENMASK(15, 8) +#define FBOUT_GET_MUL(x) FIELD_GET(FBOUT_MUL_MASK, x) +#define FBOUT_FRAC(x) ((x) << 16) +#define FBOUT_FRAC_MASK GENMASK(25, 16) +#define FBOUT_GET_FRAC(x) FIELD_GET(FBOUT_FRAC_MASK, x) +#define FBOUT_FRAC_EN BIT(26) + +#define FBOUT_PHASE CCR(1) + +#define OUT_CFG(x) CCR(2 + ((x) * 3)) +#define OUT_DIV(x) (x) +#define OUT_DIV_MASK GENMASK(7, 0) +#define OUT_GET_DIV(x) FIELD_GET(OUT_DIV_MASK, x) +#define OUT_FRAC(x) ((x) << 8) +#define OUT_GET_MASK GENMASK(17, 8) +#define OUT_GET_FRAC(x) FIELD_GET(OUT_GET_MASK, x) +#define OUT_FRAC_EN BIT(18) + +#define OUT_PHASE(x) CCR(3 + ((x) * 3)) +#define OUT_DUTY(x) CCR(4 + ((x) * 3)) + +#define CTRL CCR(23) +#define CTRL_SEN BIT(2) +#define CTRL_SADDR BIT(1) +#define CTRL_LOAD BIT(0) + +/** + * struct clkwzrd - Clock wizard private data structure + * + * @base: memory base + * @vco_clk: voltage-controlled oscillator frequency + * + */ +struct clkwzd { + void *base; + u64 vco_clk; +}; + +struct clkwzd_plat { + fdt_addr_t addr; +}; + +static int clk_wzrd_enable(struct clk *clk) +{ + struct clkwzd *priv = dev_get_priv(clk->dev); + int ret; + u32 val; + + ret = readl_poll_sleep_timeout(priv->base + SR, val, val & SR_LOCKED, + 1, 100); + if (!ret) { + writel(CTRL_SEN | CTRL_SADDR | CTRL_LOAD, priv->base + CTRL); + writel(CTRL_SADDR, priv->base + CTRL); + ret = readl_poll_sleep_timeout(priv->base + SR, val, + val & SR_LOCKED, 1, 100); + } + + return ret; +} + +static unsigned long clk_wzrd_set_rate(struct clk *clk, ulong rate) +{ + struct clkwzd *priv = dev_get_priv(clk->dev); + u64 div; + u32 cfg; + + /* Get output clock divide value */ + div = DIV_ROUND_DOWN_ULL(priv->vco_clk * 1000, rate); + if (div < 1000 || div > 255999) + return -EINVAL; + + cfg = OUT_DIV((u32)div / 1000); + + writel(cfg, priv->base + OUT_CFG(clk->id)); + + return 0; +} + +static struct clk_ops clk_wzrd_ops = { + .enable = clk_wzrd_enable, + .set_rate = clk_wzrd_set_rate, +}; + +static int clk_wzrd_probe(struct udevice *dev) +{ + struct clkwzd_plat *plat = dev_get_plat(dev); + struct clkwzd *priv = dev_get_priv(dev); + struct clk clk_in1; + u64 clock, vco_clk; + u32 cfg; + int ret; + + priv->base = (void *)plat->addr; + + ret = clk_get_by_name(dev, "clk_in1", &clk_in1); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk_in1); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + + ret = clk_enable(&clk_in1); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + clk_free(&clk_in1); + return ret; + } + + /* Read clock configuration registers */ + cfg = readl(priv->base + FBOUT_CFG); + + /* Recalculate VCO rate */ + if (cfg & FBOUT_FRAC_EN) + vco_clk = DIV_ROUND_DOWN_ULL(clock * + ((FBOUT_GET_MUL(cfg) * 1000) + + FBOUT_GET_FRAC(cfg)), + 1000); + else + vco_clk = clock * FBOUT_GET_MUL(cfg); + + priv->vco_clk = DIV_ROUND_DOWN_ULL(vco_clk, FBOUT_GET_DIV(cfg)); + + return 0; +} + +static int clk_wzrd_of_to_plat(struct udevice *dev) +{ + struct clkwzd_plat *plat = dev_get_plat(dev); + + plat->addr = dev_read_addr(dev); + if (plat->addr == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct udevice_id clk_wzrd_ids[] = { + { .compatible = "xlnx,clocking-wizard" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(clk_wzrd) = { + .name = "zynq-clk-wizard", + .id = UCLASS_CLK, + .of_match = clk_wzrd_ids, + .ops = &clk_wzrd_ops, + .probe = clk_wzrd_probe, + .of_to_plat = clk_wzrd_of_to_plat, + .priv_auto = sizeof(struct clkwzd), + .plat_auto = sizeof(struct clkwzd_plat), +}; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index d24884739b..de4dc51d4b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -396,7 +396,7 @@ config DM_74X164 config DM_PCA953X bool "PCA95[357]x, PCA9698, TCA64xx, and MAX7310 I/O ports" - depends on DM_GPIO + depends on DM_GPIO && DM_I2C help Say yes here to provide access to several register-oriented SMBus I/O expanders, made mostly by NXP or TI. Compatible diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index 2ce6271afe..2ec76d0f52 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2021 Waymo LLC * Copyright (C) 2011 Michal Simek <monstr@monstr.eu> * Copyright (C) 2011 PetaLogix * Copyright (C) 2010 Xilinx, Inc. All rights reserved. @@ -73,9 +74,22 @@ DECLARE_GLOBAL_DATA_PTR; #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ -#define DMAALIGN 128 +/* Bitmasks for XXV Ethernet MAC */ +#define XXV_TC_TX_MASK 0x00000001 +#define XXV_TC_FCS_MASK 0x00000002 +#define XXV_RCW1_RX_MASK 0x00000001 +#define XXV_RCW1_FCS_MASK 0x00000002 + +#define DMAALIGN 128 +#define XXV_MIN_PKT_SIZE 60 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN))); +static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN))); + +enum emac_variant { + EMAC_1G = 0, + EMAC_10G_25G = 1, +}; /* Reflect dma offsets */ struct axidma_reg { @@ -87,6 +101,17 @@ struct axidma_reg { u32 tail_hi; /* TAILDESC high 32 bit */ }; +/* Platform data structures */ +struct axidma_plat { + struct eth_pdata eth_pdata; + struct axidma_reg *dmatx; + struct axidma_reg *dmarx; + int phyaddr; + u8 eth_hasnobuf; + int phy_of_handle; + enum emac_variant mactype; +}; + /* Private driver structures */ struct axidma_priv { struct axidma_reg *dmatx; @@ -98,6 +123,7 @@ struct axidma_priv { struct mii_dev *bus; u8 eth_hasnobuf; int phy_of_handle; + enum emac_variant mactype; }; /* BD descriptors */ @@ -144,6 +170,14 @@ struct axi_regs { u32 uaw1; /* 0x704: Unicast address word 1 */ }; +struct xxv_axi_regs { + u32 gt_reset; /* 0x0 */ + u32 reserved[2]; + u32 tc; /* 0xC: Tx Configuration */ + u32 reserved2; + u32 rcw1; /* 0x14: Rx Configuration Word 1 */ +}; + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -375,6 +409,18 @@ static void axiemac_stop(struct udevice *dev) debug("axiemac: Halted\n"); } +static int xxv_axi_ethernet_init(struct axidma_priv *priv) +{ + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; + + writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1); + writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc); + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); + + return 0; +} + static int axi_ethernet_init(struct axidma_priv *priv) { struct axi_regs *regs = priv->iobase; @@ -430,6 +476,9 @@ static int axiemac_write_hwaddr(struct udevice *dev) struct axidma_priv *priv = dev_get_priv(dev); struct axi_regs *regs = priv->iobase; + if (priv->mactype != EMAC_1G) + return 0; + /* Set the MAC address */ int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) | (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0])); @@ -467,7 +516,6 @@ static void axi_dma_init(struct axidma_priv *priv) static int axiemac_start(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); - struct axi_regs *regs = priv->iobase; u32 temp; debug("axiemac: Init started\n"); @@ -480,8 +528,13 @@ static int axiemac_start(struct udevice *dev) axi_dma_init(priv); /* Initialize AxiEthernet hardware. */ - if (axi_ethernet_init(priv)) - return -1; + if (priv->mactype == EMAC_1G) { + if (axi_ethernet_init(priv)) + return -1; + } else { + if (xxv_axi_ethernet_init(priv)) + return -1; + } /* Disable all RX interrupts before RxBD space setup */ temp = readl(&priv->dmarx->control); @@ -515,15 +568,25 @@ static int axiemac_start(struct udevice *dev) /* Rx BD is ready - start */ axienet_dma_write(&rx_bd, &priv->dmarx->tail); - /* Enable TX */ - writel(XAE_TC_TX_MASK, ®s->tc); - /* Enable RX */ - writel(XAE_RCW1_RX_MASK, ®s->rcw1); + if (priv->mactype == EMAC_1G) { + struct axi_regs *regs = priv->iobase; + /* Enable TX */ + writel(XAE_TC_TX_MASK, ®s->tc); + /* Enable RX */ + writel(XAE_RCW1_RX_MASK, ®s->rcw1); + + /* PHY setup */ + if (!setup_phy(dev)) { + axiemac_stop(dev); + return -1; + } + } else { + struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase; + /* Enable TX */ + writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc); - /* PHY setup */ - if (!setup_phy(dev)) { - axiemac_stop(dev); - return -1; + /* Enable RX */ + writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1); } debug("axiemac: Init complete\n"); @@ -538,6 +601,14 @@ static int axiemac_send(struct udevice *dev, void *ptr, int len) if (len > PKTSIZE_ALIGN) len = PKTSIZE_ALIGN; + /* If size is less than min packet size, pad to min size */ + if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) { + memset(txminframe, 0, XXV_MIN_PKT_SIZE); + memcpy(txminframe, ptr, len); + len = XXV_MIN_PKT_SIZE; + ptr = txminframe; + } + /* Flush packet to main memory to be trasfered by DMA */ flush_cache((phys_addr_t)ptr, len); @@ -622,7 +693,7 @@ static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp) temp = readl(&priv->dmarx->control); temp &= ~XAXIDMA_IRQ_ALL_MASK; writel(temp, &priv->dmarx->control); - if (!priv->eth_hasnobuf) + if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G) length = rx_bd.app4 & 0xFFFF; /* max length mask */ else length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK; @@ -690,19 +761,34 @@ static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad, static int axi_emac_probe(struct udevice *dev) { + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; struct axidma_priv *priv = dev_get_priv(dev); int ret; - priv->bus = mdio_alloc(); - priv->bus->read = axiemac_miiphy_read; - priv->bus->write = axiemac_miiphy_write; - priv->bus->priv = priv; + priv->iobase = (struct axi_regs *)pdata->iobase; + priv->dmatx = plat->dmatx; + /* RX channel offset is 0x30 */ + priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); + priv->mactype = plat->mactype; + + if (priv->mactype == EMAC_1G) { + priv->eth_hasnobuf = plat->eth_hasnobuf; + priv->phyaddr = plat->phyaddr; + priv->phy_of_handle = plat->phy_of_handle; + priv->interface = pdata->phy_interface; + + priv->bus = mdio_alloc(); + priv->bus->read = axiemac_miiphy_read; + priv->bus->write = axiemac_miiphy_write; + priv->bus->priv = priv; - ret = mdio_register_seq(priv->bus, dev_seq(dev)); - if (ret) - return ret; + ret = mdio_register_seq(priv->bus, dev_seq(dev)); + if (ret) + return ret; - axiemac_phy_init(dev); + axiemac_phy_init(dev); + } return 0; } @@ -711,9 +797,11 @@ static int axi_emac_remove(struct udevice *dev) { struct axidma_priv *priv = dev_get_priv(dev); - free(priv->phydev); - mdio_unregister(priv->bus); - mdio_free(priv->bus); + if (priv->mactype == EMAC_1G) { + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); + } return 0; } @@ -729,14 +817,14 @@ static const struct eth_ops axi_emac_ops = { static int axi_emac_of_to_plat(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_plat(dev); - struct axidma_priv *priv = dev_get_priv(dev); + struct axidma_plat *plat = dev_get_plat(dev); + struct eth_pdata *pdata = &plat->eth_pdata; int node = dev_of_offset(dev); int offset = 0; const char *phy_mode; pdata->iobase = dev_read_addr(dev); - priv->iobase = (struct axi_regs *)pdata->iobase; + plat->mactype = dev_get_driver_data(dev); offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "axistream-connected"); @@ -744,43 +832,46 @@ static int axi_emac_of_to_plat(struct udevice *dev) printf("%s: axistream is not found\n", __func__); return -EINVAL; } - priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, + plat->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob, offset, "reg"); - if (!priv->dmatx) { + if (!plat->dmatx) { printf("%s: axi_dma register space not found\n", __func__); return -EINVAL; } - /* RX channel offset is 0x30 */ - priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30); - priv->phyaddr = -1; + if (plat->mactype == EMAC_1G) { + plat->phyaddr = -1; - offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); - if (offset > 0) { - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); - priv->phy_of_handle = offset; - } + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + if (offset > 0) { + plat->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, + "reg", -1); + plat->phy_of_handle = offset; + } - phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); - if (phy_mode) - pdata->phy_interface = phy_get_interface_by_name(phy_mode); - if (pdata->phy_interface == -1) { - printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); - return -EINVAL; - } - priv->interface = pdata->phy_interface; + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + if (pdata->phy_interface == -1) { + printf("%s: Invalid PHY interface '%s'\n", __func__, + phy_mode); + return -EINVAL; + } - priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, - "xlnx,eth-hasnobuf"); + plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node, + "xlnx,eth-hasnobuf"); + } - printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, - priv->phyaddr, phy_string_for_interface(priv->interface)); + printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase, + plat->phyaddr, phy_string_for_interface(pdata->phy_interface)); return 0; } static const struct udevice_id axi_emac_ids[] = { - { .compatible = "xlnx,axi-ethernet-1.00.a" }, + { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G }, + { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G }, { } }; @@ -793,5 +884,5 @@ U_BOOT_DRIVER(axi_emac) = { .remove = axi_emac_remove, .ops = &axi_emac_ops, .priv_auto = sizeof(struct axidma_priv), - .plat_auto = sizeof(struct eth_pdata), + .plat_auto = sizeof(struct axidma_plat), }; diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6d1c4530dd..9f82467c4e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -332,7 +332,7 @@ config DEBUG_UART_APBUART config DEBUG_UART_PL010 bool "pl010" - depends on PL01X_SERIAL + depends on PL01X_SERIAL || PL010_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL010 UART type. You will need to provide parameters to make this @@ -341,7 +341,7 @@ config DEBUG_UART_PL010 config DEBUG_UART_PL011 bool "pl011" - depends on PL011_SERIAL + depends on PL01X_SERIAL || PL011_SERIAL help Select this to enable a debug UART using the pl01x driver with the PL011 UART type. You will need to provide parameters to make this diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 799d524047..2f49f594a4 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -28,7 +28,17 @@ #define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ #define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ +#define ZYNQ_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_5_BIT 0x00000040 /* 1.5 stop bits */ +#define ZYNQ_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ + #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ +#define ZYNQ_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ +#define ZYNQ_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ + +#define ZYNQ_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ +#define ZYNQ_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ +#define ZYNQ_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ struct uart_zynq { u32 control; /* 0x0 - Control Register [8:0] */ @@ -137,6 +147,63 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) return 0; } +#if !defined(CONFIG_SPL_BUILD) +static int zynq_serial_setconfig(struct udevice *dev, uint serial_config) +{ + struct zynq_uart_plat *plat = dev_get_plat(dev); + struct uart_zynq *regs = plat->regs; + u32 val = 0; + + switch (SERIAL_GET_BITS(serial_config)) { + case SERIAL_6_BITS: + val |= ZYNQ_UART_MR_CHARLEN_6_BIT; + break; + case SERIAL_7_BITS: + val |= ZYNQ_UART_MR_CHARLEN_7_BIT; + break; + case SERIAL_8_BITS: + val |= ZYNQ_UART_MR_CHARLEN_8_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_STOP(serial_config)) { + case SERIAL_ONE_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_BIT; + break; + case SERIAL_ONE_HALF_STOP: + val |= ZYNQ_UART_MR_STOPMODE_1_5_BIT; + break; + case SERIAL_TWO_STOP: + val |= ZYNQ_UART_MR_STOPMODE_2_BIT; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + switch (SERIAL_GET_PARITY(serial_config)) { + case SERIAL_PAR_NONE: + val |= ZYNQ_UART_MR_PARITY_NONE; + break; + case SERIAL_PAR_ODD: + val |= ZYNQ_UART_MR_PARITY_ODD; + break; + case SERIAL_PAR_EVEN: + val |= ZYNQ_UART_MR_PARITY_EVEN; + break; + default: + return -ENOTSUPP; /* not supported in driver */ + } + + writel(val, ®s->mode); + + return 0; +} +#else +#define zynq_serial_setconfig NULL +#endif + static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_plat *plat = dev_get_plat(dev); @@ -198,6 +265,7 @@ static const struct dm_serial_ops zynq_serial_ops = { .pending = zynq_serial_pending, .getc = zynq_serial_getc, .setbrg = zynq_serial_setbrg, + .setconfig = zynq_serial_setconfig, }; static const struct udevice_id zynq_serial_ids[] = { diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 966d010e40..6dfdd31c8b 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -215,6 +215,45 @@ static int cdns_wdt_stop(struct udevice *dev) } /** + * cdns_wdt_expire_now - Expire the watchdog. + * + * @dev: Watchdog device + * @flags: Driver flags + * + * Access WDT and configure with minimal counter value to expire ASAP. + * Expiration issues system reset. When DEBUG is enabled count should be + * bigger to at least see debug message. + * + * Return: Always 0 + */ +static int cdns_wdt_expire_now(struct udevice *dev, ulong flags) +{ + struct cdns_wdt_priv *priv = dev_get_priv(dev); + u32 data, count = 0; + +#if defined(DEBUG) + count = 0x40; /* Increase the value if you need more time */ + debug("%s: Expire wdt%u\n", __func__, dev_seq(dev)); +#endif + + cdns_wdt_writereg(&priv->regs->zmr, CDNS_WDT_ZMR_ZKEY_VAL); + + count = (count << 2) & CDNS_WDT_CCR_CRV_MASK; + + /* Write counter access key first to be able write to register */ + data = count | CDNS_WDT_REGISTER_ACCESS_KEY; + cdns_wdt_writereg(&priv->regs->ccr, data); + + data = CDNS_WDT_ZMR_WDEN_MASK | CDNS_WDT_ZMR_RSTEN_MASK | + CDNS_WDT_ZMR_ZKEY_VAL; + + cdns_wdt_writereg(&priv->regs->zmr, data); + cdns_wdt_writereg(&priv->regs->restart, CDNS_WDT_RESTART_KEY); + + return 0; +} + +/** * cdns_wdt_probe - Probe call for the device. * * @dev: Handle to the udevice structure. @@ -247,7 +286,7 @@ static const struct wdt_ops cdns_wdt_ops = { .start = cdns_wdt_start, .reset = cdns_wdt_reset, .stop = cdns_wdt_stop, - /* There is no bit/reg/support in IP for expire_now functionality */ + .expire_now = cdns_wdt_expire_now, }; static const struct udevice_id cdns_wdt_ids[] = { |