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The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Acked-by: Priyanka Jain <priyanka.jain@nxp.com>
Acked-by: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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IFC and QSPI are muxed on board. Add fsl_fdt_fixup_flash() to disable
IFC node in dts if QSPI is enabled, or disable QSPI node in dts if
otherwise.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
[YS: Revise subject, remove commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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We shouldn't always change the status to okay. There could be
situations that the esdhc is intentionally disabled in the device
tree.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Revise subject and commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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This patch enables driver model for USB in defconfigs for LS1021A
platforms.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Function enable_layerscape_ns_access() is alreayd called soc-wide.
Remove duplicated calling from individual boards.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[YS: Add commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Function config_board_mux() reads env variable 'hwconfig' which is
only available after relocation for QSPI boot. Move calling
config_board_mux() to misc_init_r().
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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Smart voltage translator is removed from LS2080ARDB/LS2088ARDB
RevF boards. It is only used on LS2081ARDB. Programming GPIO
is only required for LS2081ARDB.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: Revise commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
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Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.
Signed-off-by: York Sun <york.sun@nxp.com>
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The environment has pretty much nothing to do with just "PPC", so
rename the macros to just __UBOOT_ENV_SECTION__ which is more
readable.
In addition, only a single macro is needed: the environment now goes
either to the default section (USE_HOSTCC is defined) or in the .text
section.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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CONFIG_SYS_USE_PPCENV is no longer used anywhere. It was used to put
the environment in the special .ppcenv section, but the last
architecture using this section (SuperH) has been changed to not use
it.
Therefore, this commit drops support for CONFIG_SYS_USE_PPCENV
entirely. We only handle two cases:
- We're building the host tool tools/envcrc, in which case the
environment is place with no special section attribute (so it
depends up in .data)
- We're building U-Boot itself, in which case the environnement is
placed in the .text section.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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This converts the following to Kconfig:
CONFIG_SYS_TEXT_BASE
The includes, whitelist, etc. were left for now but I don't get any
build errors or warnings on the omap3_logic_defconfig or
am3517_evm_defconfig builds I tried.
Signed-off-by: Adam Ford <aford173@gmail.com>
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fix the following compilation error reported by buidlman:
arm: + stm32f429-discovery
+arch/arm/mach-stm32/stm32f4/soc.c: In function 'arch_cpu_init':
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode
+ for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
+ ^
+arch/arm/mach-stm32/stm32f4/soc.c:30:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code
+make[3]: *** [arch/arm/mach-stm32/stm32f4/soc.o] Error 1
+make[2]: *** [arch/arm/mach-stm32/stm32f4] Error 2
+make[1]: *** [arch/arm/mach-stm32] Error 2
+make: *** [sub-make] Error 2
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas Manocha <vikas.manocha@st.com>
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Fix the UART input clock for the early debug UART, it should be
100MHz, instead of 88MHz.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Update the configuration files to support the device tree and driver
model. The peripheral clock and pins configuration are handled by
the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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To support driver model and device tree, use the SPI-flash-based
AT45xxx DataFlash driver, DataFlash is a kind of SPI flash.
Instead of ATMEL_DATAFLASH_SPI DataFlash older driver that will
be removed in the future.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add the dts files to support deivce tree, update the configuration
files to support the device tree and driver model. The peripheral
clock and pins configuration are handled by the clock and the pinctrl
drivers respectively.
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Strings read from devices may sometimes fail to be
NULL-terminated. The functions in lib/string.c are subject to
failure in this case. Protect against observed failures in
set_gpt_info() by switching to length-checking variants with a length
limit of the maximum possible partition table length. At the same
time, add a few checks for NULL string pointers.
Here is an example as observed in sandbox under GDB:
=> gpt verify host 0 $partitions
Program received signal SIGSEGV, Segmentation fault.
0x0000000000477747 in strlen (s=0x0) at lib/string.c:267
267 for (sc = s; *sc != '\0'; ++sc)
(gdb) bt
#0 0x0000000000477747 in strlen (s=0x0) at lib/string.c:267
#1 0x00000000004140b2 in set_gpt_info (str_part=<optimized out>,
str_disk_guid=str_disk_guid@entry=0x7fffffffdbe8, partitions=partitions@entry=0x7fffffffdbd8,
parts_count=parts_count@entry=0x7fffffffdbcf "", dev_desc=<optimized out>) at cmd/gpt.c:415
#2 0x00000000004145b9 in gpt_verify (str_part=<optimized out>, blk_dev_desc=0x7fffef09a9d0) at cmd/gpt.c:580
#3 do_gpt (cmdtp=<optimized out>, flag=<optimized out>, argc=<optimized out>, argv=0x7fffef09a8f0)
at cmd/gpt.c:783
#4 0x00000000004295b0 in cmd_call (argv=0x7fffef09a8f0, argc=0x5, flag=<optimized out>,
cmdtp=0x714e20 <_u_boot_list_2_cmd_2_gpt>) at common/command.c:500
#5 cmd_process (flag=<optimized out>, argc=0x5, argv=0x7fffef09a8f0,
repeatable=repeatable@entry=0x726c04 <flag_repeat>, ticks=ticks@entry=0x0) at common/command.c:539
Suggested-by: Lothar Waßmann <LW@karo-electronics.de>
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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This patch provides support in u-boot for renaming GPT
partitions. The renaming is accomplished via new 'gpt swap'
and 'gpt rename' commands.
The 'swap' mode returns an error if no matching partition names
are found, or if the number of partitions with one name does not equal
the number with the second name. The 'rename' variant always
succeeds as long as a partition with the provided number exists.
Rewriting the partition table has the side-effect that all partitions
end up with "msftdata" flag set. The reason is that partition type
PARTITION_BASIC_DATA_GUID is hard-coded in the gpt_fill_pte()
function. This does not appear to cause any harm.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Make the partition table available for modification by reading it from
the user-specified device into a linked list. Provide an accessor
function for command-line testing.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
[trini: Make this depend on CMD_GPT_RENAME, as it is the user of this
code]
Signed-off-by: Tom Rini <trini@konsulko.com>
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In order to read the GPT, modify the partition name strings, and then
write out a new GPT, the disk GUID is needed. While there is an
existing accessor for the partition UUIDs, there is none yet for the
disk GUID.
Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Move MAX_SEARCH_PARTITIONS to part.h so that functions in cmd
directory can find it. At the same time, increase the value to
64 since some operating systems use many, and the resources
consumed by a larger value are minimal.
Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Make minor changes to README.gpt and sandbox_defconfig to support
testing of the gpt command's functionality in the sandbox.
Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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The existing partitions-list parsing in cmd/gpt.c passes a value
from gpt_default() to set_gpt_info() that README.gpt suggests
should begin with 'partitions='. Partition-list strings should
in fact begin with 'uuid_disk', as otherwise the call from
set_gpt_info() to extract_val() to find 'uuid_disk' will fail.
Change README.gpt accordingly.
Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Changes since v6: none.
Signed-off-by: Alison Chaiken <alison@peloton-tech.com>
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Xilinx changes for v2017.09
Zynq:
- Add Z-Turn board support
fpga:
- Remove intermediate buffer from code
Zynqmp:
- dts cleanup
- change psu_init handling
- Add options to get silicon version
- Fix time handling
- Map OCM/TCM via MMU
- Add new clock driver
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With the changes to fdt_get_base_address() we need to modify the logic
in ft_verify_fdt() for how we check the validity of the CCSR address.
Tested-on: qemu-ppce500 -M mpc8544ds
Fixes: 336a44877af8 ("fdt: Correct fdt_get_base_address()")
Cc: York Sun <york.sun@nxp.com>
Cc: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
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The logic of what fdt_get_base_address() will search for and return has
changed. Rework get_phys_ccsrbar_addr_early() to perform the logic that
fdt_get_base_address used to perform.
Fixes: 336a44877af8 ("fdt: Correct fdt_get_base_address()")
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
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ahci_probe_scsi() now takes a 'base' argument, and there is an API
that prepares base address for us: ahci_probe_scsi_pci().
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
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This updates defconfig of R-Car Gen3 to keep with the latest Kconfig.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Add support for enabling and disabling the clock using the clock
framework based on the content of OF instead of doing it manually
in the board file.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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The order of parameters passed to the phy_connect() was wrong.
Moreover, only PHY address 0 was used. Replace this with code
capable of detecting the PHY address.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Add support for probing the RAVB Ethernet block from device tree.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Since we now have clock driver on the RCar Gen3 , obtain the clock
configuration using the clock framework functions. In case this
fails, fall back to the original code for pulling the clock config
directly out of OF.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Convert the SH Serial to Kconfig using tools/moveconfig.py tool
and a bit of manual adjustment to cater for failed conversions.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Since there is now a clock driver for RCar Gen3, enable it on this board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Since there is now a clock driver for RCar Gen3, enable it on this board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs .
This driver allows reading out the clock configuration set by
previous boot stages and enabling and disabling clock using
the MSTP registers. Setting clock is not supported thus far.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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