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2021-07-27doc: board: j721e_evm: Add documentation for firmware loadingKishon Vijay Abraham I1-0/+15
Add documentation for loading firmwares to be used by remote cores in the system including the environment variables that has to be set to load the firmwares. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-21-kishon@ti.com
2021-07-27doc: board: Move j721e document to doc/board/ti/ directoryKishon Vijay Abraham I3-277/+317
Move j721e document from board/ti/j721e/README to doc/board/ti/j721e_evm.rst after converting it to RST format. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-20-kishon@ti.com
2021-07-27configs: j7200_evm_a72: Add CONFIG_PREBOOT to configure ethernet PHYKishon Vijay Abraham I1-0/+1
Add CONFIG_PREBOOT to provide an automatic and easier way to configure ethernet PHY before loading the firmware. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-19-kishon@ti.com
2021-07-27env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVMKishon Vijay Abraham I1-0/+14
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 18. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-18-kishon@ti.com
2021-07-27configs: j7200_evm_a72_defconfig: Add config for torrent serdes and common ↵Aswath Govindraju1-0/+7
clock framework Add config for torrent serdes and common clock framework. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-17-kishon@ti.com
2021-07-27configs: j721e_evm_a72_defconfig: Enable the drivers required for the USB3 ↵Jean-Jacques Hiblot1-0/+6
support Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra phy driver. All of them are required for USB3 support Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-16-kishon@ti.com
2021-07-27arm: dts: k3-j7200-common-proc-board-u-boot: Add u-boot tags for torrent serdesAswath Govindraju1-0/+12
Add u-boot tags for torrent serdes. This has properties specific to u-boot on top of DT in v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com
2021-07-27arm: dts: k3-j7200-common-proc-board: Enable SERDES DTAswath Govindraju1-0/+23
Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com
2021-07-27arm: dts: k3-j7200-main: Add DT node for torrent serdesAswath Govindraju1-0/+63
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com
2021-07-27ARM: dts: k3-j721e: Add support for USB3 in USB0 instanceKishon Vijay Abraham I1-1/+18
Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com
2021-07-27board: ti: j721e: Add support for probing and configuring Torrent serdes on ↵Aswath Govindraju1-1/+33
J7200 Add support for probing and configuring Torrent serdes on J7200. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-11-kishon@ti.com
2021-07-27phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoCJean-Jacques Hiblot5-0/+1168
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com
2021-07-27phy: cadence: Add driver for Torrent SERDESAswath Govindraju3-0/+2470
Add driver for Torrent SERDES. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com
2021-07-27phy: cadence: Add driver for Sierra PHYAlan Douglas5-0/+760
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com
2021-07-27dt-bindings: ti-serdes-mux: Add defines for AM64 SoCKishon Vijay Abraham I1-0/+5
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-7-kishon@ti.com
2021-07-27dt-bindings: phy: cadence-torrent: Add defines for refclk driverKishon Vijay Abraham I1-0/+20
Add defines for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-6-kishon@ti.com
2021-07-27dt-bindings: phy: Add defines for AM64 SERDES WrapperKishon Vijay Abraham I1-0/+21
Add defines for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-5-kishon@ti.com
2021-07-27dt-bindings: phy: Add definitions for additional phy typesAswath Govindraju1-0/+1
Add definitions for additional phy types that's used specifically for Torrent SERDES. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-4-kishon@ti.com
2021-07-27dm: test: Add test case to check node name ignoring unit addressKishon Vijay Abraham I1-0/+14
Add test to check node name ignoring unit address. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20210721155849.20994-3-kishon@ti.com
2021-07-27dm: core: Add helper to compare node namesKishon Vijay Abraham I2-0/+23
Add helper to compare node names. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20210721155849.20994-2-kishon@ti.com
2021-07-27configs: am335x_evm: Support GbE PHYsPaul Barker1-0/+1
The SanCloud BeagleBone Enhanced (BBE) includes a Gigabit Ethernet PHY. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27arm: dts: Import am335x-sancloud-bbe devicetreePaul Barker4-1/+141
This device tree is imported from Linux 5.13.1 and enabled via the am335x board file and the am335x evm defconfig. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27arm: dts: Resync BeagleBone device treesPaul Barker6-215/+453
These device trees are updated to match the versions in Linux 5.13.1. The tick-timer entry in am335x-bone-common.dtsi is preserved. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27dt-bindings: Resync omap & am33xx pinctrl bindingsPaul Barker2-7/+135
These headers are updated to match the versions in Linux 5.13.1. Signed-off-by: Paul Barker <paul.barker@sancloud.com>
2021-07-27configs: j7200_evm_*_defconfig: Enable configs for HS400 supportAswath Govindraju2-3/+3
Enable configs to add support for HS400 speed mode. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210525093826.10390-4-a-govindraju@ti.com
2021-07-27arm: dts: k3-j7200-main: Add support for HS400 and update delay select ↵Aswath Govindraju1-1/+10
values for MMCSD subsystems HS400 speed mode is now supported in J7200 SoC[1]. Therefore add mmc-hs400-1_8v tag in sdhci0 device tree node. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf, (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210525093826.10390-3-a-govindraju@ti.com
2021-07-27mmc: sdhci_am654: Read ti, strobe-sel property from device treeAswath Govindraju1-0/+1
Read the strobe select value from the device tree property ti,strobe-sel, required for HS400 speed mode Fixes: a20008eabd95 ("mmc: am654_sdhci: Add Support for configuring PHY in J721e") Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210525093826.10390-2-a-govindraju@ti.com
2021-07-27mmc: sdhci: Write to HOST_CONTROL2 register for HS400 speed modeFaiz Abbas1-0/+3
Enable HS400 speed mode by writing to HOST_CONTROL2 register. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210405144428.12159-1-a-govindraju@ti.com
2021-07-27Prepare v2021.10-rc1Tom Rini1-2/+2
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-07-26Merge tag 'xilinx-for-v2021.10-rc1' of ↵Tom Rini31-151/+950
https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.10-rc1 xilinx: - Use default ENVL_NOWHERE configuration - Add support for handling compressed kernels zynqmp: - SPL malloc size extension - USB2.0 for zc1751 dc2 - Fix USB3.0 nodes - Handle lpd_lsbus clock - Cleanup macros around SYSRESET versal: - Remove PBSIZE macro zynq_sdhci: - Tap delay fixups net: - Add support for MRMAC
2021-07-26arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB nodeManish Narani13-30/+30
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26xilinx: Define kernel_comp_addr_r,kernel_comp_size env variablesRaju Kumar Pothuraju2-0/+4
Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo) using booti command. Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26arm64: versal: Drop default definitions of CONFIG_SYS_PBSIZEMichal Simek1-2/+0
It is default value which had been converted by commit 432e39806805 ("include/configs: drop default definitions of CONFIG_SYS_PBSIZE"). That's why also remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26arm64: zynqmp: Enable reset and poweroff via sysreset frameworkMichal Simek1-0/+3
reset and poweroff are called via hooks in psci driver which is going around sysreset framework that's why enable sysreset drivers and do reset and poweroff via this framework. Using this flow will allow us to call SYSTEM_WARM_RESET based on psci 1.1 spec which can be calles with reset -w command. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26arm64: zynqmp: Do not define do_reset() if sysreset is enabledMichal Simek1-0/+2
The SPL can also be compiled with sysreset drivers just fine, so update the condition to cater for that option. The same change was done by commit efa1a62ad2dd ("ARM: imx8m: Do not define do_reset() if sysreset is enabled"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26psci: Do not define do_poweroff() if CONFIG_SYSRESET_CMD_POWEROFF is enabledMichal Simek1-1/+1
CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on CONFIG_CMD_POWEROFF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26xilinx: versal: Enable Xilinx AXI MRMACAshok Reddy Soma1-0/+1
Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26net: xilinx: axi_mrmac: Add MRMAC driverAshok Reddy Soma5-0/+778
Add support for xilinx multirate(MRMAC) ethernet driver. This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. Added support for 4 ports of MRMAC for speeds 10G and 25G. MCDMA supports upto 16 channels but in this driver we have setup only one channel which is enough. Tested 10G and 25G on all 4 ports. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26net: ethtool: Add ethernet speed macros for higher speedsAshok Reddy Soma1-0/+8
Add speed macro's for higher ethernet speeds to be used in u-boot networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G, 56G, 100G and 200G inline with linux. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26clk: zynqmp: Add support for enabling clock on lpd_lsbusMichal Simek1-0/+1
lpd_lsbus is clock which is used by many IPs like dmas, gems, gpio, sdhcis, spis, ttcs, uarts, watchdog that's why make sense to also enable access to change this clock. For this clock you already get the rate. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26arm64: dts: zynqmp: Enable USB2.0 for zc1751-xm016-dc2Piyush Mehta1-2/+0
The board zynqmp-zc1751-xm016-dc2 support only USB2.0. This patch removes USB3.0 DT configuration for DC2 board. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26xilinx: Return ENVL_NOWHERE instead of ENVL_UNKNOWNMike Looijmans2-6/+6
The system refuses to boot without any environment, so return ENVL_NOWHERE when there's nowhere to store the environment instead of ENVL_UNKNOWN. This fixes that the board won't boot from eMMC when CONFIG_ENV_IS_IN_FAT is not defined, for example. Similar for other combinations. Fixes: 1025bd098aa8 "xilinx: zynqmp: Add support for saving variables" Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26mmc: zynq_sdhci: Make variables/structure staticMichal Simek1-6/+10
All these variables/structure are local and should be static. Issues are reported by sparse: drivers/mmc/zynq_sdhci.c:49:11: warning: symbol 'zynqmp_iclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:50:11: warning: symbol 'zynqmp_oclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:53:11: warning: symbol 'versal_iclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:54:11: warning: symbol 'versal_oclk_phases' was not declared. Should it be static? drivers/mmc/zynq_sdhci.c:546:24: warning: symbol 'arasan_ops' was not declared. Should it be static? Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-26mmc: zynq_sdhci: Fix kernel doc warningsMichal Simek1-12/+12
Fix these kernel doc warnings: drivers/mmc/zynq_sdhci.c:181: warning: contents before sections drivers/mmc/zynq_sdhci.c:236: warning: contents before sections drivers/mmc/zynq_sdhci.c:291: warning: contents before sections drivers/mmc/zynq_sdhci.c:297: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sdcardclk_set_phase' drivers/mmc/zynq_sdhci.c:354: warning: contents before sections drivers/mmc/zynq_sdhci.c:360: warning: Function parameter or member 'degrees' not described in 'sdhci_versal_sampleclk_set_phase' drivers/mmc/zynq_sdhci.c:467: warning: contents before sections Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-26mmc: zynq_sdhci: Split set_tapdelay function to in and outAshok Reddy Soma3-40/+50
Split arasan_zynqmp_set_tapdelay() to handle input and output tapdelays separately. This is required to handle zero values for ITAP and OTAP values. If we dont split, we will have to remove the if() in the function, which makes ITAP values to be overwritten when OTAP values are called to set and vice-versa. Restrict tap_delay value calculated to max allowed 8 bits for ITAP and 6 bits for OTAP for ZynqMP. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26mmc: zynq_sdhci: Use Mask writes for Tap delaysAshok Reddy Soma1-27/+31
Restrict tap_delay value to the allowed size(8bits for itap and 6 bits for otap) before writing to the tap delay register. Clear ITAP and OTAP delay bits before updating with the new tap value for Versal platform. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26mmc: zynq_sdhci: Allow configuring zero Tap valuesAshok Reddy Soma1-12/+4
Allow configuring ITAP and OTAP values with zero to avoid failures in some cases (one of them is SD boot mode). Legacy, SDR12 modes require to program the ITAP and OTAP values as zero, whereas for SDR50 and SDR104 modes ITAP value is zero. In SD boot mode firmware configures the SD ITAP and OTAP values and in this case u-boot has to re-configure required tap values(including zero) based on the operating mode. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26mmc: zynq_sdhci: Resolve uninitialized return valueAshok Reddy Soma1-12/+8
set_phase() functions are not modifying the ret value and returning the same uninitialized ret, return 0 instead. Keep the return type as int to return errors when the tapdelay's are set via xilinx_pm_request() in future. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26xilinx: zynqmp: increase CONFIG_SYS_SPL_MALLOC_SIZE to 16MBRicardo Salveti1-1/+1
commit 03f1f78a9b44 ("spl: fit: Prefer a malloc()'d buffer for loading images")' changed the way buffer allocation worked for SPL to a more flexible method. For xilinx zynqmp the 1MB buffer is not necessarily enough when dealing with complex fit images (e.g. containing FPGA/TF-A/OP-TEE/U-Boot proper), which can easily reach up to 10MB, so increase the default CONFIG_SYS_SPL_MALLOC_SIZE size to 16MB to cover more advanced scenarios. Signed-off-by: Ricardo Salveti <ricardo@foundries.io> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-24Merge tag 'efi-2021-10-rc1-3' of ↵Tom Rini16-50/+1798
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc1-3 Documentation: provide Makefile documentation SMBIOS: generate BIOS release date based on UEFI version improve error handling in SMBIOS table generation UEFI: correct handling of signed capsule if authentication if off
generated by cgit v1.2.3 (git 2.39.0) at 2024-09-17 22:53:31 +0300