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CR_3238 exclude opensbi memory range in device tree
See merge request sdk/u-boot!27
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CR_1432 riscv: add missing SBI extension definitions
See merge request sdk/u-boot!26
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This patch explicitly excludes the memory range of the OpenSBI in the
built-in device tree. When booting EFI, the efi loader has to know
about that zone before loading the device tree for Linux, otherwise
it tries to access 0x40000000, leading to an access violation.
Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com>
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Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
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Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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CR 3068 configs: starfive-jh7110: update the value of CONFIG_SYS_MALLOC_F_LEN
See merge request sdk/u-boot!25
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CR_3067 dts: add boot-hart-id property in dts
See merge request sdk/u-boot!24
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Update the value of CONFIG_SYS_MALLOC_F_LEN from 0x8000 to 0x10000.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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boot-hart-id is used by opensbi.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
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CR_3049 dts: add i2c5 and attach pmic configuration
See merge request sdk/u-boot!22
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CR_3006 misc: OTP: Starfive-jh7110: update the return value of starfive_otp_read
See merge request sdk/u-boot!21
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CR 2708 clk:starfive: Add vout clock driver for StarFive JH7110
See merge request sdk/u-boot!23
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CR_2828 dts: pmu : add riscv pmu dts config
See merge request sdk/u-boot!20
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Add vout clock driver for StarFive JH7110
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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i2c5 and pmic is used by opensbi power management
ops.
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
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add 7110 performance monitor for perf use
Signed-off-by: minda.chen <minda.chen@starfivetech.com>
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Update the return value to match the function prototype definition.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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CR_2876: board:starfive:evb: Set the CPU default frequency to 1.0GHz
See merge request sdk/u-boot!19
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Set to 1000M to ensure the CPU can work normally under 0.8V`
voltage
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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The frequency of pll0 is set to 1000Mhz in the bootrom
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR_2709 dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions
See merge request sdk/u-boot!18
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Remove usb/sdio0/sdio1 gpio init.
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Add pinctrl config about usb/sdio0
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Enable STARFIVE_PINCTRL and PINCTRL_FULL
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Add pinctrl driver for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Add pinctrl definitions for StarFive JH7110 SoC.
Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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CR_2555: borad:jh7110:evb: Modify ramdisk_addr_r/pxefile_addr_r/scriptaddr
See merge request sdk/u-boot!17
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The jh7110 ddr starts from 0x40000000. Using 0x80000000 may cause the
CMA space to fail
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR_2522: support gamc with jh7110B-evb
See merge request sdk/u-boot!16
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Switch the QSPI parent clock to pll0 to improve the QSPI speed
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B requires a higher IOPAD capability in 1000M mode.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B need tx_inverted by YT8521 phy, you need to read the chip
version to determine whether to use it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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Read the chip model from the rgpio3 and setenv "chip_vision"
1: jh7110B
0: JH7110A
defalut: JH7110A
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B needs switch gmac0/1 tx to rgmii phy.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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JH7110B requires tx_inverted_10/100/1000 configuration, and different
parameters
may be required in 10M/100M/1000M mode.
This parameter supports JH7110B+YT8531PHY by default. Other boards can
modify the parameters of the tx_inverted_10/100/1000 to obtain support.
If you do not configure tx_inverted_10/100/1000 in dts, the default is
0.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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support use original or inverted RGMII_TX_CLK delay train.
10M/100M/1000M can be configured independently.
tx_inverted_xx = val;
For example:
&gmac0 {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
tx_inverted_10 = <0>;
tx_inverted_100 = <1>;
tx_inverted_1000 = <1>;
};
};
0: original (default)
1: inverted
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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This patch include four items:
1.rename the driver compatible name.
2.reset action with the common API.
3.clean up code to make it is closer to readable.
4.add configuration to support 8G size
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
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Add reset property configuration to DDR control device tree node.
Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
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Replace the configuration operation for pll1 clk with common api provide
by pll module.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Switch the pll2 clk to 1188M with the comm pll interface on JH7110.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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Add common interface to set and get pll clk information for jh7110 soc.
Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
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ARP_TIMEOUT is too large, then will waite a long time for the first time
Set ARP_TIMEOUT to 500 refer to others
Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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The previous definition of apb_bus clock relationship is incorrect,so
update it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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Add saveenv config to Support saveenv
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
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Signed-off-by: samin <samin.guo@starfivetech.com>
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Configure SD card boot parameters
Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
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Change Model to "StarFive JH7110 EVB", and change riscv,isa to
"rv64imafdcbsux"
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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The ddr driver include two configs with 2G and 4G.Fist read the ddr size
config from the memory node in the dts,then match the right config and
do it.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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In the hardware design, the IPs RESET signal of jh7110 is divided into
two groups,one group is active high, and the other group is active low.
However, the software does not need to distinguish whether the RESET
signal is active high or active low,Write 1 to be assert, and write 0 to deassert.
Therefore, the software does not need to add additional logic to
distinguish these two sets of signals.
Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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