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2022-10-18config:starfive-jh7110: update starfive evb board default configyanhong.wang1-0/+8
Add DDR config to the default config for starfive evb board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: add ddr device nodeyanhong.wang1-0/+7
Add ddr device node for JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add clk inityanhong.wang3-30/+58
Add clk init for ddr on JH7110 board Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: add ddr driveryanhong.wang10-0/+3203
Add driver for JH7110 to support ddr initialization in SPL. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com> Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: update clk inityanhong.wang1-96/+23
Modify the clk init code for StarFive JH7110 platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Update pll0/pll1/pll2 clkyanhong.wang3-6/+29
Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define from clk-jh7110.c to jh7110_clk.dts Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add delay chainyanhong.wang1-12/+26
Add tx/rx delay chain for YUTAI 8521 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add macro definitionyanhong.wang1-0/+21
Add macro definition of GPIO Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive evb board supportyanhong.wang12-0/+734
Add board support for StarFive EVB. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Adjust the dependency of CLK_JH7110 & SPL_CLK_JH7110 macrosyanhong.wang1-2/+2
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive-jh7110: Adjust the dependency of RESET_JH7110 macroyanhong.wang1-1/+1
Adjust the dependency from TARGET_STARFIVE_VISIONFIVE to STARFIVE_JH7110. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang3-157/+496
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: remove unused clkyanhong.wang1-52/+4
Remove unused clock in order to reduce code size. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy inityanhong.wang1-0/+3
Add phy init for YUTAI YT8511/YT8521. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy:YUTAI: Add YT8511/yt8521 phy driveryanhong.wang4-0/+293
This adds basic support for YUTAI YT8511/YT8521 phy. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18usb:cdns3:Add StarFive wrapper driver for CDNS USB3 controlleryanhong.wang3-0/+88
Add driver to handle StarFive specific wrapper for Cadence USB3 controller present on JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: update clk&reset propertiesyanhong.wang2-53/+182
Synchronize the kernel dts file Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive: Adjust judgment conditionsyanhong.wang1-4/+5
The serial driver will call reset driver, udelay function will be called in reset driver, but the timer is not init,so udelay function call will cases error. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add rtc timer inityanhong.wang2-1/+53
The rtc timer is used early in kernel, but the clk&reset driver is not ready,so some clk&reset init is placed here. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18script: add execute permissionyanhong.wang0-0/+0
Add executable permissions for script files. /*do not upstream*/ Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18config:starfive-jh7110: add config file for jh7110yanhong.wang1-0/+75
Add basic config option for StarFive VisionFive board. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net:phy: add 10/100M register configurationyanhong.wang2-0/+14
Support 10/100M configuration. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive: add starfive visionfive board supportyanhong.wang8-0/+518
Add board support for StarFive VisionFive. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18net: dwc_eth_qos:starfive: add jh7110 supportyanhong.wang2-0/+290
Add new configuration for jh7110 soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:dts: add jh7110 supportyanhong.wang6-0/+1341
Add dts support for jh7110. The starfive visionfive support is based on jh7110 soc. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18mtd:spi-nor-ids: Add support for GD25LQ256Dyanhong.wang2-0/+6
Adds support for GigaDevice's spi nor flash Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18riscv:soc:jh7110: Add support jh7110 soc.yanhong.wang7-0/+180
Add StarFive JH7110 soc to support RISC-V arch Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:starfive-jh7110: Add clock driver for JH7110yanhong.wang7-0/+1167
Add a clock driver for StarFive JH7110 Soc platform. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18misc:OTP:Starfive-jh7110: Add driver for the Starfive otp controlleryanhong.wang3-0/+196
Added a misc driver to handle OTP memory in Starfive SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18GPIO:Starfive-jh7110: Add GPIO driver for JH7110yanhong.wang4-0/+224
Support for GPIO controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18Reset:Starfive-jh7110: Add reset driver for JH7110yanhong.wang4-0/+472
Support for reset controller on starfive JH7110 SoCs. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2021-10-04Prepare v2021.10Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-04mtd: cqspi: Fix division by zeroMarek Vasut1-0/+3
Both dummy.nbytes and dummy.buswidth may be zero. By not checking the later, it is possible to trigger division by zero and a crash. This does happen with tiny SPI NOR framework in SPL. Fix this by adding the check and returning zero dummy bytes in such a case. Fixes: 38b0852b0ea ("spi: cadence-qspi: Add support for octal DTR flashes") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Pratyush Yadav <p.yadav@ti.com> [trini: Drop Pratyush's RB as his requested changes weren't made as Marek disagreed]
2021-09-30Azure/GitLab CI: Update docker imageTom Rini2-2/+2
Rebuild our current docker image so that ca-certificates will be updated and Let's Encrypt issued certificates will work again. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-29Merge tag 'rpi-next-2021.10.2' of ↵Tom Rini2-0/+7
https://source.denx.de/u-boot/custodians/u-boot-raspberrypi - fix usb stopt; usb start; bug - update Nicolas email address
2021-09-29Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini1-2/+2
- Armada8k: Fix CP0 eMMC/SDIO support (Robert)
2021-09-29arm: rpi: perform XHCI firmware upload only onceMarek Szyprowski1-0/+6
XHCI firmware upload must be performed only once after initializing the PCI bridge. This fixes USB stack initialization after calling "usb stop; usb start" on Raspberry Pi 4B. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29mailmap: Update mail address for Nicolas Saenz julienneNicolas Saenz Julienne1-0/+1
The @suse.de address doesn't exist anymore. Update it to something not dependent on my workplace. Signed-off-by: Nicolas Saenz Julienne <nsaenz@kernel.org> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29arm: dts: armada8040: Fix CP0 eMMC/SDIO supportRobert Marko1-2/+2
During the migration to a single DTSI for the CP110-s specific pinctrl compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics. Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor. So, the mvebu-pinctrl driver check specifically for the "marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit. Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl" for CP0 and "marvell,8k-cps-pinctrl" for the CP1. This is obviously incorrect as the pinctrl driver does not know about these. So fix the regression by applying correct compatibles to the DTSI. Regression found and tested on the Puzzle M801 board. Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-28Merge branch '2021-09-28-regression-fixes'Tom Rini13-32/+52
- Reintroduce creating internally the "nor%d" style names, in order to fix some use U-Boot use-cases involving the "mtd" command. - Fix a regression over the default SPI bus mode shown by having the compiled default actually start being used. The correct default here is 0. - Fix ethernet on imx7d-sdb - Fix a regression with MTD NAND devices when OF_LIVE is enabled
2021-09-28imx: imx7d-sdb: fix ethernet, sync .dts with linuxRasmus Villemoes1-3/+3
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0 (aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync device tree with v5.5-rc1", but in the linux tree, these gpios have always been GPIO_ACTIVE_HIGH ever since this node was introduced around v4.13 (linux commit 184f39b5). I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work around the behaviour of the soft-spi driver back then, which effectively defaulted to spi-mode 3 and not 0. That was arguably a bug in the soft-spi driver, which then got fixed in 0e146993bb3 (spi: add support for all spi modes with soft spi), but that commit then broke ethernet on this board. Fix it by setting the gpios as active high, which as a bonus actually brings us in sync with the .dts in the linux source tree. Without this, one gets Net: Could not get PHY for FEC0: addr 0 No ethernet found. With this, ethernet (at least ping and tftp) works as expected from the U-Boot shell. Cc: Fabio Estevam <festevam@gmail.com> Cc: Joris Offouga <offougajoris@gmail.com> Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net> Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-09-28mtd: nand: raw: convert nand_dt_init() to ofnode_xx() interfacePatrice Chotard6-23/+18
nand_dt_init() is still using fdtdec_xx() interface. If OF_LIVE flag is enabled, dt property can't be get anymore. Updating all fdtdec_xx() interface to ofnode_xx() to solve this issue. For doing this, node parameter type must be ofnode. First idea was to convert "node" parameter to ofnode type inside nand_dt_init() using offset_to_ofnode(node). But offset_to_ofnode() is not bijective, in case OF_LIVE flag is enabled, it performs an assert(). So, this leads to update nand_chip struct flash_node field from int to ofnode and to update all nand_dt_init() callers. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-28mtd: spi: Set CONFIG_SF_DEFAULT_MODE default to 0Marek Vasut1-1/+1
Before e2e95e5e254 ("spi: Update speed/mode on change") most systems silently defaulted to SF bus mode 0. Now the mode is always updated, which causes breakage. It seems most SF which are used as boot media operate in bus mode 0, so switch that as the default. This should fix booting at least on Altera SoCFPGA, ST STM32, Xilinx ZynqMP, NXP iMX and Rockchip SoCs, which recently ran into trouble with mode 3. Marvell Kirkwood and Xilinx microblaze need to be checked as those might need mode 3. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Cc: Andreas Biessmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Tom Rini <trini@konsulko.com> Cc: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com> Cc: Vignesh Raghavendra <vigneshr@ti.com>
2021-09-28mtd: spi: nor: force mtd name to "nor%d"Patrick Delaunay4-4/+23
Force the mtd name of spi-nor to "nor" + the driver sequence number: "nor0", "nor1"... beginning after the existing nor devices. This patch is coherent with existing "nand" and "spi-nand" mtd device names. When CFI MTD NOR device are supported, the spi-nor index is chosen after the last CFI device defined by CONFIG_SYS_MAX_FLASH_BANKS. When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, this config is replaced by to cfi_flash_num_flash_banks in the include file mtd/cfi_flash.h. This generic name "nor%d" can be use to identify the mtd spi-nor device without knowing the real device name or the DT path of the device, used with API get_mtd_device_nm() and is used in mtdparts command. This patch also avoids issue when the same NOR device is present 2 times, for example on STM32MP15F-EV1: STM32MP> mtd list SF: Detected mx66l51235l with page size 256 Bytes, erase size 64 KiB, \ total 64 MiB List of MTD devices: * nand0 - type: NAND flash - block size: 0x40000 bytes - min I/O: 0x1000 bytes - OOB size: 224 bytes - OOB available: 118 bytes - ECC strength: 8 bits - ECC step size: 512 bytes - bitflip threshold: 6 bits - 0x000000000000-0x000040000000 : "nand0" * mx66l51235l - device: mx66l51235l@0 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@0 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" * mx66l51235l - device: mx66l51235l@1 - parent: spi@58003000 - driver: jedec_spi_nor - path: /soc/spi@58003000/mx66l51235l@1 - type: NOR flash - block size: 0x10000 bytes - min I/O: 0x1 bytes - 0x000000000000-0x000004000000 : "mx66l51235l" The same mtd name "mx66l51235l" identify the 2 instances mx66l51235l@0 and mx66l51235l@1. This patch fixes a ST32CubeProgrammer / stm32prog command issue with nor0 target on STM32MP157C-EV1 board introduced by commit b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled"). Fixes: b7f060565e31 ("mtd: spi-nor: allow registering multiple MTDs when DM is enabled") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> [trini: Add <dm/device.h> to <mtd.h> for DM_MAX_SEQ_STR] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-28mtd: cfi_flash: use cfi_flash_num_flash_banks only when supportedPatrick Delaunay1-1/+7
When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is activated, CONFIG_SYS_MAX_FLASH_BANKS is replaced by cfi_flash_num_flash_banks, but this variable is defined in drivers/mtd/cfi_flash.c, which is compiled only when CONFIG_FLASH_CFI_DRIVER is activated, in U-Boot or in SPL when CONFIG_SPL_MTD_SUPPORT is activated. This patch deactivates this feature CONFIG_SYS_MAX_FLASH_BANKS_DETECT when flash cfi driver is not activated to avoid compilation issue in the next patch, when CONFIG_SYS_MAX_FLASH_BANKS is used in spi_nor_scan(). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-09-27Prepare v2021.10-rc5Tom Rini1-1/+1
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27Merge https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini2-1/+9
- turris_omnia: fix leaked mtd device (Marek) - phy: marvell: cp110: Fix SATA invert polarity (Denis)
2021-09-27phy: marvell: cp110: Support SATA invert polarityDenis Odintsov1-1/+6
In commit b24bb99d cp110 configuration initially done in u-boot was removed and delegated to atf firmware as smc call. That commit didn't account for later introduced in d13b740c SATA invert polarity support. This patch adds support of passing SATA invert polarity flags to atf firmware during the smc call. Signed-off-by: Denis Odintsov <shiva@mail.ru> Cc: Baruch Siach <baruch@tkos.co.il> Cc: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-27arm: mvebu: turris_omnia: fix leaked mtd deviceMarek Behún1-0/+3
After getting MTD device via get_mtd_device_nm(), we need to put it with put_mtd_device(), otherwise we get Removing MTD device #0 (mx25l6405d) with use count 1 before booting kernel. Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Pali Rohár <pali@kernel.org> Tested-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-26Merge tag 'efi-2021-10-rc5' of ↵Tom Rini4-23/+35
https://source.denx.de/u-boot/custodians/u-boot-efi Pull request for efi-2021-10-rc5 Documentation: * add /config bindings to HTML documentation UEFI * Fix number_of_algorithms field in TCG EFI Protocol
generated by cgit v1.2.3 (git 2.39.0) at 2024-07-20 16:20:58 +0300