Age | Commit message (Collapse) | Author | Files | Lines |
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set SPL_OPENSBI_LOAD_ADDR to 0x40000000
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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add 1G DDR tuning cfg
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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When eeprom reads, you need to determine whether eeprom supports it.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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In order to read DDR info from eeprom.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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sync from vf2 and add resize DDR info from EEPROM
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR 6164 riscv: config: starfive: jh7110: mem size
See merge request sdk/u-boot!56
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reduce the mem size from 800+M to 128M
Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
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CR_5469 board: starfive: jh7110: Add support for 1.25GHz chips
See merge request sdk/u-boot!55
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Remove max cpu voltages: 1.12v, 1.10v, 1.08v.
Set the cpu max frequency to 1.25G per OTP value.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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CR_3508: riscv: dts: starfive: add zicsr_zifencei to riscv,isa string
See merge request sdk/u-boot!54
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Starting from gcc 12.x, csr and fence instructions have been
separated from the base I instruction set. special the
zicsr_zifencei string to DT riscv,isa string
Signed-off-by: Andy Hu <andy.hu@starfivetech.com>
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CR5042: net: phy: motorcomm: add Pad Drive Strength Cfg
See merge request sdk/u-boot!52
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CR_4854: uboot: evb support boot from nvme ssd
See merge request sdk/u-boot!53
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support boot from nvme ssd
Signed-off-by: shanlong.li <shanlong.li@starfivetech.com>
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CR 5041 board: starfive: copyright: Standardize the copyright format
See merge request sdk/u-boot!51
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Unify the content format of the copyright section
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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YT8531 supports Pad Drive Strength configuration.
Including rx_data/rx_clk, etc.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR_4747 dts: pmu: remove pmu dts stall cycles config.
See merge request sdk/u-boot!50
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CR 4427 configs: starfive: Enable CONFIG_OF_SEPARATE configuration
See merge request sdk/u-boot!47
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class 8 and class9 cpu stall cycles hwcounter is
not supported in U74. delete the configuration.
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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CR4563:Configure the l2 prefetcher parameter
See merge request sdk/u-boot!48
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CR_3910 Modify cpu voltage set commands
See merge request sdk/u-boot!49
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Update the cpu voltage set commands per
binning information from OTP.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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Add L2 pretcher configuration for starfive jh7110 SoC.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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The default configuration of the SIFIVE L2 Prefetcher may not be the
best combination on the JH7110, and some parameters need to be modified
to achieve the best performance.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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It should be configured in L2.
Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
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CR 4446 pinctrl hal.feng
See merge request sdk/u-boot!46
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Modify the mode of the DTB for DT Control from Embedded to separated.
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
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Add gpio-controller for node gpio and gpioa.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Support getting direction of gpio.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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starfive_pinctrl_priv struct is a priv of the parent
device (pinctrl device), not the gpio device.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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display: resize the bmp logo
See merge request sdk/u-boot!45
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reduce the bmp size as the uboot partttion is 4M
Signed-off-by: keith <keith.zhao@starfivetech.com>
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CR_4094 display: update uboot logo display function:
See merge request sdk/u-boot!42
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CR_3499_vout_console_515_changhuang.liang configs: starfive_visionfive_defconfig: Enable console to tty1
See merge request sdk/u-boot!44
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Enable console to tty1.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
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CR_4082: riscv: Fix build against binutils 2.38
See merge request sdk/u-boot!43
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CR_3910 board: starfive: jh7110: Add 1.1 & 1.02v max cpu voltage
See merge request sdk/u-boot!40
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The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a
compiled for double-float. To link to it we have to adjust how we build
U-Boot.
As U-Boot actually does not use floating point at all this should not
make a significant difference for the produced binaries.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
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The following description is copied from the equivalent patch for the
Linux Kernel proposed by Aurelien Jarno:
>From version 2.38, binutils default to ISA spec version 20191213. This
means that the csr read/write (csrr*/csrw*) instructions and fence.i
instruction has separated from the `I` extension, become two standalone
extensions: Zicsr and Zifencei. As the kernel uses those instruction,
this causes the following build failure:
arch/riscv/cpu/mtrap.S: Assembler messages:
arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
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CR_3347: riscv: dts: enable hdmi dts config in uboot
See merge request sdk/u-boot!39
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Add two more binning IC types, and set add their
max cpu voltage accordingly.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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hdmi can show a bitmap logo while uboot start
and the default resolution is 1920x1080@60fps
Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
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hdmi can show a bitmap logo while uboot start
and the default resolution is 1920x1080@60fps
Signed-off-by: keith.zhao<keith.zhao@statfivetech.com>
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CR_3696: Add cpu voltage set commands
See merge request sdk/u-boot!37
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Get the binning information from OTP,
and set change the cpu max voltage accordingly.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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CR_3504: Enable sbi command in U-Boot
See merge request sdk/u-boot!36
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CR_3455 pci: Add Starfive JH7110 pcie driver
See merge request sdk/u-boot!33
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As the i2c_designware_pci.c uses ACPI APIs,
add the ACPI table generation configuration
for its compilation.
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
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