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2022-11-03board: starfive: move eeprom macro definitionYanhong Wang2-51/+43
Move eeprom macro definition form h file to c. Signed-off-by: Yanhong Wang <yanhong.wang@linux.starfivetech.com>
2022-11-03i2c: designware: support SYS_I2C_DW in SPLYanhong Wang2-1/+8
Add SYS_I2C_DW driver to support in SPL. Signed-off-by: Yanhong Wang <yanhong.wang@linux.starfivetech.com>
2022-11-03board: starfive: Add interface to get data from eepromJianlong Huang2-0/+31
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03spl: starfive: jh7110: switch pll2 to 1188MJianlong Huang3-165/+29
Switch the pll2 clk to 1188M with the comm pll interface on JH7110. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03board: starfive: Support auto to init gmac base on eeprom dataJianlong Huang4-3/+102
PCB A have two different phy, 1000M yt8531 for gmac0, 100M yt8512 for gmac1. PCB B have two same phy, 1000M yt8531 for gmac0/gmac1. Gmac initialization is different when link different phy. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03Support boot from grubJianlong Huang2-13/+36
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03Support scan to boot from sd card or emmcJianlong Huang4-1/+62
Get bootmode, if bootmode is flash, then default boot from sd card. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03config: jh7110: read uboot by partitionsamin1-2/+2
uboot should be placed in partition-2 Signed-off-by: samin <samin.guo@starfivetech.com>
2022-11-03board: starfive: update gpio index base on visionfive2 A1.1Jianlong Huang2-26/+26
update sdio emmc uart0 gpio index base on visionfive2 new board A1.1 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03configs: starfive_visionfive2_defconfig: Support saveenvJianlong Huang2-3/+5
Add saveenv config to Support saveenv Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03add ID_EEPROM supoort for VisionFive2Jianlong Huang7-4/+815
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03 Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDRJianlong Huang3-28/+44
based on current usage. Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to Kconfig. Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03cmd/eeprom: fix data type issue for parse_numeric_paramJianlong.Huang1-2/+2
This patch fixs parse_numeric_param issue on some platfrom which has different sizes of int and long, like riscv64. On riscv64, int is 4 bytes, but long is 8 bytes. on this situation: ulong addr = parse_numeric_param(argv[index]); if argv[index] is "0x80000000", this "ulong addr" will be 0xffffffff80000000. Signed-off-by: Jianlong.Huang <jianlong.huang@starfivetech.com> Co-developed-by: Wei Fu <wefu@redhat.com> Signed-off-by: Wei Fu <wefu@redhat.com>
2022-11-03board: starfive: Add i2c5 init for VisionFive2Jianlong Huang6-5/+66
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03Support sd autobootJianlong Huang3-3/+9
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03riscv:dts:starfive-visionfive2: Add ethernet-phy node to set delay_chainyanhong.wang1-4/+11
configuration Add ethernet-phy subnode to gmac node, so the delay_chain configuration is passed through the ethernet-phy node. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-11-03board: starfive: visionfive: Add uart0 and jtag pinmuxjianlonghuang2-0/+46
Signed-off-by: jianlonghuang <jianlong.huang@starfivetech.com>
2022-11-03board: starfive: Support visionfive2Jianlong Huang13-194/+421
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-03net: phy: Support YT8531 Gigabit EthernetJianlong Huang1-0/+1
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-11-02Merge branch 'CR_2522_ECO_EVB_samin.guo' into 'jh7110-master'andy.hu7-187/+387
CR_2522: support gamc with jh7110B-evb See merge request sdk/u-boot!16
2022-11-02driver:qspi: Switch the QSPI parent clock to pll0Samin Guo2-2/+5
Switch the QSPI parent clock to pll0 to improve the QSPI speed Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01spl:starfive:jh7110: Improved GMAC0/1 TX I/O PAD capabilitySamin Guo1-15/+30
JH7110B requires a higher IOPAD capability in 1000M mode. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: Support using env to detect board versionSamin Guo2-0/+22
JH7110B need tx_inverted by YT8521 phy, you need to read the chip version to determine whether to use it. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add get_chip_typeSamin Guo2-1/+29
Read the chip model from the rgpio3 and setenv "chip_vision" 1: jh7110B 0: JH7110A defalut: JH7110A Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01board:starfive:evb: add jh7110_gmac_sel_tx_to_rgmiiSamin Guo2-0/+26
JH7110B needs switch gmac0/1 tx to rgmii phy. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01dts:starfive:jh7110: set gmac phy tx_inverted for JH7110A/B.Samin Guo1-1/+11
JH7110B requires tx_inverted_10/100/1000 configuration, and different parameters may be required in 10M/100M/1000M mode. This parameter supports JH7110B+YT8531PHY by default. Other boards can modify the parameters of the tx_inverted_10/100/1000 to obtain support. If you do not configure tx_inverted_10/100/1000 in dts, the default is 0. Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-11-01net:phy:motorcomm: Support modifying RGMII_TX_CLK delay train from dtsSamin Guo1-173/+269
support use original or inverted RGMII_TX_CLK delay train. 10M/100M/1000M can be configured independently. tx_inverted_xx = val; For example: &gmac0 { #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@0 { tx_inverted_10 = <0>; tx_inverted_100 = <1>; tx_inverted_1000 = <1>; }; }; 0: original (default) 1: inverted Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
2022-10-18ram: starfive: Make DDR driver support 8G sizeYan Hong Wang4-733/+547
This patch include four items: 1.rename the driver compatible name. 2.reset action with the common API. 3.clean up code to make it is closer to readable. 4.add configuration to support 8G size Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18riscv: dts: jh7110: Add reset property to DDR control nodeYan Hong Wang1-1/+5
Add reset property configuration to DDR control device tree node. Signed-off-by: Yan Hong Wang <yanhongwang@linux.starfivetech.com>
2022-10-18ram: starfive: jh7110: Replace the configuration operation for pll1 clkYan Hong Wang2-27/+6
Replace the configuration operation for pll1 clk with common api provide by pll module. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18clk: starfive: jh7110: Modify the parameters of clk_register()Yan Hong Wang1-34/+11
Modify the parameters pass to clk_register() for pll0/pll1/pll2 clk. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18spl: starfive: jh7110: switch pll2 to 1188MYan Hong Wang1-165/+11
Switch the pll2 clk to 1188M with the comm pll interface on JH7110. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18arch: riscv: jh7110: add pll clk configuration for jh7110Yan Hong Wang4-18/+416
Add common interface to set and get pll clk information for jh7110 soc. Signed-off-by: Yan Hong Wang <yanhong.wang@starfivetech.com>
2022-10-18configs: starfive: fix tftpboot file waite a long time for the first timeJianlong Huang2-2/+3
ARP_TIMEOUT is too large, then will waite a long time for the first time Set ARP_TIMEOUT to 500 refer to others Set PHY_ANEG_TIMEOUT needs longer aneg time for the 2nd phy Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18clk:jh7110: update apb_bus clk relationshipyanhong.wang2-51/+33
The previous definition of apb_bus clock relationship is incorrect,so update it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18configs: starfive_evb_defconfig: Support saveenvJianlong Huang2-3/+5
Add saveenv config to Support saveenv Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
2022-10-18spl:jh7110: Modify cpu frequency should be before switching pllsamin1-3/+3
Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18config:starfive-jh7110: add sd card boot configClivia.Cai1-1/+2
Configure SD card boot parameters Signed-off-by: Clivia.Cai <Clivia.Cai@starfivetech.com>
2022-10-18riscv:dts:starfive-jh7110: modify Model and riscv,isa infoyanhong.wang2-6/+6
Change Model to "StarFive JH7110 EVB", and change riscv,isa to "rv64imafdcbsux" Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18ram:starfive: Make ddr driver support 2G sizeyanhong.wang4-25/+250
The ddr driver include two configs with 2G and 4G.Fist read the ddr size config from the memory node in the dts,then match the right config and do it. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18reset:starfive:jh7110: Delete redundant logicyanhong.wang1-28/+1
In the hardware design, the IPs RESET signal of jh7110 is divided into two groups,one group is active high, and the other group is active low. However, the software does not need to distinguish whether the RESET signal is active high or active low,Write 1 to be assert, and write 0 to deassert. Therefore, the software does not need to add additional logic to distinguish these two sets of signals. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:jh7110: pll0 dynamically gets the frequencysamin1-5/+35
pll0 dynamically gets the frequency. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18spl:starfive: Add support for different CPU frequencies.samin1-0/+157
The cpu uses 1.25G by default. Lists of frequencies(MHz): -375/500/625/750/875/1000/1250 -1375/1500/1625/1750/1800 Note: Some frequencies require voltage regulation. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18spl:starfive: remove function spl_cpu_fre_150/125samin1-33/+0
replace them with spl_cpu_set_rate. Signed-off-by: samin <samin.guo@starfivetech.com>
2022-10-18board:starfive:evb: update uart3-uart5 resetsyanhong.wang2-6/+13
Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:reset:starfive-jh7110: support reset in SPLyanhong.wang2-1/+9
Update Kconfig to support reset in SPL for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18clk:riscv:starfive: update uart3-uart5 clksyanhong.wang1-16/+24
Update uart3-uart5 clks register info for StarFive JH7110 SoC. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18serial: ns16550: support a list of clkyanhong.wang1-0/+12
Add a list of clk enable operation. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18SPL:starfive-jh7110: Modify the default division factor of sdcard clkyanhong.wang2-0/+9
Modify the default division factor of sdcard clk to 4. Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
2022-10-18board:starfive:evb: add usb init configyanhong.wang3-24/+84
Add usb init config for starfive EVB board. Default set to USB2.0 Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
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